Average inductor current detection circuit and chip, electronic equipment

Abstract

An average inductor current detection circuit and chip, and electronic equipment belong to the technical field of direct current conversion circuits. By connecting with a first power transistor, a second power transistor and an inductor, a sampling circuit samples the current flowing through the inductor to output a voltage signal; a peak value acquisition circuit outputs a first voltage according to the voltage signal; the first voltage is used to characterize the peak value of the current flowing through the inductor; a valley value acquisition circuit outputs a second voltage according to the voltage signal; the second voltage is used to characterize the valley value of the current flowing through the inductor; a voltage averaging circuit averages the first voltage and the second voltage to output an average inductor current detection signal; therefore, there is no need to match the time constant of the detection resistor and the detection capacitor with the time constant of the output inductor L and its direct current resistance, that is, the direct current resistance of different output inductors can be adapted, thereby improving the accuracy of the average inductor current detection circuit; and because the voltage averaging circuit can be implemented using passive devices (resistors), the circuit is simple and the cost is low.

Description

Technical Field

[0001] The present application belongs to the technical field of direct current conversion circuits, and in particular, relates to an average inductor current detection circuit and chip, and electronic equipment. Background Art

[0002] In a current-mode DC-DC switching converter, the inductor current needs to be used as a feedback signal control loop to dynamically adjust the duty cycle of the control signal. In recent industrial applications, it is necessary to accurately measure the average current in the DC-DC converter and pass the load average current to the microcontroller in the system so that the microcontroller can obtain load-related information, including the load current and the load power required.

[0003] The related average inductor current detection circuit is as follows Figure 1 As shown, a detection resistor Rs and a detection capacitor Cs are included, which form an RC network across the output inductor L. The inductor current is detected by matching the time constant of the detection resistor Rs and the detection capacitor Cs with the time constant of the output inductor L and its DC resistance RL.

[0004] L / R L =R s / C s

[0005] Therefore, the voltage across the sensing capacitor Cs is equal to the inductor current multiplied by the resistance RL. The current sensing amplifier 104 amplifies the voltage across the sensing capacitor to generate a sensing voltage ViL1, which represents the sensed inductor current.

[0006] After switch S5 is turned off, the peak value of the inductor current detected at the output of the current detection amplifier 104 is sampled to capacitor C1. During this "first sampling window", switch S1 is turned on, while switches Sclk1, S7 and D1p are all turned off. The voltage across capacitor C1 is recorded as VC1.

[0007] In the second sampling window, the valley current of the inductor is sampled and held on capacitor C2. The switch Sckl1 is closed to sample the valley current of the inductor and store it on capacitor C2. The voltage across capacitor C2 is recorded as VC2.

[0008] Then the clock signal Clk1 closes switch S5, and switches S7 and S6 are closed at the same time. Based on the following conditions

[0009] C 1 =C 2 >>C 3

[0010] Charge sharing occurs between C1 and C2, and their voltages are tracked by the voltage on C3, which represents the average value of the sensed inductor current.

[0011] However, this detection technique assumes that the DC resistance RL of the output inductor is known, which is not common for chip designers. In addition, the charge sharing technique will lead to inaccurate measurement of the inductor current due to channel charge injection and clock feedthrough effects.

[0012] Therefore, the accuracy of the related average inductor current detection circuit is poor. Summary of the invention

[0013] The purpose of the present application is to provide an average inductor current detection circuit and an image sensor, aiming to solve the problem of poor accuracy of the related average inductor current detection circuit.

[0014] The embodiment of the present application provides an average inductor current detection circuit, which is connected to a first power transistor, a second power transistor and an inductor, and includes:

[0015] A sampling circuit configured to sample the current flowing through the inductor to output a voltage signal;

[0016] A peak value acquisition circuit, connected to the sampling circuit, configured to output a first voltage according to the voltage signal; the first voltage is used to represent the peak value of the current flowing through the inductor;

[0017] A valley value acquisition circuit, connected to the sampling circuit, configured to output a second voltage according to the voltage signal; the second voltage is used to characterize the valley value of the current flowing through the inductor;

[0018] The voltage averaging circuit is connected to the peak value acquisition circuit and the valley value acquisition circuit, and is configured to average the first voltage and the second voltage to output an average inductor current detection signal.

[0019] In one embodiment, the sampling circuit includes:

[0020] a current sampling module, connected to the first power transistor, the second power transistor and the inductor, and configured to sample the current flowing through the inductor to output a sampled current;

[0021] a conversion module, connected to the current sampling module, the peak value acquisition circuit and the valley value acquisition circuit, and configured to convert the sampled current into the voltage signal;

[0022] The conversion module includes a voltage source and a first resistor;

[0023] The first end of the first resistor constitutes the sampling current input end of the conversion module, and is connected to the current sampling module to access the sampling current; the first end of the first resistor also constitutes the voltage signal output end of the conversion module, and is connected to the peak acquisition circuit and the valley acquisition circuit to output the voltage signal; the second end of the first resistor is connected to the positive electrode of the voltage source, and the negative electrode of the voltage source is connected to the power ground.

[0024] In one embodiment, the peak value acquisition circuit includes:

[0025] A peak module, connected to the sampling circuit, configured to receive a peak control signal and obtain a peak voltage of the voltage signal in response to the peak control signal;

[0026] a first voltage stabilizing module, connected to the peak voltage module and the voltage averaging circuit, and configured to stabilize the peak voltage to output the first voltage;

[0027] The valley value acquisition circuit comprises:

[0028] A valley module, connected to the sampling circuit, configured to receive a valley control signal and obtain a valley voltage of the voltage signal in response to the valley control signal;

[0029] The second voltage stabilization module is connected to the valley module and the voltage averaging circuit, and is configured to stabilize the valley voltage to output the second voltage.

[0030] In one embodiment, the peak control signal includes a positive peak control signal and a negative peak control signal; the positive peak control signal and the negative peak control signal are inverted; the peak module includes a first transmission gate;

[0031] The input end of the first transmission gate constitutes the voltage signal input end of the peak module, and is connected to the sampling circuit to receive the voltage signal;

[0032] The output end of the first transmission gate constitutes the peak voltage output end of the peak module, and is connected to the first voltage stabilizing module to output the peak voltage;

[0033] The positive control terminal of the first transmission gate constitutes the positive peak control signal input terminal of the peak module to receive the positive peak control signal;

[0034] The negative control terminal of the first transmission gate constitutes the negative peak control signal input terminal of the peak module to receive the negative peak control signal;

[0035] The first voltage stabilization module includes a first capacitor and a first operational amplifier;

[0036] The first end of the first capacitor is connected to the non-inverting input end of the first operational amplifier and constitutes a peak voltage input end of the first voltage stabilizing module, and is connected to the peak module to receive the peak voltage;

[0037] The inverting input terminal of the first operational amplifier and the output terminal of the first operational amplifier are connected to form a first voltage output terminal of the first voltage stabilizing module, and are connected to the voltage averaging circuit to output the first voltage;

[0038] The second end of the first capacitor is connected to a power ground.

[0039] In one embodiment, it also includes:

[0040] A driving circuit is connected to the first power transistor and the second power transistor, configured to receive a control signal and an enable signal, and output a first driving signal, a first inverted driving signal, and a second driving signal according to the control signal; wherein the first driving signal is used to drive the first power transistor, the second driving signal is used to drive the second power transistor, the first driving signal and the first inverted driving signal are inverted, and the first driving signal and the second driving signal are in phase.

[0041] In one embodiment, it also includes:

[0042] a first logic circuit connected to the driving circuit and the peak value acquisition circuit, configured to receive a PWM signal and output the peak value control signal according to the PWM signal and the control signal;

[0043] The second logic circuit is connected to the driving circuit and the valley value acquisition circuit, and is configured to output the valley value control signal according to the first inverted driving signal.

[0044] In one embodiment, the peak control signal includes a positive peak control signal and a negative peak control signal; the first logic circuit includes a first inverter, a first NAND gate, a first delay device, a second inverter, a second NAND gate and a third inverter;

[0045] The first end of the first NAND gate constitutes a control signal input end of the first logic circuit and is connected to the drive circuit to receive the control signal;

[0046] The input end of the first inverter constitutes the PWM signal input end of the first logic circuit to receive the PWM signal;

[0047] The output end of the first inverter is connected to the second end of the first NAND gate, the output end of the first NAND gate is connected to the input end of the first delay device and the first input end of the second NAND gate, the output end of the first delay device is connected to the input end of the second inverter, and the output end of the second inverter is connected to the second input end of the second NAND gate;

[0048] The output end of the second NAND gate and the input end of the third inverter are connected and together constitute the negative peak control signal output end of the first logic circuit, which is connected to the peak acquisition circuit to output the negative peak control signal;

[0049] The output end of the third inverter constitutes the positive peak control signal output end of the first logic circuit, and is connected to the peak acquisition circuit to output the positive peak control signal;

[0050] The first delay device is used to delay the rising edge of the input waveform and maintain the falling edge of the input waveform to control the pulse width of the positive peak control signal;

[0051] The valley control signal includes a positive valley control signal and a negative valley control signal; the second logic circuit includes a second delay, a third delay, a fourth inverter, a third NAND gate and a fifth inverter;

[0052] The input end of the second delay device constitutes the first inverted driving signal input end of the second logic circuit, and is connected to the driving circuit to receive the first inverted driving signal;

[0053] The output end of the second delay device is connected to the input end of the third delay device and the first input end of the third NAND gate, the output end of the third delay device is connected to the input end of the fourth inverter, and the output end of the fourth inverter is connected to the second input end of the third NAND gate;

[0054] The output end of the third NAND gate and the input end of the fifth inverter are connected to form a negative valley control signal input end of the second logic circuit, and are connected to the valley acquisition circuit to output the negative valley control signal;

[0055] The output end of the fifth inverter constitutes the positive valley control signal input end of the second logic circuit, and is connected to the valley acquisition circuit to output the positive valley control signal;

[0056] The second delay device and the third delay device are both used to delay the rising edge of the input waveform and maintain the falling edge of the input waveform, wherein the delay of the third delay device is used to control the pulse width of the positive valley control signal.

[0057] In one embodiment, it also includes:

[0058] a filter circuit connected to the voltage averaging circuit and configured to filter the average inductor current detection signal;

[0059] The buffer circuit is connected to the filter circuit and is configured to buffer the filtered average inductor current detection signal.

[0060] An embodiment of the present invention further provides a chip, wherein the chip includes the above-mentioned average inductor current detection circuit.

[0061] An embodiment of the present invention further provides an electronic device, wherein the electronic device includes the above-mentioned average inductor current detection circuit.

[0062] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: the current flowing through the inductor is converted into a voltage signal, and the first voltage and the second voltage corresponding to the current peak value and the current valley value are obtained, and the average inductor current is detected by using a voltage averaging circuit. There is no need to match the time constant of the detection resistor and the detection capacitor with the time constant of the output inductor L and its DC resistance, that is, the DC resistance of different output inductors can be adapted, thereby improving the accuracy of the average inductor current detection circuit; and because the voltage averaging circuit can be implemented using passive devices (resistors), the circuit is simple and the cost is low. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] In order to more clearly illustrate the technical invention in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0064] Figure 1 A structural schematic diagram of a related average inductor current detection circuit;

[0065] Figure 2 A schematic diagram of a structure of an average inductor current detection circuit provided in one embodiment of the present application;

[0066] Figure 3 A schematic diagram of a structure of a sampling circuit in an average inductor current detection circuit provided in an embodiment of the present application;

[0067] Figure 4 A schematic diagram of a structure of a peak value acquisition circuit in an average inductor current detection circuit provided in an embodiment of the present application;

[0068] Figure 5A schematic diagram of a structure of a valley value acquisition circuit in an average inductor current detection circuit provided in an embodiment of the present application;

[0069] Figure 6 Another structural schematic diagram of an average inductor current detection circuit provided in an embodiment of the present application;

[0070] Figure 7 Another structural schematic diagram of an average inductor current detection circuit provided in an embodiment of the present application;

[0071] Figure 8 Another structural schematic diagram of an average inductor current detection circuit provided in an embodiment of the present application;

[0072] Fig. 9 A partial exemplary circuit schematic diagram of an average inductor current detection circuit provided in an embodiment of the present application;

[0073] Fig.10 A partial exemplary circuit schematic diagram of a first logic circuit in an average inductor current detection circuit provided in an embodiment of the present application;

[0074] Fig.11 A partial exemplary circuit schematic diagram of a second logic circuit in an average inductor current detection circuit provided in an embodiment of the present application;

[0075] Fig.12 A partial exemplary circuit schematic diagram of a driving circuit in an average inductor current detection circuit provided in an embodiment of the present application;

[0076] Fig.13 A signal waveform diagram corresponding to a first logic circuit in an average inductor current detection circuit provided in an embodiment of the present application;

[0077] Fig.14 This is a signal waveform diagram corresponding to the second logic circuit in the average inductor current detection circuit provided in one embodiment of the present application. DETAILED DESCRIPTION

[0078] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0079] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0080] It should be understood that the orientation or position relationship indicated by terms such as "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0081] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0082] Figure 2 The structure diagram of the average inductor current detection circuit provided by the preferred embodiment of the present application is shown. For the convenience of explanation, only the part related to the present embodiment is shown, which is described in detail as follows:

[0083] The average inductor current detection circuit is connected to the first power transistor MP, the second power transistor MN and the inductor L. The average inductor current detection circuit includes a sampling circuit 01 , a peak value acquisition circuit 02 , a valley value acquisition circuit 03 and a voltage averaging circuit 04 .

[0084] The sampling circuit 01 is connected to the first power transistor MP, the second power transistor MN and the inductor L, and is configured to sample the current flowing through the inductor L to output a voltage signal;

[0085] The peak value acquisition circuit 02 is connected to the sampling circuit 01 and is configured to output a first voltage according to the voltage signal; the first voltage is used to represent the peak value of the current flowing through the inductor L;

[0086] The valley value acquisition circuit 03 is connected to the sampling circuit 01 and is configured to output a second voltage according to the voltage signal; the second voltage is used to represent the valley value of the current flowing through the inductor L;

[0087] The voltage averaging circuit 04 is connected to the peak value acquisition circuit 02 and the valley value acquisition circuit 03, and is configured to average the first voltage and the second voltage to output an average inductor current detection signal.

[0088] In a specific implementation, the first power transistor MP may be a power upper transistor connected to the power supply; the second power transistor MN may be a power lower transistor connected to the power ground.

[0089] The above-mentioned average inductor current detection circuit is connected to the first power transistor MP, the second power transistor MN and the first end of the inductor L, the second end of the inductor L is connected to the first end of the load capacitor CL and the first end of the load resistor RL, and the second end of the load capacitor CL and the second end of the load resistor RL are commonly connected to the power ground.

[0090] like Figure 3 As shown, the sampling circuit 01 includes a current sampling module 011 and a conversion module 012 .

[0091] The current sampling module 011 is connected to the first power transistor MP, the second power transistor MN and the inductor L, and is configured to sample the current flowing through the inductor L to output the sampled current;

[0092] The conversion module 012 is connected to the current sampling module 011 , the peak value acquisition circuit 02 and the valley value acquisition circuit 03 , and is configured to convert the sampled current into a voltage signal.

[0093] The voltage signal is obtained by converting the sampling current, and the reference voltage of the voltage signal can be flexibly adjusted, so that when the current flowing through the inductor L is negative, the voltage signal is still greater than or equal to 0, thereby realizing the detection of the negative (reverse) current flowing through the inductor L.

[0094] like Figure 4 As shown, the peak value acquisition circuit 02 includes a peak value module 021 and a first voltage stabilization module 022 .

[0095] The peak module 021 is connected to the sampling circuit 01 and is configured to receive the peak control signal and obtain the peak voltage of the voltage signal in response to the peak control signal;

[0096] The first voltage stabilizing module 022 is connected to the peak module 021 and the voltage averaging circuit 04 and is configured to stabilize the peak voltage to output a first voltage.

[0097] The peak voltage of the voltage signal is sampled by the peak module 021 , and the peak voltage is maintained and a stable first voltage is output by the first voltage stabilization module 022 , thereby ensuring the accuracy of the average inductor current detection circuit.

[0098] like Figure 5 As shown, the valley value acquisition circuit 03 includes a valley value module 031 and a second voltage stabilization module 032 .

[0099] The valley module 031 is connected to the sampling circuit 01 and configured to receive the valley control signal and obtain the valley voltage of the voltage signal in response to the valley control signal;

[0100] The second voltage stabilization module 032 is connected to the valley module 031 and the voltage averaging circuit 04 , and is configured to stabilize the valley voltage to output a second voltage.

[0101] The valley voltage of the voltage signal is sampled by the valley module 031 , and the valley voltage is maintained by the second voltage stabilization module 032 to output a stable second voltage, thereby ensuring the accuracy of the average inductor current detection circuit.

[0102] like Figure 6 As shown, the above average inductor current detection circuit also includes a drive circuit 05.

[0103] The driving circuit 05 is connected to the first power transistor MP and the second power transistor MN, and is configured to receive a control signal and output a first driving signal, a first inverted driving signal and a second driving signal according to the control signal; wherein the first driving signal is used to drive the first power transistor MP, the second driving signal is used to drive the second power transistor MN, the first driving signal and the first inverted driving signal are inverted, and the first driving signal and the second driving signal are in phase.

[0104] The driving signal of the first power transistor MP and the driving signal of the second power transistor MN are generated by the same control signal, and the signal consistency is good.

[0105] like Figure 7 As shown, the above average inductor current detection circuit further includes a first logic circuit 06 and a second logic circuit 07 .

[0106] The first logic circuit 06 is connected to the driving circuit 05 and the peak value acquisition circuit 02, and is configured to receive the PWM signal and output a peak value control signal according to the PWM signal and the control signal;

[0107] The second logic circuit 07 is connected to the driving circuit 05 and the valley value acquisition circuit 03 , and is configured to output a valley value control signal according to the first inverted driving signal.

[0108] The peak control signal is generated by the PWM signal and the control signal, and the valley control signal is generated by the first inverting drive signal. Compared with the solution of obtaining the peak control signal and the valley control signal by detecting the inductor current, the peak control signal and the valley control signal have smaller delay and higher accuracy.

[0109] like Figure 8 As shown, the above average inductor current detection circuit further includes a filter circuit 08 and a buffer circuit 09 .

[0110] The filter circuit 08 is connected to the voltage averaging circuit 04 and is configured to filter the average inductor current detection signal.

[0111] The buffer circuit 09 is connected to the filter circuit 08 and is configured to buffer the filtered average inductor current detection signal.

[0112] It should be noted that if Figure 2 The average inductor current detection circuit shown can track the change of the average inductor current in a short period of time (cycle by cycle); Figure 8 The average inductor current detection circuit shown is used to track the change of the average inductor current over a long period of time (multiple cycles).

[0113] Fig. 9 FIG. 4 shows a partial exemplary circuit structure of an average inductor current detection circuit provided by an embodiment of the present invention. Fig.10 FIG. 4 shows a partial exemplary circuit structure of a first logic circuit in an average inductor current detection circuit provided by an embodiment of the present invention. Fig.11 An exemplary circuit structure of a second logic circuit in an average inductor current detection circuit provided by an embodiment of the present invention is shown. Fig.12 An exemplary circuit structure of a driving circuit in an average inductor current detection circuit provided in an embodiment of the present invention is shown. For ease of description, only the part related to the embodiment of the present invention is shown, which is described in detail as follows:

[0114] exist Fig. 9 In the figure, the conversion module 012 includes a voltage source Vref and a first resistor R1; the first end of the first resistor R1 constitutes a sampling current input end of the conversion module 012, and is connected to the current sampling module 011 to access the sampling current; the first end of the first resistor R1 also constitutes a voltage signal output end of the conversion module 012, and is connected to the peak acquisition circuit 02 and the valley acquisition circuit 03 to output a voltage signal; the second end of the first resistor R1 is connected to the positive electrode of the voltage source Vref, and the negative electrode of the voltage source Vref is connected to the power ground.

[0115] exist Fig. 9 In the embodiment, the peak control signal includes a positive peak control signal and a negative peak control signal; the positive peak control signal and the negative peak control signal are inverted; the peak module 021 includes a first transmission gate U1. The input end of the first transmission gate U1 constitutes the voltage signal input end of the peak module 021, which is connected to the sampling circuit 01 to receive the voltage signal; the output end of the first transmission gate U1 constitutes the peak voltage output end of the peak module 021, which is connected to the first voltage stabilizing module 022 to output the peak voltage; the positive control end of the first transmission gate U1 constitutes the positive peak control signal input end of the peak module 021 to receive the positive peak control signal; the negative control end of the first transmission gate U1 constitutes the negative peak control signal input end of the peak module 021 to receive the negative peak control signal.

[0116] exist Fig. 9In the embodiment, the first voltage stabilizing module 022 includes a first capacitor C1 and a first operational amplifier U2. The first end of the first capacitor C1 is connected to the non-inverting input end of the first operational amplifier U2 and constitutes the peak voltage input end of the first voltage stabilizing module 022, and is connected to the peak module 021 to access the peak voltage; the inverting input end of the first operational amplifier U2 is connected to the output end of the first operational amplifier U2 and constitutes the first voltage output end of the first voltage stabilizing module 022, and is connected to the voltage averaging circuit 04 to output the first voltage; the second end of the first capacitor C1 is connected to the power ground.

[0117] exist Fig. 9 In the example, the valley control signal includes a positive valley control signal and a negative valley control signal; the positive valley control signal and the valley peak control signal are inverted; the valley module 031 includes a second transmission gate U28. The input end of the second transmission gate U28 constitutes the voltage signal input end of the negative module, which is connected to the sampling circuit 01 to access the voltage signal; the output end of the second transmission gate U28 constitutes the valley voltage output end of the valley module, which is connected to the second voltage stabilizing circuit to output the valley voltage; the positive control end of the second transmission gate U28 constitutes the positive valley control signal input end of the valley module 031 to access the positive valley control signal; the negative control end of the second transmission gate U28 constitutes the negative valley control signal input end of the valley module 031 to access the negative valley control signal.

[0118] exist Fig. 9 In the embodiment, the second voltage stabilizing module 032 includes a second capacitor C2 and a second operational amplifier U29. The first end of the second capacitor C2 is connected to the non-inverting input end of the second operational amplifier U29 and constitutes the valley voltage input end of the second voltage stabilizing module 032, and is connected to the valley module 031 to access the valley voltage; the inverting input end of the second operational amplifier U29 is connected to the output end of the second operational amplifier U29 and constitutes the second voltage output end of the second voltage stabilizing module 032, and is connected to the voltage averaging circuit 04 to output the second voltage; the second end of the second capacitor C2 is connected to the power ground.

[0119] exist Fig. 9 In the figure, the voltage averaging circuit 04 includes a second resistor R2 and a third resistor R3; the first end of the second resistor R2 constitutes a first voltage input end of the voltage averaging circuit 04, which is connected to the peak value acquisition circuit 02 to access the first voltage; the first end of the third resistor R3 constitutes a second voltage input end of the voltage averaging circuit 04, which is connected to the valley value acquisition circuit 03 to access the second voltage; the second end of the second resistor R2 and the second end of the third resistor R3 are connected and together constitute an average inductor current detection signal output end of the voltage averaging circuit 04 to output an average inductor current detection signal.

[0120] exist Fig. 9In the embodiment, the filter circuit 08 includes a fourth resistor R4 and a third capacitor C3. The buffer circuit 09 includes a third operational amplifier U30.

[0121] exist Fig.10 In the embodiment, the peak control signal includes a positive peak control signal and a negative peak control signal; the first logic circuit 06 includes a first inverter U3, a first NAND gate U4, a first delay device U5, a second inverter U6, a second NAND gate U7 and a third inverter U8. The first end of the first NAND gate U4 constitutes the control signal input end of the first logic circuit 06, and is connected to the drive circuit 05 to receive the control signal; the input end of the first inverter U3 constitutes the PWM signal input end of the first logic circuit 06 to receive the PWM signal; the output end of the first inverter U3 is connected to the second end of the first NAND gate U4, the output end of the first NAND gate U4 is connected to the input end of the first delayer U5 and the first input end of the second NAND gate U7, the output end of the first delayer U5 is connected to the input end of the second inverter U6, and the output end of the second inverter U6 is connected to the second input end of the second NAND gate U7; the output end of the second NAND gate U7 is connected to the input end of the third inverter U8 and together constitutes the negative peak control signal output end of the first logic circuit 06, which is connected to the peak acquisition circuit 02 to output the negative peak control signal; the output end of the third inverter U8 constitutes the positive peak control signal output end of the first logic circuit 06, and is connected to the peak acquisition circuit 02 to output the positive peak control signal. The first delay device is used to delay the rising edge of the input waveform and maintain the falling edge of the input waveform to control the pulse width of the positive peak control signal.

[0122] exist Fig.11In the embodiment, the valley control signal includes a positive valley control signal and a negative valley control signal; the second logic circuit 07 includes a second delay device U9, a third delay device U10, a fourth inverter U11, a third NAND gate U12 and a fifth inverter U13. The input end of the second delay device U9 constitutes the first inverting drive signal input end of the second logic circuit 07, and is connected to the drive circuit 05 to receive the first inverting drive signal; the output end of the second delay device U9 is connected to the input end of the third delay device U10 and the first input end of the third NAND gate U12, the output end of the third delay device U10 is connected to the input end of the fourth inverter U11, and the output end of the fourth inverter U11 is connected to the second input end of the third NAND gate U12; the output end of the third NAND gate U12 is connected to the input end of the fifth inverter U13. The negative valley control signal output terminal of the second logic circuit 07 is connected and constituted, and is connected to the valley acquisition circuit 03 to output a negative valley control signal; the output terminal of the fifth inverter U13 constitutes the positive valley control signal output terminal of the second logic circuit 07, and is connected to the valley acquisition circuit 03 to output a positive valley control signal; the second delay device U9 and the third delay device U10 are both used to delay the rising edge of the input waveform and maintain the falling edge of the input waveform, and the delay of the third delay device U10 controls the pulse width of the positive valley control signal.

[0123] exist Fig.12 In the embodiment, the driving circuit 05 includes a sixth inverter U14, a first NOR gate U15, a second NOR gate U21, a fourth NAND gate U16, a fifth NAND gate U22, a first Schmitt trigger U26, a second Schmitt trigger U27, a sixth inverter U17, a seventh inverter U18, an eighth inverter U19, a ninth inverter U20, a tenth inverter U23, an eleventh inverter U24 and a twelfth inverter U25.

[0124] The first input end of the first NOR gate U15 and the first input end of the second NOR gate U21 are connected and together constitute the high-impedance signal input end of the drive circuit 05 to receive the high-impedance signal; the input end of the sixth inverter U14 and the second input end of the second NOR gate U21 are connected and together constitute the control signal input end of the drive circuit 05, which is connected to the first logic circuit 06 to receive the control signal; the output end of the sixth inverter U14 is connected to the second input end of the first NOR gate U15, and the output end of the first NOR gate U15 is connected to the fourth The first end of the NAND gate U16 is connected, the output end of the fourth NAND gate U16 is connected to the input end of the sixth inverter U17, the output end of the sixth inverter U17 is connected to the input end of the seventh inverter U18, the output end of the seventh inverter U18 is connected to the input end of the eighth inverter U19, and the output end of the eighth inverter U19 is connected to the input end of the ninth inverter U20; the output end of the ninth inverter U20 is connected to the input end of the second Schmitt trigger U27 and together constitute the first drive signal output of the drive circuit 05 The output end of the second NOR gate U21 is connected to the first input end of the fifth NAND gate U22, the output end of the fifth NAND gate U22 is connected to the input end of the tenth inverter U23, the output end of the tenth inverter U23 is connected to the input end of the eleventh inverter U24, the output end of the eleventh inverter U24 is connected to the input end of the twelfth inverter U25; the output end of the twelfth inverter U25 is connected to the input end of the first Schmitt trigger U26 and is connected to the first input end of the Schmitt trigger U26. The second drive signal output terminal of the driving circuit 05 is connected to the second power transistor MN to output the second drive signal; the inverting output terminal of the first Schmitt trigger U26 is connected to the second input terminal of the fourth NAND gate U16, and the non-inverting output terminal of the second Schmitt trigger U27 is connected to the second input terminal of the fifth NAND gate U22; the inverting output terminal of the second Schmitt trigger U27 constitutes the first inverting drive signal output terminal of the driving circuit 05, and is connected to the second logic circuit 07 to output the first inverting drive signal.

[0125] The following is a combination of working principles Figures 9 to 12 As shown for further explanation:

[0126] exist Fig. 9 In the figure, Isns_out is the sampling current output by the current sampling module 011, which detects the inductor current Imp flowing through MP. Isns_out is converted into a voltage signal by the first resistor R1, and the reference voltage Vref output by the voltage source Vref is added, which ensures that even when Imp is negative, the total voltage Vsns is still greater than 0. The voltage R1*Isns_out on the first resistor R1 is proportional to Imp. Accordingly, it can be obtained that

[0127] V sns = Isns_out * R 1 + V ref = I mp * k + V ref (1)

[0128] Where k is the linear coefficient between the voltage signal Vsns and Imp. Therefore, when Imp is 0 (MP is off), the voltage signal Vsns is Vref.

[0129] Sample_peak and Sample_val are respectively the positive peak control signal and the positive valley control signal, while the negative peak control signal Sample_peakBa and the negative valley control signal Sample_valBa are respectively obtained by inverting Sample_peak and Sample_val, and these two groups of signals respectively control the opening and closing of the first transmission gate U1 and the second transmission gate U28.

[0130] When Imp reaches the peak value, Vsns reaches the peak voltage, and Sample_peak forms a high-level narrow pulse, so that the first transmission gate U1 is turned on, thereby sampling the peak voltage of Vsns. The first capacitor C1 ensures that after the first transmission gate U1 is turned off, the input end of the first buffer (composed of the first operational amplifier) ​​U2 can still maintain the DC peak voltage.

[0131] When Imp reaches the valley value (the minimum value of Imp when MP is turned on), Vsns reaches the valley voltage, and Sample_val forms a high-level narrow pulse, so that the second transmission gate U28 is turned on, thereby sampling the valley voltage of Vsns. The second capacitor C2 ensures that after the second transmission gate U28 is turned off, the input end of the second buffer (composed of the second operational amplifier) ​​U29 can still maintain a DC valley voltage.

[0132] After passing through the unit gain buffer (first operational amplifier) ​​U2 and (second operational amplifier) ​​U29, the sampled peak voltage (first voltage) Vpeak and the sampled valley voltage (second voltage) Vvalley can be obtained. Then, through the resistor divider network (including the second resistor R2 and the third resistor R3, where R3 = R2), the average value Vavg of Vpeak and Vvalley can be obtained, and Vavg represents the instantaneous average inductor current.

[0133] Vavg can also pass through a low-pass filter circuit 08 (a fourth resistor R4 and a third capacitor C3) and a third buffer (composed of a third operational amplifier) ​​U30 to obtain an output voltage signal Vrpt, which represents an average inductor current over a longer period of time.

[0134] The peak value of Imp is recorded as Imp_peak, and the valley value is recorded as Imp_valley. According to (1), we can get:

[0135] V valley = k*I mp_valley +V ref ,

[0136] V peak = k*I mp_peak +V ref ,

[0137] Therefore

[0138] V avg =1 / 2*(V peak +V valley )=1 / 2*k*(I mp_peak +I mp_valley )+V ref

[0139] The control signal Lx_cntl controls the switches of the first power transistor MP and the second power transistor MN. When the control signal Lx_cntl is high, the first power transistor MP is turned on and the second power transistor MN is turned off. Therefore, Imp increases during this period and decreases to 0 when the control signal Lx_cntl is low. Fig.10 In the circuit, the first delay device U5 generates a relatively low delay (a few nanoseconds), thereby controlling the pulse width of Sample_peak. The inverted signal of the PWM signal Vpwm (recorded as Vpwm_bar) and the control signal Lx_cntl are input to the first NAND gate U4. In a working cycle, Vpwm_bar first changes from high to low, and after a short period of time, Lx_cntl changes to low again. Therefore, when Vpwm_bar just changes to low, the signal V4 output by the first NAND gate U4 becomes high, and then passes through the first delay device U5 to control the signal pulse width, and finally passes through the inverter to finally output the positive peak control signal Sample_peak. Fig.10 The signal waveform diagram corresponding to the first logic circuit shown is shown in Fig.13 .

[0140] The first inverse driving signal FBPgate_LS controls the generation of the positive valley control signal Sample_val. The waveform diagram of the corresponding module can be referenced. Fig.14 , Circuit Reference Fig.11 , wherein the second delay device U9 generates a larger delay, the third delay device U10 generates a smaller delay, and the delay of the third delay device U10 determines the pulse width of Sample_val.

[0141] exist Fig.12In the embodiment, the first Schmitt trigger U26 and the second Schmitt trigger U27 play an anti-interference role, improving the stability of the output signal of the driving circuit 05. The driving signal for controlling the first power transistor MP passes through the second Schmitt trigger U27, and is inverted and output to obtain the first inverted driving signal FBpgate_LS. The control signal lx_cntl and the high-impedance signal highz control the conduction and shutdown of the two power transistors through the driving circuit 05. During normal operation, the high-impedance signal highz is always at a low level.

[0142] The control signal Lx_cntl generates the switching signals (driving signals) of the two power transistors, thus determining the peak and valley moments of Imp. Fig.14 As shown, if the delay in the driving circuit 05 is ignored, when the control signal Lx_cntl is at a high level, the first power transistor MP is turned on and the second power transistor MN is turned off, so that Imp rises from the valley value to the peak value, and the inductor current during this period is Imp. When the control signal Lx_cntl is at a low level, the second power transistor MN is turned on and the first power transistor MP is turned off, so that Imp drops to 0, and the inductor current during this period is the current flowing through MN. Therefore, during the rising phase of Imp, the inductor current is consistent with it, and when Imp is 0, the inductor current continues to decrease. Therefore, the peak and valley values ​​of Imp are the peak and valley values ​​of the inductor current. Further, near the valley value of Imp, the positive valley control signal Sample_val is high, and near the peak value of Imp, the positive peak control signal Sample_peak is high, as shown in Fig.13 and Fig.14 As shown in Figure 2, the peak and valley inductor current detection is achieved.

[0143] An embodiment of the present invention further provides a chip, which includes the above-mentioned average inductor current detection circuit.

[0144] An embodiment of the present invention further provides an electronic device, which includes the above-mentioned average inductor current detection circuit.

[0145] The embodiment of the present invention is connected with a first power transistor, a second power transistor and an inductor, and a sampling circuit samples the current flowing through the inductor to output a voltage signal; a peak value acquisition circuit outputs a first voltage according to the voltage signal; the first voltage is used to characterize the peak value of the current flowing through the inductor; a valley value acquisition circuit outputs a second voltage according to the voltage signal; the second voltage is used to characterize the valley value of the current flowing through the inductor; a voltage averaging circuit averages the first voltage and the second voltage to output an average inductor current detection signal; therefore, there is no need to match the time constant of the detection resistor and the detection capacitor with the time constant of the output inductor L and its DC resistance, that is, it can adapt to different DC resistances of the output inductor, thereby improving the accuracy of the average inductor current detection circuit; and because the voltage averaging circuit can be implemented using passive devices (resistors), the circuit is simple and the cost is low.

[0146] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0147] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. An average inductor current detection circuit, connected to a first power transistor, a second power transistor and an inductor, characterized in that: include: A sampling circuit configured to sample the current flowing through the inductor to output a voltage signal; A peak value acquisition circuit, connected to the sampling circuit, configured to output a first voltage according to the voltage signal; the first voltage is used to represent the peak value of the current flowing through the inductor; A valley value acquisition circuit, connected to the sampling circuit, configured to output a second voltage according to the voltage signal; the second voltage is used to characterize the valley value of the current flowing through the inductor; a voltage averaging circuit, connected to the peak value acquisition circuit and the valley value acquisition circuit, and configured to average the first voltage and the second voltage to output an average inductor current detection signal; a driving circuit connected to the first power transistor and the second power transistor, configured to receive a control signal and an enable signal, and output a first driving signal, a first inverted driving signal, and a second driving signal according to the control signal; wherein the first driving signal is used to drive the first power transistor, the second driving signal is used to drive the second power transistor, the first driving signal and the first inverted driving signal are inverted, and the first driving signal and the second driving signal are in phase; a first logic circuit connected to the driving circuit and the peak value acquisition circuit, configured to receive a PWM signal and output a peak value control signal according to the PWM signal and the control signal; a second logic circuit, connected to the driving circuit and the valley value acquisition circuit, and configured to output a valley value control signal according to the first inverted driving signal; The sampling circuit comprises: a current sampling module, connected to the first power transistor, the second power transistor and the inductor, and configured to sample the current flowing through the inductor to output a sampled current; a conversion module, connected to the current sampling module, the peak value acquisition circuit and the valley value acquisition circuit, and configured to convert the sampled current into the voltage signal; The peak control signal includes a positive peak control signal and a negative peak control signal; the first logic circuit includes a first inverter, a first NAND gate, a first delay device, a second inverter, a second NAND gate and a third inverter; The first end of the first NAND gate constitutes a control signal input end of the first logic circuit and is connected to the drive circuit to receive the control signal; The input end of the first inverter constitutes the PWM signal input end of the first logic circuit to receive the PWM signal; The output end of the first inverter is connected to the second end of the first NAND gate, the output end of the first NAND gate is connected to the input end of the first delay device and the first input end of the second NAND gate, the output end of the first delay device is connected to the input end of the second inverter, and the output end of the second inverter is connected to the second input end of the second NAND gate; The output end of the second NAND gate and the input end of the third inverter are connected and together constitute the negative peak control signal output end of the first logic circuit, which is connected to the peak acquisition circuit to output the negative peak control signal; The output end of the third inverter constitutes the positive peak control signal output end of the first logic circuit, and is connected to the peak acquisition circuit to output the positive peak control signal; The first delay device is used to delay the rising edge of the input waveform and maintain the falling edge of the input waveform to control the pulse width of the positive peak control signal; The valley control signal includes a positive valley control signal and a negative valley control signal; the second logic circuit includes a second delay device, a third delay device, a fourth inverter, a third NAND gate and a fifth inverter; The input end of the second delay device constitutes the first inverted driving signal input end of the second logic circuit, and is connected to the driving circuit to receive the first inverted driving signal; The output end of the second delay device is connected to the input end of the third delay device and the first input end of the third NAND gate, the output end of the third delay device is connected to the input end of the fourth inverter, and the output end of the fourth inverter is connected to the second input end of the third NAND gate; The output end of the third NAND gate and the input end of the fifth inverter are connected to form a negative valley control signal input end of the second logic circuit, and are connected to the valley acquisition circuit to output the negative valley control signal; The output end of the fifth inverter constitutes the positive valley control signal input end of the second logic circuit, and is connected to the valley acquisition circuit to output the positive valley control signal; The second delay device and the third delay device are both used to delay the rising edge of the input waveform and maintain the falling edge of the input waveform. The delay of the third delay device controls the pulse width of the positive valley control signal.

2. The average inductor current detection circuit as claimed in claim 1, characterized in that: The conversion module includes a voltage source and a first resistor; The first end of the first resistor constitutes the sampling current input end of the conversion module, and is connected to the current sampling module to access the sampling current; the first end of the first resistor also constitutes the voltage signal output end of the conversion module, and is connected to the peak acquisition circuit and the valley acquisition circuit to output the voltage signal; the second end of the first resistor is connected to the positive electrode of the voltage source, and the negative electrode of the voltage source is connected to the power ground.

3. The average inductor current detection circuit as claimed in claim 1, characterized in that: The peak value acquisition circuit comprises: A peak module, connected to the sampling circuit, configured to receive a peak control signal and obtain a peak voltage of the voltage signal in response to the peak control signal; a first voltage stabilizing module, connected to the peak voltage module and the voltage averaging circuit, and configured to stabilize the peak voltage to output the first voltage; The valley value acquisition circuit comprises: A valley module, connected to the sampling circuit, configured to receive a valley control signal and obtain a valley voltage of the voltage signal in response to the valley control signal; The second voltage stabilization module is connected to the valley module and the voltage averaging circuit, and is configured to stabilize the valley voltage to output the second voltage.

4. The average inductor current detection circuit as claimed in claim 3, characterized in that: The positive peak control signal and the negative peak control signal are inverted; the peak module includes a first transmission gate; The input end of the first transmission gate constitutes the voltage signal input end of the peak module, and is connected to the sampling circuit to receive the voltage signal; The output end of the first transmission gate constitutes the peak voltage output end of the peak module, and is connected to the first voltage stabilizing module to output the peak voltage; The positive control terminal of the first transmission gate constitutes the positive peak control signal input terminal of the peak module to receive the positive peak control signal; The negative control terminal of the first transmission gate constitutes the negative peak control signal input terminal of the peak module to receive the negative peak control signal; The first voltage stabilization module includes a first capacitor and a first operational amplifier; The first end of the first capacitor is connected to the non-inverting input end of the first operational amplifier and constitutes a peak voltage input end of the first voltage stabilizing module, and is connected to the peak module to receive the peak voltage; The inverting input terminal of the first operational amplifier and the output terminal of the first operational amplifier are connected to form a first voltage output terminal of the first voltage stabilizing module, and are connected to the voltage averaging circuit to output the first voltage; The second end of the first capacitor is connected to a power ground.

5. The average inductor current detection circuit according to any one of claims 1 to 4, characterized in that: Also includes: a filter circuit connected to the voltage averaging circuit and configured to filter the average inductor current detection signal; The buffer circuit is connected to the filter circuit and is configured to buffer the filtered average inductor current detection signal.

6. A chip, characterized in that: The chip comprises the average inductor current detection circuit as claimed in any one of claims 1 to 5.

7. An electronic device, characterized in that: The electronic device comprises the average inductor current detection circuit as claimed in any one of claims 1 to 5.

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