Crossover and electronic equipment

Abstract

The embodiment of the present application discloses a frequency divider and an electronic device, the frequency divider comprising: a two-frequency divider circuit, which is composed of four CMOS inverters connected end to end, the two-frequency divider circuit is used to receive a differential clock signal, and when the frequency divider is in a working state, the differential clock signal is divided to obtain a four-phase output clock signal; a latch, which is composed of a pair of cross-coupled inverters, the latch is set between the output ends of the two CMOS inverters, and the latch is used to reduce the offset between the target output clock signals; the target output clock signal is two output clock signals with a phase difference of a preset degree in the four-phase output clock signal. In this way, no logic device gate and D flip-flop are set in the two-frequency divider circuit, and the operating frequency is only limited by the delay of a single-stage inverter, so the upper limit of the operating frequency can reach 25GHz and above; and by setting the latch, the offset between the multi-phase output clocks caused by the path delay difference can be reduced.

Description

Technical Field

[0001] The present application relates to the technical field of frequency dividers, and in particular to a frequency divider and an electronic device. Background Art

[0002] The divide-by-two frequency circuit in the frequency divider is an electronic circuit whose main function is to divide the input signal into two output signals with different frequencies. The existing common multi-phase divide-by-two frequency circuit realizes the frequency division function by alternately beating the input differential clock.

[0003] In the related art, the architecture of the common multi-phase two-way frequency division circuit is simple, and is usually composed of logic device gates and D flip-flops. However, due to factors such as multiple logic device gate delays and DFF (Data Flip-Flop, D flip-flop) setup time, there is an upper limit to its operating frequency, making it difficult to correctly divide high-frequency clocks above 12GHz, and there is a large offset between the multi-phase output clocks. Summary of the invention

[0004] To solve the above technical problems, the embodiments of the present application provide a frequency divider and an electronic device, so as to realize the correct frequency division of a high-frequency clock in a multi-phase two-division frequency circuit, while reducing the offset between multi-phase output clocks.

[0005] According to one aspect of an embodiment of the present application, a frequency divider is provided, comprising: a divide-by-two circuit, which is composed of four CMOS inverters connected end to end, and is used to receive a differential clock signal, and when the divider is in a working state, divides the differential clock signal to obtain a four-phase output clock signal; a latch, which is composed of a pair of cross-coupled inverters, and the latch is arranged between the output ends of two of the CMOS inverters, and is used to reduce the offset between target output clock signals; the target output clock signal is two output clock signals of the four-phase output clock signal, and the phase difference is a preset degree.

[0006] In some embodiments, the four CMOS inverters include a first CMOS inverter, a second CMOS inverter, a third CMOS inverter and a fourth CMOS inverter connected end to end in sequence; the latch includes a first latch; the first latch is arranged between the output end of the first CMOS inverter and the output end of the third CMOS inverter, and the first latch is used to reduce the offset between the output clock signal of the first CMOS inverter and the output clock signal of the third CMOS inverter.

[0007] In some embodiments, the latch also includes a second latch; the second latch is arranged between the output end of the second CMOS inverter and the output end of the fourth CMOS inverter, and the second latch is used to reduce the offset between the output clock signal of the second CMOS inverter and the output clock signal of the fourth CMOS inverter.

[0008] In some embodiments, there are four clock switch pairs, each clock switch pair is connected to a corresponding CMOS inverter, the CMOS inverter receives a differential clock signal through the clock switch pair connected thereto, and the clock switch pair is configured to be turned on or off simultaneously according to the differential clock signal.

[0009] In some embodiments, the clock switch pair includes two clock switches, one clock switch is used to couple one end of the CMOS inverter to a power supply voltage, and the other clock switch is used to couple the other end of the CMOS inverter to a ground voltage.

[0010] In some embodiments, the frequency divider further includes an enable switch, which is arranged at the output end of the CMOS inverter, and the first end of the enable switch is used to receive a frequency divider enable signal and be turned on or off according to the frequency divider enable signal; the second end of the enable switch is connected to the output end of the CMOS inverter, and the third end of the enable switch is connected to a power supply voltage or a ground voltage.

[0011] In some embodiments, the enable switch includes a first enable switch and a second enable switch, and the frequency divider enable signal includes a first enable signal; the first enable switch is connected to the output end of the fourth CMOS inverter, and the second enable switch is connected to the output end of the first CMOS inverter; the first enable switch and the second enable switch are used to receive the first enable signal, and when the frequency divider is in a non-working state, the output clock signal corresponding to the fourth CMOS inverter and the output clock signal corresponding to the first CMOS inverter are clamped to a second preset level according to the first enable signal.

[0012] In some embodiments, the enable switch includes a third enable switch and a fourth enable switch; the divider enable signal also includes a second enable signal; the third enable switch is connected to the output end of the second CMOS inverter, and the fourth enable switch is connected to the output end of the third CMOS inverter; the third enable switch and the fourth enable switch are used to receive the second enable signal, and when the divider is in a non-working state, the output clock signal corresponding to the second CMOS inverter and the output clock signal corresponding to the third CMOS inverter are clamped to a first preset level according to the second enable signal.

[0013] In some embodiments, the differential clock signal includes a first clock signal and a second clock signal, the second clock signal being an inverted signal of the first clock signal; the frequency divider also includes: a first anti-leakage input circuit, used to receive the first clock signal and a frequency divider enable signal, and when the frequency divider is in a non-working state, clamping the first clock signal to a first preset level according to the frequency divider enable signal; a second anti-leakage input circuit, used to receive the second clock signal and a frequency divider enable signal, and when the frequency divider is in a non-working state, clamping the second clock signal to a second preset level according to the frequency divider enable signal.

[0014] According to one aspect of an embodiment of the present application, an electronic device is provided, comprising the above-mentioned frequency divider.

[0015] In the technical solution provided in the embodiments of the present application, on the one hand, no logic device gate and D flip-flop are set in the divider, and the frequency division function can be realized by a two-division circuit composed of four CMOS inverters connected end to end. Its operating frequency is only limited by the delay of a single-stage inverter, so its upper limit of operating frequency can reach 25GHz and above; on the other hand, by inserting a latch composed of a pair of inverters between the output ends of the two CMOS inverters, the latch can stabilize its input signal and generate a slightly delayed but more stable output signal. Due to the fast response and stability of the latch, it helps to reduce the offset between multi-phase output clocks caused by path delay differences.

[0016] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0018] Figure 1 It is a circuit structure diagram of a multi-phase two-frequency dividing circuit in a frequency divider in the prior art;

[0019] Figure 2 is a circuit structure diagram of a frequency divider shown in an exemplary embodiment of the present application;

[0020] Figure 3 is a working timing diagram of a frequency divider shown in an exemplary embodiment of the present application;

[0021] Figure 4 is a structural schematic diagram of a first anti-leakage input circuit shown in an exemplary embodiment of the present application;

[0022] Figure 5 is a structural schematic diagram of a second anti-leakage input circuit shown in an exemplary embodiment of the present application;

[0023] Figure 6 It is an application schematic diagram of a frequency divider without an anti-leakage input circuit, shown in an exemplary embodiment of the present application.

[0024] Reference numerals:

[0025] 1: first PMOS tube; 2: second PMOS tube; 3: third PMOS tube; 4: fourth PMOS tube; 5: fifth PMOS tube; 6: sixth PMOS tube; 7: seventh PMOS tube; 8: eighth PMOS tube; 9: first enabling switch; 10: second enabling switch; 11: first NMOS tube; 12: second NMOS tube; 13: third NMOS tube; 14: fourth NMOS tube; 15: fifth NMOS tube; 16: sixth NMOS tube; 17: seventh NMOS tube; 18: eighth NMOS tube; 19: third enabling switch; 20: fourth enabling switch; 21: first CMOS inverter; 22: second CMOS inverter; 23: third CMOS inverter; 24: fourth CMOS inverter ; 25: the first latch; 26: the second latch; 27: the first inverter; 28: the second inverter; 29: the third inverter; 30: the fourth inverter; 31: the fifth CMOS inverter; 32: the ninth PMOS tube; 33: the ninth NMOS tube; 34: the fifth enabling switch; 35: the sixth enabling switch; 36: the seventh enabling switch; 37: the sixth CMOS inverter; 38: the tenth PMOS tube; 39: the tenth NMOS tube; 40: the seventh CMOS inverter; 41: the eleventh PMOS tube; 42: the eleventh NMOS tube; 43: the eighth enabling switch; 44: the ninth enabling switch; 45: the tenth enabling switch; 46: the eighth CMOS inverter; 47: the twelfth PMOS tube; 48: the twelfth NMOS tube. DETAILED DESCRIPTION

[0026] Here, exemplary embodiments will be described in detail, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments that are the same as the present application. Instead, they are only examples of devices and methods that are the same as some aspects of the present application as detailed in the attached claims.

[0027] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in the form of an application program, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0028] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0029] It should be noted that the "multiple" mentioned in this application refers to two or more than two. "And / or" describes the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship.

[0030] Combination Figure 1 As shown, the existing common multi-factor two-way frequency division circuit is composed of setting logic device gates and D flip-flops, and then the frequency division function is realized by alternately beating the differential input clock. Figure 1 The differential input clocks are ckp and ckm, the input end of the D flip-flop is the D end, and the output end of the D flip-flop is the Q end; wherein, the setup time of the D flip-flop refers to the period of time during which the data at the input end of the D flip-flop must remain stable before the rising edge of the differential input clock arrives. This period of time is to ensure that the flip-flop can correctly capture and latch the input data. Specifically, when the D flip-flop receives the rising edge of the clock, it will perform a series of operations internally to store the data at the input end to its output end. However, due to physical limitations, such as signal propagation delay, device response time, etc., the D flip-flop requires a certain amount of time to prepare and stabilize its internal state. Therefore, before the rising edge of the clock arrives, the data at the D end must remain stable for a period of time so that the flip-flop can correctly read and store it. Therefore, in the existing ordinary multi-phase two-way frequency division circuit, due to factors such as multiple logic device gate delays and DFF (Data Flip-Flop, D flip-flop) setup time, its operating frequency has an upper limit, it is difficult to correctly divide the high-frequency clock above 12GHz, and there is a large offset between the multi-phase output clocks.

[0031] The present application embodiment provides a frequency divider and an electronic device. Figure 2 , Figure 2 1 is a schematic diagram of a circuit structure of a frequency divider shown in an exemplary embodiment of the present application.

[0032] like Figure 2 As shown, in an exemplary embodiment, the frequency divider includes at least a two-frequency divider circuit and a latch. The two-frequency divider circuit is composed of four CMOS (Complementary Metal Oxide Semiconductor) inverters, namely, a first CMOS inverter 21, a second CMOS inverter 22, a third CMOS inverter 23 and a fourth CMOS inverter 24 connected end to end in sequence. The two-frequency divider circuit is used to receive a differential clock signal, and when the frequency divider is in a working state, divide the differential clock signal to obtain a four-phase output clock signal. In the embodiment of the present application, the differential clock signal includes a first clock signal clk and a second clock signal clkb, and the second clock signal clkb is an inverted signal of the first clock signal clk; the four-phase output clock signals include an output clock signal ckout0, an output clock signal ckout1, an output clock signal ckout2 and an output clock signal ckout3 respectively.

[0033] It should be understood that in the embodiment of the present application, the PMOS (Positive channel Metal Oxide Semiconductor) tube: the P-channel MOS tube has two P+ regions on the N-type silicon substrate, respectively called the source and the drain. There is no conduction between the two electrodes. When a sufficient positive voltage is applied to the source (the gate is grounded), the N-type silicon surface under the gate presents a P-type inversion layer, which becomes a channel connecting the source and the drain. Changing the gate voltage can change the hole density in the channel, thereby changing the resistance of the channel. This type of MOS field effect transistor is called a P-channel enhancement field effect transistor. If a P-type inversion layer channel already exists on the surface of the N-type silicon substrate without applying a gate voltage, adding an appropriate bias voltage can increase or decrease the resistance of the channel. Such a MOS field effect transistor is called a P-channel depletion field effect transistor, collectively referred to as a PMOS tube.

[0034] NMOS (Negative channel Metal Oxide Semiconductor) tube: A MOS tube consisting of a P-type substrate and two high-concentration N diffusion regions is called an N-channel MOS tube. When the tube is turned on, an N-type conductive channel is formed between the two high-concentration N diffusion regions. N-channel enhancement MOS tubes must apply a forward bias to the gate, and a conductive channel is generated only when the gate-source voltage is greater than the threshold voltage. N-channel depletion MOS tubes refer to N-channel MOS tubes that have a conductive channel when no gate voltage is applied (the gate-source voltage is zero).

[0035] The first CMOS inverter 21 is composed of a fifth PMOS transistor 5 and a fifth NMOS transistor 15 connected in series between a power supply voltage and ground. The gates of the fifth PMOS transistor 5 and the fifth NMOS transistor 15 are connected as the input end of the first CMOS inverter 21. The drains of the fifth PMOS transistor 5 and the fifth NMOS transistor 15 are connected as the output end of the first CMOS inverter 21. The output clock signal corresponding to the first CMOS inverter 21 is ckout0.

[0036] The second CMOS inverter 22 is composed of a sixth PMOS transistor 6 and a sixth NMOS transistor 16 connected in series between a power supply voltage and ground. The gates of the sixth PMOS transistor 6 and the sixth NMOS transistor 16 are connected as the input end of the second CMOS inverter 22. The drains of the sixth PMOS transistor 6 and the sixth NMOS transistor 16 are connected as the output end of the second CMOS inverter 22. The output clock signal corresponding to the second CMOS inverter 22 is ckout1.

[0037] The third CMOS inverter 23 is composed of a seventh PMOS transistor 7 and a seventh NMOS transistor 17 connected in series between a power supply voltage and ground. The gates of the seventh PMOS transistor 7 and the seventh NMOS transistor 17 are connected as input terminals of the third CMOS inverter 23. The drains of the seventh PMOS transistor 7 and the seventh NMOS transistor 17 are connected as output terminals of the third CMOS inverter 23. The output clock signal corresponding to the third CMOS inverter 23 is ckout2.

[0038] The fourth CMOS inverter 24 is composed of an eighth PMOS tube 8 and an eighth NMOS tube 18 connected in series between a power supply voltage and ground. The gates of the eighth PMOS tube 8 and the eighth NMOS tube 18 are connected as the input end of the fourth CMOS inverter 24, and the drains of the eighth PMOS tube 8 and the eighth NMOS tube 18 are connected as the output end of the fourth CMOS inverter 24. The output clock signal corresponding to the fourth CMOS inverter 24 is ckout3.

[0039] The latch is composed of a pair of cross-coupled inverters, and the latch is arranged between the output ends of two CMOS inverters. The latch is used to reduce the offset between the target output clock signals; the target output clock signals are two output clock signals with a phase difference of a preset degree among the four-phase output clock signals. The preset degree is 180 degrees. In the embodiment of the present application, the phase difference between the output clock signal ckout0 and the output clock signal ckout2 is 180 degrees, and the phase difference between the output clock signal ckout1 and the output clock signal ckout3 is 180 degrees.

[0040] like Figure 2As shown, in some embodiments, the latch includes a first latch 25 and a second latch 26. The first latch 25 is formed by cross-coupling a first inverter 27 and a second inverter 28, and the second latch 26 is formed by cross-coupling a third inverter 29 and a fourth inverter 30. In the embodiment of the present application, by setting the first latch and the second latch, the first latch and the second latch will stabilize their respective input signals (i.e., an output clock signal) and generate a slightly delayed but more stable output signal (i.e., the next output clock signal). Due to the fast response and stability of the latch, the offset between the output clock signals of each phase caused by the path delay difference can be reduced.

[0041] The first latch 25 is disposed between the output terminal of the first CMOS inverter 21 and the output terminal of the third CMOS inverter 23 , and is used to reduce the offset between the output clock signal ckout0 of the first CMOS inverter 21 and the output clock signal ckout2 of the third CMOS inverter.

[0042] The second latch 26 is disposed between the output terminal of the second CMOS inverter 22 and the output terminal of the fourth CMOS inverter 24 , and is used to reduce the offset between the output clock signal ckout1 of the second CMOS inverter 22 and the output clock signal ckout3 of the fourth CMOS inverter 24 .

[0043] In some embodiments, the frequency divider further includes four clock switch pairs; wherein each clock switch pair is connected to a corresponding CMOS inverter, the CMOS inverter receives a differential clock signal through the clock switch pair connected thereto, and the clock switch pair is configured to be turned on or off simultaneously according to the differential clock signal.

[0044] In some embodiments, the clock switch pair includes two clock switches, one clock switch for coupling one end of the CMOS inverter to a power supply voltage, and the other clock switch for coupling the other end of the CMOS inverter to a ground voltage.

[0045] In the embodiment of the present application, it can be used in a high-speed serdes (Serializer-Deserializer) clock division scheme. For example, in a half-rate serdes architecture, the PLL (phase-locked loop) VCO (voltage-controlled oscillator) oscillates at 25GHz, and then the frequency divider in the present application is used to divide and output a four-phase clock to RX (receiver) and TX (transmitter). Since the inputs of RX and TX may require a fixed output level, by setting clock switches at both ends of the CMOS inverter, the two ends of the CMOS inverter are coupled to the power supply voltage and the ground voltage respectively, so that when the divider is not working, the output clock has a fixed clamping state, thereby improving the flexibility of the divider output.

[0046] like Figure 2 As shown, Figure 2 The clock switch pair connected to the first CMOS inverter 21 includes two clock switches, one clock switch is a first PMOS transistor 1, and the other clock switch is a first NMOS transistor 11. One end of the first CMOS inverter 21 is coupled to the power supply voltage through the first PMOS transistor 1, and the other end of the first CMOS inverter 21 is coupled to the ground voltage through the first NMOS transistor 11; wherein the gate of the first PMOS transistor 1 is the input end of the first clock signal clk, and the gate of the first NMOS transistor 11 is the input end of the second clock signal clkb.

[0047] Figure 2 The clock switch pair connected to the second CMOS inverter 22 includes two clock switches, one clock switch is a second PMOS transistor 2, and the other clock switch is a second NMOS transistor 12. One end of the second CMOS inverter 22 is coupled to the power supply voltage through the second PMOS transistor 2, and the other end of the second CMOS inverter 22 is coupled to the ground voltage through the second NMOS transistor 12; wherein the gate of the second PMOS transistor 2 is the input end of the first clock signal clk, and the gate of the second NMOS transistor 12 is the input end of the second clock signal clkb.

[0048] Figure 2 The clock switch pair connected to the third CMOS inverter 23 includes two clock switches, one of which is a third PMOS transistor 3, and the other is a third NMOS transistor 13. One end of the third CMOS inverter 23 is coupled to the power supply voltage through the third PMOS transistor 3, and the other end of the third CMOS inverter 23 is coupled to the ground voltage through the third NMOS transistor 13; wherein the gate of the third PMOS transistor 3 is the input end of the first clock signal clk, and the gate of the third NMOS transistor 13 is the input end of the second clock signal clkb.

[0049] Figure 2The clock switch pair connected to the fourth CMOS inverter 24 includes two clock switches, one clock switch is a fourth PMOS transistor 4, and the other clock switch is a fourth NMOS transistor 14. One end of the fourth CMOS inverter 24 is coupled to the power supply voltage through the fourth PMOS transistor 4, and the other end of the fourth CMOS inverter 24 is coupled to the ground voltage through the fourth NMOS transistor 14; wherein the gate of the fourth PMOS transistor 4 is the input end of the first clock signal clk, and the gate of the fourth NMOS transistor 14 is the input end of the second clock signal clkb.

[0050] In some embodiments, the frequency divider further includes an enable switch; wherein the enable switch is arranged at the output end of the CMOS inverter, the first end of the enable switch is used to receive a frequency divider enable signal, and is turned on or off according to the frequency divider enable signal; the second end of the enable switch is connected to the output end of the CMOS inverter, and the third end of the enable switch is connected to the power supply voltage or the ground voltage.

[0051] In the embodiment of the present application, the enable switch is controlled to be turned on or off by the divider enable signal, so that the output clock signal of each CMOS inverter can be controlled according to the different working states of the divider; this can ensure that when the divider is not working, its output is fixed in a known state, which helps to reduce power consumption and avoid uncertain states, thereby improving stability.

[0052] In some embodiments, Figure 2 As shown, the enabling switches include a first enabling switch 9, a second enabling switch 10, a third enabling switch 19 and a fourth enabling switch 20, and the frequency divider enabling signal includes a first enabling signal en and a second enabling signal enb.

[0053] The first enabling switch 9 is connected to the output end of the fourth CMOS inverter 24 , the second enabling switch 10 is connected to the output end of the first CMOS inverter 21 , the third enabling switch 19 is connected to the output end of the second CMOS inverter 22 , and the fourth enabling switch 20 is connected to the output end of the third CMOS inverter 23 .

[0054] The first enable switch 9 and the second enable switch 10 are used to receive a first enable signal en, and when the frequency divider is in a non-operating state, the output clock signal ckout3 corresponding to the fourth CMOS inverter 24 and the output clock signal ckout0 corresponding to the first CMOS inverter 21 are clamped to a second preset level according to the first enable signal. The second preset level is a high level, that is, a power supply voltage.

[0055] The third enable switch 19 and the fourth enable switch 20 are used to receive the second enable signal enb, and when the frequency divider is in a non-operating state, the output clock signal ckout1 corresponding to the second CMOS inverter 22 and the output clock signal ckout2 corresponding to the third CMOS inverter 23 are clamped to a first preset level according to the second enable signal. The first preset level is a low level, that is, a ground voltage.

[0056] When the divider is not working, the enable switch is controlled by the input divider enable signal to pull the output clock signal ckout3 and the output clock signal ckout0 to the power supply voltage, and the output clock signal ckout1 and the output clock signal ckout2 to the ground voltage, which can ensure that when the divider is not working, its output is fixed in a known state, thereby helping to reduce power consumption and avoid uncertain states. The output can be correctly biased, thereby reducing power consumption and instability.

[0057] In some embodiments, the differential clock signal includes a first clock signal clk and a second clock signal clkb, and the second clock signal clkb is an inverted signal of the first clock signal clk. The frequency divider also includes: a first anti-leakage input circuit and a second anti-leakage input circuit. The first anti-leakage input circuit is used to receive the first clock signal and the frequency divider enable signal, and when the frequency divider is in a non-working state, the first clock signal is clamped to a first preset level according to the frequency divider enable signal. The second anti-leakage input circuit is used to receive the second clock signal and the frequency divider enable signal, and when the frequency divider is in a non-working state, the second clock signal is clamped to a second preset level according to the frequency divider enable signal. Among them, the first preset level is a low level, that is, a ground voltage; the second preset level is a high level, that is, a power supply voltage.

[0058] In the embodiment of the present application, the frequency divider enable signal includes a first enable signal en and a second enable signal enb. When the frequency divider is in a working state, the frequency divider enable signal is the first enable signal en=1, and the second enable signal enb=0; when the frequency divider is in a non-working state, the frequency divider enable signal is the first enable signal en=0, and the second enable signal enb=1. In this way, when the frequency divider is not working, the first enable signal en is 0, and the second enable signal enb is 1, so that the first anti-leakage input circuit will clamp the first clock signal clk and the second clock signal clkb to 0 and 1 respectively, so the first anti-leakage input circuit and the second anti-leakage input circuit can make the frequency divider not be affected by the state of the external input clock when it is not working, and independently maintain a silent state, while also preventing leakage from the core circuit of the frequency divider.

[0059] In some embodiments, in combination Figure 3 As shown, Figure 3This is a working timing diagram of a frequency divider shown in an exemplary embodiment of the present application. Clkin and clkbin are differential clock signals, clkin is the first clock signal before clamping, and clkbin is the second clock signal before clamping. When the frequency divider is not in operation, clkin is clamped by a first anti-leakage input circuit to obtain the clamped first clock signal clk; clkbin is clamped by a second anti-leakage input circuit to obtain the clamped second clock signal clkb.

[0060] When the frequency divider is in the non-working state, clkin and clkbin are differential clock signals, the first clock signal clk after clamping the differential clock signal is low level, and the second clock signal clkb after clamping is high level; the first enable signal en is low level, and the second enable signal enb is high level; the output clock signal ckout3 corresponding to the fourth CMOS inverter is high level, the output clock signal ckout2 corresponding to the third CMOS inverter is low level, the output clock signal ckout1 corresponding to the second CMOS inverter is low level, and the output clock signal ckout0 corresponding to the first CMOS inverter is high level.

[0061] When the frequency divider is in working state, the first clock signal clk and the second clock signal clkb are not clamped, and the first clock signal clk and the second clock signal clkb change simultaneously with time; the first enable signal en becomes a high level, and the second enable signal enb becomes a low level; the output clock signal ckout3 corresponding to the fourth CMOS inverter, the output clock signal ckout2 corresponding to the third CMOS inverter, the output clock signal ckout1 corresponding to the second CMOS inverter, and the output clock signal ckout0 corresponding to the first CMOS inverter change with the change of the differential clock signal.

[0062] In some embodiments, in combination Figure 4 As shown, Figure 4 It is a structural schematic diagram of a first anti-leakage input circuit shown in an exemplary embodiment of the present application.

[0063] The first anti-leakage input circuit is composed of a fifth CMOS inverter 31 and a sixth CMOS inverter 37 in cascade, and the output of the fifth CMOS inverter 31 is the input of the sixth CMOS inverter 37. The output end of the fifth CMOS inverter is also connected to the seventh enable switch 36, and the output end of the fifth CMOS inverter 31 is coupled to the power supply voltage through the seventh enable switch 36. Among them, the seventh enable switch is used to receive the first enable signal en, and is turned on or off according to the first enable signal. In some embodiments, the seventh enable switch is a PMOS tube, and the gate of the PMOS tube is the input end of the first enable signal en. When the first enable signal en is at a low level, the seventh enable switch is turned on; when the first enable signal en is at a high level, the seventh enable switch is turned off. In this way, by setting the divider enable signal when the divider is not working to en=0 and enb=1 respectively, the first clock signal clk can be clamped to a low level.

[0064] The fifth CMOS inverter 31 is composed of a ninth PMOS transistor 32 and a ninth NMOS transistor 33 connected in series between a power supply voltage and ground. The gates of the ninth PMOS transistor 32 and the ninth NMOS transistor 33 are connected as the input end of the fifth CMOS inverter 31, and the drains of the ninth PMOS transistor 32 and the ninth NMOS transistor 33 are connected as the output end of the fifth CMOS inverter 31.

[0065] The fifth CMOS inverter 31 is coupled to the power supply voltage through the fifth enable switch 34. The fifth enable switch is used to receive the second enable signal enb and is turned on or off according to the second enable signal. In some embodiments, the fifth enable switch 34 is a PMOS tube, and the gate of the PMOS tube is the input end of the second enable signal enb. When the second enable signal enb is at a low level, the fifth enable switch is turned on; when the second enable signal enb is at a high level, the fifth enable switch is turned off.

[0066] The fifth CMOS inverter 31 is coupled to the ground voltage through the sixth enable switch 35. The sixth enable switch is used to receive the first enable signal en and is turned on or off according to the first enable signal. In some embodiments, the sixth enable switch 35 is an NMOS tube, and the gate of the NMOS tube is the input end of the first enable signal en. When the first enable signal en is at a low level, the sixth enable switch is turned off; when the first enable signal en is at a high level, the sixth enable switch is turned on.

[0067] The sixth CMOS inverter 37 is formed by connecting the tenth PMOS transistor 38 and the tenth NMOS transistor 39 in series between the power supply voltage and the ground. The gates of the tenth PMOS transistor 38 and the tenth NMOS transistor 39 are connected as the input end of the sixth CMOS inverter 37, and the drains of the tenth PMOS transistor 38 and the tenth NMOS transistor 39 are connected as the output end of the sixth CMOS inverter 37. The source of the tenth PMOS transistor 38 is connected to the power supply voltage, and the source of the tenth NMOS transistor 39 is connected to the ground voltage.

[0068] For example, when the frequency divider is not in operation, the first enable signal en is at a low level, and the second enable signal enb is at a high level; the seventh enable switch 36 is turned on, and the input signal of the sixth CMOS inverter 37 is at a high level, then the tenth NMOS tube 39 is turned on, and the corresponding output signal of the sixth CMOS inverter 37, that is, the first clock signal clk is at a low level, so that the first NMOS tube 11 is disconnected, so that there will be no current path from the power supply to the ground in the two-frequency divider circuit, thereby preventing leakage from occurring in the core circuit of the frequency divider. At the same time, the first anti-leakage input circuit can allow the frequency divider to be independent of the state of the external input clock when it is not in operation and maintain a silent state, thereby reducing instability.

[0069] In some embodiments, in combination Figure 5 As shown, Figure 5 It is a structural schematic diagram of a second anti-leakage input circuit shown in an exemplary embodiment of the present application.

[0070] The second anti-leakage input circuit is composed of a seventh CMOS inverter 40 and an eighth CMOS inverter 46 connected in cascade, and the output of the seventh CMOS inverter 40 is the input of the eighth CMOS inverter 46. The output end of the seventh CMOS inverter 40 is also connected to the tenth enable switch 45, and the output end of the seventh CMOS inverter 40 is coupled to the ground voltage through the tenth enable switch 45. Among them, the tenth enable switch 45 is used to receive the second enable signal enb, and is turned on or off according to the second enable signal. In some embodiments, the tenth enable switch 45 is an NMOS tube, and the gate of the NMOS tube is the input end of the second enable signal enb. When the second enable signal enb is at a high level, the tenth enable switch 45 is turned on; when the second enable signal enb is at a low level, the tenth enable switch 45 is turned off. In this way, by setting the divider enable signal when the divider is not working to en=0 and enb=1 respectively, the second clock signal clkb can be clamped to a high level.

[0071] The seventh CMOS inverter 40 is composed of an eleventh PMOS transistor 41 and an eleventh NMOS transistor 42 connected in series between a power supply voltage and ground. The gates of the eleventh PMOS transistor 41 and the eleventh NMOS transistor 42 are connected as the input end of the seventh CMOS inverter 40, and the drains of the eleventh PMOS transistor 41 and the eleventh NMOS transistor 42 are connected as the output end of the seventh CMOS inverter 40.

[0072] The seventh CMOS inverter 40 is coupled to the power supply voltage through the eighth enable switch 43, and the eighth enable switch 43 is used to receive the second enable signal enb and be turned on or off according to the second enable signal. In some embodiments, the eighth enable switch 43 is a PMOS tube, and the gate of the PMOS tube is the input end of the second enable signal enb. When the second enable signal enb is at a low level, the eighth enable switch 43 is turned on; when the second enable signal enb is at a high level, the eighth enable switch 43 is turned off.

[0073] The seventh CMOS inverter 40 is coupled to the ground voltage through the ninth enable switch 44. The ninth enable switch 44 is used to receive the first enable signal en and is turned on or off according to the first enable signal. In some embodiments, the ninth enable switch 44 is an NMOS tube, and the gate of the NMOS tube is the input end of the first enable signal en. When the first enable signal en is at a low level, the ninth enable switch 44 is turned off; when the first enable signal en is at a high level, the ninth enable switch 44 is turned on.

[0074] The eighth CMOS inverter 46 is formed by connecting a twelfth PMOS transistor 47 and a twelfth NMOS transistor 48 in series between a power supply voltage and a ground, wherein the gates of the twelfth PMOS transistor 47 and the twelfth NMOS transistor 48 are connected as the input end of the eighth CMOS inverter 46, and the drains of the twelfth PMOS transistor 47 and the twelfth NMOS transistor 48 are connected as the output end of the eighth CMOS inverter 46. The source of the twelfth PMOS transistor 47 is connected to the power supply voltage, and the source of the twelfth NMOS transistor 48 is connected to the ground voltage.

[0075] For example, when the frequency divider is not working, the first enable signal en is at a low level and the second enable signal enb is at a high level; the tenth enable switch 45 is turned on, and the input signal of the eighth CMOS inverter 46 is at a low level, the twelfth PMOS tube 47 is turned on, and the corresponding output signal of the eighth CMOS inverter 46, that is, the second clock signal clkb is at a high level, so that the first NMOS tube 11 is disconnected, so that the frequency divider is not affected by the state of the external input clock when it is not working, and can independently maintain a silent state, thereby reducing instability.

[0076] See also Figure 6 , Figure 6 It is an application schematic diagram of a frequency divider without an anti-leakage input circuit, shown in an exemplary embodiment of the present application. Figure 6 The differential clock signal is directly input into each CMOS inverter. If the anti-leakage input circuit is not set, when the frequency divider is not working, the first enable signal en and the second enable signal enb are 0 and 1 respectively, the output clock signal ckout3 corresponding to the fourth CMOS inverter will be pulled to 1, and the output clock signal ckout0 corresponding to the first CMOS inverter will also be pulled to 1. If the first clock signal clk is at a high level at this time, the following will occur: Figure 5 Therefore, by setting an anti-leakage input circuit in the frequency divider, the first clock signal clk can be clamped to 0 when the frequency divider is not working, thereby cutting off the leakage path and preventing leakage from occurring in the core circuit of the frequency divider.

[0077] An embodiment of the present application further provides an electronic device, comprising the frequency divider provided in each of the above embodiments.

[0078] The above content is only a preferred exemplary embodiment of the present application and is not intended to limit the implementation scheme of the present application. A person skilled in the art can easily make corresponding changes or modifications based on the main concept and spirit of the present application. Therefore, the scope of protection of the present application shall be based on the scope of protection required by the claims.

Claims

1. A frequency divider, characterized in that: include: A two-frequency divider circuit, composed of four CMOS inverters connected end to end, the two-frequency divider circuit is used to receive a differential clock signal, and when the frequency divider is in a working state, divide the differential clock signal to obtain a four-phase output clock signal; the four CMOS inverters include a first CMOS inverter, a second CMOS inverter, a third CMOS inverter and a fourth CMOS inverter connected end to end in sequence; A latch, composed of a pair of cross-coupled inverters, the latch is arranged between the output ends of the two CMOS inverters, and the latch is used to reduce the offset between the target output clock signals; the target output clock signals are two output clock signals with a phase difference of a preset degree among the four-phase output clock signals; The differential clock signal includes a first clock signal and a second clock signal, wherein the second clock signal is an inverted signal of the first clock signal; the frequency divider further includes: a first leakage protection input circuit, configured to receive the first clock signal and a frequency divider enable signal, and when the frequency divider is in a non-operating state, clamp the first clock signal to a first preset level according to the frequency divider enable signal; a second leakage protection input circuit, configured to receive the second clock signal and the frequency divider enable signal, and when the frequency divider is in a non-operating state, clamp the second clock signal to a second preset level according to the frequency divider enable signal; The first anti-leakage input circuit is composed of a fifth CMOS inverter and a sixth CMOS inverter connected in cascade, the output of the fifth CMOS inverter is the input of the sixth CMOS inverter; the output end of the fifth CMOS inverter is also connected to a seventh enable switch, and the output end of the fifth CMOS inverter is coupled to the power supply voltage through the seventh enable switch; wherein the frequency divider enable signal includes a first enable signal; the seventh enable switch is used to receive the first enable signal, and is turned on or off according to the first enable signal; the seventh enable switch is a PMOS tube, and when the first enable signal is at a low level, the seventh enable switch is turned on; the input signal of the fifth CMOS inverter is the first clock signal before clamping; The second anti-leakage input circuit is composed of a seventh CMOS inverter and an eighth CMOS inverter connected in cascade, the output of the seventh CMOS inverter is the input of the eighth CMOS inverter; the output end of the seventh CMOS inverter is also connected to a tenth enable switch, and the output end of the seventh CMOS inverter is coupled to the ground voltage through the tenth enable switch; wherein the frequency divider enable signal also includes a second enable signal; the tenth enable switch is used to receive the second enable signal and is turned on or off according to the second enable signal; the tenth enable switch is an NMOS tube, and when the second enable signal is at a high level, the tenth enable switch is turned on; the input signal of the seventh CMOS inverter is the second clock signal before clamping; The frequency divider further includes: an enable switch, which is arranged at the output end of the CMOS inverter, wherein the first end of the enable switch is used to receive a frequency divider enable signal and is turned on or off according to the frequency divider enable signal; the second end of the enable switch is connected to the output end of the CMOS inverter, and the third end of the enable switch is connected to a power supply voltage or a ground voltage; The enable switch includes a first enable switch and a second enable switch, and the frequency divider enable signal includes a first enable signal; the first enable switch is connected to the output end of the fourth CMOS inverter, and the second enable switch is connected to the output end of the first CMOS inverter; the first enable switch and the second enable switch are used to receive the first enable signal, and when the frequency divider is in a non-working state, clamp the output clock signal corresponding to the fourth CMOS inverter and the output clock signal corresponding to the first CMOS inverter to a second preset level according to the first enable signal; The enable switch includes a third enable switch and a fourth enable switch; the frequency divider enable signal also includes a second enable signal; the third enable switch is connected to the output end of the second CMOS inverter, and the fourth enable switch is connected to the output end of the third CMOS inverter; the third enable switch and the fourth enable switch are used to receive the second enable signal, and when the frequency divider is in a non-working state, clamp the output clock signal corresponding to the second CMOS inverter and the output clock signal corresponding to the third CMOS inverter to a first preset level according to the second enable signal; The first preset level is a low level, and the second preset level is a high level.

2. The frequency divider according to claim 1, characterized in that: The latch comprises a first latch; The first latch is arranged between an output terminal of the first CMOS inverter and an output terminal of the third CMOS inverter, and is used to reduce an offset between an output clock signal of the first CMOS inverter and an output clock signal of the third CMOS inverter.

3. The frequency divider according to claim 2, characterized in that: The latch also includes a second latch; The second latch is arranged between an output terminal of the second CMOS inverter and an output terminal of the fourth CMOS inverter, and is used to reduce an offset between an output clock signal of the second CMOS inverter and an output clock signal of the fourth CMOS inverter.

4. The frequency divider according to claim 1, characterized in that: Also includes: There are four clock switch pairs, each clock switch pair is connected to a corresponding CMOS inverter, the CMOS inverter receives a differential clock signal through the clock switch pair connected thereto, and the clock switch pair is configured to be turned on or off simultaneously according to the differential clock signal.

5. The frequency divider according to claim 4, characterized in that: The clock switch pair includes two clock switches, one clock switch is used to couple one end of the CMOS inverter to a power supply voltage, and the other clock switch is used to couple the other end of the CMOS inverter to a ground voltage.

6. An electronic device, characterized in that: The device comprises the frequency divider as claimed in any one of claims 1 to 5.

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