A SiC / GaN vertical FinFET device and preparation method

Abstract

The present application relates to the technical field of power electronic device preparation, and in particular to a SiC / GaN vertical FinFET device and a preparation method. The device includes: a drain layer, an n + Type SiC substrate, n ‑ Type SiC homoepitaxial layer, buffer layer, n ‑ Type GaN epitaxial layer; the buffer layer is a two-dimensional material film or a highly doped Al(Ga)N film; n ‑ The top side of the GaN epitaxial layer is recessed and provided with a groove; the device further comprises: + Type GaN epitaxial layer, source layer and gate layer; n + The GaN epitaxial layer is located in the n ‑ The top side of the convex part between two adjacent grooves in the n-type GaN epitaxial layer; the source layer is located at n + The top side of the GaN epitaxial layer; the gate layer is located in the groove. The present application can solve the technical problems of high difficulty in generating a buffer layer and insufficient avalanche resistance of the prepared epitaxial wafer structure in the existing technology of using GaN or SiC to prepare an epitaxial wafer structure.

Description

Technical Field

[0001] The present application relates to the technical field of power electronic device preparation, and in particular to a SiC / GaN vertical FinFET device and a preparation method thereof. Background Art

[0002] Epitaxial wafer structures are required in the preparation of high-power switching devices. In the prior art, GaN (gallium nitride) and SiC (silicon carbide) are very suitable for manufacturing high-efficiency power switching devices because they have high critical breakdown electric fields and relatively large carrier mobility.

[0003] Due to the high-mobility 2D electron gas (2DEG) and small terminal capacitance, most of the GaN devices currently used are based on planar GaN high electron mobility transistors (HEMTs). However, adjusting the rated voltage of GaN HEMTs to above 650V requires expanding the lateral dimensions (increasing the distance between the gate and the drain), resulting in very low benefits per unit cost.

[0004] On the other hand, vertical power devices are more competitive in providing high-voltage blocking capabilities because they only need to increase the thickness of the vertical drift region without expanding the device area, and are easier to manage heat and package. Usually, a local pn junction is formed by p-type injection or p-type epitaxial technology to achieve an effective voltage blocking structure. However, the p-type hole mobility of GaN and SiC is not high, resulting in a large channel resistance R channel , and PN-type devices have a higher turn-on voltage, which further limits the operating frequency of the device.

[0005] However, due to the high difficulty of GaN epitaxy required for fully vertical GaN power devices, it is difficult for heterogeneous GaN epitaxial layers to reach a very high thickness, resulting in high costs; in addition, the complete GaN material exhibits a serious lack of avalanche resistance and is prone to destructive breakdown; in addition, in the existing technology of using GaN to prepare epitaxial wafer structures, thick ultra-wide bandgap semiconductor AlN and AlGaN materials are usually used as buffer layers, but in actual applications, thick AlN and AlGaN buffer layers have poor conductivity.

[0006] In summary, the existing technology of using GaN or SiC to prepare SiC / GaN vertical FinFET devices has the technical problems of high preparation cost and insufficient avalanche resistance of the prepared FinFET devices. Summary of the invention

[0007] In view of this, the purpose of the present application is to provide a SiC / GaN vertical FinFET device and a preparation method to solve the technical problems of high preparation cost and insufficient avalanche resistance of the FinFET device in the existing technology of using GaN or SiC to prepare FinFET devices.

[0008] In a first aspect, the present application provides a SiC / GaN vertical FinFET device, the device comprising: a drain layer, an n + Type SiC substrate, n - Type SiC homoepitaxial layer, buffer layer, n - Type GaN epitaxial layer;

[0009] The buffer layer is a two-dimensional material film or a highly doped Al(Ga)N film; the thickness of the buffer layer is 0.2nm to 50nm;

[0010] The - The top side of the GaN epitaxial layer is recessed and provided with a plurality of grooves;

[0011] The device also includes: + Type GaN epitaxial layer, source layer and gate layer; the n + The n-type GaN epitaxial layer is located in the - The top side of the convex portion between two adjacent grooves in the n-type GaN epitaxial layer; the source layer is located at the n + The top side of the type GaN epitaxial layer; the gate layer is located in the groove.

[0012] Preferably, the n + Type SiC substrate is bevel cut n + Type 4H-SiC substrate or bevel cut n + Type 6H-SiC substrate.

[0013] Preferably, the n - The thickness of the SiC homoepitaxial layer is 8 μm to 100 μm; - type GaN epitaxial layer and the n + The total stacking thickness of the GaN epitaxial layer is 1 μm to 30 μm.

[0014] Preferably, the n + The type SiC substrate comprises: - A SiC substrate buffer layer bonded to a SiC homoepitaxial layer; the thickness of the SiC substrate buffer layer is 0.1 μm to 4 μm.

[0015] Preferably, the two-dimensional material film includes a graphene single crystal film.

[0016] In a second aspect, the present application provides a method for preparing a SiC / GaN vertical FinFET device, the method comprising:

[0017] In n + The top side of the SiC substrate generates n - Type SiC homoepitaxial layer and buffer layer; the buffer layer is a two-dimensional material film or a highly doped Al(Ga)N film; the thickness of the buffer layer is 0.2μm to 50nm;

[0018] Generate GaN nucleation sites on the top side of the buffer layer; generate n on the top side of the buffer layer based on the GaN nucleation sites - Type GaN epitaxial layer;

[0019] In the n - The top side of the GaN epitaxial layer generates n + Type GaN epitaxial layer; in the n + A plurality of grooves are etched on the top side of the n-type GaN epitaxial layer, wherein the depth of the grooves is greater than that of the n-type GaN epitaxial layer. + The thickness of the GaN epitaxial layer;

[0020] In the n + A drain layer is formed on the bottom side of the SiC substrate and the n-type SiC substrate is located between two adjacent grooves. + A source layer is generated on the top side of the SiC / GaN epitaxial layer and a gate layer is generated at the groove to obtain a SiC / GaN vertical FinFET device.

[0021] Preferably, the + The top side of the SiC substrate generates n - Type SiC homoepitaxial layer and buffer layer, including:

[0022] Through the gradual doping based on the process temperature of 1400℃~1800℃ + A SiC substrate buffer layer is generated on a type SiC substrate;

[0023] The n is generated on the SiC substrate buffer layer at a process temperature of 1400°C to 1800°C. - Type SiC homoepitaxial layer.

[0024] Preferably, the two-dimensional material film comprises a graphene single crystal film; + The top side of the SiC substrate generates n - Type SiC homoepitaxial layer and buffer layer, and also includes:

[0025] By high temperature chemical vapor deposition, metal organic compound vapor deposition or molecular beam epitaxy -The graphene single crystal film is generated on the top side of the SiC homoepitaxial layer;

[0026] or by high temperature chemical vapor deposition or molecular beam epitaxy on the n - The highly doped Al(Ga)N thin film is grown on the top side of the SiC homoepitaxial layer.

[0027] Preferably, generating GaN nucleation sites on the top side of the buffer layer comprises:

[0028] The GaN nucleation sites are obtained by optimizing the surface of the buffer layer through the operation of plasma-activated oxygen atoms, nitrogen atoms or hydrogen atoms.

[0029] Preferably, the n - type GaN epitaxial layer and the n + The total thickness of the stacked GaN epitaxial layer is 1 μm to 30 μm; - The top side of the GaN epitaxial layer generates n + Type GaN epitaxial layer, including:

[0030] Based on the process temperature of 600℃~1300℃ - The n-type GaN epitaxial layer is generated + Type GaN epitaxial layer.

[0031] Beneficial effects:

[0032] The present application provides a SiC / GaN vertical FinFET device, comprising: a drain layer, an n + Type SiC substrate, n - Type SiC homoepitaxial layer, buffer layer, n - Type GaN epitaxial layer; the buffer layer is a two-dimensional material film or a highly doped Al(Ga)N film; n - The top side of the GaN epitaxial layer is recessed with a plurality of grooves; the device also includes: + Type GaN epitaxial layer, source layer and gate layer; n + The GaN epitaxial layer is located in the n - The top side of the convex part between two adjacent grooves in the n-type GaN epitaxial layer; the source layer is located at n + The top side of the type GaN epitaxial layer; the gate layer is located in the groove. In summary, the present application sets n - Compared with the n-type GaN drift layer in the prior art, the n-type SiC homoepitaxial layer has the advantages of strong avalanche resistance and reduces the preparation cost of the prior art that uses GaN as the epitaxial layer. The present application can also use a two-dimensional material film or a highly doped Al(Ga)N film as the n-type GaN drift layer. -Type SiC homoepitaxial layer and n - The buffer layer between the type GaN epitaxial layers reduces the difficulty of generating the buffer layer and reduces the preparation cost compared to the existing technology using Si-doped materials and thicker AlN and AlGaN materials as the buffer layer. Therefore, the present application can solve the technical problems of high preparation cost and insufficient avalanche resistance of the prepared FinFET device in the existing technology of using GaN or SiC to prepare SiC / GaN vertical FinFET devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0034] Figure 1 Schematic diagram of the structure of a SiC / GaN vertical FinFET device in an embodiment of the present application;

[0035] Figure 2 Schematic diagram of the process of preparing a SiC / GaN vertical FinFET device in an embodiment of the present application;

[0036] Figure 3 In the method for preparing the SiC / GaN vertical FinFET device in the embodiment of the present application, + The top side of the SiC substrate generates n - Schematic diagram of the implementation of type SiC homoepitaxial layer;

[0037] Figure 4 In the method for preparing the SiC / GaN vertical FinFET device in the embodiment of the present application, - Schematic diagram of the implementation of growing a two-dimensional material film on the top side of a SiC homoepitaxial layer;

[0038] Figure 5 In the method for preparing the SiC / GaN vertical FinFET device in the embodiment of the present application, - Schematic diagram of the implementation of growing a highly doped Al(Ga)N film on the top side of a SiC homoepitaxial layer;

[0039] Figure 6 In the method for preparing the SiC / GaN vertical FinFET device in the embodiment of the present application, - The top side of the GaN epitaxial layer generates n + Schematic diagram of the implementation of type GaN epitaxial layer. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution of the present application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present application.

[0041] First, the present application provides an embodiment of a SiC / GaN vertical FinFET device, such as Figure 1 As shown, Figure 1 The schematic diagram of the structure of the SiC / GaN vertical FinFET device in the embodiment of the present application includes: a drain layer 110, a n + Type SiC substrate 210, n - type SiC homoepitaxial layer 220, buffer layer 310 and n - type GaN epitaxial layer 410, and n + type GaN epitaxial layer 420 , source layer 120 and gate layer 130 .

[0042] Among them, n - The top side of the GaN epitaxial layer 410 is recessed and provided with a plurality of grooves.

[0043] The buffer layer is a two-dimensional material film or a highly doped Al(Ga)N film, and the thickness of the buffer layer 310 is 0.2 μm to 50 μm. + The n-type GaN epitaxial layer 420 is located at - The source layer 120 is located at the top side of the convex portion between two adjacent grooves in the n-type GaN epitaxial layer 410. + The top side of the GaN epitaxial layer 420 is provided; the gate layer 130 is located in the groove. The gate layer 130 includes: a metal layer 1301, an Al2O3 layer 1302 and a SiO2 layer 1303. The Al2O3 layer 1302 and the SiO2 layer 1303 are gate dielectrics.

[0044] Specifically, SiC and GaN in the embodiments of the present application are all n-type materials, avoiding the use of p-type material regions, and also have the advantages of low resistance and high switching frequency. In practical applications, high switching frequency is conducive to further reducing the size of the device. The substance doped in the highly doped Al(Ga)N film is Si.

[0045] The n used in this application embodiment +The thermal conductivity of the conductive type SiC substrate 210 is 420 W / (m·K), which is much higher than the thermal conductivity of the GaN substrate of 130-200 W / (m·K), the thermal conductivity of the Si substrate of 100 W / (m·K), and the thermal conductivity of the sapphire substrate of 25 W / (m·K). + The type SiC substrate 210 and the thicker low-doped n - The SiC homoepitaxial layer 220 is a choice with both performance and cost advantages.

[0046] In practical applications, compared with the high cost and small size (the maximum commercial size is only 2 to 4 inches) of the substrate material GaN in the prior art, which leads to the problem of high device preparation cost, the present invention embodiment n + type SiC substrate 210 and n - The material SiC of the homoepitaxial SiC layer 220 is developing rapidly in the industry, so the cost will also decrease rapidly, and the size can be further increased, so the technical solution of the present application can save costs in the preparation of the substrate layer and the epitaxial layer. - Type GaN epitaxial layer 410, n + The GaN epitaxial layer 420 fully utilizes the advantages of high electron mobility, high saturation drift velocity and high breakdown field strength of GaN materials.

[0047] In one implementation, n + The SiC substrate 210 is cut at 4° or 8°. + Type 4H-SiC substrate or bevel cut n + Type 6H-SiC substrate.

[0048] In the embodiment of the present application, n - Type GaN epitaxial layer 410 and n + Type GaN epitaxial layer 420, to achieve bevel cutting n - Type 4H-SiC homoepitaxial layer and n - Type GaN epitaxial layer 410, n + The GaN epitaxial layer 420 is integrated into the same wafer, overcoming the technical limitation of the prior art that requires thicker AlN and AlGaN buffer layers, and achieving direct epitaxy of higher-quality GaN heterostructures, thereby obtaining high-voltage and high-reliability SiC / GaN vertical FinFET devices.

[0049] In one implementation, n - The thickness of the SiC homoepitaxial layer 220 is 8 μm to 100 μm; - Type GaN epitaxial layer 410 and n +The total thickness of the stacked GaN epitaxial layer 420 is 1 μm to 30 μm. + Type SiC substrates include: - The SiC substrate buffer layer is bonded to the SiC homoepitaxial layer. The thickness of the SiC substrate buffer layer is 0.1 μm to 4 μm.

[0050] Specifically, in practical applications, low-doped n - The thickness of the SiC homoepitaxial layer 220 should be set thicker, so that the obtained n - The n-type SiC homoepitaxial layer 220 has better avalanche resistance than the n-type GaN drift region, and can improve the working stability of the device.

[0051] n - The doping concentration of the GaN epitaxial layer 410 is 1E15-2E16 cm -3 , n + The doping concentration of the GaN epitaxial layer 420 is 5E18 to 2.5E20 cm -3 .

[0052] It should be emphasized that n - Type GaN epitaxial layer 410 and n + The total thickness of the stacked GaN epitaxial layer 420 is n - The thickness of the GaN epitaxial layer 410 is n - The entire thickness of the convex portion between the two grooves in the GaN epitaxial layer 410.

[0053] In one implementation, the two-dimensional material film includes a graphene single crystal film.

[0054] Specifically, the two-dimensional material can be highly conductive and thermally conductive graphene or graphene oxide. Correspondingly, the buffer layer 310 can be a single atomic layer or a single atomic layer of graphene single crystal film. In practical applications, the graphene single crystal film can also be replaced by other van der Waals two-dimensional material films, such as NbSe2, and the remote epitaxy of the surface of the van der Waals two-dimensional material film can be used to alleviate the lattice mismatch between III-Nitride and the substrate, and epitaxially produce higher quality III-Nitride heterostructures and high-performance devices.

[0055] In the prior art, the buffer layer 310 between the SiC substrate 210 or the SiC homoepitaxial layer 220 and the GaN epitaxial layer is usually based on coaxially beveled semi-insulating SiC. However, in practical applications, beveled SiC substrates may introduce incompatibility issues, such as lattice mismatch and uneven stress distribution, which may affect the performance and life of the device. Therefore, the embodiments of the present application are implemented by -The SiC homoepitaxial layer 220 is covered with a two-dimensional material film to alleviate the vertical stacking mismatch effect that occurs in the conventional epitaxial 2H III-Nitride of the bevel-cut 4H-SiC.

[0056] In summary, the embodiment of the present application sets n - The type SiC homoepitaxial layer 220 has the advantages of strong avalanche resistance compared to the n-type GaN drift layer in the prior art and reduces the preparation cost of the prior art that uses GaN as the epitaxial layer completely; the present application can also use a two-dimensional material film or a highly doped Al(Ga)N film as the n-type GaN drift layer. - Type SiC homoepitaxial layer 220 and n - The buffer layer between the GaN epitaxial layers 410 is formed. Compared with the prior art using Si-doped materials and thicker Al(Ga)N materials as buffer layers, the embodiments of the present application reduce the difficulty of generating the buffer layer, and thus reduce the preparation cost.

[0057] Second, the present application provides an embodiment of a method for preparing a SiC / GaN vertical FinFET device, such as Figure 2 As shown, Figure 2 The schematic diagram of the process of preparing a SiC / GaN vertical FinFET device in an embodiment of the present application includes:

[0058] S110: In n + The top side of the SiC substrate generates n - Type SiC homoepitaxial layer and buffer layer.

[0059] The buffer layer is a two-dimensional material film or a highly doped Al(Ga)N film, and the thickness of the buffer layer is 0.2 μm to 50 nm.

[0060] Specifically, Figure 3 , Figure 4 and Figure 5 As shown, Figure 3 In the method for preparing the SiC / GaN vertical FinFET device in the embodiment of the present application, + The top side of the SiC substrate 210 generates n - Schematic diagram of the implementation of the SiC homoepitaxial layer 220, Figure 4 In the method for preparing the SiC / GaN vertical FinFET device in the embodiment of the present application, - Schematic diagram of the implementation of generating a two-dimensional material film on the top side of the SiC homoepitaxial layer 220, Figure 5 In the method for preparing the SiC / GaN vertical FinFET device in the embodiment of the present application, -Schematic diagram of an implementation of growing a highly doped Al(Ga)N film on the top side of a SiC homoepitaxial layer 220. The doped substance in the highly doped Al(Ga)N film is Si.

[0061] In one implementation, S110 includes (1) to (4), which are specifically as follows:

[0062] (1) Gradual doping based on a process temperature of 1400℃~1800℃ + A SiC substrate buffer layer is generated on a SiC substrate.

[0063] Specifically, the thickness of the SiC substrate buffer layer is about 0.1 μm to 4 μm. In actual operation, the SiC substrate buffer layer is generated by a gradient doping process, and the process temperature is 1400° C. to 1800° C.

[0064] (2) Based on the process temperature of 1400℃~1800℃, n is generated on the SiC substrate buffer layer. - Type SiC homoepitaxial layer.

[0065] Specifically, n - The thickness of the SiC homoepitaxial layer 220 is 8 μm to 100 μm, and the room temperature carrier concentration after nitrogen doping is 1E15 cm -3 ~2E16 cm -3 , the process temperature is between 1400℃ and 1800℃.

[0066] (3) High temperature chemical vapor deposition, metal organic compound vapor deposition or molecular beam epitaxy on n - A graphene single crystal film is grown on the top side of the SiC homoepitaxial layer.

[0067] Specifically, the generation of graphene single crystal thin film is achieved by CVD (Chemical Vapor Deposition) or MBE (Molecular beam epitaxy). In actual operation, the MBE method can also achieve the generation of multilayer graphene single crystal thin film, the generation condition is high vacuum condition heat treatment, the process temperature is 800 ℃ ~ 1700 ℃. CVD includes: HTCVD (High Temperature Chemical Vaporous Deposition, high temperature chemical vapor deposition), MOCVD (Metal-organic Chemical Vapor Deposition, metal organic compound chemical vapor deposition) or heat activated furnace tube in Ar gas atmosphere high temperature heat treatment, Ar gas pressure is 1 ~ 2000Torr, the processing temperature is 900 ℃ ~ 1700 ℃.

[0068] In actual operation, the process of generating graphene single crystal film is simple, which can be achieved by applying PECVD (plasma enhanced chemical vapor deposition) or dry etching machine in the Fab factory, or the corresponding RF source of the epitaxial machine. It has the advantages of good processing compatibility, low difficulty, stable structure and high reliability, meets the requirements of mass production, and has good market application prospects.

[0069] In actual operation, MOCVD, HVPE (HVPE is Hydride Vapor Phase Epitaxy) or MBE can also be used to grow the nanostructured carbon nanotubes. - An ultra-thin buffer layer is generated on the SiC homoepitaxial layer 220; the thickness of the ultra-thin buffer layer is 0.2nm-50nm, and the ultra-thin buffer layer can be a conductive Al(Ga)N layer or an ultra-thin buffer layer of other materials.

[0070] (4) Through high temperature chemical vapor deposition or molecular beam epitaxy on n - A highly doped Al(Ga)N film is grown on the top side of the SiC homoepitaxial layer.

[0071] Specifically, it should be emphasized here that the execution of step (3) and step (4) is not performed in a sequential order nor simultaneously, but is selectively performed, that is, in actual operation, after step (2) is executed, you can choose to execute step (3) or step (4).

[0072] S120: Generate GaN nucleation sites on the top side of the buffer layer; Generate n on the top side of the buffer layer based on the GaN nucleation sites - Type GaN epitaxial layer.

[0073] In one implementation, S120 includes (5), specifically as follows:

[0074] (5) The surface of the buffer layer is optimized by manipulating plasma-activated oxygen atoms, nitrogen atoms or hydrogen atoms to obtain GaN nucleation sites.

[0075] Specifically, the surface of the graphene single crystal film is treated by a surface treatment process such as O atoms, N atoms or H atoms to generate GaN nucleation sites.

[0076] After GaN nucleation sites are generated on the surface of the buffer layer, n - The GaN epitaxial layer 410 has a process temperature of 600°C to 1300°C.

[0077] S130: In n -The top side of the GaN epitaxial layer generates n + Type GaN epitaxial layer.

[0078] In one implementation, S130 includes (6), specifically as follows:

[0079] (6) Based on the process temperature of 600℃~1300℃ - n-type GaN epitaxial layer + Type GaN epitaxial layer.

[0080] Among them, n - Type GaN epitaxial layer 410 and n + The total stacking thickness of the GaN epitaxial layer 420 is 1 μm to 30 μm.

[0081] Specifically, Figure 6 As shown, Figure 6 In the method for preparing the SiC / GaN vertical FinFET device in the embodiment of the present application, - The top side of the GaN epitaxial layer 410 generates n + Schematic diagram of the implementation of the type GaN epitaxial layer 420, when the n + After the GaN epitaxial layer 420 is formed, a SiC / GaN hybrid epitaxial wafer can be obtained, and other processes can be performed on the SiC / GaN hybrid epitaxial wafer according to needs to form devices of different specifications or uses.

[0082] S140: In n + A plurality of grooves are etched on the GaN epitaxial layer, and the depth of the grooves is greater than n + The thickness of the GaN epitaxial layer.

[0083] S150: In n + The drain layer is formed on the bottom side of the SiC substrate and the n + A source layer is generated on the top side of the SiC / GaN epitaxial layer and a gate layer is generated in the groove to obtain a SiC / GaN vertical FinFET device.

[0084] Specifically, in the generation including n - Type GaN epitaxial layer 410 and n + After the hybrid epitaxial wafer of the type GaN epitaxial layer 420 is formed, the SiC / GaN vertical FinFET device can be finally obtained by processes such as fin groove etching, groove fillet, first oxygen silicon dielectric layer, aluminum oxide gate oxide, gate metal, second oxygen silicon dielectric layer, source electrode opening, source electrode or anode metal, gate metal opening, drain electrode or cathode metal, etc. In practical applications, the SiC / GaN vertical FinFET device can be used as a high-voltage power device.

[0085] In the embodiment of the present application, the SiC / GaN hybrid epitaxial wafer can be subjected to other processes to obtain a split-gate Fin-MOSFET (Fin Metal-Oxide-Semiconductor Field-Effect Transistor), Fin-JFET (Fin Field-Effect Transistor), PiN diode, SBD (Schottky Barrier Diode), and planar / recessed MOSFET.

[0086] The above are only embodiments of the present application and are not intended to limit the scope of protection of the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the scope of protection of the present application.

Claims

1. A SiC / GaN vertical FinFET device, characterized in that: The device comprises: a drain layer, an n + Type SiC substrate, n - Type SiC homoepitaxial layer, buffer layer, n - Type GaN epitaxial layer; The buffer layer is a two-dimensional material film or a highly doped Al(Ga)N film; the thickness of the buffer layer is 0.2 ~50 ; The - The top side of the GaN epitaxial layer is recessed and provided with a plurality of grooves; The device further comprises: + Type GaN epitaxial layer, source layer and gate layer; the n + The n-type GaN epitaxial layer is located in the - The top side of the convex portion between two adjacent grooves in the n-type GaN epitaxial layer; the source layer is located at the n + The top side of the GaN epitaxial layer is located in the groove; the gate layer is located in the groove; The - The thickness of the SiC homoepitaxial layer is 8 ~100 ; said n - type GaN epitaxial layer and the n + The total thickness of the stacked GaN epitaxial layers is 1 ~30 .

2. The SiC / GaN vertical FinFET device according to claim 1, characterized in that: The + Type SiC substrate is bevel cut n + Type 4H-SiC substrate or bevel cut n + Type 6H-SiC substrate.

3. The SiC / GaN vertical FinFET device according to claim 1, characterized in that: The + The type SiC substrate comprises: - A SiC substrate buffer layer bonded to a SiC homoepitaxial layer; the thickness of the SiC substrate buffer layer is 0.1 ~4 .

4. The SiC / GaN vertical FinFET device according to claim 1, characterized in that: The two-dimensional material film includes a graphene single crystal film.

5. A method for preparing a SiC / GaN vertical FinFET device, characterized in that: For preparing the FinFET device according to claim 1, the method comprises: In n + The top side of the SiC substrate generates n - Type SiC homoepitaxial layer and buffer layer; the buffer layer is a two-dimensional material film or a highly doped Al(Ga)N film; the thickness of the buffer layer is 0.2 ~50 ; Generate GaN nucleation sites on the top side of the buffer layer; generate n on the top side of the buffer layer based on the GaN nucleation sites - Type GaN epitaxial layer; In the n - The top side of the GaN epitaxial layer generates n + Type GaN epitaxial layer; in the n + A plurality of grooves are etched on the top side of the n-type GaN epitaxial layer, wherein the depth of the grooves is greater than that of the n-type GaN epitaxial layer. + The thickness of the GaN epitaxial layer; In the n + A drain layer is formed on the bottom side of the SiC substrate and the n-type SiC substrate is located between two adjacent grooves. + A source layer is generated on the top side of the SiC / GaN epitaxial layer and a gate layer is generated at the groove to obtain a SiC / GaN vertical FinFET device.

6. The method according to claim 5, characterized in that In n + The top side of the SiC substrate generates n - Type SiC homoepitaxial layer and buffer layer, including: Through the gradual doping based on the process temperature of 1400℃~1800℃ + A SiC substrate buffer layer is generated on a type SiC substrate; The n is generated on the SiC substrate buffer layer at a process temperature of 1400°C to 1800°C. - Type SiC homoepitaxial layer.

7. The method according to claim 5, characterized in that The two-dimensional material film comprises a graphene single crystal film; + The top side of the SiC substrate generates n - Type SiC homoepitaxial layer and buffer layer, and also includes: By high temperature chemical vapor deposition, metal organic compound vapor deposition or molecular beam epitaxy - The graphene single crystal film is generated on the top side of the SiC homoepitaxial layer; Either by high temperature chemical vapor deposition or molecular beam epitaxy - The highly doped Al(Ga)N thin film is grown on the top side of the SiC homoepitaxial layer.

8. The method according to claim 7, characterized in that Generating GaN nucleation sites on the top side of the buffer layer comprises: The GaN nucleation sites are obtained by optimizing the surface of the buffer layer through the operation of plasma-activated oxygen atoms, nitrogen atoms or hydrogen atoms.

9. The method according to claim 5, characterized in that The - type GaN epitaxial layer and the n + The total thickness of the stacked GaN epitaxial layers is 1 ~30 ; In the n - The top side of the GaN epitaxial layer generates n + Type GaN epitaxial layer, including: Based on the process temperature of 600℃~1300℃ - The n-type GaN epitaxial layer is generated + Type GaN epitaxial layer.

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