Multi-channel aggregation routing chip and electronic device, data caching method, and storage medium

Abstract

The present disclosure provides a multi-channel aggregation routing chip and electronic equipment, a data caching method, and a storage medium, which relate to the field of vehicle technology. The multi-channel aggregation routing chip includes a cache pool management module and a shared storage module, the shared storage module includes a first matrix memory access controller, a storage unit, and a second matrix memory access controller connected in sequence, and the storage unit includes multiple dual-end memories; the cache pool management module is configured to receive data write requests from different video input channels, and allocate storage space for each video input channel in the storage unit to cache the current row data; when the current row data is read, the storage space occupied by the current row data is recovered and released. With the multi-channel aggregation routing chip disclosed in the present disclosure, the cache space of each video input channel can be shared, and can be dynamically allocated according to the actual application scenario, which effectively improves the use efficiency of the row buffer, has a wide range of applications, and is highly flexible.

Description

Technical Field

[0001] The present disclosure generally relates to the technical field of vehicle-mounted chips, and in particular to a multi-channel aggregation routing chip and electronic equipment, a data caching method, and a storage medium. Background Art

[0002] In the multi-channel aggregation of in-vehicle video data, both routing and replication require the use of line buffers for data caching. The size and efficiency of the line buffers determine the maximum size of the video images that can be processed and the maximum number of channels for processing image data at the same time. The line buffers in the chip occupy 30% to 40% of the entire chip area. Therefore, how to maximize the efficiency of the line buffers and adapt to a variety of application scenarios under the condition of limited line buffers is a technical problem that needs to be solved urgently. Summary of the invention

[0003] In view of the above-mentioned defects or deficiencies in the related art, it is desired to provide a multi-channel aggregation routing chip and electronic device, a data caching method, and a storage medium, which can effectively improve the utilization efficiency of the row buffer and enhance the flexibility of the chip to adapt to the scene.

[0004] In a first aspect, the present disclosure provides a multi-way aggregation routing chip, the multi-way aggregation routing chip includes a cache pool management module and a shared storage module, the shared storage module includes a first matrix memory access controller, a storage unit and a second matrix memory access controller connected in sequence, the storage unit includes a plurality of dual-end memories;

[0005] The buffer pool management module is configured to receive data write requests from different video input channels, and allocate storage space in the storage unit for each of the video input channels to cache current row data; when the current row data is read, the storage space occupied by the current row data is reclaimed and released.

[0006] Optionally, in some embodiments of the present disclosure, the storage unit is specifically configured to buffer the current row data in sequence according to the numbering order of the dual-end memory according to the memory access address corresponding to the video input channel.

[0007] Optionally, in some embodiments of the present disclosure, the first matrix memory access controller and the second matrix memory access controller are further specifically used to arbitrate based on the priorities corresponding to the video input channels when multiple video input channels access the same dual-port memory.

[0008] Optionally, in some embodiments of the present disclosure, the buffer pool management module includes a row buffer management unit for each of the different video input channels, and the row buffer management unit is specifically used to update the row buffer occupancy status in the row buffer list corresponding to the storage space according to the operating status of the current row data.

[0009] Optionally, in some embodiments of the present disclosure, the dual-terminal memory is a static random access memory.

[0010] In a second aspect, the present disclosure provides an electronic device, comprising the multi-path aggregation routing chip as described in any one of the first aspects.

[0011] Optionally, in some embodiments of the present disclosure, the electronic device includes a camera hub.

[0012] In a third aspect, the present disclosure provides a data caching method for the multi-channel aggregation routing chip described in any one of the first aspects, the data caching method comprising:

[0013] receiving data write requests from different video input channels, and allocating storage space for each of the video input channels to cache current row data;

[0014] When the reading of the current row of data is completed, the storage space occupied by the current row of data is reclaimed and released.

[0015] Optionally, in some embodiments of the present disclosure, allocating storage space for each of the video input channels to cache current row data includes:

[0016] According to the memory access address corresponding to the video input channel, the current row data is buffered in sequence according to the serial numbering sequence of the dual-end memory.

[0017] In a fourth aspect, the present disclosure provides a computer-readable storage medium, which stores one or more programs, and the one or more programs can be executed by one or more processors to implement the steps of the data caching method described in any one of the third aspects.

[0018] It can be seen from the above technical solutions that the embodiments of the present disclosure have the following advantages:

[0019] The disclosed embodiments provide a multi-channel aggregation routing chip and an electronic device, a data caching method, and a storage medium. The multi-channel aggregation routing chip includes a cache pool management module and a shared storage module, wherein the shared storage module includes a first matrix memory access controller, a storage unit, and a second matrix memory access controller connected in sequence, and the storage unit includes a plurality of dual-end memories, so that the cache pool management module in the multi-channel aggregation routing chip can receive data write requests from different video input channels, and allocate storage space in the storage unit for each video input channel to cache current row data, that is, the cache space of each video input channel is shared and can be dynamically allocated according to actual application scenarios, and after the current row data is read, the storage space occupied by the current row data is recovered and released, which greatly improves the use efficiency of the row buffer memory, has a wide range of applications, and is highly flexible. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Other features, objects and advantages of the present disclosure will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0021] Figure 1 A structural block diagram of a multi-channel aggregation routing chip provided in an embodiment of the present disclosure;

[0022] Figure 2 A schematic diagram of the hardware structure of a multi-channel aggregation routing chip provided in an embodiment of the present disclosure;

[0023] Figure 3 A schematic diagram of the hardware structure of another multi-channel aggregation routing chip provided in an embodiment of the present disclosure;

[0024] Figure 4 A schematic diagram of the structure of a shared storage module provided in an embodiment of the present disclosure;

[0025] Figure 5 A schematic diagram of accessing a video input channel provided by an embodiment of the present disclosure;

[0026] Figure 6 A structural block diagram of an electronic device provided in an embodiment of the present disclosure;

[0027] Figure 7 A flowchart of a data caching method provided in an embodiment of the present disclosure.

[0028] Reference numerals

[0029] 1-multi-channel aggregation routing chip, 101-cache pool management module, 102-shared storage module, 1021-first matrix memory access controller, 1022-storage unit, 1023-second matrix memory access controller, 2-electronic device. DETAILED DESCRIPTION

[0030] In order to enable those skilled in the art to better understand the disclosed solution, the technical solution in the disclosed embodiment will be clearly and completely described below in conjunction with the drawings in the disclosed embodiment. Obviously, the described embodiment is only a part of the disclosed embodiment, not all of the embodiments. Based on the embodiments in the disclosed embodiment, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the disclosed embodiment.

[0031] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present disclosure described can be implemented in sequences other than those illustrated or described herein.

[0032] In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus that includes a series of steps or modules is not necessarily limited to those steps or modules explicitly listed, but may include other steps or modules not explicitly listed or inherent to these processes, methods, products, or apparatuses.

[0033] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other. Figures 1 to 7 The multi-channel aggregation routing chip and electronic device, data caching method, and storage medium provided by the embodiments of the present disclosure are described in detail.

[0034] Please refer to Figure 1 , which is a structural block diagram of a multi-channel aggregation routing chip provided by an embodiment of the present disclosure. The multi-channel aggregation routing chip 1 includes a cache pool management module 101 and a shared storage module 102. The shared storage module 102 includes a first matrix memory access controller 1021, a storage unit 1022, and a second matrix memory access controller 1023 connected in sequence. The storage unit 1022 includes a plurality of dual-end memories, for example, the dual-end memories can be static random access memories (SRAM). Among them, the cache pool management module 101 can receive data write requests from different video input channels, and allocate storage space for each video input channel in the storage unit 1022 to cache the current row data; and when the current row data is read, the storage space occupied by the current row data is recovered and released.

[0035] For example, Figure 2As shown in the current in-vehicle video data multi-channel aggregation routing chip, the line buffer of each video input channel is fixed, the line buffers of each channel cannot be uniformly addressed, and cannot be shared with each other. It cannot be flexibly adjusted according to the application scenario during the use of the chip. That is to say, when the image sizes of the video input channels are different, the line buffers occupied by small-sized images and large-sized images are the same, and the buffer memory utilization rate is not high, which seriously limits the support for larger-sized images. Figure 3 As shown, the cache space of each video input channel (corresponding to PIPE0, PIPE1, PIPE2 and PIPE3, etc.) in the multi-channel aggregation routing chip 1 of the embodiment of the present disclosure can be shared, and the cache pool management module 101 can dynamically allocate the cache space according to the actual application scenario, which effectively improves the utilization efficiency of the line buffer memory and has strong flexibility.

[0036] Furthermore, if Figure 4 As shown, it is a structural diagram of a shared storage module provided by an embodiment of the present disclosure. Among them, wr arbiter represents the first matrix memory access controller 1021, rd arbiter represents the second matrix memory access controller 1023, both of which are in the form of NxM matrix, and bank0~bank7 represents the storage unit 1022, that is, it contains 8 SRAMbanks, and these 8 SRAMs are organized together using an interleaving strategy. For example, when the video input channel accesses the cache pool, the storage unit 1022 can buffer the current row data in the order of the numbering of the dual-end memory according to the memory access address corresponding to the video input channel, and the lower 3 bits of the memory access address are used as bank decoding to determine which dual-end memory needs to be accessed currently. For example Figure 5 As shown, burst5 corresponds to the access of video input channel 5, and burst6 corresponds to the access of video input channel 6. Burst5 will sequentially access bank0 to bank7, and burst6 will only sequentially access bank2 and bank3.

[0037] For another example, the first matrix memory access controller 1021 and the second matrix memory access controller 1023 can ensure that each video input channel can access different dual-end memories at the same time. When multiple video input channels access the same dual-end memory, the first matrix memory access controller 1021 and the second matrix memory access controller 1023 can arbitrate based on the priorities corresponding to the video input channels, and the priorities can be configured through the control register. Since the embodiment of the present disclosure adopts a dual-end memory, the read and write channels can access the same bank at the same time without arbitration.

[0038] For another example, the buffer pool management module 101 may include line buffer management units for different video input channels, that is, line buffer management units for 8 video input channels, and these 8 line buffer management units have the same hardware structure. During initialization, the system allocates an exclusive storage space in the buffer pool according to actual needs. The storage space consists of a base address and a space size, and the storage space can be further divided into several line buffers (line buffers), each of which can cache 1 line of video data of the current video input channel. The line buffer management unit will create a line buffer list for these line buffers as shown in Table 1. After the system is initialized, all line buffers in the storage space are marked as free, and the line buffer occupancy status can be updated in the line buffer list corresponding to the storage space according to the operating status of the current line data.

[0039] Table 1 Line buffer list

[0040] index Base_addr length Free_flag

[0041] For example, when the input module needs to write video data, it can request a row buffer from the row buffer management unit, and then the row buffer management unit selects the idle row buffer with the smallest table number value (i.e., index) from all the table entries with Free_flag=1 and allocates it to the current request, and marks the row buffer as occupied. Furthermore, after the input module completes writing the current row data, it notifies the corresponding output module of the row buffer information. Finally, the output module completes the output of the current row data and sends information to the row buffer management unit, and the row buffer management unit re-marks the row buffer as idle after receiving the corresponding information.

[0042] As another aspect, the present disclosure provides an electronic device. Figure 6 , which is a structural block diagram of an electronic device provided by an embodiment of the present disclosure, the electronic device 2 includes Figures 1 to 5 The multi-channel aggregation routing chip 1 of the corresponding embodiment. For example, the electronic device 2 may include a camera hub.

[0043] As another aspect, the present disclosure provides a method for Figures 1 to 5 The data caching method of the multi-channel aggregation routing chip 1 in any one of the corresponding embodiments. Figure 7 , which is a flow chart of a data caching method provided by an embodiment of the present disclosure, the data caching method specifically comprises the following steps:

[0044] S101, receiving data write requests from different video input channels, and allocating storage space for each video input channel to cache current row data.

[0045] Exemplarily, the cache pool management module 101 in the multi-channel aggregation routing chip 1 can receive data write requests from different video input channels and allocate storage space for each video input channel in the storage unit 1022, and the storage unit 1022 can buffer the current row data in sequence according to the numbering order of the dual-end memory according to the memory access address corresponding to the video input channel.

[0046] S102: When the reading of the current row of data is completed, the storage space occupied by the current row of data is recovered and released.

[0047] Exemplarily, after receiving the information that the output module has completed outputting the current row of data, the row buffer management unit may re-mark the occupied row buffers in the row buffer list as free, so as to prepare for being allocated to the video input channel again.

[0048] As another aspect, the present disclosure provides a computer-readable storage medium for storing program code, the program code for executing the aforementioned Figure 7 Any implementation manner of the data caching method of the corresponding embodiment.

[0049] It should be noted that, for the description of the same steps and the same contents in this embodiment as those in other embodiments, reference can be made to the description in other embodiments and will not be repeated here.

[0050] The multi-channel aggregation routing chip and electronic device, data caching method, and storage medium provided by the embodiments of the present disclosure include a cache pool management module and a shared storage module, wherein the shared storage module includes a first matrix memory access controller, a storage unit, and a second matrix memory access controller connected in sequence, and the storage unit includes a plurality of dual-end memories, thereby the cache pool management module in the multi-channel aggregation routing chip can receive data write requests from different video input channels, and allocate storage space in the storage unit for each video input channel to cache the current row data, that is, the cache space of each video input channel is shared and can be dynamically allocated according to the actual application scenario, and after the current row data is read, the storage space occupied by the current row data is recovered and released, which greatly improves the use efficiency of the row buffer, has a wide range of applications, and is highly flexible.

[0051] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and modules described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0052] In the several embodiments provided in the present disclosure, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or modules, which can be electrical, mechanical or other forms. The modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the scheme of this embodiment.

[0053] In addition, each functional module in each embodiment of the present disclosure may be integrated into a processing unit, or each module may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of a software functional unit. If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it may be stored in a computer-readable storage medium.

[0054] Based on such understanding, the technical solution of the present disclosure, in essence, or the part that contributes to the prior art, or the whole or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the data caching method of each embodiment of the present disclosure. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc., various media that can store program codes.

[0055] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A multi-channel aggregation routing chip, characterized in that: include: Cache pool management module and shared storage module; The shared storage module includes a first matrix memory access controller, a storage unit and a second matrix memory access controller connected in sequence, and the storage unit includes a plurality of two-terminal memories; The buffer pool management module is used to receive data write requests from different video input channels, and allocate storage space in the storage unit for each of the video input channels to cache current row data; When the reading of the current row of data is completed, the storage space occupied by the current row of data is recovered and released; The storage unit is used to buffer the current row data in sequence according to the serial numbering sequence of the dual-end memory according to the memory access address corresponding to the video input channel; The first matrix memory access controller and the second matrix memory access controller are used for arbitrating based on the priorities corresponding to the video input channels when a plurality of the video input channels access the same dual-end memory.

2. The multi-channel aggregation routing chip according to claim 1, characterized in that: The buffer pool management module includes respective line buffer management units for the different video input channels, and the line buffer management units are specifically configured to update the line buffer occupancy status in the line buffer list corresponding to the storage space according to the operation status of the current line data.

3. The multi-channel aggregation routing chip according to claim 1, characterized in that: The dual-terminal memory is a static random access memory.

4. An electronic device, characterized in that: The electronic device comprises the multi-path aggregation routing chip according to any one of claims 1 to 3.

5. The electronic device according to claim 4, characterized in that: The electronic device includes a camera hub.

6. A data caching method for the multi-channel aggregation routing chip according to any one of claims 1 to 3, characterized in that: The data caching method comprises: Receiving data write requests from different video input channels through a buffer pool management module, and allocating storage space for each of the video input channels to cache current row data; The storage unit sequentially buffers the current row data according to the serial numbering sequence of the dual-end memory according to the memory access address corresponding to the video input channel; When a plurality of the video input channels access the same two-port memory, the first matrix memory access controller and the second matrix memory access controller perform arbitration based on the priorities corresponding to the video input channels; When the reading of the current row of data is completed, the buffer pool management module reclaims and releases the storage space occupied by the current row of data.

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