Method for improving the strength of integrated package chip pads

Abstract

The present invention discloses a method for improving the strength of a chip pad for integrated packaging, and relates to the technical field of semiconductor integrated packaging. The present invention comprises the following steps: S1: firstly prepare a temporary carrier substrate and a temporary carrier film, and arrange a microchip on the temporary carrier film. The specific process is as follows: S101: firstly determine the materials of the temporary carrier substrate and the temporary carrier film, and then clean and pretreat the temporary carrier substrate and the temporary carrier film to remove surface pollutants, and perform surface modification; the present invention accurately detects the quality of microchips through a comprehensive evaluation model, and detailed position planning rules. The present invention ensures the precise layout and high quality standards of the microchips, which not only optimizes the electrical connection and thermal management efficiency, but also improves the performance and process yield of the overall packaging structure.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor integrated packaging, and in particular to a method for improving the strength of a pad of an integrated packaging chip. Background Art

[0002] In the field of semiconductor integrated packaging technology, with the development trend of electronic equipment towards high performance, miniaturization and multifunctionality, higher requirements are placed on the packaging technology of integrated circuits. Especially in the process of rewiring (ReDi str ibuted Layer, RDL) of single-chip or multi-chip integrated packaging, the pad is a key part of the connection circuit, and its strength and reliability directly affect the performance and life of the entire chip.

[0003] The traditional pad manufacturing process usually places the metal pad on the lower organic planarization layer. However, due to the insufficient bonding force between the metal pad and the planarization organic layer, this structure is prone to problems such as desorption, delamination and poor welding strength between the pad and the lower planarization layer during chip application. These problems not only reduce the process yield, but also seriously affect the reliability and performance of the product, limiting the development of integrated circuit packaging technology.

[0004] In order to solve the above problems and improve the mechanical strength and bonding reliability of the pads, new integrated packaging technologies need to be developed. This technology should be able to effectively enhance the bonding force between the pads and the underlying materials, reduce the generation of defects, improve the yield of the packaging process, and ensure the long-term reliability of the packaged chip.

[0005] In order to solve the above defects, a technical solution is now provided. Summary of the invention

[0006] The purpose of the present invention is to solve the problem of insufficient bonding strength between the metal pad and the planarized organic layer in the traditional pad manufacturing process. This structure is prone to problems of desorption, stratification and poor welding strength between the pad and the underlying planarization layer during chip application, and a method for improving the pad strength applied to integrated packaging chips is proposed.

[0007] The purpose of the present invention can be achieved through the following technical solutions:

[0008] The method for improving the strength of the pad of an integrated package chip includes the following steps:

[0009] S1: First, prepare a temporary carrier substrate and a temporary carrier film, and arrange the microchip on the temporary carrier film. The specific process is as follows:

[0010] S101: firstly determining the materials of the temporary carrier substrate and the temporary carrier film, then cleaning and pre-treating the temporary carrier substrate and the temporary carrier film to remove surface pollutants and perform surface modification;

[0011] S102: The microchip needs to be subjected to quality inspection to ensure that the size, shape and electrical performance of the microchip meet the requirements by obtaining the quality parameters of the microchip, the quality parameters including dimensional accuracy, surface roughness, electrical characteristics and structural integrity;

[0012] S103: Analyze the quality parameters of the microchip to obtain the size difference value, RMS value, special deviation value and missing value respectively. After normalization, use the sum of the size difference value and the RMS value as the radius to establish a bottom circle, then use the special deviation value as the height to establish a cone model, then use the vertex of the cone model as the center of the sphere and the missing value as the radius to establish a spherical model, calculate the volume of the cone and the sphere after fusion, and record it as the quality judgment value;

[0013] S104: comparing the calculated quality judgment value with a preset quality judgment threshold, and when the quality judgment value exceeds the preset quality judgment threshold, it is determined that the quality of the microchip does not meet the standard;

[0014] S2: fine-tune the position of the microchip using the position planning rules to ensure that the position accuracy of the microchip meets the design requirements;

[0015] S3: then manufacturing a metal microcolumn or a semiconductor material microcolumn with a metal plated surface, and placing the microcolumn at a preset pad position of the microchip;

[0016] S4: making an organic or inorganic adhesive layer, and combining it with the supporting substrate through the adhesive layer;

[0017] S5: Then check the bonding interface to ensure there are no bubbles, cracks or other defects, and then perform a bonding strength test;

[0018] S6: separating the temporary carrier substrate and the temporary carrier film to obtain a planarized microchip;

[0019] S7: Finally, the flattened surfaces of the microchip and microcolumn are processed, and the processes of making a dielectric film, a rewiring layer and a protective layer are carried out to complete the integrated packaging of the microchip.

[0020] Furthermore, the specific process of S103 respectively analyzing the quality parameters of the microchip to obtain the size difference value, RMS value, special deviation value and missing evaluation value is as follows:

[0021] The dimensional accuracy is measured by measuring the length, width and thickness of the microchip through an optical microscope, a scanning electron microscope or an atomic force microscope, and calculating the difference between the measured value and the preset value to obtain the length difference, width difference and thickness difference respectively, and then summing them after normalization and recording them as the dimension difference value;

[0022] Surface roughness is measured by a surface profilometer or atomic force microscope and expressed as RMS value;

[0023] Electrical characteristics The resistance, capacitance, inductance, current and voltage characteristics of the microcell are evaluated by electrical testing equipment and calibrated as Z, R, G, I and Y respectively. Then the standard resistance, capacitance, inductance, current and voltage are preset and calibrated as Z respectively. 标 , R 标 , G 标 ,I 标 and Y 标 , after normalization, enter the following formula: To obtain the special deviation value TPZ;

[0024] Structural integrity is verified by verifying the structural integrity of the microchip, detecting the cracks, defects and voids of the microchip using SEM, transmission electron microscopy or X-ray computed tomography technology, and statistically analyzing the number of cracks, crack area, defect area and void volume. After normalization, the number of cracks is multiplied by the crack area, plus the preset correction coefficient, and the result is added to the sum of the defect area and void volume multiplied by the preset weight factor to obtain the defect value.

[0025] Furthermore, the process of the location planning rule in S2 is as follows:

[0026] Plan the layout of the microchips on the carrier film according to the package design and the requirements of the final product, including the spacing between the microchips, the arrangement and the location of the pads;

[0027] When planning the location of microchips, electrical performance and thermal management should be considered. The arrangement of microchips should be conducive to the optimization of electrical connections and the effective dissipation of heat.

[0028] The location planning of the microchip should also take into account the mechanical strength of the overall structure. The layout of the pads and micro-pillars must ensure sufficient strength to resist the stress that may be encountered during subsequent processing and use;

[0029] Position planning needs to take into account the requirements of subsequent process steps to ensure the smooth progress of the process;

[0030] After the planning is completed, the rationality of the microchip location planning is verified through computer simulation and prototype testing.

[0031] Furthermore, the size of the micro-columns manufactured in S3 matches the size of the designed pads, the thickness is the same as the thickness of the microchip, and the number is consistent with the number of pads.

[0032] Furthermore, the specific operation steps of S4 are as follows:

[0033] Firstly, an organic or inorganic bonding material is selected, the organic bonding material is epoxy resin, and the inorganic bonding material is glass or ceramic material, and the bonding material has good bonding performance, thermal stability and chemical stability;

[0034] According to the required thickness and uniformity of the adhesive layer, the adhesive layer is prepared by spin coating, spray coating, dip coating and drop coating technology, and the amount of adhesive material and the coating speed are controlled during the coating process;

[0035] After coating, the adhesive layer is cured. For organic adhesive materials, the curing is carried out by heating or UV irradiation. The temperature, time and UV intensity of the curing conditions are optimized according to the characteristics of the adhesive material.

[0036] After the adhesive layer cures and forms the proper adhesion, the microchip and micropillars are precisely aligned and placed on the adhesive layer, using precision pick-and-place equipment to ensure accurate alignment;

[0037] After the microchip is placed on the adhesive layer, a preset pressure is applied to ensure good contact and bonding between the adhesive layer and the microchip and micropillars, and the magnitude and duration of the preset pressure are adjusted according to the characteristics of the adhesive material and the strength of the microchip;

[0038] After applying pressure, a post-curing process is performed to further improve the bonding strength, including heat curing at high temperature, ultraviolet light irradiation or laser irradiation process for post-treatment.

[0039] Furthermore, the specific steps of inspecting the bonding interface in S5 are as follows:

[0040] First, the evaluation parameters of the bonding interface are obtained for comprehensive analysis, including: bubbles and cracks, bonding layer thickness and uniformity, surface roughness, bonding strength, viscoelasticity and thermal properties, and chemical composition and structure;

[0041] Then a quantitative evaluation model is created. The quantitative evaluation model weights the above parameters according to their importance in affecting the bonding quality and calculates a comprehensive score. Specifically:

[0042] First, determine the evaluation parameters and their weights: bubble number and size B, crack length and depth C, bonding layer thickness and uniformity D, surface roughness A, bonding strength S, thermal performance matching T, and chemical composition and structure M, and assign a weight W to each parameter;

[0043] Then, a quantitative score is assigned to each parameter according to the actual measurement value and standard. After normalization, the comprehensive score ZP is calculated by the following formula: ZP = (B*W b )+(C*W c )+(D*W d )+(A*W a )+(S*W s )+(T*W t )+(M*W m );

[0044] The calculated comprehensive score ZP is then compared with a plurality of preset comprehensive score intervals, and the preset plurality of comprehensive score intervals are respectively set to correspond to different bonding evaluation levels, so as to determine the level of bonding interface evaluation.

[0045] Compared with the prior art, the present invention has the following beneficial effects:

[0046] (1) The present invention significantly improves the mechanical strength of the pad and the reliability of the bonding interface by combining the micro-pillars at the bottom of the microchip pad and optimizing the bonding layer preparation and curing process. This enhanced structural design and material selection effectively resist external stress and reduce defects, thereby extending the service life of the chip and improving the stability of the package;

[0047] (2) The present invention, through the comprehensive evaluation model to accurately detect the quality of microchips, and the detailed location planning rules, the present invention ensures the precise layout and high quality standards of microchips, which not only optimizes the electrical connection and thermal management efficiency, but also improves the performance and process yield of the overall packaging structure;

[0048] (3) The present invention adopts a quantitative evaluation model and comprehensively considers multiple key parameters to conduct a comprehensive quality evaluation of the bonding interface. This method can accurately judge the quality of the bonding layer and ensure that each step in the packaging process meets high standards, thereby ensuring the high performance and high reliability of the final product. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to facilitate understanding by those skilled in the art, the present invention is further described below in conjunction with the accompanying drawings;

[0050] Figure 1 is a flow chart of the method of the present invention;

[0051] Figure 2 It is a schematic diagram of the strength improvement structure in the present invention. DETAILED DESCRIPTION

[0052] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0053] It should be understood that the terms "include" and "comprising" used in the specification and claims of the present disclosure indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or collections thereof.

[0054] It should also be understood that the terms used in this disclosure are only for the purpose of describing specific embodiments and are not intended to limit the disclosure. As used in this disclosure and claims, the singular forms of "a", "an", and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It should also be further understood that the term "and / or" used in this disclosure and claims refers to any combination of one or more of the associated listed items and all possible combinations, including these combinations.

[0055] like Figure 1-Figure 2 As shown, the method for improving the strength of the integrated package chip pad includes the following steps:

[0056] Prepare a temporary carrier substrate and a temporary carrier film, and arrange the microchip on the temporary carrier film so that the electrodes of the microchip face the temporary carrier film. The specific process is as follows:

[0057] First, a temporary carrier substrate and a temporary carrier film material are selected, and the selected material has good thermal stability, chemical stability and compatibility with subsequent processes; then the temporary carrier substrate and the temporary carrier film are cleaned and pre-treated to remove surface pollutants, and surface modification is performed to improve the adhesion of the microchip and the success rate of subsequent processes; then the microchip needs to be quality tested to ensure that its size, shape and electrical performance meet the requirements, specifically by obtaining the quality parameters of the microchip, which include: dimensional accuracy, surface roughness, electrical characteristics and structural integrity;

[0058] The dimensional accuracy is measured by measuring the length, width and thickness of the microchip through an optical microscope, a scanning electron microscope (SEM) or an atomic force microscope (AFM), and the difference between the measured value and the preset value is calculated to obtain the length difference, width difference and thickness difference respectively, which are summed up after normalization and recorded as the size difference value, and this size difference value is used as a standard for measuring dimensional accuracy; the surface roughness is measured by a surface profilometer or an atomic force microscope and expressed as RMS (root mean square roughness); the smoothness of the microchip surface will affect its performance and the reliability of the connection; the electrical characteristics are evaluated by electrical testing equipment on the resistance, capacitance, inductance, current and voltage characteristics of the microcell, which are calibrated as Z, R, G, I and Y respectively, and then the standard resistance, capacitance, inductance, current and voltage are preset and calibrated as Z respectively 标 , R 标 , G 标 ,I 标 and Y 标 , after normalization, enter the following formula: To obtain the characteristic deviation value TPZ, and use the obtained characteristic deviation value as the standard for measuring the electrical characteristics of the microcell; structural integrity: by verifying the structural integrity of the microchip, the cracks, defects and voids of the microchip are detected using scanning electron microscopy (SEM), transmission electron microscopy (TEM) or X-ray computed tomography (X-rayCT) technology, and the number of cracks, crack area, defect area and void volume are counted, and after normalization, the number of cracks is multiplied by the crack area and the preset correction coefficient is added, and the sum of the defect area and void volume is multiplied by the preset weight factor to obtain the defect value, wherein the preset correction coefficient and weight factor are set between 0.8-0.95 and 1.02-1.11 respectively;

[0059] After normalizing the obtained size difference value, RMS value, special deviation value and missing evaluation value respectively, the sum of the size difference value and the RMS value is used as the radius to establish the bottom circle, and then the special deviation value is used as the height to establish a cone model, and then the vertex of the cone model is used as the center of the sphere and the missing evaluation value is used as the radius to establish a spherical model, and the volume of the cone and the sphere after fusion is calculated and recorded as the quality judgment value, and this quality judgment value is used as a standard for measuring the quality detection of the microchip; then the calculated quality judgment value is compared with the preset quality judgment threshold value, when the quality judgment value exceeds the preset quality judgment threshold value, it is judged that the quality of the microchip does not meet the standard, and the operator is reminded to replace the microchip;

[0060] After the microchip quality inspection is completed, precision pick-and-place equipment such as a chip bonding machine is used to accurately place the microchip in the predetermined position on the temporary carrier film. This process needs to be carried out in a strictly controlled environment to avoid contamination and damage.

[0061] After the microchip is placed, the position of the microchip is fine-tuned to ensure that the position accuracy of the microchip meets the design requirements. The specific microchip position planning rules are as follows:

[0062] According to the requirements of the package design and the final product, the layout of the microchip on the carrier film is planned, including the spacing between the microchips, the arrangement method and the position of the pads; when planning the position of the microchip, electrical performance and thermal management are considered, and the arrangement of the microchips should be conducive to the optimization of electrical connections and the effective dissipation of heat; the position planning of the microchip should also take into account the mechanical strength of the overall structure, and the layout of the pads and micro-columns should ensure sufficient strength to resist the stress that may be encountered during subsequent processes and use; the position planning should take into account the requirements of subsequent process steps, such as the production of the redistribution layer (RDL) and the connection between the pads and micro-columns, to ensure the smooth progress of the process; after completing the planning, the rationality of the microchip position planning is verified through computer simulation and prototype testing to ensure the performance and reliability of the final product;

[0063] Then, metal micro-pillars or semiconductor material micro-pillars with metal coating on the surface are made, the size of the micro-pillars matches the size of the designed pads, the thickness is equivalent to the thickness of the microchip, and the number is consistent with the number of pads, and then the micro-pillars are placed at the preset pad positions of the microchip;

[0064] After the micro-columns and micro-chips are arranged, an organic or inorganic adhesive layer is made, and the adhesive layer is combined with the carrier substrate. The carrier substrate, the adhesive layer, the micro-chip and the micro-column layer are firmly bonded by high temperature, ultraviolet irradiation and laser irradiation process. The specific process is as follows:

[0065] First, select organic or inorganic adhesive materials. For organic adhesive materials, select epoxy resin, and for inorganic adhesive materials, select glass or ceramic materials. The selected materials must have good adhesive properties, thermal stability and chemical stability. According to the required thickness and uniformity of the adhesive layer, prepare the adhesive layer by spin coating, spray coating, dip coating, drop coating or other fine coating techniques. During the coating process, the amount of adhesive material and the coating speed must be controlled to ensure the uniformity and consistency of the adhesive layer.

[0066] After coating, the adhesive layer is cured. For organic adhesive materials, the curing is carried out by heating or UV light irradiation. The curing conditions such as temperature, time, and UV light intensity are optimized according to the characteristics of the adhesive material. After the adhesive layer is cured and forms appropriate viscosity, the microchip and microcolumn are precisely aligned and placed on the adhesive layer, and precise pick-and-place equipment is used to ensure accurate alignment.

[0067] After the microchip is placed on the adhesive layer, a preset pressure is applied to ensure good contact and adhesion between the adhesive layer and the microchip and the microcolumn, and the magnitude and duration of the preset pressure are adjusted according to the characteristics of the adhesive material and the strength of the microchip; after the pressure is applied, a post-curing process is performed to further improve the bonding strength, including a post-treatment by a thermal curing process at a high temperature, an ultraviolet light irradiation process, or a laser irradiation process;

[0068] After bonding is completed, the bonding interface is inspected to ensure that there are no bubbles, cracks or other defects, and then a bonding strength test, such as a tensile test, a shear test or a peel test, is performed to verify the reliability of the bonding layer. The specific steps for the bonding interface inspection are as follows:

[0069] Obtain the evaluation parameters of the bonding interface for comprehensive analysis, where the evaluation parameters include:

[0070] Bubbles and cracks: Check the number and size of bubbles. Ideally, there should be as few or no bubbles at the bonding interface as possible. Bubbles can become a source of stress concentration, leading to bonding failure. For cracks, evaluate their length, width, and depth. The presence of cracks may indicate stress concentration in the bonding layer or material mismatch, resulting in reduced bonding strength. Bonding layer thickness and uniformity: Measure the thickness of the bonding layer to ensure its consistency across the entire bonding area. Uneven thickness may cause local stress concentration, affecting bonding strength. Evaluate the uniformity of the bonding layer, including consistency in color, brightness, and contrast. Uneven bonding layers may indicate uneven material distribution or problems during the curing process. Surface roughness: The surface roughness measurement results should meet design specifications. Higher surface roughness may This results in a reduction in the bonding area, which in turn affects the bonding strength. Bonding strength: The data obtained through tensile testing, shear testing, or peeling testing can directly reflect the mechanical strength of the bonding layer. The test results should meet or exceed the design requirements to ensure the reliability of the bonding interface. Viscoelasticity and thermal properties: The viscoelastic properties reflect the performance of the bonding layer under dynamic loads. The bonding layer should have good damping properties to absorb and disperse vibration and shock. Thermal performance parameters, including the coefficient of thermal expansion, should match the materials of the microchip and the carrier substrate to avoid stress caused by thermal expansion mismatch. Chemical composition and structure: The chemical composition and structure of the bonding layer are confirmed through analytical techniques such as XPS or FTIR. Changes in the chemical composition may affect the chemical stability and long-term performance of the bonding layer.

[0071] Then a quantitative evaluation model is created, which weights the above parameters according to their importance in affecting the bonding quality and calculates a comprehensive score. Specifically: first determine the evaluation parameters and their weights: bubble number and size B, crack length and depth C, bonding layer thickness and uniformity D, surface roughness A, bonding strength S, thermal performance matching T and chemical composition and structure M, and assign a weight W to each parameter, which reflects the importance of the parameter in the overall bonding quality; then, for each parameter, a quantitative score is given according to the actual measurement value and standard, and the score is a ratio between 0 and 1, where 1 means perfect and 0 means completely unsatisfactory; the comprehensive score ZP is calculated by the following formula: ZP = (B*W b )+(C*W c )+(D*W d )+(A*W a )+(S*W s )+(T*W t )+(M*W m ); and comparing the calculated comprehensive score ZP with a plurality of preset comprehensive score intervals, wherein the preset plurality of comprehensive score intervals correspond to different bonding evaluation levels, thereby determining the level of bonding interface evaluation;

[0072] Then, the temporary carrier substrate and the temporary carrier film are separated to obtain a flattened microchip, and it is determined that the electrode surface and one of the surfaces of the microcolumns are in the same plane; the surfaces of the microchip and the microcolumns are then processed, and the dielectric film, rewiring layer and protective layer processes are performed to complete the integrated packaging of the microchip. Through high-temperature annealing, reflow and laser treatment processes, the pads are tightly combined with the microcolumns, and the microcolumns are confined in the adhesive layer material, thereby greatly improving the mechanical strength of the pads of the integrated packaged chip.

[0073] The preferred embodiments of the present invention disclosed above are only used to help explain the present invention. The preferred embodiments do not describe all the details in detail, nor do they limit the invention to only specific implementation methods. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for improving the strength of a pad of an integrated package chip, characterized in that: The following steps are involved: S1: First, prepare a temporary carrier substrate and a temporary carrier film, and arrange the microchip on the temporary carrier film. The specific process is as follows: S101: firstly determining the materials of the temporary carrier substrate and the temporary carrier film, then cleaning and pre-treating the temporary carrier substrate and the temporary carrier film to remove surface pollutants and perform surface modification; S102: The microchip needs to be subjected to quality inspection to ensure that the size, shape and electrical performance of the microchip meet the requirements by obtaining the quality parameters of the microchip, the quality parameters including dimensional accuracy, surface roughness, electrical characteristics and structural integrity; S103: Analyze the quality parameters of the microchip to obtain the size difference value, RMS value, special deviation value and missing value respectively. After normalization, use the sum of the size difference value and the RMS value as the radius to establish a bottom circle, then use the special deviation value as the height to establish a cone model, then use the vertex of the cone model as the center of the sphere and the missing value as the radius to establish a spherical model, calculate the volume of the cone and the sphere after fusion, and record it as the quality judgment value; The specific process of analyzing the quality parameters of the microchip to obtain the error value, RMS value, special deviation value and missing value is as follows: The dimensional accuracy is measured by measuring the length, width and thickness of the microchip through an optical microscope, a scanning electron microscope or an atomic force microscope, and calculating the difference between the measured value and the preset value to obtain the length difference, width difference and thickness difference respectively, and then summing them after normalization and recording them as the dimension difference value; Surface roughness is measured by a surface profilometer or atomic force microscope and expressed as RMS value; Electrical characteristics The resistance, capacitance, inductance, current and voltage characteristics of the microcell are evaluated by electrical testing equipment and calibrated as Z, R, G, I and Y respectively. Then the standard resistance, capacitance, inductance, current and voltage are preset and calibrated as , after normalization, enter the following formula: To obtain the special deviation value TPZ; Structural integrity: The structural integrity of the microchip is verified, and the cracks, defects and voids of the microchip are detected using scanning electron microscopy, transmission electron microscopy or X-ray computed tomography technology, and the number of cracks, crack area, defect area and void volume are counted. After normalization, the number of cracks is multiplied by the crack area, plus the preset correction coefficient, and the sum of the defect area and void volume multiplied by the preset weight factor is added to obtain the defect value; S104: comparing the calculated quality judgment value with a preset quality judgment threshold, and when the quality judgment value exceeds the preset quality judgment threshold, it is determined that the quality of the microchip does not meet the standard; S2: fine-tune the position of the microchip using the position planning rules to ensure that the position accuracy of the microchip meets the design requirements; S3: then manufacturing a metal microcolumn or a semiconductor material microcolumn with a metal plated surface, and placing the microcolumn at a preset pad position of the microchip; S4: making an organic or inorganic adhesive layer, and combining it with the supporting substrate through the adhesive layer; S5: Then check the bonding interface to ensure there are no bubbles, cracks or other defects, and then perform a bonding strength test; S6: separating the temporary carrier substrate and the temporary carrier film to obtain a planarized microchip; S7: Finally, the flattened surfaces of the microchip and microcolumn are processed, and the processes of making a dielectric film, a rewiring layer and a protective layer are carried out to complete the integrated packaging of the microchip.

2. The method for improving the strength of the integrated package chip pad according to claim 1, characterized in that: The process of the location planning rule in S2 is as follows: Plan the layout of the microchips on the carrier film according to the package design and the requirements of the final product, including the spacing between the microchips, the arrangement and the location of the pads; When planning the location of microchips, electrical performance and thermal management should be considered. The arrangement of microchips should be conducive to the optimization of electrical connections and the effective dissipation of heat. The location planning of the microchip should also take into account the mechanical strength of the overall structure, and the layout of the pads and micro-pillars needs to ensure sufficient strength; Position planning needs to take into account the requirements of subsequent process steps to ensure the smooth progress of the process; After the planning is completed, the rationality of the microchip location planning is verified through computer simulation and prototype testing.

3. The method for improving the strength of the integrated package chip pad according to claim 1, characterized in that: The size of the micro-columns produced in S3 matches the size of the designed pads, the thickness is the same as the thickness of the microchip, and the number is consistent with the number of pads.

4. The method for improving the strength of the integrated package chip pad according to claim 1, characterized in that: The specific operation steps of S4 are as follows: Firstly, an organic or inorganic bonding material is selected, the organic bonding material is epoxy resin, and the inorganic bonding material is glass or ceramic material, and the bonding material has good bonding performance, thermal stability and chemical stability; According to the required thickness and uniformity of the adhesive layer, the adhesive layer is prepared by spin coating, spray coating, dip coating and drop coating technology, and the amount of adhesive material and the coating speed are controlled during the coating process; After coating, the adhesive layer is cured. For organic adhesive materials, the curing is carried out by heating or UV irradiation. The temperature, time and UV intensity of the curing conditions are optimized according to the characteristics of the adhesive material. After the adhesive layer cures and forms the proper adhesion, the microchip and micropillars are precisely aligned and placed on the adhesive layer, using precision pick-and-place equipment to ensure accurate alignment; After the microchip is placed on the adhesive layer, a preset pressure is applied to ensure good contact and bonding between the adhesive layer and the microchip and micropillars, and the magnitude and duration of the preset pressure are adjusted according to the characteristics of the adhesive material and the strength of the microchip; After applying pressure, a post-curing process is performed to further improve the bonding strength, including heat curing at high temperature, ultraviolet light irradiation or laser irradiation process for post-treatment.

5. The method for improving the strength of the integrated package chip pad according to claim 1, characterized in that: The specific steps of inspecting the bonding interface in S5 are as follows: First, the evaluation parameters of the bonding interface are obtained for comprehensive analysis, including: bubbles and cracks, bonding layer thickness and uniformity, surface roughness, bonding strength, viscoelasticity and thermal properties, and chemical composition and structure; Then a quantitative evaluation model is created. The quantitative evaluation model weights the above parameters according to their importance in affecting the bonding quality and calculates a comprehensive score. Specifically: First, determine the evaluation parameters and their weights: bubble number and size B, crack length and depth C, bonding layer thickness and uniformity D, surface roughness A, bonding strength S, thermal performance matching T, and chemical composition and structure M, and assign a weight W to each parameter; Then, a quantitative score is assigned to each parameter based on the actual measurement value and standard. After normalization, the comprehensive score ZP is calculated using the following formula: ; The calculated comprehensive score ZP is then compared with a plurality of preset comprehensive score intervals, and the preset plurality of comprehensive score intervals are respectively set to correspond to different bonding evaluation levels, so as to determine the level of bonding interface evaluation.

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