A timing violation detection method, device and terminal device based on path display

Abstract

The present invention discloses a timing violation detection method, device and terminal equipment based on path display. The present invention first takes the timing path with the smallest timing margin value in a timing path group as the target timing path, and colors the target transmission path and the target capture path in the target timing path according to a first color and a second color respectively, and when it is determined that there is an overlapping path between the target transmission path and the target capture path, the overlapping path is colored according to a third color; and the first color, the second color and the third color are all different. The present invention can distinguish and display each path through different colors, thereby enhancing the intuitiveness of timing analysis, and by automatically calculating the filling ratio of the overlapping path, it can automatically determine whether the clock deviation is too large to generate the corresponding timing violation detection result. The present invention can realize accurate timing violation detection, so as to achieve better timing convergence effect and improve the reliability of chip design.

Description

Technical Field

[0001] The present invention relates to the technical field of timing violation detection of chips, and in particular to a timing violation detection method, device and terminal equipment based on path display. Background Art

[0002] In chip design, achieving final timing closure is a necessary step. In the process of achieving timing closure, it is necessary to use EDA tools or manually to repair the timing paths that violate the rules. There are many reasons for timing violations, including clock tree imbalance, insufficient driving capability of standard cells, too long routing distance between standard cells, mutual interference between wires, and too large total delay of data paths.

[0003] Accurately and quickly finding the cause of the timing violation in the timing path, and then performing targeted timing violation repairs, is crucial to quickly achieve timing convergence. When analyzing the timing path, EDA (Electronic Design Automation) tools are often used to generate relevant timing reports, and then timing optimization is performed based on the timing reports to achieve final timing convergence.

[0004] The timing report generally contains many timing paths, and these timing paths are divided into different timing path groups according to different clock domains and path types. When performing timing optimization, the EDA tool will optimize each timing path group, with the goal of making the timing slack of all timing paths in the timing path group positive, so that the timing of all timing paths can converge. The timing slack in the timing report is used to measure the degree of completion of the timing path. It represents the difference between the time required for the timing path to complete its operation and the given clock cycle. If the timing slack is positive, it means that the timing path has enough time margin to complete its operation. On the contrary, if the timing slack is negative, it means that the timing path cannot complete its operation within the specified clock cycle, that is, there is a timing violation. When performing timing optimization through EDA tools, it mainly makes the timing slack of the timing path group positive, so as to ensure the timing convergence of the timing path.

[0005] After the timing optimization is completed through the EDA tool, there will still be a timing path in each timing path group whose timing slack is still negative, which can be used as a critical path. Since the EDA tool cannot perform better optimization on this critical path, each timing path group cannot achieve better timing convergence effect. Moreover, after the timing optimization is performed through the EDA tool of the prior art, since the unit distribution and path routing of each sub-path in this critical timing path cannot be obtained from the timing report, the timing path cannot be observed intuitively, and a more detailed or more accurate timing violation analysis cannot be performed on the critical timing path, and the cause of the timing violation cannot be accurately found, resulting in poor timing convergence effect when verifying the chip design, thereby resulting in low reliability of the chip design. Summary of the invention

[0006] The embodiments of the present invention provide a timing violation detection method, apparatus and terminal device based on path display, which realizes more accurate timing violation detection of the target timing path (i.e., the key timing path) based on automatic path color display and color ratio calculation, so as to accurately find out the cause of the timing violation. This can effectively solve the problem in the prior art that the timing path cannot be intuitively observed, and a more detailed or more accurate timing violation analysis cannot be performed on the key timing path, and the cause of the timing violation cannot be accurately found.

[0007] An embodiment of the present invention provides a timing violation detection method based on path display, comprising:

[0008] Acquire a timing report including a plurality of timing path groups, and for each timing path group, use a timing path with the smallest timing margin value in the timing path group as a target timing path; wherein each timing path group includes a plurality of timing paths; each timing path corresponds to a timing margin value for measuring the degree of completion of the timing path; each timing path includes a launch path and a capture path;

[0009] Coloring a target emission path and a target capture path in the target timing path according to a first color and a second color respectively;

[0010] When it is determined that there is an overlapping path between the target emission path and the target capture path, the overlapping path is colored according to a third color; wherein the first color, the second color and the third color are all different;

[0011] According to the filling areas of the first color, the second color and the third color in the target timing path, the filling proportion of the third color in the total path is calculated; wherein the total path is the sum of the emission path and the capture path;

[0012] When it is determined that the filling proportion corresponding to the third color is less than the preset proportion threshold, a first timing violation detection result is generated; wherein the first timing violation detection result includes: a large clock deviation.

[0013] Preferably, each timing path also includes a data path;

[0014] Before generating timing violation detection results, it also includes:

[0015] coloring the target data path in the target timing path according to a fourth color;

[0016] The fourth color is different from the first color, the second color and the third color.

[0017] Preferably, the target transmission path, the target capture path and the target data path each include a plurality of different standard cells; each standard cell is connected via a port;

[0018] After the target data path in the target timing path is colored according to the fourth color, the following data display operation is performed for the target transmission path, the target capture path, and the target data path:

[0019] Extracting the unit data of each standard unit and extracting the interconnection data of the connection lines between the standard units; wherein the unit data includes: unit name, input port information and output port information;

[0020] The interconnection data and the cell data of each standard cell are displayed on the corresponding path.

[0021] Preferably, it also includes:

[0022] For the target transmit path, target capture path, and target data path, the following violation detection operations are performed:

[0023] Calculate the interconnection length of the connection lines between two adjacent standard cells in the path;

[0024] The lengths of each interconnection are compared with a preset length threshold, and when it is determined that at least one interconnection length is greater than the preset length threshold, a second timing violation detection result is generated; wherein the second timing violation detection result includes: the interconnection line is too long.

[0025] Preferably, after generating the second timing violation detection result, the method further includes:

[0026] Obtaining a path region where the interconnection length greater than a preset length threshold is located;

[0027] Comparing the number of standard cells in the path area with a preset cell number threshold;

[0028] When the number of standard cells in the determination path region is greater than the preset cell number threshold, an updated second timing violation detection result is generated; wherein the updated second timing violation detection result includes: the standard cell density is too large;

[0029] When the number of standard cells in the determination path area is not greater than the preset cell number threshold, an updated second timing violation detection result is generated; wherein the updated second timing violation detection result includes: the standard cells are placed too far apart.

[0030] Preferably, it also includes:

[0031] Using each standard cell in the target data path as a detection standard cell;

[0032] For each detection standard cell, extracting driving index data of the detection standard cell in the timing report for characterizing the driving capability of the standard cell; wherein the driving index data includes: voltage swing, signal transmission speed and fan-out coefficient;

[0033] When it is determined that the voltage swing, the signal transmission speed or the fan-out coefficient is less than the corresponding preset indicator threshold, a third timing violation detection result is generated;

[0034] The third timing violation detection result includes: the driving capability of the detection standard unit is too weak.

[0035] Preferably, after generating the third timing violation detection result, the method further includes:

[0036] Obtain the target cell name of the detection standard cell in the third timing violation detection result;

[0037] Generate an editing interface for changing a standard unit; wherein the editing interface includes: a plurality of standard units to be selected; each standard unit to be selected corresponds to different driving index data;

[0038] In response to a selection operation by a user in the editing interface, the standard cell corresponding to the target cell name in the target data path is then replaced with a selected standard cell corresponding to the selection operation.

[0039] Based on the above method embodiments, the present invention provides corresponding device embodiments.

[0040] An embodiment of the present invention provides a timing violation detection device based on path display, comprising: a target timing path marking module, a first coloring module, a second coloring module, a filling ratio calculation module and a timing violation detection module;

[0041] The target timing path marking module is used to obtain a timing report including a plurality of timing path groups. For each timing path group, the timing path with the smallest timing margin value in the timing path group is used as the target timing path; wherein each timing path group includes a plurality of timing paths; each timing path corresponds to a timing margin value used to measure the degree of completion of the timing path; each timing path includes a launch path and a capture path;

[0042] The first coloring module is used to color the target emission path and the target capture path in the target timing path according to a first color and a second color respectively;

[0043] The second coloring module is used to color the overlapping path according to a third color when it is determined that there is an overlapping path between the target emission path and the target capture path; wherein the first color, the second color and the third color are all different;

[0044] The filling ratio calculation module is used to calculate the filling ratio of the third color in the total path according to the filling areas of the first color, the second color and the third color in the target timing path; wherein the total path is the sum of the emission path and the capture path;

[0045] The timing violation detection module is used to generate a first timing violation detection result when it is determined that the filling proportion corresponding to the third color is less than a preset proportion threshold; wherein the first timing violation detection result includes: a large clock deviation.

[0046] Based on the above method embodiments, the present invention provides corresponding terminal device embodiments.

[0047] Another embodiment of the present invention provides a terminal device, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, and when the processor executes the computer program, a timing violation detection method based on path display described in the above-mentioned embodiment of the invention is implemented.

[0048] Based on the above method embodiments, the present invention provides corresponding storage medium item embodiments.

[0049] Another embodiment of the present invention provides a storage medium, wherein the computer-readable storage medium includes a stored computer program, wherein when the computer program is running, the device where the computer-readable storage medium is located is controlled to execute a timing violation detection method based on path display as described in the above-mentioned embodiment of the invention.

[0050] The following beneficial effects are achieved by implementing the present invention:

[0051] The embodiment of the present invention provides a timing violation detection method, apparatus and terminal device based on path display. After the EDA tool completes the timing optimization, in order to solve the problem that there is still a critical path with negative timing slack in each timing path group, which causes each timing path group to fail to perform timing convergence better, the present invention adopts the following timing violation detection scheme for each timing path group in the timing report: first, a timing path with the smallest timing margin value in a timing path group is taken as a target timing path, that is, the critical path can be extracted, so that a target launch path and a target capture path in the target timing path are colored according to a first color and a second color respectively, and when it is determined that there is an overlapping path between the target launch path and the target capture path, the overlapping path is colored according to a third color; it can be understood that the first color, the second color and the third color are all different, and each path can be displayed with different colors to distinguish the routing of the three paths, so that the designer or user can distinguish the routing of the three paths when laying out the layout. The path routing of the timing path can be intuitively observed in the local wiring stage, thereby enhancing the intuitiveness of the timing analysis and allowing designers to identify potential problem areas more quickly; further, the present invention also automatically calculates the fill ratio of the overlapping path in the total path corresponding to the transmission path and the capture path, so as to accurately determine whether the clock deviation is too large, and when it is determined that the fill ratio is less than a preset threshold, it can automatically generate a timing violation detection result including a large clock deviation analysis result. The present invention can achieve more accurate timing violation detection of the target timing path (i.e., the key timing path) based on automated path color display and color ratio calculation to accurately find the cause of the timing violation. When verifying the chip design, better timing convergence effect can be achieved, thereby improving the reliability and performance of the chip design. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 It is a flowchart of a timing violation detection method based on path display provided by an embodiment of the present invention.

[0053] Figure 2 It is a flowchart of steps for displaying a timing path in chip layout and routing provided by an embodiment of the present invention.

[0054] Figure 3 It is a coloring schematic diagram of a timing path provided by an embodiment of the present invention.

[0055] Figure 4 It is an effect diagram showing a timing path in chip layout and wiring provided by an embodiment of the present invention.

[0056] Figure 5It is a structural schematic diagram of a timing violation detection device based on path display provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0057] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0058] like Figure 1 FIG. 1 is a flow chart of a timing violation detection method based on path display provided by an embodiment of the present invention. The timing violation detection method based on path display includes:

[0059] Step S1: obtaining a timing report including a plurality of timing path groups, and for each timing path group, taking a timing path with the smallest timing margin value in the timing path group as a target timing path;

[0060] Each timing path group includes a plurality of timing paths; each timing path corresponds to a timing margin value used to measure the degree of completion of the timing path; each timing path includes a transmission path and a capture path;

[0061] Step S2: coloring the target emission path and the target capture path in the target timing path according to the first color and the second color respectively;

[0062] Step S3: when it is determined that there is an overlapping path between the target emission path and the target capture path, coloring the overlapping path according to a third color; wherein the first color, the second color and the third color are all different;

[0063] Step S4: Calculate the filling ratio of the third color in the total path according to the filling areas of the first color, the second color, and the third color in the target timing path; wherein the total path is the sum of the emission path and the capture path;

[0064] Step S5: when it is determined that the filling proportion corresponding to the third color is less than the preset proportion threshold, generating a first timing violation detection result;

[0065] Among them, the first timing violation detection result includes: the clock deviation is large.

[0066] For step S1, in a preferred embodiment, in order to solve the problem that there is still a critical path with negative timing slack in each timing path group, which causes each timing path group to fail to perform timing closure better, after the EDA tool completes the timing optimization, the present invention can adopt the following timing violation detection scheme for each timing path group in the timing report:

[0067] The timing path with the smallest timing margin value in a timing path group is marked as the target timing path. It can be understood that the present invention can extract the timing path whose timing slack is still negative and whose corresponding timing slack value is the smallest, and use it as the critical path, so that the present invention can display the actual layout and routing of the physical distribution and routing of the critical path through subsequent steps.

[0068] Schematically, after performing timing analysis, the EDA tool will generate a related timing report, which contains many specific timing paths. These timing paths are divided into different timing path groups according to different clock domains (clock do main) and path types. Each timing path has a timing slack. If the slack is positive, timing convergence has been achieved; if the slack is negative, it means that the timing violation needs to be fixed. In each path group, there is a critical path with the worst timing slack. The timing optimization process will give priority to optimizing the critical path, and timing optimization will only be performed if the slack value of the timing path is negative, and no optimization is required if the slack value is positive.

[0069] After the EDA tool timing optimization process is completed, there will still be a timing path with the worst slack (the slack value is negative at this time) in the path group, which is the final critical path. Due to various reasons, the tool cannot perform further optimization on this critical path. It is also because of the existence of this critical path that other timing paths in the path group to which it belongs whose slack is still negative cannot be further optimized by the tool. Therefore, in the timing analysis process after timing optimization, it is necessary to analyze the critical paths in each path group to find the reasons for its timing violations, so that optimization plans can be formulated for these reasons, so that other timing paths in the path group to which it belongs whose slack is still negative can achieve subsequent optimization.

[0070] There are many reasons for critical path violations, including: weak driving capability of standard cells, too long interconnects, too large clock deviation, etc. For the timing analysis of critical paths, the physical distribution and routing of standard cells in this timing path cannot be obtained from the timing report alone, so it is necessary to display it in the actual layout and routing. The timing violation detection method based on path display of the present invention can display the complete path of the extracted critical path.

[0071] For step S2, in a preferred embodiment, in order to better see the routing of different paths in the layout and wiring, the present invention can color different paths according to different colors and display them in the layout of the chip.

[0072] Schematically, a complete timing path includes a launch path, a capture path, and a data path;

[0073] The launch path refers to the path from the clock source (such as PLL, i.e. phase-locked loop) to the clock input port (CK port) of the first flip-flop (reg1), and this path describes how the clock signal reaches and triggers the action of the first register.

[0074] The capture path is the path that also starts from the clock source (PLL) but goes to the clock input port (CK port) of the second flip-flop (reg2). This path describes how the clock signal arrives and is ready to trigger the action of the second register. Similar to the launch path, the capture path also contains buffers, drivers, and interconnects on the clock tree. Since both the launch path and the capture path originate from the same clock source, there are usually overlapping parts between them, and these overlapping parts share the same clock network components.

[0075] The data path is the path that starts from the data output port (Q port) of the first flip-flop (reg1), passes through possible combinational logic and interconnection lines, and finally reaches the data input port (D port) of the second flip-flop (reg2). This data path describes how the data signal is transferred between the two registers.

[0076] When performing timing analysis, it is necessary to ensure that the clock signals on the transmission path and the capture path meet the requirements of the setup time and the hold time, and the data on the data path must reach the destination register within the correct time window. If the timing of any path does not meet the requirements, it may be necessary to optimize the design. In order to fully display the layout and wiring information of a specific timing path, it is possible to quickly and intuitively check whether there are timing violations caused by distance, connection and other problems on the timing path. The present invention can distinguish and color the target transmission path and the target capture path in the target timing path, so that the target transmission path and the target capture path can be displayed in different colors, which is convenient for chip designers to intuitively observe the routing conditions of each sub-path, and is conducive to analyzing whether there are timing violations caused by distance, connection and other problems on the timing path.

[0077] For step S3, in a preferred embodiment, the present invention can also color and render the overlapping path between the target emission path and the target capture path, so that the designer can intuitively view the direction of the overlapping path. When the present invention determines that there is an overlapping path between the target emission path and the target capture path, the overlapping path can be colored according to a third color.

[0078] Illustratively, the first color, the second color and the third color are all different.

[0079] In order to better distinguish the distribution of different paths in the timing path in chip layout and routing, the present invention also colors the target data path in the target timing path according to a fourth color. It can be understood that the fourth color is different from the first color, the second color and the third color.

[0080] like Figure 2 and Figure 3 As shown, the embodiment of the present invention can analyze a single timing report, so that the steps of displaying the timing path in chip layout and routing are as follows:

[0081] Step 1: Script 1 generates a timing report, which records a specified timing path information;

[0082] Step 2: Script 2 analyzes the report of step 1 to obtain the launch path, capture path, and data path of the timing path, and marks them as path1, path2, and path3;

[0083] Step 3: Script 3 extracts the standard cells, input and output ports, and interconnection line information between ports on path1, and colors them (i.e., the emission path) with color 1 in the chip layout and routing;

[0084] Step 4: Script 4 extracts the standard cells, input and output ports, and interconnection line information between ports on path2, and colors them (i.e., captured paths) with color 2 in chip layout and routing;

[0085] Step 5: Script 5 identifies the part that is repeatedly colored in steps 3 and 4, and recolors the part with color 3;

[0086] Step 6: Script 6 extracts the standard cells, input and output ports, and interconnection line information between ports on path3, and colors them (i.e., data paths) with color 4 in the chip layout and routing.

[0087] Step 7: Use different colors to distinguish different paths in the timing path and the distribution of standard cells and interconnect lines in the path during chip layout and routing.

[0088] As can be seen from the above, the target transmission path, the target capture path and the target data path in the target timing path all include a number of different standard cells, and each standard cell is connected through a port;

[0089] Then, after the target data path in the target timing path is colored according to the fourth color, the embodiment of the present invention performs the following data display operations on the target emission path, the target capture path, and the target data path:

[0090] First, extract the unit data of each standard unit, and extract the interconnection data of the connection lines between the standard units; wherein the unit data includes: unit name, input port information and output port information;

[0091] The interconnection data and the cell data of each standard cell are displayed on the corresponding path.

[0092] Then the processing steps for each partial path (target transmission path, target capture path or target data path) of the embodiment of the present invention may be:

[0093] Use the script to obtain the standard cell information on the path, including the name of the standard cell and the port name of the standard cell that the timing path passes through;

[0094] Get the name of the interconnection line from the output port of one standard cell to the input port of the next standard cell through the script;

[0095] The obtained standard cells, ports and interconnects are found in the chip layout and wiring through the script, and are painted with agreed colors (such as the first color, the second color or the fourth color) and displayed.

[0096] As for the overlapping part of the launch path and the capture path, after the script detects this part, it is painted with another agreed color to show that it is the overlapping part.

[0097] like Figure 4 As shown, the path where launch and capture overlap is called a common path. The present invention colors different paths differently, so that the launch path, capture path, common path and data path of the timing path can be quickly distinguished in chip layout and wiring, and the distribution of each standard unit and interconnection line on the timing path can also be intuitively seen.

[0098] Therefore, the present invention enables designers to quickly obtain and observe timing path information through automated script processing, avoiding the cumbersome process of manual search and annotation, which greatly improves design efficiency and shortens product development cycle. Different paths are presented in different colors, so that designers can intuitively distinguish different parts in the timing path. For example, the launch path, capture path, data path and their overlapping parts are clearly displayed in the chip layout wiring diagram, which greatly simplifies the analysis and understanding process of complex timing paths. When there is a problem with the timing analysis, such as the setup time or hold time does not meet the requirements, the designer can quickly locate the path part where the problem is, that is, the paths of different colors can make the problem area more prominent in the layout wiring diagram, thereby accelerating the process of troubleshooting and repairing.

[0099] For step S4, in a preferred embodiment, after coloring different paths with different colors, in order to automatically detect the specific cause of the timing violation, the present invention can calculate the filling ratio of the third color in the total path based on the filling areas of the first color, the second color and the third color in the target timing path; wherein the total path is the sum of the transmission path and the capture path.

[0100] Specifically, the method of the present invention can distinguish the actual layout and routing of the launch path and the capture path by color. Clock skew will affect the timing, and a large clock skew often causes the timing to fail to converge. It can be understood that in the timing analysis of the chip, the launch path and the capture path are two key concepts. The launch path refers to the path from sending the clock signal to the data being driven out, and the capture path is the path from receiving the clock signal to the data being captured. The clock skew of these two paths is crucial to ensure the correct transmission of data.

[0101] When there is partial overlap between the launch path and the capture path, this overlapping path is called a common path. The existence of a common path means that during the data transmission and reception process, a part of the path is shared, so the clock skew on this part of the path is the same.

[0102] If the proportion of the common path in the launch and capture paths is larger, it means that the two paths are synchronized in more parts, that is, the clock skew they experience is similar or the same. Since clock skew is one of the important factors leading to timing violations, a larger proportion of the common path usually means a smaller clock skew.

[0103] When a timing violation occurs, whether the clock deviation is too large is usually an important factor to pay attention to. In the layout and routing, different colors are used to distinguish the launch path, capture path, and common path, and by calculating the fill ratio of the common path in the total length of the launch path and capture path, it is possible to quickly and accurately determine whether the clock deviation is too large.

[0104] For step S5, in a preferred embodiment, the fill ratio obtained in step 4 is compared with a preset threshold value. If the fill ratio is greater than the threshold value, it can be considered that the ratio of the common path is large enough and the clock deviation is relatively small. Indicatively, this threshold value is usually an empirical value based on design specifications and timing requirements.

[0105] If it is determined that the filling ratio corresponding to the third color is less than the preset ratio threshold, a first timing violation detection result is generated; wherein the first timing violation detection result is: the clock deviation is large.

[0106] The timing path display method provided by the present invention not only allows the designer to intuitively see the layout and routing conditions of the launch path, capture path and common path, but also can automatically determine whether the clock deviation is too large based on the calculation of the color fill ratio. The present invention can accurately locate the cause of the timing violation, help to discover and solve potential timing problems in the early stage of chip design, and improve the reliability and performance of the design.

[0107] In a preferred embodiment, if the first timing violation detection result is generated, and it is indicated that the clock skew is too large to cause the timing violation, a clock skew constraint can be further set, and the clock number synthesis stage can be returned to repair the violation. Indicatively, the clock skew (useful skew) can also be set to repair some specific timing violations.

[0108] In a preferred embodiment, for the target transmission path, the target capture path, and the target data path, the embodiment of the present invention may also perform the following violation detection operations:

[0109] Calculate the interconnection length of connection lines between two adjacent standard cells in one of the target transmission path, the target capture path and the target data path;

[0110] Each interconnection length is compared with a preset length threshold, and when it is determined that at least one interconnection length is greater than the preset length threshold, a second timing violation detection result is generated; wherein the second timing violation detection result includes: the interconnection line is too long.

[0111] It is understandable that there are two reasons for the excessive length of interconnection lines. One is that the standard cells are placed too far apart, and the other is that the standard cells are close to each other, but the density of standard cells in the area is too high. There are too many interconnection lines between cells, and there is insufficient routing space. The interconnection lines between cells cannot go directly from A to B, but need to bypass the densely populated area, resulting in excessively long routing lines.

[0112] After generating the second timing violation detection result, the embodiment of the present invention further includes:

[0113] Obtaining a path region where the interconnection length greater than a preset length threshold is located;

[0114] Comparing the number of standard cells in the path area with a preset cell number threshold;

[0115] When the number of standard cells in the determination path region is greater than the preset cell number threshold, an updated second timing violation detection result is generated; wherein the updated second timing violation detection result includes: the standard cell density is too large;

[0116] When the number of standard cells in the determination path area is not greater than the preset cell number threshold, an updated second timing violation detection result is generated; wherein the updated second timing violation detection result includes: the standard cells are placed too far apart.

[0117] For the judgment of these two second timing violation detection results, in addition to being able to view the actual routing of the interconnection lines through the color-differentiated display of the present invention to obtain the results, the present invention can also automatically calculate the length of each interconnection line, so that when it is determined that at least one interconnection length is greater than a preset length threshold, a second timing violation detection result is generated, and the second timing violation detection result is updated based on the comparison of the number of standard cells in the path area with the preset cell number threshold. This detection result can clearly point out the problem of the interconnection line being too long, so that the designer can quickly locate the cause of the violation and repair the timing violation in time. For example, the designer can adjust the position of the standard cell, add a buffer, or re-perform layout and wiring operations according to the detection results to improve the timing performance.

[0118] Illustratively, if it is found that the updated second timing violation detection result is that the standard unit is placed too far away, resulting in too long connections, distance constraints can be set between the units, that is, returning to the automated placement and routing stage, setting corresponding distance constraints to repair it.

[0119] If the updated second timing violation detection result is found to be that the standard cell density is too high, the maximum density constraint can be set in the layout and routing stage to avoid too high density. If only a few distances are too large or the density is too high, the designer can also manually add buffers between standard cells or move the position of the standard cell where the detour occurs.

[0120] In a preferred embodiment, the timing path display method provided by the present invention also uses different colors to display the layout and routing of the data path. Generally speaking, in the clock tree synthesis stage, the distance between the standard cells in the launch path and the capture path, and the driving capability, will be strictly controlled. The data path is formed before the clock tree synthesis, and often there will be a situation where the distance is too large and the driving capability is too weak. When the driving capability is too weak, it is necessary to replace the standard cell or add a buffer cell (buffer) to solve it. Regardless of the method used, it is necessary to find a standard cell with weak driving capability.

[0121] Then the embodiment of the present invention also includes:

[0122] Using each standard cell in the target data path as a detection standard cell;

[0123] For each detection standard cell, extracting driving index data of the detection standard cell in the timing report for characterizing the driving capability of the standard cell; wherein the driving index data includes: voltage swing, signal transmission speed and fan-out coefficient;

[0124] When it is determined that the voltage swing, signal transmission speed or fan-out coefficient is less than the corresponding preset indicator threshold, a third timing violation detection result is generated; wherein the third timing violation detection result includes: the driving capability of the detection standard unit is too weak.

[0125] Obtain the target cell name of the detection standard cell in the third timing violation detection result;

[0126] Generate an editing interface for changing a standard unit; wherein the editing interface includes: a plurality of standard units to be selected; each standard unit to be selected corresponds to different driving index data;

[0127] In response to a selection operation by a user in the editing interface, the standard cell corresponding to the target cell name in the target data path is then replaced with a selected standard cell corresponding to the selection operation.

[0128] Illustratively, the driving capability of the standard cell will be reflected in the timing report. By obtaining the name of the corresponding standard cell in the timing report, the standard cell can be found in the layout and routing interface, and an editing interface corresponding to the replacement of the standard cell can be generated, so that the user can select a standard cell with appropriate driving capability in the editing interface. After responding to the user's selection operation in the editing interface, the standard cell corresponding to the target cell name in the target data path can be replaced with the selected standard cell corresponding to the selection operation, so as to achieve the replacement of the standard cell with weak driving capability.

[0129] The present invention displays the layout and routing of the data path through different colors, so that engineers can intuitively understand the distribution of the data path in the chip layout and routing. At the same time, the embodiment of the present invention also provides a complete solution to the problem of too weak driving capability that may occur in the data path.

[0130] First, the embodiment of the present invention takes each standard cell in the target data path as a detection object, and extracts driving index data of these standard cells in the timing report for characterizing the driving capability. These driving index data include key parameters such as voltage swing, signal transmission speed and fan-out coefficient, which can directly reflect the driving capability of the standard cell.

[0131] Then, the embodiment of the present invention compares these driving index data with the preset index threshold. If any one of the voltage swing, signal transmission speed or fan-out coefficient of a standard cell is less than the corresponding preset threshold, then the driving capability of the standard cell is considered to be too weak, and a third timing violation detection result is generated. The present invention can quickly identify the standard cell with insufficient driving capability, providing a clear target for subsequent optimization operations.

[0132] Furthermore, the target cell name of the standard cell detected in the third timing violation detection result is obtained, and an editing interface for changing the standard cell is generated. This editing interface contains several standard cells to be selected, each of which has different driving index data. This allows engineers or users to intuitively compare the driving capabilities of different standard cells in the editing interface and select the most suitable replacement cell.

[0133] Finally, when the designer user completes the selection operation in the editing interface, the embodiment of the present invention will automatically replace the standard cells with too weak driving capability in the target data path with the selected standard cells with stronger driving capability, thereby realizing automatic repair of timing violations and greatly improving the repair efficiency and accuracy.

[0134] In summary, the embodiment of the present invention can quickly find out the cause of the timing violation through the above scheme, such as large clock deviation, too long interconnection line or too weak driving ability of the detection standard unit, so that the corresponding repair can be carried out in time according to the cause of the timing violation. This not only improves the efficiency and quality of chip design, but also reduces the workload of engineers. Thus, the present invention can effectively detect violations in the target transmission path, target capture path and target data path, providing strong support for the timing optimization of chip design, so that chip designers can more conveniently perform timing analysis and optimization work.

[0135] like Figure 5 As shown, based on the above-mentioned various embodiments of the timing violation detection method based on path display, the present invention provides a corresponding device embodiment;

[0136] An embodiment of the present invention provides a timing violation detection device based on path display, comprising: a target timing path marking module, a first coloring module, a second coloring module, a filling ratio calculation module and a timing violation detection module;

[0137] The target timing path marking module is used to obtain a timing report including a plurality of timing path groups. For each timing path group, the timing path with the smallest timing margin value in the timing path group is used as the target timing path; wherein each timing path group includes a plurality of timing paths; each timing path corresponds to a timing margin value used to measure the degree of completion of the timing path; each timing path includes a launch path and a capture path;

[0138] The first coloring module is used to color the target emission path and the target capture path in the target timing path according to a first color and a second color respectively;

[0139] The second coloring module is used to color the overlapping path according to a third color when it is determined that there is an overlapping path between the target emission path and the target capture path; wherein the first color, the second color and the third color are all different;

[0140] The filling ratio calculation module is used to calculate the filling ratio of the third color in the total path according to the filling areas of the first color, the second color and the third color in the target timing path; wherein the total path is the sum of the emission path and the capture path;

[0141] The timing violation detection module is used to generate a first timing violation detection result when it is determined that the filling proportion corresponding to the third color is less than a preset proportion threshold; wherein the first timing violation detection result includes: a large clock deviation.

[0142] It should be noted that the device embodiments described above are merely schematic, wherein the modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, and may be located in one place or distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. In addition, in the accompanying drawings of the device embodiments provided by the present invention, the connection relationship between the modules indicates that there is a communication connection between them, which may be specifically implemented as one or more communication buses or signal lines. Those of ordinary skill in the art can understand and implement it without paying creative labor.

[0143] Those skilled in the art can clearly understand that, for the sake of convenience and simplicity, the specific working process of the device described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0144] Based on the above-mentioned various embodiments of the timing violation detection method based on path display, the present invention provides corresponding terminal equipment item embodiments.

[0145] An embodiment of the present invention provides a terminal device, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein when the processor executes the computer program, it implements a timing violation detection method based on path display as described in any method embodiment of the present invention.

[0146] The terminal device may be a computing terminal device such as a desktop computer, a notebook, a palm computer, a cloud server, etc. The terminal device may include, but is not limited to, a processor and a memory.

[0147] The processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc. The processor is the control center of the terminal device, and uses various interfaces and lines to connect various parts of the entire terminal device.

[0148] The memory can be used to store the computer program, and the processor realizes various functions of the terminal device by running or executing the computer program stored in the memory and calling the data stored in the memory. The memory can mainly include a program storage area and a data storage area, wherein the program storage area can store an operating system, at least one application required for a function, etc.; the data storage area can store data created according to the use of the mobile phone, etc. In addition, the memory can include a high-speed random access memory, and can also include a non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), at least one disk storage device, a flash memory device or other volatile solid-state storage device.

[0149] Based on the above-mentioned various embodiments of the timing violation detection method based on path display, the present invention provides a corresponding storage medium item embodiment.

[0150] An embodiment of the present invention provides a storage medium, which includes a stored computer program, wherein when the computer program is running, the device where the computer-readable storage medium is located is controlled to execute a timing violation detection method based on path display as described in any method embodiment of the present invention.

[0151] The storage medium is a computer-readable storage medium, and the computer program is stored in the computer-readable storage medium. When the computer program is executed by the processor, the steps of each method embodiment described above can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form, etc. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, USB flash drive, mobile hard disk, disk, optical disk, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electric carrier signal, telecommunication signal and software distribution medium, etc. It should be noted that the content contained in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electric carrier signals and telecommunication signals.

[0152] The above is a preferred embodiment of the present invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A timing violation detection method based on path display, characterized in that: include: Acquire a timing report including a plurality of timing path groups, and for each timing path group, use a timing path with the smallest timing margin value in the timing path group as a target timing path; wherein each timing path group includes a plurality of timing paths; each timing path corresponds to a timing margin value for measuring the degree of completion of the timing path; each timing path includes a launch path and a capture path; Coloring a target emission path and a target capture path in the target timing path according to a first color and a second color respectively; When it is determined that there is an overlapping path between the target emission path and the target capture path, the overlapping path is colored according to a third color; wherein the first color, the second color and the third color are all different; According to the filling areas of the first color, the second color and the third color in the target timing path, the filling proportion of the third color in the total path is calculated; wherein the total path is the sum of the emission path and the capture path; When it is determined that the filling proportion corresponding to the third color is less than the preset proportion threshold, a first timing violation detection result is generated; wherein the first timing violation detection result includes: a large clock deviation.

2. A timing violation detection method based on path display as claimed in claim 1, characterized in that: Each timing path also includes a data path; Before generating timing violation detection results, it also includes: coloring the target data path in the target timing path according to a fourth color; The fourth color is different from the first color, the second color and the third color.

3. A timing violation detection method based on path display as claimed in claim 2, characterized in that: The target transmission path, the target capture path and the target data path all include a plurality of different standard cells; each standard cell is connected via a port; After the target data path in the target timing path is colored according to the fourth color, the following data display operation is performed for the target transmission path, the target capture path, and the target data path: Extracting the unit data of each standard unit and extracting the interconnection data of the connection lines between the standard units; wherein the unit data includes: unit name, input port information and output port information; The interconnection data and the cell data of each standard cell are displayed on the corresponding path.

4. A timing violation detection method based on path display as claimed in claim 3, characterized in that: Also includes: For the target transmit path, target capture path, and target data path, the following violation detection operations are performed: Calculate the interconnection length of the connection lines between two adjacent standard cells in the path; Comparing each interconnect length with a preset length threshold, and generating a second timing violation detection result when it is determined that at least one interconnect length is greater than the preset length threshold; Wherein, the second timing violation detection result includes: the interconnection line is too long.

5. A timing violation detection method based on path display as claimed in claim 4, characterized in that: After generating the second timing violation detection result, further comprising: Obtaining a path region where the interconnection length greater than a preset length threshold is located; Comparing the number of standard cells in the path area with a preset cell number threshold; When the number of standard cells in the determination path region is greater than the preset cell number threshold, an updated second timing violation detection result is generated; wherein the updated second timing violation detection result includes: the standard cell density is too large; When the number of standard cells in the determination path area is not greater than the preset cell number threshold, an updated second timing violation detection result is generated; wherein the updated second timing violation detection result includes: the standard cells are placed too far apart.

6. A timing violation detection method based on path display as claimed in claim 5, characterized in that: Also includes: Using each standard cell in the target data path as a detection standard cell; For each detection standard cell, extracting driving index data of the detection standard cell in the timing report for characterizing the driving capability of the standard cell; wherein the driving index data includes: voltage swing, signal transmission speed and fan-out coefficient; When it is determined that the voltage swing, the signal transmission speed or the fan-out coefficient is less than the corresponding preset indicator threshold, a third timing violation detection result is generated; The third timing violation detection result includes: the driving capability of the detection standard unit is too weak.

7. A timing violation detection method based on path display as claimed in claim 6, characterized in that: After generating the third timing violation detection result, it also includes: Obtain the target cell name of the detection standard cell in the third timing violation detection result; Generate an editing interface for changing a standard unit; wherein the editing interface includes: a plurality of standard units to be selected; each standard unit to be selected corresponds to different driving index data; In response to a selection operation by a user in the editing interface, the standard cell corresponding to the target cell name in the target data path is then replaced with a selected standard cell corresponding to the selection operation.

8. A timing violation detection device based on path display, characterized in that: include: A target timing path marking module, a first coloring module, a second coloring module, a fill ratio calculation module, and a timing violation detection module; The target timing path marking module is used to obtain a timing report including a plurality of timing path groups. For each timing path group, the timing path with the smallest timing margin value in the timing path group is used as the target timing path; wherein each timing path group includes a plurality of timing paths; each timing path corresponds to a timing margin value used to measure the degree of completion of the timing path; each timing path includes a launch path and a capture path; The first coloring module is used to color the target emission path and the target capture path in the target timing path according to a first color and a second color respectively; The second coloring module is used to color the overlapping path according to a third color when it is determined that there is an overlapping path between the target emission path and the target capture path; wherein the first color, the second color and the third color are all different; The filling ratio calculation module is used to calculate the filling ratio of the third color in the total path according to the filling areas of the first color, the second color and the third color in the target timing path; wherein the total path is the sum of the emission path and the capture path; The timing violation detection module is used to generate a first timing violation detection result when it is determined that the filling proportion corresponding to the third color is less than a preset proportion threshold; wherein the first timing violation detection result includes: a large clock deviation.

9. A terminal device, characterized in that: The method comprises a processor, a memory and a computer program stored in the memory and configured to be executed by the processor, wherein when the processor executes the computer program, a timing violation detection method based on path display as claimed in any one of claims 1 to 7 is implemented.

10. A storage medium, characterized in that: The storage medium includes a stored computer program, wherein when the computer program is executed, the device where the storage medium is located is controlled to execute a timing violation detection method based on path display as claimed in any one of claims 1 to 7.

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