Method and system for batch testing of chips, electronic equipment, and storage medium

Abstract

The present application discloses a method for batch testing of chips and its system, electronic device, and storage medium; it relates to the field of chip testing; the method includes: generating a test configuration file in response to a test configuration instruction, and sending the test configuration file to a test device; in response to a test start instruction, according to the test configuration file, performing parallel test processing on batches of chips to be tested at the same time; monitoring the parallel test processing, and obtaining the test status information of each chip in real time; classifying and summarizing multiple test status information to obtain second test status summary information, and uploading the second test status summary information to a host computer; sorting and statistically processing the second test status summary information to obtain the chip batch test situation, and displaying the chip batch test situation; when the parallel test is completed, generating a log file recording the chip batch test situation. It can improve the test efficiency and automation of batch test chips.

Description

Technical Field

[0001] The present application relates to the field of chip testing, and in particular to a method for batch testing of chips and its system, electronic equipment, and storage medium. Background Art

[0002] Chip testing is an important stage in chip manufacturing to ensure chip quality. With the development of ultra-large-scale integrated circuits, ultra-large chips require more complex and rigorous testing processes due to their design complexity in order to produce high-quality chips to meet customer needs.

[0003] With the widespread application of chips, the market demand for chips is also increasing. At present, in the chip testing process, a one-to-one method is usually adopted, that is, one PC corresponds to one test board, and the next chip can be replaced and processed after the test is completed. Although this ensures the stability of the test, the PC (host computer program) can only process the chips tested on the corresponding test board at the same time. When testing batches of chips, it takes a lot of time to organize and analyze the test log results of multiple test boards; in this way, the test efficiency is low and the test automation is low, which makes it difficult to meet the large number of chip testing needs. Summary of the invention

[0004] The purpose of this application is to solve at least one of the technical problems existing in the prior art.

[0005] The embodiments of the present application provide a method for batch testing of chips and its system, electronic device, and storage medium, which can improve the testing efficiency and automation level of batch testing of chips.

[0006] In a first aspect, an embodiment of the present application provides a method for batch testing of chips, which is applied to a system for batch testing of chips, the system comprising: a host computer, a test device, a mother-child test board, and a transfer controller; wherein the test device comprises a plurality of test ports, each of which is connected to a mother-child test board, the mother-child test board comprises a plurality of sub-boards, each of which is connected to a plurality of chips to be tested and the transfer controller; the test device is respectively connected to the host computer and the transfer controller in communication;

[0007] The method comprises:

[0008] The host computer generates a test configuration file in response to the input test configuration instruction, and sends the test configuration file to the test device;

[0009] The test device responds to the test start instruction and performs parallel test processing on the batch of chips to be tested according to the received test configuration file;

[0010] The transfer controller monitors the parallel test process and obtains the test status information of each chip in real time;

[0011] The transfer controller and the test device classify and summarize the plurality of test status information to obtain second test status summary information, and upload the second test status summary information to the host computer;

[0012] The host computer performs sorting and statistical processing according to the received second test status summary information to obtain chip batch test status, and displays the chip batch test status;

[0013] When the parallel test of the batch of chips to be tested is completed, the host computer generates a log file recording the batch test status of the chips.

[0014] In the second aspect, an embodiment of the present application provides a system for batch testing of chips, comprising: a host computer, a test device, a mother-and-child test board, and a transit controller; wherein the test device comprises a plurality of test ports, each of the test ports being connected to a mother-and-child test board, the mother-and-child test board comprising a plurality of sub-boards, each of which being connected to a plurality of chips to be tested and the transit controller; the test device is respectively communicated with the host computer and the transit controller; the system for batch testing of chips is used to execute the method for batch testing of chips as described in any one of the embodiments of the first aspect.

[0015] In a third aspect, an embodiment of the present application provides an electronic device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the method for batch testing of chips as described in any one of the embodiments of the first aspect is implemented.

[0016] In a fourth aspect, an embodiment of the present application provides a storage medium, which is a computer-readable storage medium, and the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the method for batch testing of chips as described in any one of the embodiments of the first aspect.

[0017] The embodiment of the present application includes: when a chip batch test is performed using a system for chip batch testing, first, the host computer generates a test configuration file in response to the input test configuration instruction, and sends the test configuration file to the test equipment; secondly, the test equipment responds to the test start instruction, and performs parallel test processing on the batch of chips to be tested according to the received test configuration file; thereby improving the chip test efficiency; at the same time, the transit controller monitors the parallel test processing and obtains the test status information of each chip in real time; the transit controller and the test equipment classify and summarize the multiple test status information to obtain second test status summary information, and upload the second test status summary information to the host computer; then, the host computer performs sorting and statistical processing based on the received second test status summary information to obtain the chip batch test status, and displays the chip batch test status; finally, when the parallel test of the batch of chips to be tested is completed, the host computer generates a log file recording the chip batch test status; the batch test status is automatically counted, thereby improving the automation level of batch testing chips. That is to say, the embodiment of the present application can perform parallel testing on batch chips and automatically generate chip batch testing conditions, thereby improving the testing efficiency and automation level of batch testing chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a structural schematic diagram of a system for batch testing of chips provided by an embodiment of the present application;

[0019] Figure 2 is a structural schematic diagram of a mother-child test board connected to a test device provided by another embodiment of the present application;

[0020] Figure 3 It is a flowchart of a method for batch testing of chips provided by an embodiment of the present application;

[0021] Figure 4 is a schematic diagram of a test configuration file generated according to an embodiment of the present application;

[0022] Figure 5 This is a schematic diagram of a software interface for triggering a screening machine provided by an embodiment of the present application;

[0023] Figure 6 It is a working schematic diagram of a test device provided by an embodiment of the present application performing parallel test processing on batches of chips to be tested according to a test configuration file;

[0024] Figure 7 This is a schematic diagram of classification and aggregation processing provided by an embodiment of the present application;

[0025] Figure 8 is a schematic diagram of the conversion relationship between test states provided by an embodiment of the present application;

[0026] Fig. 9 It is a schematic diagram of the hardware structure of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0027] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments.

[0028] It should be noted that although a logical order is shown in the flowchart in the description of the present application, in some cases, the steps shown or described may be performed in an order different from that in the flowchart. In the description of the present application, a number of means one or more, and a plurality of means two or more. The description of "first" and "second" is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0030] The present application provides a method for batch testing of chips, a system for batch testing of chips, an electronic device, and a computer-readable storage medium; the method includes: generating a test configuration file in response to a test configuration instruction, and sending the test configuration file to a test device; in response to a test start instruction, according to the test configuration file, performing parallel test processing on batches of chips to be tested at the same time; monitoring the parallel test processing, and obtaining the test status information of each chip in real time; classifying and summarizing multiple test status information to obtain second test status summary information, and uploading the second test status summary information to a host computer; sorting and statistically processing the second test status summary information to obtain the chip batch test situation, and displaying the chip batch test situation; when the parallel test is completed, generating a log file recording the chip batch test situation. It can improve the test efficiency and automation of batch test chips.

[0031] The embodiments of the present application are further described below in conjunction with the accompanying drawings.

[0032] On the one hand, if Figure 1 and Figure 2As shown, the system for batch testing of chips includes: a host computer, a test device, a mother-child test board, and a relay controller; wherein the test device includes multiple test ports, each test port is connected to a mother-child test board, the mother-child test board includes multiple sub-boards, each sub-board is connected to multiple chips to be tested and a relay controller; the test device is communicated with the host computer and the relay controller respectively.

[0033] The host computer is used to generate a test configuration file in response to the input test configuration instruction, and send the test configuration file to the test device.

[0034] The test equipment is used to: respond to the test start instruction, and according to the received test configuration file, perform parallel test processing on batches of chips to be tested at the same time, thereby improving the chip test efficiency.

[0035] The transfer controller is used to monitor the parallel test processing and obtain the test status information of each chip in real time; the transfer controller and the test equipment are also used to classify and summarize multiple test status information to obtain second test status summary information, and upload the second test status summary information to the host computer.

[0036] The host computer is used to: perform sorting and statistical processing according to the received second test status summary information to obtain the chip batch test status and display the chip batch test status; when the parallel test of the batch of chips to be tested is completed, the host computer generates a log file recording the chip batch test status; automatically performs statistics on the batch test status, thereby improving the degree of automation of batch testing chips.

[0037] In some embodiments, Figure 2 As shown, two chips to be tested are placed on the daughter board. When the specifications of the daughter board are expanded, three, four, or more chips can also be placed. This application does not make specific restrictions on this.

[0038] According to the system for batch testing of chips provided in the embodiment of the present application, when using the system for batch testing of chips to perform batch testing of chips, the host computer, testing equipment, and transfer controller cooperate with each other to perform parallel testing on batch chips and automatically generate chip batch testing status, thereby improving the testing efficiency and automation level of batch testing chips.

[0039] like Figure 1As shown, the system for batch testing of chips also includes: a manipulator; the manipulator is connected to the host computer in communication, and the manipulator is set next to the test equipment, and is used for loading and unloading under the control of the host computer; that is, the chip to be tested is placed on the sub-board of the mother-child test board. A test start button is set on the mother-child test board. When the host computer indicates to use the fixture trigger mode, after the loading is completed, the manipulator can trigger the test start button on the mother-child test board, thereby sending a third start trigger instruction to the test equipment, so that the test equipment responds to the third start trigger instruction and starts testing all the chips to be tested on the mother-child test board that issued the third start trigger instruction.

[0040] In one embodiment, the host computer and the manipulator, and the host computer and the testing equipment communicate based on the TCP / IP protocol.

[0041] It can be understood that in some embodiments, the host computer controls the robot to automatically pick up and load materials according to the input chip order information, and places the materials (i.e., the chips to be tested) on the correct base to ensure that the test of the chips to be tested can be carried out normally; after the test is completed, the host computer controls the robot to unload materials according to BIN, and places the tested chips into the unloading area.

[0042] Those skilled in the art will appreciate that the system structure shown in the figure does not constitute a limitation on the embodiments of the present application, and may include more or fewer components than shown in the figure, or a combination of certain components, or a different arrangement of components.

[0043] The system embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0044] Those skilled in the art will appreciate that the system architecture and application scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of the system architecture and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are equally applicable to similar technical problems.

[0045] Based on the above system structure, various embodiments of the method for batch testing of chips of the present application are proposed below.

[0046] On the other hand, Figure 3As shown, an embodiment of the present application provides a method for batch testing of chips, which is applied to a system for batch testing of chips, the system comprising: a host computer, a test device, a mother-child test board, and a transfer controller; wherein the test device comprises a plurality of test ports, each test port is connected to a mother-child test board, the mother-child test board comprises a plurality of sub-boards, each sub-board is connected to a plurality of chips to be tested, and a transfer controller; the test device is respectively connected to the host computer and the transfer controller in communication. The method for batch testing of chips includes but is not limited to steps S110 to S160.

[0047] Step S110: the host computer generates a test configuration file in response to the input test configuration instruction, and sends the test configuration file to the test device.

[0048] Step S120: the test equipment responds to the test start instruction and performs parallel test processing on batches of chips to be tested according to the received test configuration files.

[0049] Step S130: The transfer controller monitors the parallel test process and obtains the test status information of each chip in real time.

[0050] Step S140: the transfer controller and the test device classify and summarize the multiple test status information to obtain second test status summary information, and upload the second test status summary information to the host computer.

[0051] Step S150: the host computer performs sorting and statistical processing according to the received second test status summary information to obtain chip batch test status and displays the chip batch test status.

[0052] Step S160: When the parallel test of the batch of chips to be tested is completed, the host computer generates a log file recording the batch test status of the chips.

[0053] It is understandable that the test configuration file includes at least one test plan; different test plans include different test tasks, and test tasks include test cases. Different types of chips require different test cases. That is, different test plans have different target test objects (chips to be tested). This is conducive to batch testing of different types of chips in parallel, thereby improving test efficiency and universality.

[0054] Through step S110 to step S160, when the chip batch test is performed using the system for chip batch test, first, the host computer generates a test configuration file in response to the input test configuration instruction, and sends the test configuration file to the test equipment; secondly, the test equipment responds to the test start instruction, and according to the received test configuration file, performs parallel test processing on the batch of chips to be tested at the same time; thereby improving the chip test efficiency; at the same time, the transit controller monitors the parallel test processing and obtains the test status information of each chip in real time; the transit controller and the test equipment classify and summarize the multiple test status information to obtain the second test status summary information, and upload the second test status summary information to the host computer; then, the host computer performs sorting and statistical processing according to the received second test status summary information to obtain the chip batch test status, and displays the chip batch test status; finally, when the parallel test of the batch of chips to be tested is completed, the host computer generates a log file recording the chip batch test status; the batch test status is automatically counted, thereby improving the automation level of batch testing chips. That is to say, the embodiment of the present application can perform parallel testing on batch chips and automatically generate chip batch testing conditions, thereby improving the testing efficiency and automation level of batch testing chips.

[0055] According to some embodiments of the present application, the test configuration instruction includes: a function package selection instruction, a test plan creation instruction, and a configuration file creation instruction; further illustrating step S110, wherein the host computer generates a test configuration file in response to the input test configuration instruction, including but not limited to the following steps:

[0056] In response to a function package selection instruction, multiple target function packages are determined from a candidate function package list; in response to a test plan creation instruction, a test task and a test plan including the test task are created according to the multiple target function packages; in response to a configuration file creation instruction, a test configuration file is generated according to at least one test plan.

[0057] In this way, the user manually determines multiple target function packages in the candidate function package list according to the type of the chip to be tested through the display operation interface provided by the host computer, thereby dynamically importing the target function package. The host computer creates user-defined test tasks based on multiple target function packages, and then generates a test plan based on the configured candidate test port range, the type information of the target test object, and the generated test task. In this way, multiple test plans for different types of chips to be tested can be obtained, and finally a test configuration file is generated based on multiple test plans. This is to facilitate the subsequent batch testing of different types of chips in parallel, thereby improving test efficiency and universality.

[0058] Take an example, combined with Figure 4 , which explains how to test the configuration file.

[0059] It is determined that the candidate function list includes multiple candidate function packages: function package 1, function package 2, function package 3, ..., function package N.

[0060] When the chip type of the chip to be tested connected to the preset candidate test port range (ports 1-4) is A, that is, the type information of the target test object is type A, function package 1, function package 3 and function package 5 are dynamically imported from the candidate function list to obtain test task A. Test task A is used to test the chip to be tested of type A. According to the selected test port range (ports 1-4), the type information of the target test object (chip type A), and test task A, a test plan A1 is generated.

[0061] When the chip type of the chip to be tested connected to the preset candidate test port range (port 5-21) is B, that is, the type information of the target test object is type B, function package 1, function package 3, function package 7, function package 9, and function package 19 are dynamically imported from the candidate function list to obtain test task B. Test task B is used to test the chip to be tested of type B. According to the selected test port range (port 5-21), the type information of the target test object (chip type B), and test task B, test plan B is generated.

[0062] When the chip type of the chip to be tested connected to the preset candidate test port range (ports 22-30) is A, that is, the type information of the target test object is type A, function package 1, function package 3 and function package 5 are dynamically imported from the candidate function list to obtain test task A. Test task A is used to test the chip to be tested of type A. According to the selected test port range (ports 22-30), the type information of the target test object (chip type A), and test task A, a test plan A1 is generated.

[0063] It can be understood that since test plan A1 and test plan A2 include the same test task A, test plan A1 and test plan A2 are the same test plan, and only the indicated post-candidate test port ranges are different. However, since test plan A1 and test plan B include the same test task A, they are different test plans.

[0064] In one embodiment, during the process of generating the test plan A2, the test task A in the previously generated test plan A1 can be directly called without the need to re-import the function package to generate the test task A, so as to improve the efficiency of generating the test configuration file.

[0065] It is understandable that for ease of description, Figure 3A and B are used to represent chip models, and other identifiers can be used to represent chip types in practice. In addition, it should be noted that this application does not impose specific restrictions on the number and type of test plans included in a test configuration file, and the number and type of function packages included in the test task.

[0066] According to some embodiments of the present application, in step S120, that is, before the test device responds to the test start instruction, the method also includes but is not limited to the following steps: the host computer receives the trigger mode selection instruction input by the click operation; in response to the trigger mode selection instruction, a target trigger mode is determined from multiple candidate trigger modes; the target trigger mode is used to indicate the triggering method of the test start instruction. In this way, multi-mode triggering is achieved, and the flexibility of batch testing is improved. And when a trigger mode fails, other trigger modes can be used; to a certain extent, the smooth progress of batch testing is guaranteed.

[0067] It should be noted that the candidate trigger modes include: host computer trigger mode, fixture trigger mode, and screening machine trigger mode. The test start instruction includes: first start trigger instruction, second start trigger instruction, and third start trigger instruction.

[0068] In one embodiment, when the determined target trigger mode is the host computer trigger mode, the host computer sends a first start trigger instruction to the test device in response to the first test start control being triggered, so that the test device starts testing all connected chips to be tested.

[0069] In one embodiment, when the determined target trigger mode is the screening machine trigger mode, the host computer sends a second start trigger instruction to the test device in response to the second test start control being triggered, so that the test device determines at least one mother-child test board according to the second start trigger instruction, and starts testing all the chips to be tested on the mother-child test board. Specifically, Figure 5 As shown in the figure, one column represents a mother-child test board connected to one port, and "#1" represents the serial number of the mother-child test board. The mother-child test board includes multiple chips, and the chip serial numbers are represented by Arabic numerals such as 1, 2, 3, and 4. For each mother-child test board in the software interface, that is, each column of chips to be tested, set the start control and the end control; the start control is used to pause and start the test of the chip to be tested in the column, and the end control is used to end the test of the chip to be tested in the column.

[0070] In one embodiment, when the determined target trigger mode is the fixture trigger mode, when the test start button on the mother-child test board is triggered, the mother-child test board sends a third start trigger instruction to the test equipment, so that the test equipment responds to the third start trigger instruction and starts testing all the chips to be tested on the mother-child test board that issues the third start trigger instruction.

[0071] According to some embodiments of the present application, step S120 is further described, and step S120 includes but is not limited to steps S121 to S126.

[0072] Step S121: The test device obtains at least one test plan from the test configuration file; wherein different test plans have different target test objects;

[0073] Step S122: Obtain the corresponding candidate test port range, test task, and type information of the target test object from the test plan;

[0074] Step S123: performing chip type matching verification processing according to the candidate test port range and the type information of the target test object to obtain a verification result, and determining the target test port range from the candidate test port range according to the verification result;

[0075] Step S124: determining a plurality of target test ports according to the target test port range; wherein the models of the chips to be tested connected to the plurality of target test ports within a target test port range are the same;

[0076] Step S125: when the target test port is in an idle state, issuing corresponding test tasks to the chips under test connected to the multiple target test ports;

[0077] Step S126: in response to the test start instruction, the states of the plurality of target test ports are changed from the idle state to the test state, and the plurality of connected chips to be tested are controlled to execute the test task.

[0078] It can be understood that the idle state means that the test port is available for testing and is not currently being tested. The test state means that the test port is occupied and a test task is being performed.

[0079] It is understandable that the test configuration file may include one or more test plans, and the number of test plans obtained by the test device from the test configuration file is related to the selection of the configuration stage. Therefore, this application does not impose specific restrictions on the number of test plans obtained from the test configuration file.

[0080] Through steps S121 to S126, when the test equipment receives the test configuration file, it obtains at least one test plan from the test configuration file, obtains the candidate test port range, test task, and type information of the target test object in each test plan; matches and confirms the type of the chip to be tested that is connected to the candidate test port range, obtains the verification result, and re-determines the target test port range; to ensure that the type of the test task issued matches the type of the chip to be tested, and to ensure the normal progress of the chip test. Finally, multiple connected chips to be tested are tested in parallel.

[0081] It is understandable that when testing batches of chips, individual chips of other types (such as type B) may be mixed in the type A chip pile to be tested. When a manipulator is used for fully automated material removal, the manipulator can only ensure that the chip is placed in the correct position, but cannot directly determine that other types of chips are mixed in; when loading materials manually, loading errors may also occur. If one or more chips of type C are accidentally placed on the mother-child test board connected to port 1 in the candidate test port range (ports 1-4) that should be connected to the type A chip to be tested, if test task A is directly issued to the type C chip through port 1, the test may go wrong and report erroneous test status information, which ultimately affects the test statistics of this batch of type A chips to be tested. Therefore, the embodiment of the present application improves the reliability of chip batch testing by setting a mechanism for matching and verifying chip types.

[0082] According to some embodiments of the present application, step S123 is further described, and step S123 includes but is not limited to steps S1231 to S1236.

[0083] Step S1231: The test device obtains the type information of the target test object from the test plan.

[0084] Step S1232: Send a device serial number acquisition instruction to the chip under test that is connected to a port within the candidate test port range.

[0085] Step S1233: receiving the device serial number returned by the chip under test in response to the device serial number acquisition instruction.

[0086] Step S1234: Determine the type of chip to be tested according to the device serial number.

[0087] Step S1235: When it is determined that the type of the chip to be tested matches the type information of the target test object, the candidate test port range is determined to be the target test port range.

[0088] Step S1236: When it is determined that the type of the chip under test does not match the type information of the target test object, determine the non-target test port to which the chip under test of the mismatched type is connected; update the candidate test port range according to the non-target test port to obtain the target test port range.

[0089] It is understandable that the device serial number of each chip to be tested is unique, but the type of the chip to be tested can also be learned from it.

[0090] Through steps S1231 to S1236, after the test equipment obtains the type information of the target test object from the test plan, it broadcasts the device serial number acquisition instruction to the chip to be tested that is connected to the port within the candidate test port range; after receiving the device serial number returned by the chip to be tested, the type of the connected chip to be tested is determined from it, and the consistency is matched with the type information of the target test object. If all the connected chips to be tested match the type information of the target test object, the candidate test port range is determined to be the target test port range; if some of the connected chips to be tested do not match the type information of the target test object, the identifier of the non-target test port to which the chip to be tested with the mismatched type is connected is determined, and the non-target test port is removed from the candidate test port range to obtain an updated target test port range. In this way, the embodiment of the present application improves the accuracy and reliability of chip batch testing by setting a mechanism for matching and verifying chip types and a mechanism for determining the target test port range.

[0091] Take an example, combined with Figure 4 and Figure 6 , further illustrating that the test equipment performs parallel testing on batches of chips to be tested according to the test configuration file.

[0092] First, when the test device receives the test configuration file, Figure 4 The test configuration file shown obtains the test plan A1, obtains the candidate test port range (test ports 1-4), the test task A, and the type information of the target test object (chip type A) in the test plan A1.

[0093] Secondly, the test device broadcasts a device serial number acquisition instruction to the chips on the parent-child test board connected to test ports 1-4 according to the candidate test port range, and obtains the device serial numbers of all chips to be tested and determines the types of all chips to be tested.

[0094] Then, a consistency match is performed with the type information of the target test object.

[0095] Next, if it is determined that all connected chips to be tested match the type information of the target test object and are all type A, the candidate test port range (test ports 1-4) is determined as the target test port range (test ports 1-4).

[0096] In addition, if it is determined that the type information of the partially connected chip under test does not match the type information of the target test object, such as Figure 6 As shown, chip B is mixed into the mother-child test board connected to test port 3, so test port 3 is determined to be a non-target test port, and test port 3 is eliminated from the candidate test port range, and the target test port range is obtained as: target test ports 1-2, and test port 4.

[0097] Finally, the test task is issued to the target test port range (target test ports 1-2 and test port 4) to perform parallel testing on batches of chips to be tested.

[0098] In some embodiments, the test device may report non-target test ports to a host computer to prompt management personnel to check and replace other types of chips mixed in to ensure normal operation.

[0099] According to some embodiments of the present application, step S140 is further described, and step S140 includes but is not limited to steps S141 to S143.

[0100] Step S141: within a preset first cycle, the transfer controller performs a first classification and aggregation process on the plurality of test status information acquired and cached according to the type of the chip under test, to obtain classified first test status aggregation information;

[0101] Step S142: the transfer controller forwards the first test status summary information to the test device and deletes the cached test status information;

[0102] Step S143: within the preset second cycle, the test equipment performs a second classification and aggregation process on the first test status summary information uploaded by multiple transfer controllers according to the type of the chip under test, obtains the classified second test status summary information, and uploads the second test status summary information to the host computer.

[0103] It is understandable that when batches of chips are tested in parallel, a test status information will be generated for each chip. If the test equipment collects, temporarily stores, and forwards each test status information in real time, it will involve a large amount of transmission data, which will require high performance of the test equipment. It is also easy to cause congestion, packet loss, etc., which is not conducive to data management and can easily reduce the efficiency of batch testing. Therefore, execute steps S141 to S143, set up multiple transfer control devices, perform a first classification and summary process within a preset first cycle, and then forward it to the test equipment, which will perform a second classification and summary process, and upload the second test status summary information to the host computer, so that the host computer can analyze and process it to obtain the chip batch test status.

[0104] Take an example, combined with Figure 7 , further explaining the specific process of classification and aggregation processing.

[0105] In the first cycle, the transit controller 1 receives and caches multiple test status information from the mother-child test board #2, the mother-child test board #3, and the mother-child test board #4 at the same time in an unordered manner. When the mother-child test board #2, the mother-child test board #3, and the mother-child test board #4 all test chip A, the first test status summary information obtained by classification and aggregation only includes the test status information of chip A, as shown in FIG. Figure 7 shown.

[0106] Similarly, in the first cycle, the transit controller 2 obtains and caches multiple test status information from the mother-child test board #5, the mother-child test board #6, and the mother-child test board #7, and receives and caches multiple test status information in an unordered manner. When the mother-child test board #5, the mother-child test board #6, and the mother-child test board #7 test chip A, chip B, and chip C respectively, the first test status summary information obtained by classification and aggregation includes the test status information of chip A, chip B, and chip C, as shown in FIG. Figure 7 shown.

[0107] The transfer controller 1 and the transfer controller 2 upload their respective first test status summary information to the test device. The test device classifies and summarizes the first test status summary information according to the principle of merging the same type to obtain the second test status summary information. The second test status summary information includes the test status information of chip A, chip B, and chip C. Figure 7 shown.

[0108] The test device reports the second test status summary information to the host computer so that the host computer can perform analysis and processing.

[0109] It is understandable that the first period and the second period can be set according to actual conditions, and this application does not impose any specific limitation on this.

[0110] According to some embodiments of the present application, step S150 is further described, and step S150 includes but is not limited to steps S151 to S155.

[0111] Step S151: The host computer obtains the test status information of each tested chip of the same type from the second test status summary information each time it receives a second test status summary information; wherein the test status information includes: a test port unique identifier, a mother-child test board serial number, a chip serial number, a test status field, and a timestamp; wherein the timestamp is used to indicate the time when the test status information is generated;

[0112] Step S152: performing a first sorting process on the test status information in the second test status summary information according to the sorting rule from small to large, the mother-child test board serial number, and the chip serial number to obtain sorted third test status summary information;

[0113] Step S153: acquiring previously recorded parent-child test board sequencing information from the previously acquired first test state record table;

[0114] Step S154: performing a second sorting process according to the sorting rule from small to large, according to the sorting information of the parent-child test boards and the sorted third test status summary information, and updating the first test status record table to obtain a second test status record table;

[0115] Step S155: After the reordering is completed, statistical processing is performed according to the second test status record table to obtain chip batch test status.

[0116] It should be noted that the test status fields and their meanings are shown in Table 1.

[0117] Table 1

[0118] Test Status Field meaning UnActive Inactive Idle idle Y good N bad Fail fail Stop stop Busy_Voltage Indicates that the voltage setting has timed out Busy_Config Indicates that the timing parameter configuration has timed out Busy_Open Indicates that the opening timeout Busy_Init Indicates initialization timeout Busy_Mrr Indicates that the MR value acquisition timed out. Busy_Function Indicates that the functional test has timed out Busy_Current Indicates that the power consumption test has timed out. Busy_System Indicates that the system boot timed out Busy_Close Indicates shutdown timeout

[0119] It can be understood that the statistical processing includes: counting the total number of chip types in each state, counting the yield of a certain type of chip, etc. According to the test status field, the chip status (good, bad, timeout) is divided, and the conversion relationship between the test status is as follows: Figure 8 shown.

[0120] Through steps S151 to S155, the second test status summary information can be sorted to obtain an ordered second test status record table for easy viewing and statistics, thereby improving the efficiency of subsequent statistical processing and helping to improve the overall batch test efficiency.

[0121] An example is given to further illustrate the sorting process.

[0122] When the host computer receives a Figure 7 The second test status summary information shown first obtains the test status information of each chip to be tested of type A, type B, and type C respectively.

[0123] The test status information of each chip to be tested of type A is first sorted from small to large according to the serial number of the parent-child test board, and then sorted according to the chip serial number from small to large; at the same time, the test status information of each chip to be tested of type B and the test status information of each chip to be tested of type C are sorted; thus, the sorted third test status summary information is obtained.

[0124] Since the test status information of each chip to be tested of type A has been sorted, it is only necessary to compare the sub-parent test board serial number with the sub-parent test board sorting information of the first test status record table previously recorded. Similarly, the same process is applied to types B and C. In the second test status record table, the sub-parent test board serial number is sorted from small to large, and under each sub-parent test board serial number, the chip serial number is sorted from small to large.

[0125] In one embodiment, the upper function in the present application can select the factory mode and the non-factory mode in response to the input mode selection instruction. The factory mode refers to fully automated processing, and the non-factory mode refers to semi-automated processing.

[0126] It should be noted that for the sake of ease of description, a relatively small number of application scenarios are selected for illustration in the specific embodiments of the present application. Based on the same method, the embodiments of the present application can be applied to more complex application scenarios, which will not be described in detail here.

[0127] Thirdly, refer to Fig. 9 The electronic device 900 includes: a memory 920, a processor 910, and a computer program stored in the memory 920 and executable on the processor. When the processor 910 executes the computer program, the method for batch testing of chips according to the first aspect is implemented.

[0128] The processor 910 and the memory 920 may be connected via a bus or in other ways.

[0129] The processor 910 can be implemented by a general-purpose central processing unit, a microprocessor, an application-specific integrated circuit, or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application.

[0130] The memory 920, as a non-transient computer-readable storage medium, can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory 920 may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0131] The non-transient software program and instructions required to implement the method for batch testing of chips in the above embodiment are stored in the memory. When executed by the processor, the method for batch testing of chips in the above embodiment is executed, for example, the above described method is executed. Figure 3 The method steps shown in .

[0132] The device embodiments or system embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0133] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, which stores computer-executable instructions, and the computer-executable instructions are executed by a processor or a controller, for example, by a processor in the above-mentioned device embodiment, so that the above-mentioned processor can execute the method for batch testing of chips in the above-mentioned embodiment, for example, execute the above-mentioned Figure 3 The method steps shown in .

[0134] It will be appreciated by those skilled in the art that all or some of the steps and systems in the disclosed method above may be implemented as software, firmware, hardware and appropriate combinations thereof. Some physical components or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor or a microprocessor, or may be implemented as hardware, or may be implemented as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or a non-transitory medium) and a communication medium (or a temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that may be used to store desired information and may be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0135] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the above-mentioned implementation mode. Technical personnel familiar with the field can also make various equivalent deformations or substitutions without violating the spirit of the present application. These equivalent deformations or substitutions are all included in the scope defined by the present application.

Claims

1. A method for batch testing of chips, characterized in that: A system for batch testing of chips, the system comprising: a host computer, a test device, a mother-child test board, and a transfer controller; wherein the test device comprises a plurality of test ports, each of which is connected to a mother-child test board, the mother-child test board comprises a plurality of sub-boards, each of which is connected to a plurality of chips to be tested; the transfer controller is connected to a preset number of the mother-child test boards; the test device is respectively connected to the host computer and the transfer controller in communication; The method comprises: The host computer generates a test configuration file in response to the input test configuration instruction, and sends the test configuration file to the test device; The test device responds to the test start instruction and performs parallel test processing on the batch of chips to be tested according to the received test configuration file; The transfer controller monitors the parallel test process and obtains the test status information of each chip in real time; The transfer controller and the test device classify and summarize the plurality of test status information to obtain second test status summary information, and upload the second test status summary information to the host computer; The host computer performs sorting and statistical processing according to the received second test status summary information to obtain chip batch test status, and displays the chip batch test status; When the parallel test of the batch of chips to be tested is completed, the host computer generates a log file recording the batch test status of the chips; The test device responds to the test start instruction and performs parallel test processing on the batch of chips to be tested according to the received test configuration file, including: The test device obtains at least one test plan from the test configuration file; wherein different test plans have different target test objects; From the test plan, obtain the corresponding candidate test port range, test task, and type information of the target test object; Perform chip type matching verification processing according to the candidate test port range and the type information of the target test object to obtain a verification result, and determine the target test port range from the candidate test port range according to the verification result; Determine a plurality of target test ports according to the target test port range; wherein the chips to be tested connected to the plurality of target test ports within a target test port range are of the same model; When the target test port is in an idle state, issuing the corresponding test task to the chips to be tested connected to the multiple target test ports; In response to a test start instruction, the states of the plurality of target test ports are changed from the idle state to the test state, and the plurality of the connected chips to be tested are controlled to execute the test task.

2. The method for batch testing of chips according to claim 1, characterized in that: The chip type matching verification process is performed according to the candidate test port range and the type information of the target test object to obtain a verification result, and according to the verification result, a target test port range is determined from the candidate test port range, including: The test device obtains type information of the target test object from the test plan; Sending a device serial number acquisition instruction to the chip under test connected to a port within the candidate test port range; Receiving a device serial number returned by the chip under test in response to the device serial number acquisition instruction; Determine the type of chip to be tested according to the device serial number; When it is determined that the type of the chip to be tested matches the type information of the target test object, determining the candidate test port range as the target test port range; When it is determined that the type of the chip under test does not match the type information of the target test object, a non-target test port to which the chip under test of the mismatched type is connected is determined; and the candidate test port range is updated according to the non-target test port to obtain the target test port range.

3. The method for batch testing of chips according to claim 1, characterized in that: The transfer controller and the test device classify and summarize the plurality of test status information to obtain second test status summary information, and upload the second test status summary information to the host computer, including: In a preset first cycle, the transfer controller performs first classification and aggregation processing on the plurality of test status information acquired and cached according to the type of the chip under test, to obtain classified first test status aggregation information; The transfer controller forwards the first test status summary information to the test device and deletes the cached test status information; Within the preset second cycle, the testing device performs a second classification and aggregation process on the first test status summary information uploaded by multiple relay controllers according to the type of the chip under test, obtains the classified second test status summary information, and uploads the second test status summary information to the host computer.

4. The method for batch testing of chips according to claim 3, characterized in that: The host computer performs sorting and statistical processing according to the received second test status summary information to obtain chip batch test status, including: Each time the host computer receives the second test status summary information, it obtains the test status information of each tested chip of the same type from the second test status summary information; wherein the test status information includes: a test port unique identifier, a mother-child test board serial number, a chip serial number, a test status field, and a timestamp; wherein the timestamp is used to indicate the time when the test status information is generated; Performing a first sorting process on the test status information in the second test status summary information according to a small-to-large sorting rule, the mother-child test board serial number, and the chip serial number to obtain sorted third test status summary information; From the first test state record table previously recorded, obtain the previously recorded parent-child test board sorting information; According to the sorting rule from small to large, a second sorting process is performed according to the parent-child test board sorting information and the sorted third test status summary information, and the first test status record table is updated to obtain a second test status record table; After the reordering is completed, statistical processing is performed according to the second test status record table to obtain the chip batch test status.

5. The method for batch testing of chips according to claim 1, characterized in that: Before the test device responds to the test start instruction, the method further includes: The host computer receives a trigger mode selection instruction input by a click operation; In response to the trigger mode selection instruction, a target trigger mode is determined from a plurality of candidate trigger modes; the target trigger mode is used to indicate a triggering method of the test start instruction.

6. The method for batch testing of chips according to claim 1, characterized in that: The test configuration instructions include: function package selection instructions, test plan creation instructions, and configuration file creation instructions; the host computer generates a test configuration file in response to the input test configuration instructions, including: In response to the function package selection instruction, determining a plurality of target function packages from the candidate function package list; In response to the test plan creation instruction, create a test task and a test plan including the test task according to the multiple target function packages; In response to a configuration file creation instruction, the test configuration file is generated according to at least one of the test plans.

7. A system for batch testing of chips, characterized in that: include: A host computer, a test device, a mother-child test board, and a transit controller; wherein the test device comprises a plurality of test ports, each of the test ports being connected to a mother-child test board, the mother-child test board comprising a plurality of sub-boards, each of which being connected to a plurality of chips to be tested and the transit controller; the test device is respectively communicatively connected to the host computer and the transit controller; the system for batch testing of chips is used to execute the method for batch testing of chips as described in any one of claims 1 to 6.

8. An electronic device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method for batch testing of chips as claimed in any one of claims 1 to 6 when executing the computer program.

9. A storage medium, characterized in that: The storage medium is a computer-readable storage medium, and the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the method for batch testing of chips as claimed in any one of claims 1 to 6.

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