Thermal field calculation method, device and computer equipment for three-dimensional integrated circuit

Abstract

The present application discloses a thermal field calculation method, device and computer equipment for a three-dimensional integrated circuit. The method comprises the following steps: obtaining a three-dimensional spatial topological structure and material characteristics by reading a circuit device model and a circuit information structure corresponding to the three-dimensional integrated circuit; layering the circuit device model according to the three-dimensional spatial topological structure and the material characteristics, obtaining layer distribution information and device distribution information corresponding to the circuit device model, wherein the layer distribution information is used to divide the circuit device model into a plurality of layers; obtaining circuit parameters corresponding to each component layer in the plurality of layers according to the circuit information structure, and defining the circuit parameters corresponding to each component layer in a preset simulation environment; the circuit parameters at least include one or more of a heat source network, a power consumption parameter and a device temperature; meshing the metal region and the non-metal region in the layer layer by layer according to the material characteristics and the device distribution information; performing finite element analysis on the circuit device model, and outputting a temperature distribution diagram and a temperature value matrix data structure.

Description

Technical Field

[0001] The present invention belongs to the technical field of finite element analysis, and in particular relates to a thermal field calculation method, device and computer equipment for a three-dimensional integrated circuit. Background Art

[0002] 3D stacking packaging technology stacks multiple chips vertically together through silicon via technology to achieve higher integration. However, this also makes heat dissipation more difficult, and thermal management has become one of the main core issues in the advanced packaging industry.

[0003] In order to solve the heat dissipation problem of three-dimensional integrated circuits, researchers around the world have proposed many thermal management solutions, such as thermal conductive TSV (Through-Silicon Via) technology, liquid circulation system, heat sink and air cooling fin technology, embedded microchannel, spray cooling, or the use of new materials such as graphene and nanotubes with good thermal conductivity. However, no matter which thermal management solution is used, it needs to be based on thermal analysis. The existing three-dimensional integrated circuit thermal analysis mainly relies on finite element simulation software such as COMSOL and ANSYS. If the grid encryption or adaptive mesh method (AMR) is simply used, the simulation of large-scale integrated circuits may cause acute problems such as excessive memory usage or long simulation time. Therefore, a method for efficiently extracting thermal resistance networks in three-dimensional integrated circuit thermal simulation is studied, which eliminates the grid structure division during finite element simulation solution, poor density control due to cross-scale, and inaccurate calculation accuracy. At the same time, it eliminates the simulation performance problems caused by large-scale grid encryption. Summary of the invention

[0004] The embodiments of the present application provide a thermal field calculation method, device and computer equipment for a three-dimensional integrated circuit, which can solve the problems of grid structure subdivision during traditional finite element simulation, poor density control due to cross-scale, and inaccurate calculation accuracy. At the same time, the provided method eliminates the simulation performance problems caused by large-scale grid encryption.

[0005] In a first aspect, an embodiment of the present application provides a thermal field calculation method for a three-dimensional integrated circuit, comprising:

[0006] Obtaining a circuit device model and a circuit information structure corresponding to the three-dimensional integrated circuit to be calculated;

[0007] Reading the circuit device model to obtain the three-dimensional spatial topological structure corresponding to the three-dimensional integrated circuit, and reading the circuit information structure to obtain the material properties corresponding to the three-dimensional spatial topological structure;

[0008] The circuit device model is layered according to the three-dimensional spatial topological structure and material properties, and layer distribution information corresponding to the circuit device model and device distribution information corresponding to the circuit device model are obtained; the layer distribution information is used to divide the circuit device model into multiple layers;

[0009] Obtaining circuit parameters corresponding to each component layer in the multiple layers according to the circuit information structure, and defining the circuit parameters corresponding to each component layer in a preset simulation environment; the circuit parameters include at least one or more of a heat source network, a power consumption parameter, and a device temperature;

[0010] According to the material characteristics and device distribution information, meshing is performed layer by layer in multiple layers for metal and non-metal regions in each layer;

[0011] Finite element analysis is performed on multiple circuit device model element layers after meshing to output a temperature distribution diagram and a temperature value matrix data structure corresponding to the thermal field of the three-dimensional integrated circuit.

[0012] In a second aspect, the present application also provides a thermal field calculation device, comprising:

[0013] A structure acquisition module, which acquires a circuit device model and a circuit information structure corresponding to the three-dimensional integrated circuit to be calculated;

[0014] a structure reading module, which reads the circuit device model to obtain a three-dimensional spatial topological structure corresponding to the three-dimensional integrated circuit, and reads the circuit information structure to obtain material properties corresponding to the three-dimensional spatial topological structure;

[0015] A model layering module, which layers the circuit device model according to the three-dimensional spatial topological structure and material properties, and obtains layer distribution information and device distribution information corresponding to the circuit device model; the layer distribution information is used to divide the circuit device model into multiple layers;

[0016] A parameter definition module, which obtains circuit parameters corresponding to each component layer in the plurality of layers according to the circuit information structure, and defines the circuit parameters corresponding to each component layer in a preset simulation environment; the circuit parameters include at least one or more of a heat source network, a power consumption parameter, and a device temperature;

[0017] A mesh division module, which divides the metal area and the non-metal area in each layer into meshes layer by layer in the plurality of layers according to the material properties and the device distribution information;

[0018] The simulation calculation module performs finite element analysis on the meshed circuit device model to output a temperature distribution diagram and a temperature value matrix data structure corresponding to the thermal field of the three-dimensional integrated circuit.

[0019] In a third aspect, the present application further provides a computer device, comprising a processor and a memory, wherein the memory is used to store a computer program, and when the computer program is executed by the processor, the thermal field calculation method of the three-dimensional integrated circuit as described in the first aspect is implemented.

[0020] In a fourth aspect, the present application further provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, the thermal field calculation method of a three-dimensional integrated circuit as described in the first aspect is implemented. Compared with the prior art, the present application has at least the following beneficial effects:

[0021] 1. Improve the accuracy of thermal resistance extraction: By combining multiple methods such as experimental measurement and numerical simulation, the limitations of a single method are overcome and the accuracy and precision of thermal resistance extraction are improved. For the same example, when the simulation resource processing is better than COMSOL and ANSYS, the accuracy error is within 3%.

[0022] 2. Optimize heat dissipation design: During the modeling process, this device supports the following heat dissipation design models for three-dimensional integrated circuits: thermal conductive TSV technology model, liquid circulation system model, heat sink and air cooling fin technology model, embedded microchannel model, and spray cooling heat dissipation model. It brings visual editing and numerical distribution of models to thermal management and heat dissipation optimization design, helping to optimize heat dissipation solutions and improve the performance and stability of electronic equipment and integrated circuits.

[0023] 3. Reduce testing costs and time: Through numerical simulation and other methods, the complexity and time-consuming nature of experimental measurements can be reduced, testing costs and time can be reduced, and R&D efficiency can be improved. By supporting the merging and separation of various integrated circuits, and supporting simulation, modification, and re-simulation of components and materials of various circuits, the flexibility of simulation is greatly improved and costs and time are reduced.

[0024] 4. Solve the thermal distribution problem of complex three-dimensional integrated circuits: Through the thermal resistance calculation method model to simplify the grid and locally encrypt the grid, the accuracy and reliability of the finite element calculation method are improved, and the calculation problem of thermal distribution in complex three-dimensional integrated circuits is solved. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic flow chart of a thermal field calculation method for a three-dimensional integrated circuit shown in an embodiment of the present application;

[0026] Figure 2 A schematic structural diagram of a circuit device model corresponding to a three-dimensional integrated circuit shown in an embodiment of the present application;

[0027] Figure 3 A schematic diagram of a heat group network of a three-dimensional stacked chip equivalent circuit shown in an embodiment of the present application;

[0028] Figure 4 A schematic diagram of a series region equivalent circuit heat group network shown in an embodiment of the present application;

[0029] Figure 5 A schematic diagram of a parallel area equivalent circuit thermal group network shown in an embodiment of the present application;

[0030] Figure 6 This is a schematic diagram of the structure of a thermal field calculation device shown in an embodiment of the present application;

[0031] Figure 7 A schematic diagram of the structure of a computer device shown in an embodiment of the present application. DETAILED DESCRIPTION

[0032] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0033] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0034] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0035] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0036] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0037] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0038] The technical solution of the embodiment of the present application is introduced below.

[0039] 3D stacking packaging technology stacks multiple chips vertically together through silicon via technology to achieve higher integration. However, this also makes heat dissipation more difficult, and thermal management has become one of the main core issues in the advanced packaging industry.

[0040] In order to solve the heat dissipation problem of three-dimensional integrated circuits, researchers around the world have proposed many thermal management solutions, such as thermal conductive TSV technology, liquid circulation system, heat sink and air cooling fin technology, embedded microchannel, spray cooling, or the use of new materials such as graphene and nanotubes with good thermal conductivity. However, no matter which thermal management solution is used, it needs to be based on thermal analysis. The existing three-dimensional integrated circuit thermal analysis mainly relies on finite element simulation software, such as COMSOL and ANSYS. If the grid encryption or adaptive mesh method (AMR) is simply used, the simulation of large-scale integrated circuits may cause acute problems such as excessive memory usage or long simulation time. Therefore, a method for efficiently extracting thermal resistance networks in three-dimensional integrated circuit thermal simulation is studied, which eliminates the grid structure division during finite element simulation solution, poor density control due to cross-scale, and inaccurate calculation accuracy. At the same time, it eliminates the simulation performance problems caused by large-scale grid encryption.

[0041] To solve the above problems, please refer to Figure 1 , Figure 1 The following is a flow chart of a thermal field calculation method for a three-dimensional integrated circuit provided in an embodiment of the present application. The thermal field calculation method for a three-dimensional integrated circuit provided in an embodiment of the present application can be applied to computer devices, including but not limited to smart phones, laptops, tablet computers, desktop computers, physical servers, and cloud servers. Figure 1 As shown, the thermal field calculation method of the three-dimensional integrated circuit of this embodiment includes steps S101 to S106, which are described in detail as follows:

[0042] Step S101, obtaining a circuit device model and a circuit information structure corresponding to a three-dimensional integrated circuit to be calculated.

[0043] Specifically, the method provided in this application can realize thermal analysis of a three-dimensional integrated circuit of any structure, and firstly, it is necessary to obtain Figure 2 The circuit device model corresponding to the three-dimensional integrated circuit to be analyzed is shown in FIG. Figure 3 The equivalent circuit diagram shown is used as the circuit information structure. Then, the model structure of the three-dimensional circuit structure to be analyzed and the corresponding circuit information can be confirmed by performing a merging operation in the vertical direction.

[0044] It should be noted that if Figure 2 The three-dimensional circuit structure provided is a three-layer structure. The embodiment of the present application can analyze a three-dimensional circuit structure with any number of layers, and the embodiment of the present application does not limit the number of layers of the analyzed three-dimensional circuit model.

[0045] Step S102 , reading the circuit device model to obtain a three-dimensional spatial topological structure corresponding to the three-dimensional integrated circuit, and reading the circuit information structure to obtain material properties corresponding to the three-dimensional spatial topological structure.

[0046] Specifically, after obtaining the circuit device model corresponding to the three-dimensional integrated circuit, it can be Figure 2 The model shown in FIG. 1 determines the three-dimensional spatial topological structure corresponding to the three-dimensional integrated circuit to be analyzed, and according to Figure 3 The equivalent circuit diagram shown as a circuit information structure can obtain the corresponding material properties of each part in the three-dimensional topological structure in the vertical direction, such as wires, thermal resistors and other devices and their corresponding material types, circuit characteristics and other parameters.

[0047] In some embodiments, the layering also includes a dielectric layer and a wiring layer; the reading of the circuit information structure to obtain the material properties corresponding to the three-dimensional space topological structure includes: parsing the circuit information structure to obtain the material properties corresponding to each structural unit in the three-dimensional space topological structure in the vertical direction, so as to determine the layer distribution information and device distribution information corresponding to the three-dimensional space topological structure in the vertical direction according to the material properties; wherein the layer distribution information is used to divide the circuit device model into a component layer, a dielectric layer and a wiring layer.

[0048] The circuit information structure can be used to determine the material properties of each structural unit in the vertical direction in the three-dimensional topological space. For the parts that cannot be analyzed, the present application can also define the parts as conductive materials, such as copper, to ensure that subsequent analysis of the model can be run accurately.

[0049] Step S103, layering the circuit device model according to the three-dimensional spatial topological structure and material properties, obtaining layer distribution information corresponding to the circuit device model and device distribution information corresponding to the circuit device model; the layer distribution information is used to divide the circuit device model into multiple layers.

[0050] Specifically, after obtaining the three-dimensional spatial topological structure and material properties corresponding to the three-dimensional integrated circuit to be analyzed in the vertical direction, the present application analyzes the three-dimensional integrated circuit based on the three-dimensional spatial topological structure and material properties corresponding to the three-dimensional integrated circuit. Figure 2 The circuit device model shown is layered to obtain the layer distribution information and device distribution information corresponding to the circuit device model. The layer distribution information can be used to determine how many layers the structure of the circuit distribution model includes, and the device distribution information can be used to determine the device type corresponding to each layer. Then, the subsequent finite element analysis of the re-layered circuit device model can reduce the complexity and time consumption of experimental measurement. At the same time, the corresponding position of each circuit device in the model can also be confirmed based on the device distribution information.

[0051] In some embodiments, the layering of the circuit device model according to the three-dimensional space topological structure and material properties includes: obtaining electrical connection information corresponding to each of the structural units according to the three-dimensional space topological structure; completing the layering of the circuit device model according to the electrical connection information and material properties corresponding to each of the structural units; wherein the electrical connection information and material properties corresponding to the structural units in each of the component layers are the same.

[0052] This application has two major principles for layering: the first principle is to try not to change the electrical connection information of the original circuit, and the second principle is to try to make the characteristics of each stacked material consistent. This can ensure the accuracy of the layering and effectively reduce the calculation time in the subsequent simulation calculation process.

[0053] Step S104, obtaining circuit parameters corresponding to each component layer in multiple layers according to the circuit information structure, and defining the circuit parameters corresponding to each component layer in a preset simulation environment; the circuit parameters include at least one or more of a heat source network, power consumption parameters, and device temperature.

[0054] Specifically, the circuit parameters corresponding to each component layer (such as the resistance value of the thermal resistor, power consumption and other circuit parameters) can be obtained according to the circuit information structure, and the circuit parameters corresponding to each component layer can be defined in a preset simulation environment, thereby completing the setting of the electrical characteristics of the component layer before simulation.

[0055] In some embodiments, the circuit parameters corresponding to each component layer in the multiple layers are obtained according to the circuit information structure, and the circuit parameters corresponding to each component layer are defined in a preset simulation environment, including: determining the active end in the component layer according to the heat source network, and setting the length, width and thickness parameters of the active end; determining the power consumption parameters corresponding to each component layer according to the material properties in the simulation environment corresponding to the finite element analysis, or determining the device temperature corresponding to each component layer.

[0056] The present application sets the active end in the three-dimensional integrated circuit, determines the corresponding power consumption parameters or device temperature for each component layer, and completes the setting of the initial conditions of the model. The length, width and thickness parameters are defined in the simulation environment, and the length, width and thickness parameters can be arbitrarily modified by the method provided in the present application to obtain the thermal field conditions corresponding to each parameter.

[0057] Step S105 , meshing the metal region and the non-metal region in each layer layer by layer in the multiple layers according to the material characteristics and the device distribution information.

[0058] Specifically, according to the material properties and device distribution information, the metal area and non-metal area in the component layer can be determined, and then each layer is divided into n*n equally divided vertical hexahedrons in the vertical direction according to the material thermal characteristics and device distribution, and the height is the thickness of the layer; each layer of the metal material equally divided area is further divided into n*n equally divided vertical tetrahedrons in the vertical direction, and the height is the thickness of the layer. The tetrahedron division standard (the first principle is to divide and symmetry as much as possible, and the second principle is to keep the thermal characteristics consistent as much as possible). If the first division does not meet the requirements, the encrypted unit divided area continues to iterate to achieve the purpose of equal division and symmetry (to solve the problem of modeling and segmentation of thermal resistance models of stacked chips of different sizes. This method supports the setting of thermal conduction model parameters of thermal vias in stacks, the setting of thermal conduction model parameters of radiator air cooling, and the setting of microchannel cooling layer model parameters).

[0059] Step S106, performing finite element analysis on the multiple circuit device model element layers after meshing to output a temperature distribution diagram and a temperature value matrix data structure corresponding to the thermal field of the three-dimensional integrated circuit.

[0060] Specifically, the method provided by the present application can be run in any common finite element simulation environment (such as Ansys, Comsol), and then based on the divided grid and defined parameters, finite element analysis is performed on multiple layers layer by layer, and then the temperature distribution map and temperature value matrix data structure corresponding to the thermal field of the three-dimensional integrated circuit are output to complete the thermal analysis of the three-dimensional integrated circuit. By combining multiple methods such as experimental measurement and numerical simulation, the limitations of a single method are overcome and the precision and accuracy of thermal resistance extraction are improved.

[0061] In some embodiments, before performing finite element analysis on the meshed circuit device model, it also includes: dividing the multiple layers into series thermal resistance areas and parallel thermal resistance areas according to the device distribution information; respectively determining the equivalent thermal resistances corresponding to the series thermal resistance areas and the parallel thermal resistance areas; setting thermal field boundary conditions corresponding to the multiple component layers in the simulation environment corresponding to the finite element analysis; updating the component layer according to the equivalent thermal resistances corresponding to the series thermal resistance areas and the parallel thermal resistance areas, so as to re-mesh the updated component layer.

[0062] like Figure 4 and Figure 5 As shown, the present application merges the series and parallel parts of the three-dimensional integrated circuit in the vertical direction, and can encrypt the circuit structure in the form of an equivalent circuit without affecting the simulation effect. At the same time, the temperature setting of the insulation area of ​​the model and the thermal field boundary conditions such as wind speed are set. The equivalent thermal resistance is extracted, and the extracted equivalent thermal resistance is reused to determine the density and distribution of the grid, including the simplification of the grid. This can simplify the structure of the model and improve the speed of simulation calculation.

[0063] like Figure 4 The thermal resistance Q of the equivalent circuit corresponding to the circuit structure shown is:

[0064] ;

[0065] Finally, according to Joule's law, the three-layer series structure can be converted into an equivalent resistance R th1 and R th2 In series. total = R th1 +R th2 . T1, T2 and T3 are Figure 4 The corresponding temperature at each component layer.

[0066] like Figure 5 The thermal resistance Q of the equivalent circuit corresponding to the circuit structure shown is:

[0067] ;

[0068] The parallel part can then be converted into an equivalent resistor R th1 and R th2 In parallel, Q1 and Q2 are Figure 5 The equivalent thermal resistances of the two parallel regions, T1 and T2, are shown in Figure 5 The corresponding temperature at each component layer. total = R th1 +R th2 .

[0069] In some embodiments, the finite element analysis of the meshed circuit device model includes: constructing a sparse matrix solver according to Fourier's law and a heat conduction formula; and performing finite element analysis on the plurality of component layers according to the sparse matrix solver.

[0070] According to Fourier's law, the corresponding formula is:

[0071] ; where Q cond is the heat flux to be calculated, k is the thermal conductivity, A is the cross-sectional area perpendicular to the direction of heat conduction, is the temperature change rate of the object along the x direction. L is the length of the layer to be calculated, and T1 and T2 are the temperatures before and after the change.

[0072] In such Figure 2 In the three-layer TSV (Through-Silicon Via) structure shown in the figure, a corresponding vertical heat conduction model can be established for the sparse matrix solver:

[0073] .

[0074] Where K is the equivalent thermal conductivity in the vertical direction, h is the total height of the three layers, h1, h2 and h3 are the heights of the three layers respectively, the first layer is composed of copper and bcb resin material, and the ratio of copper: bcb resin material is α:1. The second layer is composed of copper and silicon dioxide, and the ratio of copper: silicon dioxide is β:1. The third layer is composed of copper, silicon dioxide and silicon, and the ratio of copper: silicon dioxide: silicon is σ:ε:1. Kcu, Kbcb, Ksio2 and Ksi are the thermal conductivities of copper, bcb, silicon dioxide and silicon respectively.

[0075] In some embodiments, after performing finite element analysis on the gridded circuit device model to output a temperature distribution diagram and a temperature value matrix data structure corresponding to the thermal field of the three-dimensional integrated circuit, it also includes: obtaining a thermal crosstalk factor corresponding to a metal area of ​​the circuit device model according to the temperature distribution diagram and the temperature value matrix data structure; setting the thermal crosstalk factor corresponding to the metal area in a simulation environment corresponding to the finite element analysis; re-performing finite element analysis according to the thermal crosstalk factor, and updating the temperature distribution diagram and the temperature value matrix data structure.

[0076] By introducing the thermal crosstalk factor for optimization, the mesh can be re-formed and finite element calculation can be performed, thereby improving the accuracy of thermal field analysis.

[0077] Compared with the prior art, this application has at least the following beneficial effects:

[0078] 1. Improve the accuracy of thermal resistance extraction: By combining multiple methods such as experimental measurement and numerical simulation, the limitations of a single method are overcome and the accuracy and precision of thermal resistance extraction are improved. For the same example, when the simulation resource processing is better than COMSOL and ANSYS, the accuracy error is within 3%.

[0079] 2. Optimize heat dissipation design: During the modeling process, this device supports the following heat dissipation design models for three-dimensional integrated circuits: thermal conductive TSV technology model, liquid circulation system model, heat sink and air cooling fin technology model, embedded microchannel model, and spray cooling heat dissipation model. It brings visual editing and numerical distribution of models to thermal management and heat dissipation optimization design, helping to optimize heat dissipation solutions and improve the performance and stability of electronic equipment and integrated circuits.

[0080] 3. Reduce testing costs and time: Through numerical simulation and other methods, the complexity and time-consuming nature of experimental measurements can be reduced, testing costs and time can be reduced, and R&D efficiency can be improved. By supporting the merging and separation of various integrated circuits, and supporting simulation, modification, and re-simulation of components and materials of various circuits, the flexibility of simulation is greatly improved and costs and time are reduced.

[0081] 4. Solve the thermal distribution problem of complex three-dimensional integrated circuits: Through the thermal resistance calculation method model to simplify the grid and locally encrypt the grid, the accuracy and reliability of the finite element calculation method are improved, and the calculation problem of thermal distribution in complex three-dimensional integrated circuits is solved.

[0082] In order to implement the thermal field calculation method of the three-dimensional integrated circuit corresponding to the above method embodiment, so as to achieve the corresponding functions and technical effects. Figure 6 , Figure 6 The following is a block diagram of a thermal field calculation device 200 provided in an embodiment of the present application. For ease of description, only the parts related to the present embodiment are shown. The thermal field calculation device 200 provided in an embodiment of the present application includes:

[0083] The structure acquisition module 201 is used to acquire the circuit device model and circuit information structure corresponding to the three-dimensional integrated circuit to be calculated;

[0084] The structure reading module 202 is used to read the circuit device model to obtain the three-dimensional spatial topological structure corresponding to the three-dimensional integrated circuit, and read the circuit information structure to obtain the material properties corresponding to the three-dimensional spatial topological structure;

[0085] A model layering module 203 is used to layer the circuit device model according to the three-dimensional spatial topological structure and material properties, and obtain layer distribution information and device distribution information corresponding to the circuit device model; the layer distribution information is used to divide the circuit device model into multiple layers;

[0086] A parameter definition module 204 is used to obtain circuit parameters corresponding to each component layer in the plurality of layers according to the circuit information structure, and define the circuit parameters corresponding to each component layer in a preset simulation environment; the circuit parameters include at least one or more of a heat source network, a power consumption parameter, and a device temperature;

[0087] A mesh division module 205, configured to perform mesh division on the metal region and the non-metal region in each layer in the plurality of layers according to the material properties and the device distribution information;

[0088] The simulation calculation module 206 is used to perform finite element analysis on the meshed circuit device model to output a temperature distribution diagram and a temperature value matrix data structure corresponding to the thermal field of the three-dimensional integrated circuit.

[0089] The above-mentioned thermal field calculation device can implement the thermal field calculation method of the three-dimensional integrated circuit of the above-mentioned method embodiment. The options in the above-mentioned method embodiment are also applicable to this embodiment and will not be described in detail here. The rest of the contents of the embodiment of this application can refer to the contents of the above-mentioned method embodiment, and will not be repeated in this embodiment.

[0090] Figure 7 This is a schematic diagram of the structure of a computer device provided in one embodiment of the present application. Figure 7 As shown, the computer device 3 of this embodiment includes: at least one processor 30 ( Figure 3 Only one is shown in the figure), a memory 31 and a computer program 32 stored in the memory 31 and executable on the at least one processor 30, wherein the processor 30 implements the steps of any of the above method embodiments when executing the computer program 32.

[0091] The computer device 3 may be a computing device such as a smart phone, a tablet computer, a desktop computer, a cloud server, etc. The computer device may include but is not limited to a processor 30 and a memory 31. Those skilled in the art will understand that Figure 7 It is only an example of computer device 3 and does not constitute a limitation on computer device 3. It may include more or fewer components than shown in the figure, or a combination of certain components, or different components, for example, it may also include input and output devices, network access devices, etc.

[0092] The processor 30 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0093] In some embodiments, the memory 31 may be an internal storage unit of the computer device 3, such as a hard disk or memory of the computer device 3. In other embodiments, the memory 31 may also be an external storage device of the computer device 3, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the computer device 3. Further, the memory 31 may also include both an internal storage unit and an external storage device of the computer device 3. The memory 31 is used to store an operating system, an application program, a boot loader (BootLoader), data, and other programs, such as the program code of the computer program. The memory 31 may also be used to temporarily store data that has been output or is to be output.

[0094] In addition, an embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.

[0095] An embodiment of the present application provides a computer program product. When the computer program product is run on a computer device, the computer device implements the steps in the above-mentioned method embodiments when executing the computer device.

[0096] In several embodiments provided in the present application, it is understood that each box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved.

[0097] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for a computer device to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, and other media that can store program codes.

[0098] The specific embodiments described above further describe the purpose, technical solutions and beneficial effects of the present application in detail. It should be understood that the above description is only a specific embodiment of the present application and is not intended to limit the scope of protection of the present application. It is particularly pointed out that for those skilled in the art, any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of protection of the present application.

Claims

1. A method for calculating the thermal field of a three-dimensional integrated circuit, characterized in that: include: Obtaining a circuit device model and a circuit information structure corresponding to the three-dimensional integrated circuit to be calculated; Reading the circuit device model to obtain a three-dimensional spatial topological structure corresponding to the three-dimensional integrated circuit, and reading the circuit information structure to obtain material properties corresponding to the three-dimensional spatial topological structure; The circuit device model is layered according to the three-dimensional spatial topological structure and material properties, and layer distribution information and device distribution information corresponding to the circuit device model are obtained; the layer distribution information is used to divide the circuit device model into multiple layers; Obtaining circuit parameters corresponding to each component layer in the plurality of layers according to the circuit information structure, and defining the circuit parameters corresponding to each component layer in a preset simulation environment; the circuit parameters at least include one or more of a heat source network, a power consumption parameter, and a device temperature; According to the material properties and the device distribution information, meshing the metal region and the non-metal region in each layer in the plurality of layers one by one; Finite element analysis is performed on the meshed circuit device model to output a temperature distribution diagram and a temperature value matrix data structure corresponding to the thermal field of the three-dimensional integrated circuit; wherein the circuit device model is a three-layer structure of a through silicon via process; the finite element analysis of the meshed circuit device model includes: constructing a sparse matrix solver according to Fourier's law and a heat conduction formula; performing finite element analysis on the circuit device model according to the sparse matrix solver, and the heat conduction model corresponding to the circuit device model in the vertical direction includes: ； Where K is the equivalent thermal conductivity in the vertical direction, h is the total height of the three layers corresponding to the three-layer structure, , and There are three layers of height, the first layer is made of copper and Resin material composition, copper: The ratio of resin material is ; The second layer is composed of copper and silicon dioxide, and the ratio of copper to silicon dioxide is ; The third layer is composed of copper, silicon dioxide and silicon, and the ratio of copper: silicon dioxide: silicon is ; , , and Copper, , thermal conductivity of silica and silicon; Among them, after outputting the temperature distribution map and temperature value matrix data structure corresponding to the thermal field of the three-dimensional integrated circuit, it also includes: obtaining the thermal crosstalk factor corresponding to the metal area of ​​the circuit device model according to the temperature distribution map and the temperature value matrix data structure; setting the thermal crosstalk factor corresponding to the metal area in the simulation environment corresponding to the finite element analysis; re-performing finite element analysis according to the thermal crosstalk factor, and updating the temperature distribution map and temperature value matrix data structure.

2. The method according to claim 1, characterized in that The layering further includes a dielectric layer and a wiring layer; and the step of reading the circuit information structure to obtain material properties corresponding to the three-dimensional spatial topological structure includes: Parsing the circuit information structure, obtaining material properties corresponding to each structural unit in the three-dimensional spatial topological structure in the vertical direction, and determining layer distribution information and device distribution information corresponding to the three-dimensional spatial topological structure in the vertical direction according to the material properties; The layer distribution information is used to divide the circuit device model into a component layer, a dielectric layer and a wiring layer.

3. The method according to claim 1, characterized in that The step of stratifying the circuit device model according to the three-dimensional spatial topological structure and material properties includes: Acquire electrical connection information corresponding to each structural unit according to the three-dimensional spatial topological structure; According to the electrical connection information and material properties corresponding to each of the structural units, the circuit device model is layered; The electrical connection information and material properties corresponding to the structural units in each of the component layers are the same.

4. The method according to claim 1, characterized in that: The acquiring circuit parameters corresponding to each component layer in the plurality of layers according to the circuit information structure, and defining the circuit parameters corresponding to each component layer in a preset simulation environment, comprises: Determine the active end in the component layer according to the heat source network, and set the length, width and thickness parameters of the active end; In the simulation environment corresponding to the finite element analysis, the power consumption parameter corresponding to each of the component layers is determined according to the material characteristics, or the device temperature corresponding to each of the component layers is determined.

5. The method according to claim 1, characterized in that Before performing finite element analysis on the meshed circuit device model, the method further includes: Dividing the plurality of layers into series thermal resistance regions and parallel thermal resistance regions according to the device distribution information; Determine the equivalent thermal resistances corresponding to the series thermal resistance region and the parallel thermal resistance region respectively; Setting thermal field boundary conditions corresponding to a plurality of the component layers in a simulation environment corresponding to the finite element analysis; The component layer is updated according to the equivalent thermal resistances corresponding to the series thermal resistance region and the parallel thermal resistance region, so as to re-grid the updated component layer.

6. A thermal field calculation device, characterized in that: include: A structure acquisition module, used to acquire a circuit device model and circuit information structure corresponding to the three-dimensional integrated circuit to be calculated; A structure reading module, used for reading the circuit device model to obtain the three-dimensional spatial topological structure corresponding to the three-dimensional integrated circuit, and reading the circuit information structure to obtain the material properties corresponding to the three-dimensional spatial topological structure; A model layering module, used to layer the circuit device model according to the three-dimensional spatial topological structure and material properties, and obtain layer distribution information and device distribution information corresponding to the circuit device model; the layer distribution information is used to divide the circuit device model into multiple layers; A parameter definition module, used to obtain circuit parameters corresponding to each component layer in the plurality of layers according to the circuit information structure, and define the circuit parameters corresponding to each component layer in a preset simulation environment; the circuit parameters include at least one or more of a heat source network, a power consumption parameter, and a device temperature; A mesh division module, used for performing mesh division for the metal region and the non-metal region in each layer layer by layer in the plurality of layers according to the material properties and the device distribution information; A simulation calculation module is used to perform finite element analysis on the meshed circuit device model to output a temperature distribution diagram and a temperature value matrix data structure corresponding to the thermal field of the three-dimensional integrated circuit; wherein the circuit device model is a three-layer structure of a through silicon via process; the finite element analysis of the meshed circuit device model includes: constructing a sparse matrix solver according to Fourier's law and a heat conduction formula; performing finite element analysis on the circuit device model according to the sparse matrix solver, and the heat conduction model corresponding to the circuit device model in the vertical direction includes: ； Where K is the equivalent thermal conductivity in the vertical direction, h is the total height of the three layers corresponding to the three-layer structure, , and There are three layers of height, the first layer is made of copper and Resin material composition, copper: The ratio of resin material is ; The second layer is composed of copper and silicon dioxide, and the ratio of copper to silicon dioxide is ; The third layer is composed of copper, silicon dioxide and silicon, and the ratio of copper: silicon dioxide: silicon is ; , , and Copper, , thermal conductivity of silica and silicon; Among them, after outputting the temperature distribution map and temperature value matrix data structure corresponding to the thermal field of the three-dimensional integrated circuit, it also includes: obtaining the thermal crosstalk factor corresponding to the metal area of ​​the circuit device model according to the temperature distribution map and the temperature value matrix data structure; setting the thermal crosstalk factor corresponding to the metal area in the simulation environment corresponding to the finite element analysis; re-performing finite element analysis according to the thermal crosstalk factor, and updating the temperature distribution map and temperature value matrix data structure.

7. A computer device, characterized in that: The computer device includes a memory and a processor; The memory is used to store computer programs; The processor is used to execute the computer program and implement the steps of the thermal field calculation method of a three-dimensional integrated circuit according to any one of claims 1 to 5 when executing the computer program.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the processor implements the steps of the thermal field calculation method for a three-dimensional integrated circuit according to any one of claims 1 to 5.

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