Multi-channel parallel battery management system and battery data transmission method based on SOPC architecture

Abstract

The present invention relates to the field of battery management, and discloses a multi-channel parallel battery management system based on SOPC architecture and a battery data transmission method. The system includes a host computer, a middle computer and a lower computer. The middle computer is configured with a Zynq chip of SOPC architecture and multiple RS485 interfaces connected to the lower computer. The Zynq chip includes a PL module and a PS connected to the host computer. The PL module receives multiple groups of battery data of the battery channel of the lower computer through the RS485 interface; the PL module uses a parallel processing method to perform protocol parsing on multiple groups of battery data to unload the battery data to obtain pure data, and uses a DMA method to transmit the pure data to the PS through an AXI bus; the PS packages the pure data and saves it to an eMMC memory, and sends the packaged data to the host computer through Ethernet. The present invention shares tasks with the PL module and the PS based on the SOPC architecture to achieve efficient parallel processing of multi-channel battery data.

Description

Technical Field

[0001] The present invention relates to the field of battery management, and in particular to a multi-channel parallel battery management system based on SOPC architecture and a battery data transmission method. Background Art

[0002] With the promotion of environmental protection policies and the advancement of science and technology, the application of new energy vehicles (such as electric vehicles) and large-scale energy storage systems is becoming more and more widespread. These devices use a large number of battery packs as energy sources, and the importance of battery management systems is highlighted. Each battery pack contains dozens to thousands of single cells. In order to ensure safe and efficient operation, real-time monitoring and precise management of battery status are crucial, which requires fast and accurate collection, processing and analysis of a large amount of battery data.

[0003] Traditional battery management systems usually use single-channel data acquisition, and the typical data processing method is polling. The intermediate computer polls each channel. If the system is connected to 64 slave computers, all 64 slave computers must be polled, which takes a long time and increases the time consumption of battery data management and processing.

[0004] However, as the scale of battery packs expands and the demand for control increases, the battery management system can no longer meet the high requirements for data transmission. The data transmission efficiency of existing solutions is low, which affects the production capacity of battery packs. Therefore, the use of multi-channel data acquisition has become more urgent.

[0005] The disclosure of the above background technology content is only used to assist in understanding the concept and technical solution of the present application. It does not necessarily belong to the prior art of the present application, nor does it necessarily provide technical guidance. In the absence of clear evidence that the above content has been disclosed before the filing date of the present application, the above background technology should not be used to evaluate the novelty and creativity of the present application. Summary of the invention

[0006] The purpose of the present invention is to provide a multi-channel parallel battery management system based on SOPC architecture, which can quickly realize efficient transmission and processing of battery pack data and improve the performance and response time of data transmission.

[0007] To achieve the above object, the technical solution adopted by the present invention is as follows:

[0008] A multi-channel parallel battery management system based on SOPC architecture, comprising a host computer, a middle computer and a lower computer, wherein the middle computer is provided with a plurality of RS485 interfaces for connecting to the lower computers, and each lower computer is configured with a plurality of battery channels for transmitting battery data;

[0009] The intermediate computer is also configured with a Zynq chip of SOPC architecture, and the Zynq chip includes a processing system and a PL module that communicate through the AXI-lite protocol, wherein the processing system is configured with an eMMC memory, the processing system is connected to the host computer, and the PL module is configured to receive multiple groups of battery data of the battery channel through the RS485 interface;

[0010] The battery management system processes and transmits multi-channel parallel battery data by dividing tasks in the following manner:

[0011] The PL module performs protocol parsing on the multiple groups of battery data in a parallel processing manner to unload the frame header, data length bit, function bit, check bit, and frame tail in the battery data to obtain pure data, and transmits the pure data to the processing system through the AXI bus in a DMA manner;

[0012] The processing system packages the pure data and saves the packaged data to the eMMC memory, and sends the packaged data stored in the eMMC memory to the host computer via Ethernet.

[0013] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, the middle computer can be configured with 64 RS485 interfaces to connect to 64 slave computers, and each slave computer can be configured to connect to 8 channel batteries;

[0014] The battery management system processes the battery data of 512 channels in parallel through the task division method.

[0015] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, the PL module is an FPGA, which is configured to simultaneously receive data packets from all lower computers in parallel and simultaneously unload the processing of the received data packets in parallel;

[0016] The processing system is also configured with a DDR3 memory, which includes two 256M×16bit DDR3 SDRAMs to combine the data bit width into 32 bits. The DDR3 memory is configured to cache the pure data obtained by the FPGA unloading the processing data packet.

[0017] Further, based on any one of the above technical solutions or a combination of multiple technical solutions, the PL module further includes:

[0018] The PL module encrypts the pure data.

[0019] Furthermore, based on any one of the technical solutions or a combination of multiple technical solutions mentioned above, the PL module uses AES or RSA encryption algorithm to encrypt the pure data, and uses Huffman coding or LZ77 to compress the data before transmission.

[0020] Furthermore, based on any one of the technical solutions or a combination of multiple technical solutions described above, the battery management system provided by the present invention also includes a display screen, and the PL module is also configured with an HDMI display interface connected to the display screen, so that the display screen can display the package data stored in the eMMC memory.

[0021] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, the processing system is also configured with a QSPI FLASH interface, a USB interface and an Ethernet port;

[0022] The PL module is also configured with a JTAG debugging port.

[0023] Further, based on any one of the technical solutions or a combination of multiple technical solutions mentioned above, the processing system is configured to initiate a data transmission request to the PL module as a master end, and respond to the access request of the PL module as a slave end.

[0024] According to another aspect of the present invention, a multi-channel parallel battery data transmission method based on SOPC architecture is provided, comprising the following steps:

[0025] The lower computer is connected to multiple channel batteries to obtain multi-channel battery data;

[0026] Configuring a mid-level computer: The mid-level computer has a Zynq chip, which includes a processing system and a PL module that communicate via an AXI-lite protocol;

[0027] The PL module receives multi-channel battery data from the lower computer in parallel through the RS485 interface;

[0028] The Zynq chip processes and transmits multi-channel battery data by dividing tasks in the following way:

[0029] The PL module performs protocol parsing on the multi-channel battery data in a parallel processing manner to unload the frame header, data length bit, function bit, check bit, and frame tail in the battery data to obtain pure data, and transmits the pure data to the processing system through the AXI bus in a DMA manner;

[0030] The processing system packages the pure data and saves the packaged data to an eMMC memory, and sends the packaged data stored in the eMMC memory to a host computer via Ethernet.

[0031] Further, based on any one of the above technical solutions or a combination of multiple technical solutions, before transmitting the pure data to the processing system through the AXI bus, it also includes:

[0032] The PL module encrypts the pure data using an encryption algorithm, and compresses the encrypted data using Huffman coding or LZ77.

[0033] The beneficial effects brought by the technical solution provided by the present invention are as follows:

[0034] a. Multi-channel parallel battery data transmission is conducive to meeting the high-precision and high-efficiency requirements of new energy vehicles and energy storage systems for battery management. The parallel transmission idea solves the problem of long-term occupation of RS485 channels, which is in line with the trend of intelligent and networked management brought about by the development of information technology;

[0035] b. By improving the parallelism of data transmission and processing, we can achieve real-time and accurate monitoring of battery status, enhance fault warning capabilities, ensure safe and stable operation of the system, and use cloud computing resources for in-depth data analysis to improve the overall benefits of battery use;

[0036] c. The SOPC architecture divides the tasks, with the PL module and PS taking on their respective tasks, effectively solving the problem of insufficient resources: the PL module performs data unloading to obtain pure data, and uses DMA to move the pure data to the AXI bus; the PS packages the pure data and saves the packaged data to the eMMC memory, and sends the packaged data stored in the eMMC memory to the host computer via Ethernet. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0038] Figure 1 A schematic diagram of a SOPC architecture of a multi-channel data parallel battery management system provided by an exemplary embodiment of the present invention;

[0039] Figure 2 for Figure 1 The circuit module block diagram of the battery management system shown;

[0040] Figure 3 A flowchart of a multi-channel parallel battery data transmission method based on SOPC architecture is provided for an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0041] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0042] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, device, product or equipment that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0043] In one embodiment of the present invention, a multi-channel parallel battery management system based on SOPC (System on a ProgrammableChip) architecture is provided, which uses the multi-channel parallel data processing technology of SOPC architecture to perform multiple data processing tasks simultaneously, and each channel processes data independently, rather than polling one by one in sequence, thereby significantly reducing the overall processing time; and additional instructions are added to refresh the data saved by the lower computer in real time, and further realize the reading of historical data for protocol processing. Multi-channel parallel data processing technology is a technology that utilizes the parallel capabilities of hardware and software to improve system performance and efficiency by processing multiple data streams simultaneously. It is widely used in various scenarios that require high-speed and large-scale data processing, and its use in battery management systems can effectively improve production capacity.

[0044] In one embodiment of the present invention, a multi-channel parallel battery management system based on SOPC architecture includes a host computer, a middle computer and a lower computer, such as Figure 1As shown, the middle computer is provided with a Zynq chip of SOPC architecture and multiple RS485 interfaces for connecting to the lower computers, and each lower computer is configured with multiple battery channels for transmitting battery data. The Zynq chip includes a processing system (PS) and a PL (Programmable Logic) module that communicate via the AXI-lite protocol. Figure 2 As shown, the processing system is configured with an eMMC (embedded MultiMedia Card) memory and a DDR3 memory, and the processing system is connected to the host computer. In this embodiment, the PL module is an FPGA (Field Programmable Gate Array), which is configured to simultaneously and in parallel receive multiple sets of battery data from the battery channels of all the lower computers through the RS485 interface. Zynq is a new generation of fully programmable system-on-chip (fully programmable means that both hardware and software can be programmed), and its essential feature is the combination of a PS (such as a dual-core ARM processor) and a PL module (such as a field programmable gate array FPGA logic component).

[0045] The PS (ARM processor) part of the SOPC architecture mainly includes the boot BOOT of the entire system, the system image file is loaded and stored in the eMMC, and the user's temporary data is cached in the DDR3 memory. Finally, it includes Gigabit Ethernet management, remote upgrade, and local debugging serial port RS232; the PL module of the SOPC architecture mainly uses the general IO port, expands multiple RS485 interfaces, and transmits data with the lower computer.

[0046] In this embodiment, the FPGA of the system is interconnected with the lower computer through the RS485 interface. The system is designed to have 8 battery channels for each lower computer. The number of RS485 interfaces set in the middle computer is 64 to achieve the connection of 64 lower computers, thus forming a total of 512 battery channels; when the system sends a data request instruction, the 512 battery channels of the 64 lower computers will simultaneously send all battery data in parallel to the FPGA. Accordingly, the DDR3 memory includes two 256M×16bit DDR3 SDRAMs to combine the data bit width into 32 bits, and the DDR3 memory is configured to cache the pure data obtained by the FPGA unloading the processing data packet.

[0047] The battery management system processes and transmits multi-channel parallel battery data in parallel by dividing tasks in the following manner:

[0048] First, the PL module (FPGA) performs protocol parsing on the multiple groups of battery data in a parallel processing manner to unload the frame header, data length bit, function bit, check bit, and frame tail in the battery data to obtain pure data. Optionally, the FPGA simultaneously performs unloading processing operations on 512 channels of battery data in parallel, and uses DMA (Direct Memory Access) to transmit the pure data to the processing system through the AXI bus;

[0049] Secondly, the processing system packages the pure data and saves the packaged data to the eMMC memory, and sends the packaged data stored in the eMMC memory to the host computer via Ethernet, and the host computer parses the data.

[0050] Offloading data means decomposing the data processing tasks originally performed on the local device, and transferring the decomposed pure data (the original data remaining after unloading the unimportant parts such as the frame header and frame tail) to other devices or platforms with stronger computing power and / or larger storage capacity for processing. The main purpose of offloading data, i.e., data processing, is to reduce the computing burden of the local device, save energy, improve processing efficiency, and use more powerful computing resources to achieve more complex data analysis or advanced functions. The following is a specific embodiment of offloading data:

[0051] In the data packet sent by the lower computer, A55A EE FF XXXXXXXX 01 A55A, A55A is the frame header, EE is the data length, FF is the function bit, XXXXXXXX represents pure data (i.e., the original battery data), 01 is the check bit, and A55A is the frame tail. The data processing unloading mainly processes the frame header, data length bit, function bit, check bit, and frame tail of the received data packet through FPGA, and only retains the pure data bit to the PS end. PS assembles the data and saves it to eMMC, and then PS sends the assembled data to the upper computer through Gigabit Ethernet. By unloading the data, the amount of data can be effectively reduced while retaining important core data. Only transmitting valid data can export data more quickly, greatly improving the transmission efficiency.

[0052] Using SOPC multi-channel DMA transmission architecture, FPGA receives 512 sets of data at the same time. The data volume is large, and the system requires real-time transmission. In order to solve the problem of efficient data transmission, DMA is used. With independent processing capabilities, the channel can run independently of the processor and is responsible for data transmission between the device and the main memory, thereby reducing the burden on the processor. The processor only needs to issue I / O instructions to the channel (such as starting the channel program, specifying transmission parameters, etc.), and then it can continue to perform other tasks without directly participating in data handling. With batch processing capabilities, the channel can perform a series of continuous operations and support efficient transmission of batch data, which is particularly suitable for processing large-scale data transmission requirements of equipment. With multiplexing function, one channel can serve multiple peripherals, and concurrent control of multiple devices can be achieved through multiplexing technology, further improving the overall throughput of the system.

[0053] The 512 sets of battery data received by the FPGA are moved to the AXI bus using DMA and transmitted to the PS (ARM processor). The PS stores the data in the eMMC and transmits it to the host computer through the network port. In system design, channels and DMA are used in combination to form the so-called "channel DMA" or "channel with DMA function". This combination usually has the following characteristics: First, as an extension of the DMA controller, the channel is not only responsible for the control logic of the I / O device, but also acts as an advanced DMA controller, which can schedule and manage multiple DMA transfer operations and even support complex DMA transfer modes; second, with enhanced I / O management functions, the channel can handle more complex I / O tasks, such as synchronization between devices, data format conversion, error detection and recovery, etc., rather than just simple data handling. Combined with the DMA function, it can efficiently perform these tasks while directly accessing large amounts of data in memory. Finally, it has higher concurrency capabilities: channels combined with DMA capabilities can more effectively support concurrent transmission of multiple devices, and through hardware-level multiplexing and priority management, ensure that DMA requests from different devices can be scheduled and served in a timely and reasonable manner.

[0054] In summary, both channels and DMA are technologies designed to improve data transmission efficiency and reduce processor burden. Channels are more like a small processor focused on I / O management, while DMA is a direct memory access mechanism. When the two are used together, channels can provide higher-level I / O services and management functions, while using DMA technology to directly and efficiently transfer data, jointly optimizing data flow in the system.

[0055] like Figure 1As shown, the battery management system provided by the present invention also includes a display screen, and the PL module is also configured with an HDMI display interface connected to the display screen, so that the display screen can display the package data stored in the eMMC memory.

[0056] The PL module (FPGA) of the whole system has the following functions: First, it expands the RS485 interface. Most traditional battery management systems use ARM or MCU for control. The number of UART interfaces is limited, and it is usually necessary to use the RS485 bus networking method to implement it. This traditional method usually encounters RS485 bus channel occupancy, and each sub-device needs to wait. This method is feasible for transmitting low data volume, but with the rapid development of new energy, this transmission method is obviously unable to meet the production of battery management systems, and traditional battery management systems usually manage one device with one board. The embodiment of the present invention can effectively solve the problem of RS485 bus occupancy, and can transmit data more efficiently. At the same time, the simplified system can effectively reduce costs. One board can manage multiple devices, so this architecture can effectively reduce costs. The second is that it has a display function. Traditional battery management systems usually require an external computer to perform battery function tests and troubleshooting. The embodiment of the present invention connects the display module to the SOPC system and then installs the display screen to the battery cabinet. The production operator can directly perform battery function tests on the cabinet, which greatly improves convenience. At the same time, when encountering product production failures, they can directly perform troubleshooting and analysis on the cabinet, thereby improving production capacity. The third is data unloading preprocessing. The FPGA part directly collects all data uploaded by the lower-level battery. The data is uploaded in a fixed protocol format. Since the lower-level battery system is relatively large, 512 battery pack data are uploaded at the same time, resulting in a large processing pressure on the upper computer, and the processing power requirements of the upper computer processor are very strong. This will cause ordinary upper computer equipment to be unable to be used normally, or the processing time is long, and it is impossible to achieve real-time performance. Therefore, data unloading is adopted, that is, the data is processed by the FPGA and the upper computer together, so that the processing pressure of the upper computer can be shared. The first step to realize data unloading is to obtain data, which is used to obtain the source data of the data battery pack, and to determine the data format (i.e., frame header, data length bit, function bit, check bit, frame tail) specified by the battery system followed by the source data group; the second step is that FPGA unloads the actual useful data (pure data) of the battery pack to the source data group according to the data format, so that the data type between the FPGA data unloading module data and the lower computer source data group is consistent, and at the same time, valid data is extracted, and unloading work such as removing the frame header and frame tail is performed to obtain actual useful data.

[0057] In another embodiment, unlike the above method of directly sending pure data to the processing system, the PL module first encrypts the pure data, and then transmits the encrypted pure data to the processing system through the AXI bus. The traditional battery management system mainly faces insufficient processor resources, high energy consumption, insufficient real-time performance, and no encryption protection. The data processing unloading method of the SOPC architecture processes part of it on the FPGA through a task-dividing method, and then the PS side performs package assembly, which effectively solves the problem of insufficient resources; at the same time, because the FPGA has real-time processing capabilities, it effectively improves the real-time performance of the product; in the process of processing data packets, the FPGA implements data encryption to achieve encryption protection.

[0058] FPGA performs protocol analysis on the raw data sent by the lower computer, such as extracting key information based on the message structure, or encapsulating data according to specific protocols (such as Modbus, TCP / IP, UDP) so that the upper computer or network system can identify and process it. For high-bandwidth data streams, FPGA can execute efficient compression algorithms (such as Huffman coding, LZ77, etc.) in real time to reduce data transmission volume, save network bandwidth and storage space. Before the data leaves the middle computer, FPGA can implement encryption algorithms such as AES and RSA to ensure the security of data during transmission. FPGA can implement fast PID controllers or other real-time control algorithms to adjust the control signals of the lower computer in real time to ensure system response speed and stability. When processing lower computer data, FPGA can play an important role in data acquisition, preprocessing, interface conversion, security processing, real-time control, etc. with its hardware programmability and parallel processing capabilities.

[0059] The PS (ARM processor) part of the whole system has the following functions: the main control module is equipped with Xilinx's ZYNQ7020 as the core processor, which is a SoC architecture that integrates the software programmability of the ARM® processor and the hardware programmability of the FPGA. It can not only realize important analysis and hardware acceleration, but also highly integrates CPU, DSP, ASSP and mixed signal functions on a single device, realizing the functions of both hardware programming and software programming.

[0060] like Figure 2As shown, the PS (ARM processor) provides 1GB of DDR3 memory, more than 4GB of eMMC storage, 256Mb of FLASH, USB interface and Gigabit Ethernet. All of the above interfaces are hung on the PS (ARM processor) part to assist the PS in packaging and uploading the converted data. According to the above, the FPGA will receive 512 sets of battery data from the lower computer at the same time, and then perform protocol analysis. After parsing the field, the data will be moved to the AXI bus to the PS through DMA. At this time, the data received by the PS is pure data processed by the FPGA. At this time, the PS will package and compile the data, and the data will also be saved in the EMMC. Since the pure data is given to the upper computer and cannot be recognized, the PS will package the data. The packaged data can be quickly transmitted to the upper computer using Gigabit Ethernet. Since the lower computer uses RS485 with a transmission rate of only 1M, Gigabit Ethernet can be transmitted at Gigabit, and the data volume will not be in the dilemma of being unable to be uploaded in time.

[0061] Zynq's PS is mainly responsible for general processing, control logic and management of external interfaces in the system. The PS contains one or more high-performance processor cores, providing powerful computing power for running operating systems (such as Linux, RTOS, etc.), applications, middleware, and user interface software components. The integrated memory controller supports connection with various types of external DRAM (such as DDR3, DDR4, etc.), providing high-speed, large-capacity main memory support for processors and other system components, including first-level cache (L1) and possible second-level cache (L2) to reduce the processor's access to main memory latency, improve data access speed, support multiple power states and power management strategies, and ensure that energy efficiency is optimized while meeting performance requirements.

[0062] The interaction between PS (ARM processor) and PL (Programmable Logic) is carried out through the Advanced Extension Interface (AXI) for efficient and flexible data exchange. PS can initiate data transmission requests as the master end, or respond to PL access requests as the slave end. PS is responsible for configuring, initializing and managing the logic design of the PL part, including loading FPGA configuration files (bitstreams), dynamically reconfiguring PL logic, monitoring PL status, etc. At the same time, it provides a variety of timer resources, such as private timers, global timers, watchdog timers, etc., for task scheduling, timeout detection, periodic event processing, etc., managing internal and external interrupt requests, ensuring that PS can respond to various interrupt events in a timely manner, and realizing efficient processing of asynchronous events. Zynq's PS, as the hub and control center of the system, provides powerful computing power, rich peripheral interfaces, system management and security functions, and also closely cooperates with PL through efficient AXI interfaces to achieve deep integration and collaborative work of software and hardware, providing a highly integrated and customizable platform solution for various embedded applications.

[0063] The system in this embodiment is also configured with a dynamic memory part, which usually refers to the memory area that can be dynamically allocated and reclaimed by the operating system (such as Linux) during operation, and is used to support the operation of applications and temporary storage of data. The main advantage of this architecture is that it can transmit a large amount of data in parallel, so it is particularly important for temporary data caching. The dynamic storage of Zynq PS mainly refers to its DDR RAM connected through the memory controller. This part of memory resources is managed by the operating system, through the virtual memory mechanism, dynamic memory allocation function and stack automatic management, to provide the application with the storage space required for runtime that can be dynamically allocated and released. In addition, the cache inside the PS is also an important part of its memory hierarchy, ensuring the high speed of data access and maintaining data consistency with the main memory through the cache consistency mechanism.

[0064] In one embodiment of the present invention, two DDR3 devices are connected to the PS end of ZYNQ, each DDR3 device has a bit width of 16 bits, a power supply level VDDQ of 1.5V, and a maximum transmission rate of 1600Mb / s. The system uses two DDR3 chips to splice the data bit width into 32 bits. When the system PL receives a large amount of data, DMA is used to move the data. Since the amount of data is too large to be moved at one time, the data will be temporarily cached. At this time, DDR3 caches the data at a transmission rate of 1600Mb / s to solve data congestion. At the same time, the device can normally receive data from the lower computer, effectively improving the system transmission efficiency.

[0065] In this embodiment, the DDR3 memory of the PS (ARM processor) part is designed as two 256M×16-bit DDR3 memories, and the clock frequency is set to 400MHz for calculation. The bandwidth of the data DDR is:

[0066] 400MHz×2×16bit×2=25600Mbit / 8=3200MB / s=3.125GB / s. Such data bandwidth plus the estimated maximum channel loss of 20% can achieve an actual bandwidth of 2.5GB / s, which can meet the system data real-time storage and processing bandwidth requirements without adding additional data processing and storage.

[0067] The eMMC data storage part of the multi-channel parallel battery management system based on the SOPC architecture of this embodiment uses one eMMC as a solid-state memory, and requires receiving the lower computer data from the RS485 of the FPGA. The data stream is transferred to the solid-state storage, and when the data needs to be read out, it can be used as data read back for analysis.

[0068] The eMMC (Embedded MultiMedia Card) mounted on the Zynq chip (PS) refers to connecting one or more eMMC storage devices to the PS part of the Zynq SoC as the auxiliary or main non-volatile storage medium of the system. eMMC is an embedded storage solution that integrates flash memory, controller and interface protocol. It is usually used to store operating systems, applications, user data, etc. eMMC is an "embedded multimedia memory card" built based on parallel data transmission technology. Each data channel can perform read and write transmissions, but only read or write operations can be performed at the same time. eMMC is equivalent to Nand Flash + master control IC. One of its obvious advantages is that a controller is integrated in the package to provide a standard interface and manage flash memory.

[0069] The eMMC of this device can store Bootloader, Linux kernel, device tree and other data required for startup. As the system startup medium, in the startup process of Zynq SoC, the Boot ROM of PS will search for the startup device according to the preset startup eMMC and configure it to start from eMMC. The Boot ROM will read and execute the Bootloader code therein, and then guide the system startup process. The eMMC can store the Linux root file system (rootfs), which contains user space applications, library files, configuration files, etc. required for the operation of the operating system. After the system starts, the kernel will mount the root file system on the eMMC, so that the system enters the user space and starts running user applications. In addition to system data, eMMC can also be used to store data, log files, databases, etc. generated by user applications, providing persistent data storage space. eMMC uses a high-speed serial interface and supports a higher data transfer rate. Compared with traditional parallel flash memory interfaces (such as NOR Flash), it has higher data throughput. The low power consumption characteristics are taken into consideration when designing eMMC, which is suitable for battery-powered embedded devices. The integrated controller provides error correction (ECC), bad block management, health monitoring (SMART) and other functions, which improves the reliability of data storage. eMMC is divided into multiple logical partitions, such as Boot partition, system partition (to store root file system), user data partition, etc. These partitions may use different file system formats (such as ext4, FAT32, etc.) to meet the storage requirements of different types of data. The eMMC mounted on the Zynq PS is a non-volatile storage device that provides the system with boot, operating system storage, user data storage and other functions. It is connected to the PS through the eMMC interface, has the characteristics of high speed, low power consumption, high reliability, etc., and has good software support in the Linux operating system, which is convenient for system deployment, upgrade and maintenance.

[0070] With the rapid development of new energy, battery business has been greatly improved, and a large amount of data is transmitted. The traditional battery management system uses UART to transmit data. As the amount of data increases, the transmission capacity of the serial port is limited and cannot meet the transmission requirements. The present invention uses Gigabit Ethernet for transmission, which can solve the problem of limited data transmission in the battery management system. The Gigabit Ethernet function integrated in the Zynq chip (PS) provides a high-speed and reliable network communication interface, so that the Zynq SoC can be connected to a local area network (LAN) or a wide area network (WAN) to realize data transmission and reception. Ethernet supports 10 / 100 / 1000Mbps rate adaptation, and the maximum theoretical transmission rate is 1Gbps (gigabits per second), which is suitable for high-bandwidth data transmission requirements. It supports full-duplex mode and can send and receive data at the same time, thereby improving communication efficiency. Multiple protocols, compatible with Ethernet standards, support for multiple network protocols, suitable for various network applications, Zynq's integrated Gigabit Ethernet function provides the system with high-speed, standard network access capabilities, supports multiple network protocols and applications, and is seamlessly integrated with the operating system network stack through the supporting driver. It is widely used in data acquisition, remote control, network services and other scenarios, and can be configured and troubleshooted through standard network management tools.

[0071] Ethernet interface, uniformly uses RGMII interface to connect with PS, PHY chip uses the currently more mature monolithic integrated high-performance Gigabit Ethernet physical layer chip, fully supports IEEE802.3 protocol, built-in 1.25G serial deserializer, and meets Gigabit network transmission applications, supports GMII, RGMII, TBI and other MAC layer interfaces, maximum power consumption of 0.75W, and supports automatic power reduction function, designed to carry network transformer to ensure high reliability and transmission of network output, Gigabit Ethernet data transmission rate can reach 1000Mbps or 1Gbps, equivalent to about 125MB of data per second. Gigabit Ethernet is developed on the basis of traditional Ethernet, aiming to meet the growing demand for network bandwidth, especially in the local area network (LAN) environment where high-speed data transmission is required. However, the amount of data in the battery management system is increasing, and Gigabit Ethernet is particularly suitable for this environment, which can quickly solve the data transmission bottleneck of the traditional battery management system.

[0072] The PS (ARM processor) part and PL (programmable logic) part of the Zynq architecture development platform of the multi-channel parallel battery data unloading system of the SOPC architecture provided in the embodiment of the present invention use the AXI-Lite high-speed bus interface in the processor chip inside the Zynq architecture processing chip, and use 2 AXI 64-bit Master (master mode) and Slave (slave mode), as well as 4 AXI 64-bit Memories and 16 interrupt signals to perform main information interaction, protocol forwarding and parsing and data communication between the PS (processing system) part and the PL (programmable logic) part, and realize remote online upgrade, configuration management, log maintenance and timely communication of the host device server and the control platform through the Gigabit Ethernet RGMII interface.

[0073] In summary, the multi-channel parallel battery management system based on SOPC architecture can achieve efficient, reliable and low-energy multi-channel data transmission and improve the performance and response speed of data transmission. Data processing offloading is a technical means to transfer computing tasks from resource-constrained local devices to other more powerful computing platforms, aiming to solve the performance bottlenecks, energy consumption problems, real-time requirements and privacy protection challenges of local processing. Realizing data processing offloading involves multiple technical aspects such as network transmission, task scheduling, interface standards, security protection, etc., and needs to deal with practical challenges such as network conditions, energy consumption trade-offs, and privacy compliance. Data processing offloading has become one of the key strategies to improve system performance and user experience.

[0074] In one embodiment of the present invention, a multi-channel parallel battery data transmission method based on SOPC architecture is provided. Figure 3 As shown, the method comprises the following steps:

[0075] The lower computer is connected to multiple channel batteries to obtain multi-channel battery data;

[0076] Configuring a mid-level computer: The mid-level computer has a Zynq chip, which includes a processing system and a PL module that communicate via an AXI-lite protocol;

[0077] The PL module receives multi-channel battery data from the lower computer in parallel through the RS485 interface;

[0078] The Zynq chip processes and transmits multi-channel battery data by dividing tasks in the following way:

[0079] The PL module performs protocol parsing on the multi-channel battery data in a parallel processing manner to unload the frame header, data length bit, function bit, check bit, and frame tail in the battery data to obtain pure data, and transmits the pure data to the processing system through the AXI bus in a DMA manner;

[0080] The processing system packages the pure data and saves the packaged data to an eMMC memory, and sends the packaged data stored in the eMMC memory to a host computer via Ethernet.

[0081] In one embodiment of the present invention, before transmitting the pure data to the processing system through the AXI bus, the method further includes:

[0082] The PL module encrypts the pure data using an encryption algorithm, and compresses the encrypted data using Huffman coding or LZ77.

[0083] It should be noted that the multi-channel parallel battery data transmission method based on SOPC architecture provided in this embodiment and the multi-channel parallel battery management system based on SOPC architecture provided in the above embodiment belong to the same inventive concept. The full text of the above battery management system embodiment is introduced into the present battery data transmission method embodiment by reference and will not be repeated here.

[0084] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0085] The above is only a specific implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A multi-channel parallel battery management system based on SOPC architecture, characterized in that: It includes an upper computer, a middle computer and a lower computer, wherein the middle computer is provided with a plurality of RS485 interfaces for connecting to the lower computers, and each lower computer is provided with a plurality of battery channels for transmitting battery data; The intermediate computer is also configured with a Zynq chip of SOPC architecture, and the Zynq chip includes a processing system and a PL module that communicate through the AXI-lite protocol, wherein the processing system is configured with an eMMC memory, the processing system is connected to the host computer, and the PL module is configured to receive multiple groups of battery data of the battery channel through the RS485 interface; The battery management system processes and transmits multi-channel parallel battery data by dividing tasks in the following manner: The PL module performs protocol parsing on the multiple groups of battery data in a parallel processing manner to unload the frame header, data length bit, function bit, check bit, and frame tail in the battery data to obtain pure data, and transmits the pure data to the processing system through the AXI bus in a DMA manner; The processing system packages the pure data and saves the packaged data to the eMMC memory, and sends the packaged data stored in the eMMC memory to the host computer via Ethernet.

2. The battery management system according to claim 1, characterized in that: The middle computer can be configured with 64 RS485 interfaces to connect to 64 slave computers, and each slave computer can be configured to connect to 8 channel batteries; The battery management system processes the battery data of 512 channels in parallel through the task division method.

3. The battery management system according to claim 2, characterized in that: The PL module is an FPGA, which is configured to simultaneously receive data packets from all lower computers in parallel and simultaneously unload the processing of the received data packets in parallel; The processing system is also configured with a DDR3 memory, which includes two 256M×16bit DDR3 SDRAMs to combine the data bit width into 32 bits. The DDR3 memory is configured to cache the pure data obtained by the FPGA unloading the processing data packet.

4. The battery management system according to claim 1, characterized in that: Before transmitting the pure data to the processing system through the AXI bus, the PL module further includes: The PL module encrypts the pure data.

5. The battery management system according to claim 4, characterized in that: The PL module uses AES or RSA encryption algorithm to encrypt the pure data, and uses Huffman coding or LZ77 to compress the data before transmission.

6. The battery management system according to claim 1, characterized in that: It also includes a display screen, and the PL module is also configured with an HDMI display interface connected to the display screen, so that the display screen can display the package data stored in the eMMC memory.

7. The battery management system according to claim 1, characterized in that: The processing system is also equipped with a QSPIFLASH interface, a USB interface and an Ethernet port; The PL module is also configured with a JTAG debugging port.

8. The battery management system according to claim 1, characterized in that: The processing system is configured to initiate a data transmission request to the PL module as a master, and to respond to an access request of the PL module as a slave.

9. A multi-channel parallel battery data transmission method based on SOPC architecture, characterized in that: The following steps are involved: The lower computer is connected to multiple channel batteries to obtain multi-channel battery data; Configuring a mid-level computer: The mid-level computer has a Zynq chip, which includes a processing system and a PL module that communicate via an AXI-lite protocol; The PL module receives multi-channel battery data from the lower computer in parallel through the RS485 interface; The Zynq chip processes and transmits multi-channel battery data by dividing tasks in the following way: The PL module performs protocol parsing on the multi-channel battery data in a parallel processing manner to unload the frame header, data length bit, function bit, check bit, and frame tail in the battery data to obtain pure data, and transmits the pure data to the processing system through the AXI bus in a DMA manner; The processing system packages the pure data and saves the packaged data to an eMMC memory, and sends the packaged data stored in the eMMC memory to a host computer via Ethernet.

10. The multi-channel parallel battery data transmission method according to claim 9, characterized in that: Before transmitting the pure data to the processing system through the AXI bus, the method further includes: The PL module encrypts the pure data using an encryption algorithm, and compresses the encrypted data using Huffman coding or LZ77.

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