Single resistor sampling method and device

Abstract

The present invention provides a single resistor sampling method and device, and relates to the field of current sampling technology. The present invention can preferentially obtain the current values ​​of each phase corresponding to the motor in the previous adjustment interval. When entering the current adjustment interval, the sampling signal is first determined, and then the pulse width control signal under the current adjustment interval is determined according to the current values ​​of each phase and the sampling signal, and the pulse width adjustment signal is obtained to drive and control the motor. Among them, the pulse width control signal is set before the sampling signal. Finally, the currents of each phase corresponding to the motor in the current adjustment interval are sampled according to the sampling signal. Based on this, the present invention can avoid generating additional phase shifting steps during the sampling process according to the pre-set sampling signal, and then combine the pulse width control signal that matches the level state corresponding to the sampling signal to reduce the noise of the motor; at the same time, the sampling signal is used to obtain the current signal corresponding to the current adjustment interval to obtain a more accurate sampling value.

Description

Technical Field

[0001] The present invention relates to the technical field of current sampling, and in particular to a single resistor sampling method and device. Background Art

[0002] Permanent magnet synchronous motors (hereinafter referred to as motors) are widely used in AC speed regulation, metallurgy and mining, industrial manufacturing and other fields. Among them, the stator three-phase winding current is an important parameter of the motor vector control system, and the sampling method and sampling accuracy of the stator three-phase winding current will directly determine the cost of the motor vector control system, the impact of the closed loop and the safety of the motor.

[0003] In the prior art, a single resistor sampling method is often used to determine the three-phase current of the motor, and then the motor is controlled based on the three-phase current. Figure 1 For example, Figure 1 The schematic diagram of the circuit for single resistor sampling is shown; specifically, a sampling resistor can be placed at the output of the inverter's bus capacitor, and the sampling resistor is used to sample the DC bus current, so as to reconstruct the three-phase current through an algorithm based on the correspondence between the DC bus current and the motor phase current under different voltage vectors. In fact, the motor control process actually controls the three-phase voltage of the motor. Taking the space vector pulse width modulation control algorithm as an example, the control algorithm generates a three-phase phase current modulation signal, such as a pulse width phase current modulation signal (Pulse Width Modulation, PWM), and can complete the control of the motor by adjusting the high-level duration corresponding to the pulse width phase current modulation signal, and then determining the phase voltage of the corresponding phase based on the high-level duration. Figure 2 For example, Figure 2 shows a pulse width modulation signal under a control period T; wherein, T u , T v and T w are the high level durations corresponding to the U phase, V phase and W phase respectively. Taking the U phase as an example, the corresponding phase voltage can be expressed as: Udc*(T u / T), where Udc is the bus voltage; t1 to t7 are the level durations in each non-zero time sequence.

[0004] When sampling with a single resistor sampling method, it is necessary to measure the current of the DC bus multiple times through a non-zero basic vector within a control cycle to determine the phase current of the motor. Since the change and stability of the current requires a certain amount of time, the actual sampling time needs to be greater than the minimum duration of the non-zero vector, that is, the sampling window value, to ensure the accuracy of the sampling. In the prior art, the actual sampling time corresponding to each phase is usually made greater than the sampling window value by phase shifting. However, frequent phase shifting will cause the three-phase output voltage distortion to increase, resulting in unstable motor operation or generating large electromagnetic noise, making single resistor sampling difficult to apply to scenarios with higher noise requirements.

[0005] Based on this, there is an urgent need for a single resistor sampling method that can sample accurate current without phase shifting and reduce motor noise without changing the single resistor sampling circuit. Summary of the invention

[0006] The object of the present invention is to provide a single resistor sampling method and device, which can sample a more accurate current without phase shifting without changing the single resistor sampling circuit.

[0007] The embodiments of the present invention can be implemented as follows:

[0008] In a first aspect, the present invention provides a single resistor sampling method, the single resistor sampling method comprising the following steps:

[0009] Obtain the current value of each phase corresponding to the motor in the previous adjustment interval;

[0010] When entering the current adjustment interval, determining a sampling signal, wherein the preset sampling interval corresponding to the sampling signal is greater than the sampling window time;

[0011] And determine the pulse width control signal in the current adjustment interval according to the current value of each phase and the sampling signal, and obtain the pulse width adjustment signal to drive and control the motor;

[0012] Wherein, the pulse width modulation signal includes three phase current modulation signals, each phase current modulation signal corresponds to the three phases of the motor respectively, and the phase current modulation signal includes a sampling signal and a pulse width control signal; the pulse width control signal is set before the sampling signal;

[0013] The currents of each phase corresponding to the motor in the current adjustment range are sampled according to the sampling signal.

[0014] Preferably, when the pulse width control signal includes a high level duration, the step of determining the pulse width control signal in the current adjustment interval according to the current values ​​of each phase and the sampling signal includes:

[0015] Determine the first high level duration corresponding to the current modulation signal of each phase in the current regulation interval according to the current value of each phase;

[0016] For any phase, determining the second high level duration corresponding to the sampling signal of the current phase;

[0017] The third high level duration of each pulse width control signal in the current adjustment interval is determined according to each first high level duration and the second high level duration of the corresponding phase, so as to obtain the pulse width control signal in the current adjustment interval.

[0018] Preferably, when the sampling signal includes at least two consecutive preset sampling intervals, and each preset sampling interval corresponds to a different non-zero vector, the step of determining, for any phase, the second high level duration corresponding to the sampling signal in the current phase includes:

[0019] Determining the conduction duration of each non-zero vector under the sampling signal according to the level state of each non-zero vector in the corresponding preset sampling interval;

[0020] The sum of the conduction durations corresponding to all non-zero vectors is used as the second high level duration corresponding to the current phase down-sampling signal;

[0021] Wherein, each of the preset sampling intervals is greater than the sampling window time.

[0022] Preferably, the step of determining the conduction duration of each non-zero vector under the sampling signal according to the level state of each non-zero vector in the corresponding preset sampling interval includes:

[0023] If the level state is a low level, the conduction duration of the non-zero vector in the current preset sampling interval is zero;

[0024] If the level state is a high level, the conduction duration of the non-zero vector in the current preset sampling interval is the time corresponding to the preset sampling period.

[0025] Preferably, when the sampling signal includes two consecutive preset sampling intervals, and the corresponding non-zero vectors in each preset sampling interval are 001 and 011 respectively, the second high level duration corresponding to each phase satisfies:

[0026] T 2u =0; T 2v =t2; T 2w =t1+t2; t1 <t2

[0027] Among them, T 2u is the duration of the second high level corresponding to the first phase; T 2v is the second high level duration corresponding to the second phase; T 2wis the second high level duration corresponding to the third phase; t1 is the period of the first preset sampling interval; and t2 is the period of the second preset sampling interval.

[0028] Preferably, the step of determining the third high level duration of each pulse width control signal in the current adjustment interval according to each first high level duration and the second high level duration of the corresponding phase includes:

[0029] For any phase, the third high level duration of each pulse width control signal in the current adjustment interval is obtained by subtracting the corresponding second high level duration from the first high level duration corresponding to the current phase.

[0030] Preferably, when the pulse width control signal also includes a distribution position of a high level, the step of determining a sampling signal when entering the current adjustment interval, and determining the pulse width control signal in the current adjustment interval according to the current values ​​of each phase and the sampling signal also includes:

[0031] For any phase, according to the level state corresponding to the sampling signal and the pulse width control signal in the current adjustment interval, the distribution position of the high level in the pulse width control signal is determined as the pulse width control waveform in the current adjustment interval.

[0032] Preferably, the step of determining the distribution position of the high level in the pulse width control signal comprises:

[0033] Determine whether the level states corresponding to the sampling signals are all the same; if they are all the same, then the end time of the high level corresponding to the pulse width control signal in the current adjustment interval is continuous with the start time corresponding to the sampling signal in the current adjustment interval;

[0034] Or the start time of the high level corresponding to the pulse width control signal in the current adjustment interval is continuous with the end time corresponding to the sampling signal in the previous adjustment interval.

[0035] Preferably, after the step of determining whether the level states corresponding to the sampling signals are all the same, the step further includes:

[0036] If they are not the same, then determine whether the level state corresponding to the sampling signal is from high to low, and if so, the end time of the high level corresponding to the pulse width control signal in the current adjustment interval is continuous with the start time corresponding to the sampling signal in the current adjustment interval;

[0037] Or if they are not the same, determine whether the level state corresponding to the sampling signal is from low to high; if so, the start time of the high level corresponding to the pulse width control signal in the current adjustment interval is continuous with the end time corresponding to the sampling signal in the previous adjustment interval.

[0038] In a second aspect, the present invention further provides a single resistor sampling device, comprising:

[0039] Memory for storing computer programs;

[0040] A processor is used to execute the computer program to implement the steps of the single resistor sampling method as described in any one of the first aspects.

[0041] The beneficial effects of the embodiments of the present invention are as follows:

[0042] The present invention obtains the current values ​​of each phase corresponding to the motor in the previous adjustment interval. When entering the current adjustment interval, the sampling signal is determined, and then the pulse width control signal under the current adjustment interval is determined according to the current values ​​of each phase and the sampling signal, and the pulse width adjustment signal is obtained to drive and control the motor. Among them, the pulse width adjustment signal includes three phase current modulation signals, each phase current modulation signal corresponds to the three phases of the motor respectively, and the phase current modulation signal includes a sampling signal and a pulse width control signal; the pulse width control signal is set before the sampling signal. Finally, the current of each phase corresponding to the motor in the current adjustment interval is sampled according to the sampling signal. Based on this, the present invention is based on the pre-set sampling signal to avoid generating additional phase shift steps during the sampling process, and according to the pulse width control signal matching the level state corresponding to the sampling signal, the adjustment times of each phase level are adjusted to reduce the noise of the motor; at the same time, the sampling signal is used to obtain the current signal corresponding to the current adjustment interval, so as to avoid the influence of the previous adjustment interval on the sampling current of the current adjustment interval, and thus obtain a more accurate sampling value. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0044] Figure 1 The schematic diagram of the circuit for sampling a single resistor;

[0045] Figure 2 This is an example diagram of a conventional pulse width modulation signal;

[0046] Figure 3 A flow chart of the steps of a single resistor sampling method provided by the present invention;

[0047] Figure 4 This is one of the example diagrams of the pulse width phase current modulation signal in the present invention;

[0048] Figure 5 It is one of the sub-step schematic diagrams of step 103 in the present invention;

[0049] Figure 6 It is a schematic diagram of the steps of step 201 in the present invention;

[0050] Figure 7 This is the second example diagram of the pulse width phase current modulation signal in the present invention;

[0051] Figure 8 It is a schematic diagram of the steps of step 202 in the present invention;

[0052] Fig. 9 This is the third example diagram of the pulse width phase current modulation signal in the present invention;

[0053] Figure 10 a ) is a fourth example diagram of a pulse width phase current modulation signal in the present invention;

[0054] Figure 10 b ) is a fifth example diagram of a pulse width phase current modulation signal in the present invention;

[0055] Figure 10 c ) is a sixth example diagram of a pulse width phase current modulation signal in the present invention;

[0056] Fig.11 This is the second schematic diagram of the sub-steps of step 103 in the present invention;

[0057] Figure 12 a ) is the seventh example diagram of the pulse width phase current modulation signal in the present invention;

[0058] Figure 12 b ) is an eighth example diagram of a pulse width phase current modulation signal in the present invention;

[0059] Figure 13 ( a ) is a ninth example of a pulse width phase current modulation signal in the present invention;

[0060] Figure 13 ( b ) is a tenth example diagram of a pulse width phase current modulation signal in the present invention;

[0061] Fig.14 The eleventh example of the pulse width phase current modulation signal in the present invention;

[0062] Fig.15 This is the twelfth example of the pulse width phase current modulation signal in the present invention. DETAILED DESCRIPTION

[0063] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0064] The conventional single resistor sampling method usually samples twice in one sampling cycle, and each sampling requires a combination of different non-zero vectors to obtain the corresponding phase currents of any two phases in the motor, and then determine the phase current of the third phase based on the relationship between the phase currents in the motor. However, since the change and stabilization of the current requires a certain amount of time, the corresponding sampling cycle needs to be greater than the minimum value of the non-zero vector duration, that is, the sampling window value described in this article. If it is found during the sampling process that the corresponding sampling cycle is less than the sampling window value, the accurate current value cannot be determined within the corresponding sampling cycle. In order to sample a more accurate current value, the prior art usually shifts the phase, for example, during the process of generating the pulse width control signal, the pulse width of the corresponding phase is moved to the left so that the sampling period after the shift is greater than the corresponding sampling window value. However, this method will greatly increase the three-phase output voltage distortion, affect the stability of the motor operation, and thus make single resistor sampling unable to be applied to scenes with high noise.

[0065] Based on this, the present invention provides a single resistor sampling solution, so that accurate current can be sampled without phase shifting without changing the single resistor sampling circuit, and the motor noise can be reduced.

[0066] The inventive concept will be described in detail below.

[0067] Please refer to Figure 3 In a first aspect, the present invention provides a single resistor sampling method, the single resistor sampling method comprising the following steps:

[0068] Step 101: Obtain the current value of each phase corresponding to the motor in the previous adjustment interval.

[0069] Step 102: When entering the current adjustment interval, determine the sampling signal, wherein the preset sampling intervals corresponding to the sampling signals are all greater than the sampling window time.

[0070] Step 103: determine the pulse width control signal in the current adjustment interval according to the current value of each phase and the sampling signal, and obtain the pulse width adjustment signal to drive and control the motor.

[0071] Among them, the pulse width modulation signal includes three phase current modulation signals, each phase current modulation signal corresponds to the three phases of the motor respectively, and the phase current modulation signal includes a sampling signal and a pulse width control signal; the pulse width control signal is set before the sampling signal.

[0072] Step 104: Sample the currents of each phase corresponding to the motor in the current adjustment range according to the sampling signal.

[0073] It should be noted that the pulse width modulation signal in this embodiment is the PWM signal used in motor regulation to control the three-phase voltage of the motor. Figure 4 The pulse width modulation signal includes two parts: a sampling signal and a pulse width control signal. The sampling signal is arranged after the pulse width control signal, and t1 and t2 correspond to the level duration in the sampling signal respectively.

[0074] Continue to refer to the above Figure 4 , the pulse width control signal is on the left side of the pulse width regulation signal. Based on this, in this embodiment, the corresponding three-phase voltage can be adjusted by the pulse width control signal in the current regulation interval, and then the adjusted three-phase voltage in the current regulation interval can be obtained through the sampling signal corresponding to the sampling part, so as to obtain a more accurate sampling value.

[0075] In this embodiment, it is necessary to first set the sampling period corresponding to the sampling signal to a parameter greater than the sampling window time when entering the current adjustment period. In this embodiment, there is no need to perform a phase shift operation to ensure the accuracy of the sampled value. In a possible implementation, the sampling signal in this embodiment can be a combination of two non-zero vectors, and can remain unchanged in each adjustment interval, so as to sample the phase currents of any two phases in each adjustment period without the need to perform a secondary determination of the sampling object. It should be noted that in this embodiment, the sampling signal samples the current or voltage signal adjusted by the pulse width control signal corresponding to the current adjustment interval.

[0076] In addition, in this embodiment, the pulse width control signal in the current adjustment interval can be constructed based on the phase current corresponding to the previous adjustment interval and the sampling signal. It should be noted that the sampling signal and the pulse width control signal in the present invention are correlated, and the number of flips of each phase level of the pulse width adjustment signal in the current adjustment interval can be reduced based on this, so as to reduce the switching loss of the device that executes the pulse width adjustment signal.

[0077] Taking the frequency conversion circuit that executes the pulse width modulation signal as an example, when the pulse width modulation signal has too many level flips in the current adjustment cycle, the switching loss corresponding to the frequency conversion circuit will be greatly increased, the temperature of the frequency conversion device will increase, and the device performance corresponding to the frequency conversion circuit will be affected. This embodiment can reduce the number of level flips of the pulse width modulation signal in the current adjustment cycle through the correlation between the sampling signal and the pulse width control signal, thereby ensuring the device performance.

[0078] Please refer to Figure 5In one possible implementation, when the pulse width control signal includes a high level duration, step 103 of determining the pulse width control signal in the current adjustment interval according to each phase current value and the sampling signal includes steps 201 to 203.

[0079] Step 201: Determine the first high level duration corresponding to the current modulation signal of each phase in the current regulation interval according to the current value of each phase.

[0080] Step 202: For any phase, determine the second high level duration corresponding to the down-sampled signal of the current phase.

[0081] Step 203: determine the third high level duration of each pulse width control signal in the current adjustment interval according to each first high level duration and the second high level duration of the corresponding phase, and obtain the pulse width control signal in the current adjustment interval.

[0082] In this embodiment, the first high level duration corresponding to each phase can be determined based on the current value of each phase corresponding to the motor in the previous adjustment interval, that is, the high level duration under the phase current modulation signal corresponding to each phase. Since each phase current modulation signal in the pulse width modulation signal includes a sampling signal and a pulse width control signal in the modulation interval, that is, the sampling signal and the pulse width control signal corresponding to each phase are in a continuous state in time, based on this, the first high level duration corresponding to each phase current modulation signal can be equal to the sum of the high level durations of the corresponding sampling signal and the pulse width control signal. Once the second high level duration corresponding to the sampling signal is determined, the high level duration of the pulse width control signal, that is, the third high level duration, can be calculated accordingly.

[0083] In one possible implementation, please refer to Figure 6 The step 201 of determining the first high level duration corresponding to the current modulation signal of each phase in the current adjustment interval according to the current value of each phase includes steps 301 to 303.

[0084] Step 301, obtaining the motor's own parameters and the total time corresponding to the current adjustment interval;

[0085] Step 302, determining the voltage of each phase corresponding to the current adjustment interval according to its own parameters and the current value of each phase;

[0086] Step 303: determine the first high level duration corresponding to each phase current modulation signal in the current regulation interval according to each phase voltage and the total time.

[0087] This embodiment can determine the three-phase voltage required to be executed in the current adjustment interval based on the motor's own parameters, such as the motor speed and other information, and the current values ​​of each phase corresponding to the motor in the previous adjustment interval obtained first, and then determine the first high-level duration of the corresponding phase based on the corresponding bus voltage and phase voltage formula. Taking the U phase as an example, the calculation formula of the corresponding first high-level duration T1 satisfies: T1=T*(Uu / Udc), where Udc is the bus voltage, Uu is the voltage corresponding to the U phase, and T is the time corresponding to the adjustment interval.

[0088] Then, the corresponding second high level duration is determined according to the type of the sampling signal, such as the combination of non-zero vectors, and the third high level duration is determined according to the first high level duration and the second high level duration to obtain the corresponding pulse width control signal.

[0089] In one possible implementation, the sampling signal may include at least two consecutive preset sampling intervals, each preset sampling interval corresponds to a different non-zero vector, wherein each preset sampling interval is greater than the sampling window time. In this embodiment, when the non-zero vector is composed of three pseudo-random codes, such as 001, each pseudo-random code corresponds to each phase of the motor, for example, the level states corresponding to the U phase, V phase and W phase of the motor are 0, 0 and 1, respectively, wherein the sampling period corresponding to the sampling signal is greater than the duration of each level state, that is, each preset sampling interval is greater than the sampling window time. In this embodiment, the non-zero vector may be the following 6 types: 001, 010, 011, 100, 101, 110, wherein the combination of two different non-zero vectors may correspond to 30 combinations, and each combination may respectively determine a sampling signal. Please refer to Figure 7 This embodiment provides a pulse width phase current modulation signal corresponding to the non-zero vector combinations corresponding to the sampling signal: 001, 011, wherein the level duration corresponding to the preset sampling signal needs to be greater than the sampling window time to determine the second high level duration corresponding to the sampling signal, that is, the period of the preset sampling intervals corresponding to t1 and t2 respectively needs to be greater than the sampling window value T min (There is a minimum value for non-zero vector duration).

[0090] Please refer to Figure 8 Based on the above sampling signal, in this embodiment, for any phase, step 202 of determining the second high level duration corresponding to the sampling signal in the current phase includes steps 401 and 402.

[0091] Step 401 : Determine the conduction duration of each non-zero vector under a sampling signal according to the level state of each non-zero vector in the corresponding preset sampling interval, wherein each preset sampling interval is greater than the sampling window time.

[0092] Step 402: Use the sum of the conduction durations corresponding to all non-zero vectors as the second high-level duration corresponding to the current-phase downsampled signal.

[0093] In a possible implementation manner, step 401 of determining the conduction duration of each non-zero vector in the sampling signal according to the level state of each non-zero vector in the corresponding preset sampling interval is specifically as follows:

[0094] If the level state is low level, the conduction duration of the non-zero vector in the current preset sampling interval is zero. If the level state is high level, the conduction duration of the non-zero vector in the current preset sampling interval is the time corresponding to the preset sampling period.

[0095] Please continue to refer to Figure 7 , when the non-zero vector combinations corresponding to the sampling signal are: 001, 010, and the time periods corresponding to the respective preset sampling intervals are t1, t2, which are the periods of the second preset sampling interval described below. Among them, the second high-level durations corresponding to each phase are: T 2u =0; T 2v =t2; T 2w =t1 + t2; t1 < t2. Among them, T 2u is the second high-level duration corresponding to the first phase; T 2v is the second high-level duration corresponding to the second phase; T 2w is the second high-level duration corresponding to the third phase; t1 is the period of the first preset sampling interval; t2 is the period of the second preset sampling interval.

[0096] In this embodiment, taking the U phase as an example, at this time, the level states corresponding to the first preset sampling interval and the second preset sampling interval are: 0, 0, then the corresponding second high-level duration T 2u is zero.

[0097] Similarly, in this embodiment, taking the V phase as an example, at this time, the level states corresponding to the first preset sampling interval and the second preset sampling interval are: 0, 1, then the corresponding second high-level duration T 2v then satisfies: T 2v =t2.

[0098] Similarly, in this embodiment, taking the W phase as an example, at this time, the level states corresponding to the first preset sampling interval and the second preset sampling interval are: 1, 1, then the corresponding second high-level duration T 2w then satisfies: T 2w ==t1 + t2.

[0099] Similarly, please refer to Fig. 9, when the non-zero vector combinations corresponding to the sampling signal are: 001, 010, and the time periods corresponding to the preset sampling intervals are t1, t2, which are the periods of the second preset sampling intervals described below. Among them, the second high level duration corresponding to each phase is: T 2u =0; T 2v =t2; T 2w =t1; t1 <t2。

[0100] In this embodiment, taking the U phase as an example, at this time, the level states corresponding to the first preset sampling interval and the second preset sampling interval are: 0, 0 respectively, then the corresponding second high level duration T at this time 2u is zero.

[0101] Similarly, in this embodiment, taking the V phase as an example, at this time, the level states corresponding to the first preset sampling interval and the second preset sampling interval are: 0 and 1 respectively, then the corresponding second high level duration T at this time 2v Then it satisfies: T 2v =t2.

[0102] Similarly, in this embodiment, taking the W phase as an example, the level states corresponding to the first preset sampling interval and the second preset sampling interval are 1 and 0 respectively, and the corresponding second high level duration T at this time is 2w Then it satisfies: T 2w =t1.

[0103] Based on this, the third high level duration can be determined according to the first high level duration and the second high level duration corresponding to each phase current modulation signal to obtain the corresponding pulse width control signal, especially the pulse width corresponding to each pulse width control signal, that is, the third high level signal.

[0104] In a possible implementation, step 303 of determining the first high level duration corresponding to the current modulation signal of each phase in the current regulation interval according to the voltage of each phase and the total time is:

[0105] For any phase, the third high level duration of each pulse width control signal in the current adjustment interval is obtained by subtracting the corresponding second high level duration from the first high level duration corresponding to the current phase.

[0106] Based on this, the pulse width adjustment signal corresponding to the current phase can be obtained according to the pulse width control signal corresponding to the sampling signal. It should be noted that in this embodiment, the sampling signal is set at the back end of the pulse width control signal, so that in the current adjustment cycle, the motor phase voltage is first adjusted according to the corresponding pulse width control signal, and then the corresponding sampling signal is used for sampling, so as to obtain a more accurate voltage sampling value in the current adjustment cycle, thereby avoiding the pulse width control signal corresponding to the previous adjustment interval affecting the sampling value of the current adjustment interval.

[0107] Since the above embodiment only determines the duration of the third high level, the proportion of the high level in the current adjustment interval, for example, the duty cycle, can be limited accordingly. However, since the distribution position of the high level in the pulse width control signal is uncertain, please refer to FIG. 10 ( a )、Figure 10( b ) and Figure 10 ( c ), among which Figure 10 ( a )、Figure 10( b ) and Figure 10 ( c ) show different distributions of high levels in the pulse width control signal. At this time, it can be seen that the corresponding high level position can be set at the leftmost, rightmost or middle position of the pulse width control signal. Different distribution positions will result in different number of level flips of the pulse width modulation signal in an adjustment interval.

[0108] Specifically, please refer to Figure 10 ( a ), when the non-zero vector combinations corresponding to the sampling signals are: 001, 010, and the high level of the pulse width control signal is distributed at the leftmost of the pulse width modulation signal, that is, the high level part of the pulse width control signal at this time is continuous with the end time of the sampling signal in the pulse width modulation signal under the previous adjustment interval, at this time, taking the U phase as an example, the phase current modulation signal corresponding to the U phase flips twice. Similarly, the phase current modulation signal corresponding to the V phase flips twice, and the phase current modulation signal corresponding to the W phase flips 4 times.

[0109] Similarly, please refer to Figure 10 ( b ), when the non-zero vector combinations corresponding to the sampling signals are: 001, 010, and the high level of the pulse width control signal is distributed on the rightmost side of the pulse width modulation signal, that is, the high level part of the pulse width control signal at this time is continuous with the starting time of the sampling signal in the pulse width modulation signal under the current adjustment interval, at this time, taking the U phase as an example, the phase current modulation signal corresponding to the U phase flips 2 times. Similarly, the phase current modulation signal corresponding to the V phase flips 4 times, and the phase current modulation signal corresponding to the W phase flips 2 times.

[0110] Similarly, please refer to Figure 10 ( c), when the non-zero vector combinations corresponding to the sampling signals are: 001, 010, and the high level distribution in the pulse width control signal is in the middle of the pulse width modulation signal, at this time, taking the U phase as an example, the phase current modulation signal corresponding to the U phase flips 2 times. Similarly, the phase current modulation signal corresponding to the V phase flips 4 times, and the phase current modulation signal corresponding to the W phase flips 4 times.

[0111] Frequent level flipping will increase device loss. Based on this, in order to reduce the number of level flipping, this embodiment can determine the distribution position of the high level in the pulse width control signal according to the level state corresponding to the sampling signal and the pulse width control signal in the current adjustment range.

[0112] In one possible implementation, please refer to Fig.11 , when entering the current regulation interval, determining the sampling signal, and determining the pulse width control signal in the current regulation interval according to the current value of each phase and the sampling signal, step 103 also includes step 204:

[0113] For any phase, according to the level state corresponding to the sampling signal and the pulse width control signal in the current adjustment interval, the distribution position of the high level in the pulse width control signal is determined as the pulse width control waveform in the current adjustment interval.

[0114] In this embodiment, the step 204 of determining the distribution position of the high level in the pulse width control signal according to the level state corresponding to the sampling signal and the pulse width control signal in the current adjustment interval includes step 501:

[0115] Step 501: determine whether the level states corresponding to the sampling signals are all the same. If they are the same, the high level corresponding to the pulse width control signal in the current adjustment interval is continuous with the sampling signal.

[0116] Please refer to FIG. 12 (a). When the level states corresponding to the sampling signals are all low levels, the start time of the high level corresponding to the pulse width control signal in the current adjustment interval is continuous with the end time corresponding to the sampling signal in the previous adjustment interval.

[0117] Please refer to FIG. 12 ( b ). When the level states corresponding to the sampling signals are all low levels, the end time of the high level corresponding to the pulse width control signal in the current adjustment interval is continuous with the start time corresponding to the sampling signal in the current adjustment interval.

[0118] Please refer to FIG. 13 (a). When the level states corresponding to the sampling signals are all high level, the start time of the high level corresponding to the pulse width control signal in the current adjustment interval is continuous with the end time corresponding to the sampling signal in the previous adjustment interval.

[0119] Please refer to FIG. 13 ( b ). When the level states corresponding to the sampling signals are all low levels, the end time of the high level corresponding to the pulse width control signal in the current adjustment interval is continuous with the start time corresponding to the sampling signal in the current adjustment interval.

[0120] It can be seen from the diagram in the above embodiment that the corresponding level flipping times is two, and the flipping times of each phase level can be further adjusted to reduce the noise of the motor.

[0121] In this embodiment, step 502 is included after step 501 of determining whether the level states corresponding to the sampling signals are the same.

[0122] Step 502: If they are not the same, determine whether the level state corresponding to the sampling signal is from high to low. If so, the end time of the high level corresponding to the pulse width control signal in the current adjustment interval is continuous with the start time corresponding to the sampling signal in the current adjustment interval.

[0123] Please refer to Fig.14 When the level state corresponding to the sampling signal is from high to low, the end time of the high level corresponding to the pulse width control signal in the current adjustment interval is continuous with the start time corresponding to the sampling signal in the current adjustment interval.

[0124] In this embodiment, step 503 is included after step 501 of determining whether the level states corresponding to the sampling signals are the same.

[0125] Step 503: If they are not the same, determine whether the level state corresponding to the sampling signal is from low to high. If so, the start time of the high level corresponding to the pulse width control signal in the current adjustment interval is continuous with the end time corresponding to the sampling signal in the previous adjustment interval.

[0126] Please refer to Fig.15 When the level state corresponding to the sampling signal is from low to high, the start time of the high level corresponding to the pulse width control signal in the current adjustment interval is continuous with the end time corresponding to the sampling signal in the previous adjustment interval.

[0127] Based on this, the present embodiment provides a single resistor sampling method. After the sampling signal is determined, the high level duration and the distribution position of the high level in the pulse width control signal can be determined according to the level state of the sampling signal, so as to avoid adding additional phase shifting steps in the sampling process, and ensure that the corresponding pulse width control signal flips the least number of times within an adjustment interval, thereby reducing the noise of the motor, obtaining a more accurate sampling value, and avoiding the interference of the previous adjustment interval on the current adjustment interval.

[0128] In a second aspect, the present invention further provides a single resistor sampling device, comprising: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of any one of the single resistor sampling methods of the first aspect.

[0129] It should be noted that the single resistor sampling device provided in this embodiment can execute the method flow shown in the above single resistor sampling method flow implementation method to achieve the corresponding technical effect. For the sake of brief description, for the parts not mentioned in this embodiment, please refer to the corresponding contents in the above embodiment.

[0130] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0131] In addition, the functional modules in the various embodiments of the present invention may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0132] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, and other media that can store program codes.

[0133] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A single resistor sampling method, characterized in that: The single resistance sampling method comprises the following steps: Obtain the current value of each phase corresponding to the motor in the previous adjustment interval; When entering the current adjustment interval, determining a sampling signal, wherein the preset sampling interval corresponding to the sampling signal is greater than the sampling window time; And determine the pulse width control signal in the current adjustment interval according to the current value of each phase and the sampling signal, and obtain the pulse width adjustment signal to drive and control the motor; Wherein, the pulse width modulation signal includes three phase current modulation signals, each phase current modulation signal corresponds to the three phases of the motor respectively, and the phase current modulation signal includes a sampling signal and a pulse width control signal; the pulse width control signal is set before the sampling signal; Sampling each phase current corresponding to the motor in the current adjustment range according to the sampling signal; When the pulse width control signal includes a high level duration, the step of determining the pulse width control signal in the current adjustment interval according to the current values ​​of each phase and the sampling signal includes: Determine the first high level duration corresponding to the current modulation signal of each phase in the current regulation interval according to the current value of each phase; For any phase, determining the second high level duration corresponding to the sampling signal of the current phase; Determine the third high level duration of each pulse width control signal in the current adjustment interval according to each first high level duration and the second high level duration of the corresponding phase, and obtain the pulse width control signal in the current adjustment interval; When the sampling signal includes at least two consecutive preset sampling intervals, and each preset sampling interval corresponds to a different non-zero vector, the step of determining the second high level duration corresponding to the sampling signal in the current phase for any phase includes: Determining the conduction duration of each non-zero vector under the sampling signal according to the level state of each non-zero vector in the corresponding preset sampling interval; The sum of the conduction durations corresponding to all non-zero vectors is used as the second high level duration corresponding to the current phase down-sampling signal; Wherein, each of the preset sampling intervals is greater than the sampling window time.

2. The single resistor sampling method according to claim 1, characterized in that: The step of determining the conduction duration of each non-zero vector under the sampling signal according to the level state of each non-zero vector in the corresponding preset sampling interval includes: If the level state is a low level, the conduction duration of the non-zero vector in the current preset sampling interval is zero; If the level state is a high level, the conduction duration of the non-zero vector in the current preset sampling interval is the time corresponding to the preset sampling period.

3. The single resistor sampling method according to claim 1, characterized in that: When the sampling signal includes two consecutive preset sampling intervals, and the corresponding non-zero vectors in each preset sampling interval are 001 and 011 respectively, the second high level duration corresponding to each phase satisfies: T 2u =0; T 2v =t2; T 2w =t1+t2; t1< t2 Among them, T 2u is the duration of the second high level corresponding to the first phase; T 2v is the second high level duration corresponding to the second phase; T 2w is the second high level duration corresponding to the third phase; t1 is the period of the first preset sampling interval; and t2 is the period of the second preset sampling interval.

4. The single resistor sampling method according to claim 1, characterized in that: The step of determining the third high level duration of each pulse width control signal in the current adjustment interval according to each first high level duration and the second high level duration of the corresponding phase comprises: For any phase, the third high level duration of each pulse width control signal in the current adjustment interval is obtained by subtracting the corresponding second high level duration from the first high level duration corresponding to the current phase.

5. The single resistor sampling method according to claim 1, characterized in that: When the pulse width control signal also includes a distribution position of a high level, the step of determining a sampling signal when entering the current adjustment interval, and determining the pulse width control signal in the current adjustment interval according to the current values ​​of each phase and the sampling signal also includes: For any phase, according to the level state corresponding to the sampling signal and the pulse width control signal in the current adjustment interval, the distribution position of the high level in the pulse width control signal is determined as the pulse width control waveform in the current adjustment interval.

6. The single resistor sampling method according to claim 5, characterized in that: The step of determining the distribution position of the high level in the pulse width control signal comprises: Determine whether the level states corresponding to the sampling signals are all the same; if they are all the same, then the end time of the high level corresponding to the pulse width control signal in the current adjustment interval is continuous with the start time corresponding to the sampling signal in the current adjustment interval; Or the start time of the high level corresponding to the pulse width control signal in the current adjustment interval is continuous with the end time corresponding to the sampling signal in the previous adjustment interval.

7. The single resistor sampling method according to claim 6, characterized in that: After the step of determining whether the level states corresponding to the sampling signals are the same, the method further includes: If they are not the same, then determine whether the level state corresponding to the sampling signal is from high to low, and if so, the end time of the high level corresponding to the pulse width control signal in the current adjustment interval is continuous with the start time corresponding to the sampling signal in the current adjustment interval; Or if they are not the same, determine whether the level state corresponding to the sampling signal is from low to high; if so, the start time of the high level corresponding to the pulse width control signal in the current adjustment interval is continuous with the end time corresponding to the sampling signal in the previous adjustment interval.

8. A single resistor sampling device, characterized in that: include: Memory for storing computer programs; A processor is used to execute the computer program to implement the steps of the single resistor sampling method according to any one of claims 1 to 7.

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