Packaging structure and preparation method thereof, circuit board and electronic device

Abstract

The present application relates to a packaging structure and a preparation method thereof, as well as a circuit board and an electronic device. The packaging structure includes a stacked structure, the stacked structure includes a dielectric layer, and the dielectric layer includes a first dielectric layer and a second dielectric layer; at least one side of the first dielectric layer is provided with a second dielectric layer, and a power device is buried in the first dielectric layer. The packaging structure not only eliminates the need for a housing, a sealant, etc., thereby improving the degree of integration, but also can, to a certain extent, block the heat generated by the power device from being transferred to at least one side of the packaging structure, thereby alleviating the thermal impact of the power device on other components on the corresponding surface of the packaging structure when the power device is working.

Description

Technical Field

[0001] The present application relates to the field of semiconductor packaging technology, and in particular to a packaging structure, a method for preparing a packaging structure, a circuit board, and an electronic device. Background Art

[0002] System-in-Package (SIP) technology is an integrated circuit packaging technology that integrates multiple devices into a single package, which increases the integration of the finished device, reduces the size and power consumption. The high integration, high efficiency and high power of the system-in-package power module have brought good news to the fields of power conversion and motor control.

[0003] At present, most packaged power modules still use a ternary structure of power device-bonding wire-substrate. The working principle of this structure can be summarized as follows: the bottom of the power device is welded to the copper-clad ceramic board (DBC), and the surface electrode of the power device is connected to the DBC through bonding wires. The power device and other devices are electrically connected through bonding wires and the upper copper layer of the DBC. This ternary structure usually has the following disadvantages, including: the power module has a low operating frequency, and the bonding wire introduces a large parasitic inductance, which leads to more serious overvoltage, parasitic oscillation, and electromagnetic interference (EMI) under high-frequency current changes. The packaged power module still needs to be mounted on the surface of the circuit board, resulting in area waste and increasing the product volume. In order to ensure the stability of the power module, potting glue needs to be injected into the shell, making the product heavier.

[0004] In order to meet the development requirements of miniaturization, integration and high frequency of packaged power modules, the related technology uses embedded packaging technology to integrate power devices from the surface of the substrate to the inside of the substrate. However, the packaged power module prepared by the embedded packaging technology generates a lot of heat during operation, which is easy to affect other devices set on the surface of the packaged power module. Summary of the invention

[0005] The embodiments of the present application provide a packaging structure to at least partially solve the above technical problems.

[0006] In order to achieve the above-mentioned purpose, according to the first aspect of the present application, a packaging structure is provided, including a stacked structure, the stacked structure includes a dielectric layer, the dielectric layer includes a first dielectric layer and a second dielectric layer; the second dielectric layer is arranged on at least one side of the first dielectric layer, and a power device is buried in the first dielectric layer.

[0007] Optionally, the packaging structure further includes protective layers located on opposite sides of the stacked structure, at least one of the protective layers is provided with a pad, and the second dielectric layer is located between the first dielectric layer and the protective layer provided with the pad.

[0008] Optionally, a heat insulation structure is embedded in the second dielectric layer.

[0009] Optionally, the thermal insulation structure corresponds to the power device.

[0010] Optionally, the thermal insulation structure comprises an insulating covering layer and a thermal insulation core layer, and the insulating covering layer covers the surface of the thermal insulation core layer.

[0011] Optionally, the thermal insulation core layer comprises a thermal insulation material, and the thermal insulation material includes at least one of asbestos, aerogel, rock wool, vacuum board and graphite felt.

[0012] Optionally, the stacked structure further includes a circuit layer, the power device is electrically connected to the circuit layer, and the pad is electrically connected to the circuit layer.

[0013] Optionally, the circuit layer includes a first circuit layer and a second circuit layer; the first circuit layer is adjacent to the first dielectric layer, the power device is electrically connected to the first circuit layer, the second circuit layer is adjacent to the protective layer, and the pad is electrically connected to the second circuit layer.

[0014] Optionally, a heat sink is embedded in the first dielectric layer, the power device is disposed on the heat sink, and a heat dissipation end surface of the heat sink extends out of the first dielectric layer.

[0015] Optionally, the stacked structure further includes a first circuit layer; a first electrode connection layer is further embedded in the first dielectric layer, and the power device is connected to the first circuit layer via the first electrode connection layer.

[0016] Optionally, the first dielectric layer includes a first body portion and a first packaging portion, and the power device and the first electrode connection layer are buried in the first packaging portion.

[0017] Optionally, the power device has a surface electrode, the surface electrode includes three independent sub-surface electrodes; the first electrode connection layer includes three independent sub-electrode connection layers; the sub-surface electrodes are connected to the sub-electrode connection layers in a one-to-one correspondence.

[0018] Optionally, a heat sink is buried in the first dielectric layer, and the heat sink includes an insulating body and a conductive layer and a thermal conductive layer located on two opposite surfaces of the insulating body; the power device has a first surface and a second surface opposite to each other, one of the three sub-surface electrodes is distributed on the second surface, and the other two are distributed on the first surface at intervals; the sub-surface electrode located on the second surface is connected to the conductive layer, and the conductive layer is also connected to one of the sub-electrode connecting layers; the thermal conductive layer partially extends out of the first dielectric layer.

[0019] Optionally, the dielectric layer further includes a third dielectric layer, the third dielectric layer is located on one side of the first dielectric layer, and a second device is buried in the third dielectric layer.

[0020] Optionally, the stacked structure further includes a third circuit layer, wherein the third circuit layer is adjacent to the third dielectric layer and is electrically connected to the second device.

[0021] Optionally, the second device includes at least one of a passive device and a control chip.

[0022] Optionally, a second electrode connection layer is further embedded in the third dielectric layer, and the second device is connected to the third circuit layer via the second electrode connection layer.

[0023] Optionally, the third dielectric layer includes a second body portion and a second packaging portion, and the second device and the second electrode connection layer are buried in the second packaging portion.

[0024] Optionally, the second dielectric layer is located between the first dielectric layer and the third dielectric layer.

[0025] Optionally, the packaging structure is provided with a metallized through hole, and the metallized through hole passes through the stacked structure and is electrically connected to the circuit layer.

[0026] Optionally, the packaging structure further includes a conductive column, which is disposed in the stacked structure and is electrically connected to the circuit layer.

[0027] Optionally, the dielectric layer is an organic dielectric layer, which includes a resin and a reinforcing material, the resin includes at least one of epoxy resin, polytetrafluoroethylene, phenolic resin, polyphenylene ether and bismaleimide triazine resin, and the reinforcing material includes at least one of a paper base, glass cloth and a metal core.

[0028] Optionally, the thickness of the circuit layer is 0.5Oz~4Oz.

[0029] Optionally, the circuit layer comprises at least one of copper, silver and gold.

[0030] Optionally, the power device includes a silicon carbide power device.

[0031] According to a second aspect of the present application, a method for preparing a packaging structure is provided, comprising:

[0032] Providing a first substrate and a second substrate, wherein the first substrate includes a first dielectric sheet, and the second substrate includes a second dielectric sheet;

[0033] embedding a power device in the first dielectric sheet of the first substrate;

[0034] The first substrate and the second substrate are stacked together and subjected to a first heat pressing process to obtain a packaging structure.

[0035] According to a third aspect of the present application, a circuit board is also provided, which includes the above-mentioned packaging structure.

[0036] According to a fourth aspect of the present application, an electronic device is also provided, the electronic device comprising the above-mentioned circuit board.

[0037] The packaging structure provided in the embodiment of the present application buries the power device in the first dielectric layer of the stacked structure, which eliminates the need for a housing, sealant, etc., reduces the volume and weight of the packaging module, and improves the degree of integration. The stacked structure also includes a second dielectric layer, which is located on at least one side of the first dielectric layer, so that the second dielectric layer can, to a certain extent, block the heat generated by the power device from being transferred to at least one side of the surface of the packaging structure, thereby alleviating the thermal impact of the power device on other components on the corresponding surface of the packaging structure when the power device is working.

[0038] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0040] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same figure numbers represent the same parts in the following description.

[0041] Figure 1 is a schematic cross-sectional structural diagram of a packaging structure provided in an exemplary embodiment of the present disclosure;

[0042] Figure 2 yes Figure 1 A magnified schematic diagram of part A;

[0043] Figure 3 yes Figure 1 A magnified schematic diagram of part B;

[0044] Figure 4 yes Figure 1 A magnified schematic diagram of part C;

[0045] Figure 5 is a flow chart of a method for preparing a packaging structure provided in an exemplary embodiment of the present disclosure;

[0046] Figure 6~Figure 10 is a flow chart of preparing a packaging structure provided in an exemplary embodiment of the present disclosure;

[0047] Fig.11 is a schematic structural diagram of an electronic device provided in an exemplary embodiment of the present disclosure.

[0048] Description of reference numerals:

[0049] 10. Packaging structure;

[0050] 1. Layered structure;

[0051] 11, circuit layer; 111, first circuit layer; 112, second circuit layer; 113, third circuit layer;

[0052] 12, dielectric layer; 121, first dielectric layer; 121a, first main body; 121b, first packaging part; 122, second dielectric layer; 123, third dielectric layer; 123a, second main body; 123b, second packaging part;

[0053] 13. power device; 13a. first surface; 13b. second surface;

[0054] 131, first electrode connection layer; 131a, first sub-electrode connection layer; 131b, second sub-electrode connection layer; 131c, third sub-electrode connection layer;

[0055] 132, heat sink; 132a, insulating body; 132b, conductive layer; 132c, heat conducting layer;

[0056] 133, surface electrode; 133a, first sub-surface electrode; 133b, second sub-surface electrode; 133c, third sub-surface electrode;

[0057] 14. second device; 141. second electrode connection layer;

[0058] 15. thermal insulation structure; 151. thermal insulation core layer; 152. insulation cover layer;

[0059] 16. Metallized through holes;

[0060] 17. Conductive column;

[0061] 2. Protective layer; 2a. First protective layer; 2b. Second protective layer; 21. Pad;

[0062] 3. first substrate; 31. first dielectric sheet; 32. metal layer; 33. first mounting groove; 34. first hole; 35. second mounting groove; 36. second hole; 37. first positioning hole; 38. first mounting hole;

[0063] 301, first sub-base plate; 302, second sub-base plate; 4, second base plate; 41, second dielectric sheet; 42, second positioning hole; 43, second mounting hole; 44, third mounting groove;

[0064] 100. Circuit board;

[0065] 1000. Electronic equipment. DETAILED DESCRIPTION

[0066] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0067] First, see Figures 1 to 4 and Fig.11 The embodiment of the present application provides a packaging structure 10, which is used in an electronic device 1000, including but not limited to a mobile terminal, a household appliance, an intelligent robot, and a vehicle. Taking a vehicle as an example, the vehicle includes a vehicle body and a circuit board 100 disposed on the vehicle body, and the packaging structure 10 is disposed on the circuit board 100.

[0068] Specifically, the packaging structure 10 includes a stacked structure 1, the stacked structure 1 includes a dielectric layer 12, the dielectric layer 12 includes a first dielectric layer 121 and a second dielectric layer 122; the second dielectric layer 122 is disposed on at least one side of the first dielectric layer 121, and a power device 13 is buried in the first dielectric layer 121.

[0069] The dielectric layer 12 refers to a non-conductive layer structure, and the dielectric layer 12 is used to electrically isolate some charged structures or charged devices in the stacked structure 1. The dielectric layer 12 can be an organic dielectric layer, which not only has good insulation but also has a heat insulation effect. The organic dielectric layer contains resin, and the resin can include at least one of epoxy resin, polytetrafluoroethylene, phenolic resin, polyphenylene ether (PPO) resin and bismaleimide triazine (BT) resin. The organic dielectric layer can also contain reinforcing materials, which are used to enhance the mechanical strength of the organic dielectric layer, and the reinforcing materials can include at least one of paper base, glass cloth and metal core.

[0070] The dielectric layer 12 includes a first dielectric layer 121 and a second dielectric layer 122, and the first dielectric layer 121 and the second dielectric layer 122 refer to different dielectric layers 12. In the stacked structure 1, the number of layers of the first dielectric layer 121 is at least one layer, that is, it can be one layer or multiple layers. In the stacked structure 1, the number of layers of the second dielectric layer 122 is also at least one layer, that is, it can be one layer or multiple layers. The number of layers of the first dielectric layer 121 and the number of layers of the second dielectric layer 122 can be the same or different.

[0071] The second dielectric layer 122 is disposed on at least one side of the first dielectric layer 121. The second dielectric layer 122 may be disposed on one side of the first dielectric layer 121, or on both sides of the first dielectric layer 121. The first dielectric layer 121 and the second dielectric layer 122 may be disposed adjacent to each other, or may be disposed at intervals. For example, other structures, such as the circuit layer 11, may be disposed between the first dielectric layer 121 and the second dielectric layer 122.

[0072] The first dielectric layer 121 is a power device layer. A power device 13 is embedded in the first dielectric layer 121. Embedding here means embedding an object in whole or in part into another object. The number of power devices 13 embedded in the first dielectric layer 121 can be one or more. The number of layers of the first dielectric layer 121 can be one or more.

[0073] The power device 13, also known as a power electronic device or a power semiconductor device, is an electronic component that can process and control electrical energy. The main function of the power device 13 is to convert electrical energy from one form to another or to transmit electrical energy to other devices. The power device 13 usually needs to withstand higher voltages and currents, and has characteristics such as high withstand voltage, large current, and low internal resistance, which enables the power device 13 to efficiently control and transmit electrical energy in the circuit. Common power devices 13 include power diodes, thyristors (SCRs), insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs), silicon carbide (SiC) power devices, and gallium nitride (GaN) power devices. As an example, the power device 13 is a silicon carbide power device, which has the advantages of low conduction loss, high switching frequency, and high thermal conductivity, thereby having the advantage of miniaturized integration of power modules.

[0074] The second dielectric layer 122 is a heat-insulating layer. The second dielectric layer 122 is located on one side of the first dielectric layer 121. In this way, when the power device 13 is working, the heat generated by the power device 13 will be blocked by the second dielectric layer 122, thereby reducing the heat transfer to at least one side of the surface of the packaging structure 10, thereby reducing the thermal impact on other components arranged on the corresponding surface of the packaging structure 10. The number of layers of the second dielectric layer 122 can be one or more layers. Generally, the more layers of the second dielectric layer 122, the better the heat insulation effect. Usually, one or more second dielectric layers 122 can be arranged on one side of the first dielectric layer 121, and the second dielectric layer 122 is used to block the heat propagation of the first dielectric layer 121, or one or more second dielectric layers 122 can be arranged on both sides of the first dielectric layer 121, and the second dielectric layer 122 is used to block the heat of the first dielectric layer 121 from propagating to both sides.

[0075] The packaging structure 10 provided in the embodiment of the present application buries the power device 13 in the first dielectric layer 121 of the stacked structure 1. This method eliminates the need for a housing, sealant, etc., reduces the volume and weight of the packaging module, and improves the degree of integration. The stacked structure 1 also includes a second dielectric layer 122, which is located on at least one side of the first dielectric layer 121. In this way, the second dielectric layer 122 can, to a certain extent, block the heat generated by the power device 13 from being transferred to at least one side of the surface of the packaging structure 10, thereby alleviating the thermal impact of the power device 13 on other components on the corresponding surface of the packaging structure 10 when the power device 13 is working.

[0076] In some embodiments, see Figure 1 and Figure 2 The packaging structure 10 further includes protective layers 2 located on opposite sides of the stacked structure 1 , at least one protective layer 2 is provided with a pad 21 , and the second dielectric layer 122 is located between the first dielectric layer 121 and the protective layer 2 provided with the pad 21 .

[0077] The stacked structure 1 has two opposite side surfaces along the thickness direction, and a protective layer 2 is also provided on the two side surfaces of the stacked structure 1. It can be understood that the number of protective layers 2 in the package structure 10 is two. For the sake of distinction, the protective layer 2 located on one side of the stacked structure 1 is called the first protective layer 2a, and the protective layer 2 located on the other side of the stacked structure 1 is called the second protective layer 2b. The protective layer 2 is an insulating coating, and the protective layer 2 is used to protect the stacked structure 1 to prevent the stacked structure 1 from short circuiting and external erosion. As an example, the protective layer 2 is a solder resist layer, and the solder resist layer contains solder resist ink (also called green oil).

[0078] A soldering pad 21 is provided on at least one protective layer 2. The soldering pad 21 may be provided on the first protective layer 2a, the soldering pad 21 may be provided on the second protective layer 2b, or both the first protective layer 2a and the second protective layer 2b may be provided with the soldering pad 21. The number of soldering pads 21 provided on the protective layer 2 may be one or more. The soldering pad 21 is a basic building block of surface mount assembly, and the soldering pad 21 may be used for surface assembly of chip components. In other words, by providing the soldering pad 21, it is possible to continue to mount other components (called surface mount components or STM components) on the packaging structure 10. The surface mount components here may be power devices or non-power devices, which are not limited here.

[0079] By providing the protective layer 2, the protective layer 2 can be used to protect the stacked structure 1; by providing the pad 21 on the protective layer 2, other components can continue to be mounted on the packaging structure 10; because the second dielectric layer 122 in the stacked structure 1 is located between the protective layer 2 with the pad 21 and the first dielectric layer 121, the second dielectric layer 122 can block the heat generated by the power device 13 from being transferred to the pad 21 to a certain extent, thereby alleviating the thermal impact of the power device 13 on the surface mounted components when it is working.

[0080] In some embodiments, see Figure 1 and Figure 2 The stacked structure 1 further includes a circuit layer 11 , the power device 13 is electrically connected to the circuit layer 11 , and the pad 21 is connected to the circuit layer 11 .

[0081] The stacked structure 1 includes a circuit layer 11 and a dielectric layer 12 . The circuit layer 11 and the dielectric layer 12 are stacked together. The dielectric layer 12 can electrically isolate the circuit layer 11 in the stacked structure 1 .

[0082] The circuit layer 11 refers to a wired metal layer for current transmission. The metal layer can be patterned by laser laser engraving or wet etching to form the circuit layer 11. The circuit layer 11 may contain at least one of copper, silver and gold. As an example, the circuit layer 11 is a copper layer, and the mass content of copper in the copper layer is higher than 99.8wt%. Copper not only has good electrical conductivity and thermal conductivity, but also has stable chemical properties and is cheap. The circuit layer 11 is usually thin, and the thickness of the circuit layer 11 can be 0.5Oz, 1Oz, 2Oz or 4Oz. Here Oz is the thickness unit of the circuit layer 11, and 1Oz is equivalent to 35μm. That is to say, the thickness of the circuit layer 11 can be 17.5μm~140μm, for example, 17.5μm, 30μm, 50μm, 70μm, 90μm, 120μm or 140μm.

[0083] By providing the circuit layer 11 and electrically connecting the circuit layer 11 with the power device 13 and the pad 21 , the circuit conduction between the power device 13 and the pad 21 is achieved.

[0084] In some embodiments, see Figure 1 and Figure 2 The circuit layer 11 includes a first circuit layer 111 and a second circuit layer 112 . The first circuit layer 111 is adjacent to the first dielectric layer 121 . The power device 13 is electrically connected to the first circuit layer 111 . The second circuit layer 112 is adjacent to the protective layer 2 . The pad 21 is electrically connected to the second circuit layer 112 .

[0085] The circuit layer 11 includes a first circuit layer 111 and a second circuit layer 112, and the first circuit layer 111 and the second circuit layer 112 refer to different circuit layers 11. The number of layers of the first circuit layer 111 in the stacked structure 1 is at least one layer, that is, it can be one layer or multiple layers. The first circuit layer 111 is adjacent to the first dielectric layer 121, and adjacent means adjacent and connected. The first circuit layer 111 can be provided on one side surface of the first dielectric layer 121, or the first circuit layer 111 can be provided on both sides of the first dielectric layer 121. In this way, the number of first circuit layers 111 is related to the number of first dielectric layers 121.

[0086] The power device 13 is embedded in the first dielectric layer 121, and the power device 13 is connected to the first circuit layer 111, so as to realize circuit conduction. Optionally, the power device 13 is entirely embedded in the first dielectric layer 121, and the power device 13 is indirectly connected to the first circuit layer 111 through the first electrode connection layer 131. Optionally, the surface electrode on the power device 13 is exposed outside the first dielectric layer 121 and is directly connected to the first circuit layer 111.

[0087] The second circuit layer 112 is adjacent to the protective layer 2, and the number of layers of the second circuit layer 112 can be one or two. For example, the first protective layer 2a may be provided with a pad 21, and the pad 21 is connected to the second circuit layer 112 adjacent to the first protective layer 2a; the second protective layer 2b may be provided with a pad 21, and the pad 21 is connected to the second circuit layer 112 adjacent to the second protective layer 2b; or the first protective layer 2a and the second protective layer 2b may be provided with pads 21, and each pad 21 is connected to a different second circuit layer 112.

[0088] In the packaging structure 10 provided in the embodiment of the present application, the stacked structure 1 includes a multi-layer circuit layer 11 (at least including a first circuit layer 111 and a second circuit layer 112), the power device 13 is connected to the first circuit layer 111 to achieve electrical conduction, and the pad 21 is connected to the second circuit layer 112 in the stacked structure 1 nearby, thereby achieving a more complex electrical connection.

[0089] In some embodiments, see Figure 2 The packaging structure 10 also includes a first circuit layer 111, a first electrode connecting layer 131 is buried in the first dielectric layer 121, and the power device 13 is connected to the first electrode connecting layer 131, and the first electrode connecting layer 131 is connected to the first circuit layer 111, that is, the power device 13 is connected to the first circuit layer 111 through the first electrode connecting layer 131, thereby achieving circuit conduction.

[0090] Usually, the first electrode connection layer 131 is mostly buried in the first dielectric layer 121, but the first electrode connection layer 131 still retains an end surface exposed on one side surface of the first dielectric layer 121, so as to be connected to the first circuit layer 111. As an example, the first electrode connection layer 131 can be a copper electrode, a silver electrode or a gold electrode.

[0091] The packaging structure 10 provided in the embodiment of the present application buries the first electrode connection layer 131 in the first dielectric layer 121 of the stacked structure 1, and the power device 13 is electrically connected to the first circuit layer 111 in the stacked structure 1 through the first electrode connection layer 131. This method eliminates the participation of bonding wires and reduces parasitic inductance.

[0092] In some embodiments, see Figure 2 The first dielectric layer 121 includes a first body portion 121a and a first packaging portion 121b, and the power device 13 and the first electrode connection layer 131 are buried in the first packaging portion 121b.

[0093] The first dielectric layer 121 includes a first main body portion 121a and a first packaging portion 121b. The first main body portion 121a and the first packaging portion 121b are integrally arranged, for example, the first packaging portion 121b is embedded in the first main body portion 121a. The first packaging portion 121b is arranged throughout the first main body portion 121a. The thickness of the first packaging portion 121b is equal to the thickness of the first main body portion 121a, and the surface of the first packaging portion 121b is flush with the surface of the first main body portion 121a. The main material of the first main body portion 121a and the main material of the first packaging portion 121b can be the same or different. Optionally, the main material for preparing the first main body portion 121a is different from the main material for preparing the first packaging portion 121b. As an example, the main material of the first main body portion 121a includes epoxy resin, and the main material of the first packaging portion 121b includes bismaleimide triazine resin. The first dielectric layer 121 obtained in this way has better performance while taking into account the price, thereby reducing the production cost of the packaging structure 10. It can be understood that the main material of the first body part 121a and the main material of the first packaging part 121b are both dielectric materials, such as organic resin. In addition, the power device 13 and the first electrode connection layer 131 are buried in the first packaging part 121b, which can reduce the manufacturing difficulty.

[0094] In some embodiments, a heat sink 132 is further embedded in the first dielectric layer 121 , the power device 13 is disposed on the heat sink 132 , and a heat dissipation end surface of the heat sink 132 extends out of the first dielectric layer 121 .

[0095] The package structure 10 further includes a heat sink 132 for dissipating heat from the power device 13. As an example, the heat sink 132 may be an active metal brazing (AMB) ceramic substrate, a direct bond copper (DBC) ceramic substrate, or a graphite plate.

[0096] Exemplarily, the power device 13, the heat sink 132 and the first electrode connection layer 131 are all buried in the first packaging part 121b of the first dielectric layer 121, and the first packaging part 121b can be used to fix and protect the power device 13, the heat sink 132 and the first electrode connection layer 131. In detail, the power device 13 is completely buried in the first packaging part 121b. Although the heat sink 132 and the vast majority of the first electrode connection layer 131 are buried in the first packaging part 121b, the first electrode connection layer 131 still retains an end surface exposed on one side surface of the first packaging part 121b to connect with the first circuit layer 111, and the heat sink 132 also retains an end surface (specifically a heat dissipation end surface) exposed on one side surface of the first packaging part 121b for heat dissipation. In the first packaging part 121b, the heat sink 132 and the first electrode connection layer 131 are both connected to the power device 13. The power device 13 is connected to one end of the first electrode connection layer 131, and the other end of the first electrode connection layer 131 extends to one side surface of the first packaging part 121b and is connected to the first circuit layer 111, so that the power device 13 is electrically connected to the first circuit layer 111 through the first electrode connection layer 131. The power device 13 is arranged on one side surface of the heat sink 132, for example, the power device 13 is welded on the heat sink 132, and the other side surface of the heat sink 132 is exposed to the other side surface of the first packaging part 121b and is connected to another circuit layer 11 (for example, the second circuit layer 112), and the second circuit layer 112 is adjacent to the first dielectric layer 121 in addition to the protective layer 2, and the power device 13 can transfer heat to the second circuit layer 112 through the heat sink 132 to achieve heat dissipation. Here, the heat sink 132 is connected to the second circuit layer 112, and only heat transfer can be achieved between the heat sink 132 and the second circuit layer 112, and current cannot be circulated, that is, the heat sink 132 and the second circuit layer 112 are thermally conductively connected. Optionally, the second dielectric layer 122 is located on a side of the first dielectric layer 121 away from the heat sink 132 .

[0097] The heat sink 132 is provided to dissipate heat from the power device 13 , thereby reducing the risk of thermal failure of the power device 13 .

[0098] Of course, in other embodiments, the first dielectric layer 121 may also only include the first body portion 121 a , and the power device 13 , the heat sink 132 , and the first electrode connection layer 131 are all buried in the first body portion 121 a .

[0099] In some embodiments, see Figure 2 The power device 13 has a surface electrode 133, and the surface electrode 133 includes three independent sub-surface electrodes; the first electrode connection layer 131 includes three independent sub-electrode connection layers; the sub-surface electrodes are connected to the sub-electrode connection layers in a one-to-one correspondence.

[0100] Specifically, taking the power device 13 as a metal oxide semiconductor field effect transistor as an example, the surface electrode 133 of the power device 13 includes three independent sub-surface electrodes, namely a first sub-surface electrode 133a, a second sub-surface electrode 133b and a third sub-surface electrode 133c, wherein the first sub-surface electrode 133a is a gate (G), the second sub-surface electrode 133b is a source (S), and the third sub-surface electrode 133c is a drain (D), which respectively assume the functions of control, input and output.

[0101] The first electrode connection layer 131 includes three independent sub-electrode connection layers, namely a first sub-electrode connection layer 131 a , a second sub-electrode connection layer 131 b and a third sub-electrode connection layer 131 c .

[0102] The sub-surface electrodes are connected to the sub-electrode connecting layers one by one, that is, the first sub-surface electrode 133a and the first sub-electrode connecting layer 131a are connected in sequence, the second sub-surface electrode 133b and the second sub-electrode connecting layer 131b are connected in sequence, and the third sub-surface electrode 133c and the third sub-electrode connecting layer 131c are connected in sequence.

[0103] By providing a plurality of independent sub-electrode connection layers, different sub-surface electrodes are respectively connected to the circuit layer 11 , thereby ensuring the stability and reliability of the operation of the power device 13 .

[0104] In some embodiments, see Figure 2The heat sink 132 includes an insulating body 132a and a conductive layer 132b and a thermal conductive layer 132c located on two opposite surfaces of the insulating body 132a; the power device 13 has a first surface 13a and a second surface 13b that are opposite to each other, one of the three sub-surface electrodes is distributed on the second surface 13b, and the other two are distributed on the first surface 13a at intervals; the sub-surface electrode located on the second surface is connected to the conductive layer 132b, and the conductive layer 132b is also connected to a sub-electrode connecting layer; the thermal conductive layer 132c partially extends out of the first dielectric layer 121.

[0105] Specifically, the heat sink 132 includes an insulating body 132a, a conductive layer 132b and a thermal conductive layer 132c, which form a sandwich structure, that is, the insulating body 132a is in the middle, and the conductive layer 132b and the thermal conductive layer 132c are respectively located on both sides of the insulating body 132a, and the insulating body 132a separates the conductive layer 132b and the thermal conductive layer 132c, so that the conductive layer 132b and the thermal conductive layer 132c cannot be electrically connected, so that the conductive layer 132b and the thermal conductive layer 132c can be set as metal layers, because metal has good electrical conductivity, thermal conductivity and molding effect. Optionally, the insulating body 132a is a ceramic sheet. Take the heat sink 132 as a DBC ceramic substrate as an example for explanation, the DBC ceramic substrate has a copper-ceramic-copper three-layer structure, wherein the ceramic in the middle is the insulating body 132a, and the copper layers on both sides are the conductive layer 132b and the thermal conductive layer 132c. Optionally, the heat conductive layer 132 c is connected to the second circuit layer 112 .

[0106] When the heat sink 132 is connected to the power device 13, the conductive layer 132b on the heat sink 132 is connected to the power device 13 to achieve conductivity, and the thermal conductive layer 132c on the heat sink 132 partially extends out of the first packaging portion 121b to facilitate heat dissipation.

[0107] The power device 13 has two opposite surfaces, namely a first surface 13a and a second surface 13b, wherein the second surface 13b faces the heat sink 132. Usually, the heat sink 132 is larger than the power device 13, that is, the top surface area of ​​the conductive layer 132b in the heat sink 132 is larger than the surface area of ​​the second surface 13b of the power device 13.

[0108] The surface electrode 133 on the power device 13 includes a first sub-surface electrode 133a, a second sub-surface electrode 133b and a third sub-surface electrode 133c. The first sub-surface electrode 133a and the second sub-surface electrode 133b are spaced apart and distributed on the first surface 13a of the power device 13, and the third sub-surface electrode 133c is independently distributed on the second surface 13b of the power device 13.

[0109] The first electrode connecting layer 131 includes a first sub-electrode connecting layer 131a, a second sub-electrode connecting layer 131b and a third sub-electrode connecting layer 131c, wherein the first sub-electrode connecting layer 131a and the second sub-electrode connecting layer 131b are directly opposite to the first surface 13a of the power device 13, while the third sub-electrode connecting layer 131c is staggered from the power device 13, and the third sub-electrode connecting layer 131c is arranged on the conductive layer 132b of the heat dissipation plate 132, and the third sub-electrode connecting layer 131c is electrically connected to the third sub-surface electrode 133c through the conductive layer 132b. In this way, the first sub-electrode connecting layer 131a, the second sub-electrode connecting layer 131b and the third sub-electrode connecting layer 131c are all located on one side of the heat sink 132 and extend in a direction away from the heat sink 132, so that the first sub-electrode connecting layer 131a, the second sub-electrode connecting layer 131b and the third sub-electrode connecting layer 131c are all connected to the same circuit layer 11 on one side of the first dielectric layer 121, that is, the first circuit layer 111.

[0110] Through the above arrangement, three sub-electrode connection layers can be led out on the same side of the first dielectric layer 121 , and the three sub-electrode connection layers are then connected to the same circuit layer 11 .

[0111] In some embodiments, see Figure 3 A heat insulation structure 15 is embedded in the second dielectric layer 122 .

[0112] The heat insulation structure 15 is embedded in the second dielectric layer 122. The heat insulation structure 15 may be arranged to penetrate the second dielectric layer 122, or three sides of the heat insulation structure 15 may be surrounded by the second dielectric layer 122, or the heat insulation structure 15 may be completely surrounded by the second dielectric layer 122. The number of the heat insulation structure 15 in the second dielectric layer 122 may be one or more.

[0113] By providing the heat insulation structure 15 in the second dielectric layer 122 , the heat insulation structure 15 can better block the propagation of heat, thereby improving the heat insulation effect of the second dielectric layer 122 .

[0114] In some embodiments, see Figure 1 , the position of the heat insulation structure 15 in the second dielectric layer 122 corresponds to the position of the power device 13 in the first dielectric layer 121. Optionally, in the radial direction, the size of the heat insulation structure 15 is larger than the size of the power device 13.

[0115] By arranging the heat insulation structure 15 to correspond to the power device 13 , the heat insulation structure 15 can effectively block the propagation of heat, thereby improving the heat insulation effect of the second dielectric layer 122 .

[0116] In some embodiments, the thermal insulation structure 15 includes at least a thermal insulation core layer 151, and the thermal insulation core layer 151 includes a thermal insulation material with high thermal resistance and capable of preventing heat transfer. As an example, the thermal insulation material includes at least one of asbestos, aerogel, rock wool, vacuum board and graphite felt.

[0117] In some embodiments, the insulating structure 15 includes an insulating cover layer 152 and an insulating core layer 151 .

[0118] The thermal insulation structure 15 may further include an insulating covering layer 152, and the insulating covering layer 152 covers the surface of the thermal insulation core layer 151. The insulating covering layer 152 may cover one side surface of the thermal insulation core layer 151, or both sides, or even the insulating covering layer 152 completely covers the thermal insulation core layer 151. When the thermal insulation structure 15 is arranged to penetrate the second dielectric layer 122, the insulating covering layer 152 may be used to completely cover the thermal insulation core layer 151, and the insulating covering layer 152 may effectively prevent the circuit layer 11 on both sides of the second dielectric layer 122 from being conducted through the thermal insulation structure 15. The insulating covering layer 152 includes an insulating medium. As an example, the insulating medium includes a resin.

[0119] In some embodiments, see Figure 4 The dielectric layer 12 further includes a third dielectric layer 123 . The third dielectric layer 123 is located on one side of the first dielectric layer 121 . The second device 14 is buried in the third dielectric layer 123 .

[0120] That is to say, in addition to the first dielectric layer 121 and the second dielectric layer 122, the stacked structure 1 may also include a third dielectric layer 123, and the third dielectric layer 123 is located on one side of the first dielectric layer 121. The number of the third dielectric layer 123 may be one or more. The third dielectric layer 123 may be distributed in multiple positions in the stacked structure 1. As an example, the stacked structure 1 includes three dielectric layers 12, namely the first dielectric layer 121, the second dielectric layer 122 and the third dielectric layer 123. The third dielectric layer 123 may be located between the first dielectric layer 121 and the second dielectric layer 122, the first dielectric layer 121 may be located between the third dielectric layer 123 and the second dielectric layer 122, or the second dielectric layer 122 may be located between the first dielectric layer 121 and the third dielectric layer 123.

[0121] A second device 14 is embedded in the third dielectric layer 123, and the second device 14 refers to other devices except the power device. Optionally, the second device 14 includes at least one of a passive device and a control chip. As an example, the passive device includes at least one of a temperature control element, a temperature sensing element, a strain gauge, a resistor and a capacitor. The control chip includes a processor. The number of the second devices 14 in the third dielectric layer 123 can be one or more.

[0122] In order to more clearly distinguish the power device 13 from the second device 14, the power device 13 is a power chip, and the second device 14 is a current control chip. The power chip is a switch device that can control the on and off of a large current, and the current control chip controls the magnitude and direction of the output current according to the input signal, and does not flow a large current itself. In some cases, the current control chip can be used as a driver chip for the power chip.

[0123] By setting a third dielectric layer 123 in the stacked structure 1 and burying second devices 14 in the third dielectric layer 123 , different second devices 14 have different functions. In this way, the third dielectric layer 123 can be functionalized by introducing different second devices 14 , thereby expanding the use of the packaging structure 10 .

[0124] In addition, since the power device 13 generates high heat when working, the power device 13 is concentrated in the first dielectric layer 121 to facilitate thermal management (including heat dissipation and insulation), while the second device 14 is arranged in the third dielectric layer 123, and the third dielectric layer 123 is used as a functional layer.

[0125] In some embodiments, there are multiple second devices 14, and the third dielectric layer 123 includes multiple stacked sub-layers, and the multiple second devices 14 can be respectively arranged in different sub-layers. Here, the sub-layers of the third dielectric layer 123 can be directly connected.

[0126] In some embodiments, the stacked structure 1 further includes a third circuit layer 113 , the third circuit layer 113 is adjacent to the third dielectric layer 123 , and the second device 14 is electrically connected to the third circuit layer 113 .

[0127] Usually, the third circuit layer 113 to which the second device 14 is connected and the first circuit layer 111 to which the power device 13 is connected are not the same circuit layer 11 .

[0128] The second device 14 is buried in the third dielectric layer 123 and connected to the third circuit layer 113 , thereby achieving electrical conduction.

[0129] In some embodiments, see Figure 4 A second electrode connection layer 141 is also buried in the third dielectric layer 123 , the second device 14 is connected to the second electrode connection layer 141 , and the second device 14 is connected to the third circuit layer 113 through the second electrode connection layer 141 .

[0130] The package structure 10 further includes a second electrode connection layer 141, which is used to electrically connect the second device 14 to the nearest circuit layer 11, namely, the third circuit layer 113. As an example, the second electrode connection layer 141 can be a copper electrode, a silver electrode, or a gold electrode.

[0131] The second device 14 and the third circuit layer 113 are conductively connected by providing the second electrode connection layer 141 . Compared with bonding wires, the second electrode connection layer 141 can also effectively reduce parasitic inductance.

[0132] In some embodiments, see Figure 4 The third dielectric layer 123 includes a second body portion 123a and a second packaging portion 123b, and the second device 14 and the second electrode connection layer 141 are buried in the second packaging portion 123b.

[0133] The third dielectric layer 123 includes a second body portion 123a and a second packaging portion 123b, which are integrally arranged, for example, the second packaging portion 123b is embedded in the second body portion 123a. The second packaging portion 123b is arranged throughout the second body portion 123a, the thickness of the second packaging portion 123b is equal to the thickness of the second body portion 123a, and the surface of the second packaging portion 123b is flush with the surface of the second body portion 123a. The main body material of the second body portion 123a and the main body material of the second packaging portion 123b can be the same or different.

[0134] Specifically, the second device 14 and the second electrode connection layer 141 are both buried in the second packaging part 123b, and the second packaging part 123b can be used to fix and protect the second device 14 and the second electrode connection layer 141. In detail, the second device 14 is completely buried in the second packaging part 123b, and most of the second electrode connection layer 141 is buried in the second packaging part 123b. The second electrode connection layer 141 also retains an end surface exposed on one side surface of the second packaging part 123b to connect with the third circuit layer 113. In the second packaging part 123b, the second electrode connection layer 141 is connected to the second device 14, so that the second device 14 is electrically connected to the circuit layer 11 through the second electrode connection layer 141.

[0135] By configuring the third dielectric layer 123 to include a second body portion 123a and a second packaging portion 123b, and using the second packaging portion 123b to embed the second device 14 and the second electrode connection layer 141, the cost and manufacturing difficulty of the packaging structure 10 can be regulated.

[0136] Of course, in other embodiments, the third dielectric layer 123 may also only include the second body portion 123 a , and the second device 14 and the second electrode connection layer 141 are both buried in the second body portion 123 a .

[0137] In some embodiments, see Figure 1 , the second dielectric layer 122 is located between the first dielectric layer 121 and the third dielectric layer 123 .

[0138] In this way, the second dielectric layer 122 can also better separate the first dielectric layer 121 and the third dielectric layer 123 , thereby reducing the thermal impact of heat propagation on the second device 14 when the power device 13 is working.

[0139] In some embodiments, see Figure 1 The packaging structure 10 is provided with a metallized through hole 16 , which penetrates the stacked structure 1 and is electrically connected to the circuit layer 11 .

[0140] The metallized through hole 16 is also called a PTH (Plating Through Hole) hole, which refers to a hole with a conductive metal on the inside, such as a copper foil on the inside of the hole. The metallized through hole 16 penetrates the stacked structure 1, that is, the metallized through hole 16 penetrates the circuit layer 11 and the dielectric layer 12. The metallized through hole 16 is electrically connected to the circuit layer 11. As an example, the circuit layer 11 includes a first circuit layer 111, a second circuit layer 112, and a third circuit layer 113. The metallized through hole 16 is electrically connected to the first circuit layer 111, the second circuit layer 112, and the third circuit layer 113. Different circuit layers 11 can be electrically connected through the metallized through hole 16.

[0141] By using the metallized through-holes 16 as paths for inter-layer circuit connection, electrical connection between the circuit layers 11 in the stacked structure 1 can be achieved.

[0142] In some embodiments, see Figure 1 The packaging structure 10 further includes a conductive column 17 , which is disposed in the stacked structure 1 and is electrically connected to the circuit layer 11 .

[0143] The conductive pillar 17 is a metal pillar. As an example, the conductive pillar 17 is a copper pillar. The conductive pillar 17 is arranged in the stacked structure 1, that is, the conductive pillar 17 passes through the circuit layer 11 and the dielectric layer 12. The conductive pillar 17 has a large cross-sectional area, and the interlayer resistance is smaller than that of the metallized through-hole 16, and can carry a larger overcurrent. At the same time, the copper pillar passes through the interlayer, the thermal conductivity of the metal is high, and the overcurrent temperature rise is small, which can provide a heat dissipation channel for the heat generated by each component in the stacked structure 1. The conductive pillar 17 is electrically connected to the circuit layer 11. As an example, the circuit layer 11 includes a first circuit layer 111, a second circuit layer 112 and a third circuit layer 113. The conductive pillar 17 is electrically connected to the first circuit layer 111, the second circuit layer 112 and the third circuit layer 113, so that different circuit layers 11 can also be electrically connected through the conductive pillar 17.

[0144] By arranging the conductive pillars 17 in the stacked structure 1 , the conductive pillars 17 can not only serve as paths for conducting large currents between layers, but also serve as heat dissipation channels, thereby improving the heat dissipation effect of the packaging structure 10 .

[0145] Second, see Figure 5 The present application also provides a method for preparing a packaging structure 10, including:

[0146] S1, providing a first substrate 3 and a second substrate 4, wherein the first substrate 3 includes a first dielectric sheet 31, and the second substrate 4 includes a second dielectric sheet 41;

[0147] S2, embedding the power device 13 in the first dielectric sheet 31 of the first substrate 3;

[0148] S3 , stacking the first substrate 3 and the second substrate 4 together, and performing a first hot pressing process to obtain a packaging structure 10 .

[0149] The preparation method of the packaging structure 10 provided in the embodiment of the present application is simple in process and easy to manufacture. The prepared packaging structure 10 buries the power device 13 in the first dielectric sheet 31 of the stacked structure 1. This method eliminates the need for a housing, sealant, etc., reduces the volume and weight of the packaging module, and improves the degree of integration. In the packaging structure 10, the first substrate 3 and the second substrate 4 are stacked together, and the second dielectric sheet 41 is located on one side of the first dielectric sheet 31. In this way, the second dielectric sheet 41 can block the heat generated by the power device 13 from being transferred to at least one side of the surface of the packaging structure 10, thereby alleviating the thermal impact of the power device 13 on the components on the corresponding surface of the packaging structure 10 when the power device 13 is working.

[0150] In some embodiments, see Figures 5 to 10 , the present application embodiment provides a method for preparing a packaging structure 10, comprising:

[0151] S1, providing a first substrate 3 and a second substrate 4, wherein the first substrate 3 includes a first dielectric sheet 31, and a metal layer 32 is disposed on at least one side of the first dielectric sheet 31; and the second substrate 4 includes a second dielectric sheet 41, and a metal layer 32 is disposed on at most one side of the second dielectric sheet 41;

[0152] S2, embedding the power device 13 in the first dielectric sheet 31 of the first substrate 3, connecting the power device 13 to the metal layer 32 on one side surface of the first dielectric sheet 31, and etching the metal layer 32 connected to the power device 13 to form a first circuit layer 111;

[0153] S31, stacking the first substrate 3 and the second substrate 4 together, and performing a first hot pressing process to obtain a stacked structure 1, wherein at least one side surface of the stacked structure 1 is a metal layer 32, and the second dielectric sheet 41 is located between the metal layer 32 on one side surface of the stacked structure 1 and the first dielectric sheet 31;

[0154] S32, etching the metal layer 32 on the surface of the stacked structure 1 into a patterned second circuit layer 112;

[0155] S33, respectively providing protective layers 2 on opposite sides of the stacked structure 1;

[0156] S34 , at least disposing a pad 21 on the protection layer 2 adjacent to the second circuit layer 112 to obtain a packaging structure 10 .

[0157] Specifically, a first substrate 3 and a second substrate 4 are provided in step S1 , wherein the number of the first substrate 3 can be one or more, the number of the second substrate 4 can be one or more, and the number of the first substrate 3 and the second substrate 4 ultimately affects the structure of the obtained packaging structure 10 .

[0158] The first substrate 3 and the second substrate 4 can be self-made or purchased.

[0159] The first substrate 3 includes a first dielectric sheet 31, and a metal layer 32 is provided on at least one side of the surface of the first dielectric sheet 31. It can be understood that the first substrate 3 is a multi-layer structure. As an example, the first substrate 3 can be a sandwich structure of "metal layer-first dielectric sheet-metal layer"; the first substrate 3 can also be a double-layer structure of "first dielectric sheet-metal layer".

[0160] The second substrate 4 includes a second dielectric sheet 41, and at most one side of the second dielectric sheet 41 is provided with a metal layer 32. As an example, the second substrate 4 may be a double-layer structure of "second dielectric sheet-metal layer" or a single-layer structure including only the second dielectric sheet.

[0161] The first dielectric sheet 31 includes a non-conductive dielectric material. Optionally, the dielectric material includes a resin, and the resin may include at least one of epoxy resin, polytetrafluoroethylene, phenolic resin, polyphenylene oxide (PPO) resin, and bismaleimide triazine (BT) resin. The first dielectric sheet 31 may also include a reinforcing material, and the reinforcing material is used to enhance the mechanical strength of the first dielectric sheet 31. The reinforcing material may include at least one of a paper base, a glass cloth, and a metal core. As an example, the first substrate 3 may be a double-sided copper clad laminate.

[0162] The second dielectric sheet 41 is similar to the first dielectric sheet 31, and also includes a non-conductive dielectric material, such as resin, in the second dielectric sheet 41. The second dielectric sheet 41 may also include a reinforcing material. As an example, the first dielectric sheet 31 and the second dielectric sheet 41 are both prepreg sheets (also called PP sheets).

[0163] See also Figure 6In step S2, a power device 13 is embedded in the first substrate 3. When there are multiple first substrates 3, the power device 13 may be embedded in one of the first substrates 3, in several of the first substrates 3, or in all of the first substrates 3. Furthermore, the number of power devices 13 embedded in a single first substrate 3 may be one or more.

[0164] See also Fig. 9 In step S31, when preparing the stacked structure 1, by adjusting the number, structure and / or stacking order of the first substrate 3 and the second substrate 4, at least one side surface of the stacked structure 1 can be made into a metal layer 32, and the second dielectric sheet 41 is located between the metal layer 32 on one side surface of the stacked structure 1 and the first dielectric sheet 31.

[0165] Here, one side surface of the stacked structure 1 may be the metal layer 32, or both sides of the stacked structure 1 may be the metal layer 32. The second dielectric sheet 41 is located between the metal layer 32 on one side surface of the stacked structure 1 and the first dielectric sheet 31. When both sides of the stacked structure 1 are metal layers 32 and there is only one second dielectric sheet 41, the second dielectric sheet 41 may be arranged between the metal layer 32 on one side of the stacked structure 1 and the first dielectric sheet 31, and the metal layer 32 on the other side of the stacked structure 1 may also be adjacent to the first dielectric sheet 31. In this case, at least the pad 21 located on one side of the stacked structure 1 may be further spaced apart from the first dielectric sheet 31.

[0166] As an example, a first substrate 3 constructed as "metal layer-first dielectric sheet-metal layer" and a second substrate 4 constructed as "second dielectric sheet-metal layer" are stacked together in sequence to obtain a stacked structure 1 constructed as "metal layer-first dielectric sheet-metal layer-second dielectric sheet-metal layer".

[0167] As an example, a first substrate 3 constructed as a "first dielectric sheet-metal layer" and a second substrate 4 constructed as a "second dielectric sheet-metal layer" are stacked together in sequence to obtain a stacked structure 1 constructed as a "first dielectric sheet-metal layer-second dielectric sheet-metal layer".

[0168] When there are multiple first substrates 3, at least one of the first substrates 3 has a power device 13 embedded therein. Thus, in preparing the stacked structure 1, when stacking the first substrates 3, the first circuit layer 111 on the first substrate 3 can be oriented inwards or outwards.

[0169] As an example, a first substrate 3 constructed as “first circuit layer-first dielectric sheet-metal layer”, a second substrate 4 constructed as “second dielectric sheet” and a first substrate 3 constructed as “metal layer-first dielectric sheet-metal layer” are stacked together in sequence to obtain a stacked structure 1 constructed as “first circuit layer-first dielectric sheet-metal layer-second dielectric sheet-metal layer-first dielectric sheet-metal layer”.

[0170] As an example, a second substrate 4 constructed as "metal layer-second dielectric sheet" and a first substrate 3 constructed as "first circuit layer-first dielectric sheet-metal layer" are stacked together in sequence to obtain a stacked structure 1 constructed as "metal layer-second dielectric sheet-first circuit layer-first dielectric sheet-metal layer".

[0171] That is, the first circuit layer 111 in the stacked structure 1 can be located on the surface of the stacked structure 1 or inside the stacked structure 1. Optionally, the first circuit layer 111 is located inside the stacked structure 1, which can reduce the damage to the fine circuits on the first circuit layer 111 during the first hot pressing process.

[0172] See also Fig. 9 In step S32, the metal layer 32 on the surface of the stacked structure 1 is etched into a second circuit layer 112. If the metal layer 32 is disposed on one surface of the stacked structure 1, one layer of the second circuit layer 112 can be etched. If the metal layer 32 is disposed on both surfaces of the stacked structure 1, two layers of the second circuit layer 112 can be etched. As an example, the metal layer 32 can be etched into the second circuit layer 112 by wet etching.

[0173] As an example, the structure of the stacked structure 1 is “first circuit layer-first dielectric sheet-metal layer-second dielectric sheet-metal layer-first dielectric sheet-metal layer”. After etching the surface metal layer 32, a stacked structure 1 having a structure of “first circuit layer-first dielectric sheet-metal layer-second dielectric sheet-metal layer-first dielectric sheet-second circuit layer” can be obtained.

[0174] See also Fig.10 In the middle (a), in step S33, protective layers 2 are respectively provided on opposite sides of the stacked structure 1. As an example, the protective layer 2 is a solder resist layer, which can be obtained by applying solder resist ink on opposite sides of the stacked structure 1 by screen printing.

[0175] See also Fig.10In the middle (b) figure, in step S34, a pad 21 is provided on at least the protective layer 2 adjacent to the second circuit layer 112 to obtain a package structure 10. Here, the pads 21 may be provided on the protective layers 2 on both sides of the stacked structure 1, or may be provided on one of the protective layers 2. When the pad 21 is provided on only one of the protective layers 2, the pad 21 must be provided on the protective layer 2 adjacent to the second circuit layer 112. As an example, the pad area reserved on the protective layer 2 is subjected to surface treatment, including but not limited to chemical nickel-gold plating, organic layer solder preservation treatment, etc., to obtain the pad 21.

[0176] The preparation method of the packaging structure 10 provided in the embodiment of the present application is simple in process and easy to manufacture. The prepared packaging structure 10 buries the power device 13 in the first dielectric sheet 31 of the stacked structure 1, and the power device 13 is connected to the first circuit layer 111 in the stacked structure 1. This method eliminates the need for a housing, a sealant, etc., reduces the volume and weight of the packaging module, and improves the degree of integration. The packaging structure 10 also includes a protective layer 2, on which a soldering pad 21 is provided. The soldering pad 21 can be used to continue mounting other components on the surface of the packaging structure 10, and the second dielectric sheet 41 in the stacked structure 1 is located between the soldering pad 21 and the first dielectric sheet 31. In this way, the second dielectric sheet 41 can block the heat generated by the power device 13 from being transferred to the soldering pad 21, thereby alleviating the thermal impact of the power device 13 on the surface mounted components when it is working.

[0177] In some embodiments, both side surfaces of the first dielectric sheet 31 are provided with a metal layer 32, and both side surfaces of the second dielectric sheet 41 are not provided with a metal layer 32, that is, the first substrate 3 includes the first dielectric sheet 31 and the metal layer 32, and the second substrate 4 includes only the second dielectric sheet 41. The number of the first substrates 3 is one more than the number of the second substrates 4. It can be understood that the number of the first substrates 3 is multiple, that is, at least two, and the number of the second substrates 4 is at least one, that is, the number of the second dielectric sheets 41 can be one or more.

[0178] The first substrate 3 includes a first dielectric sheet 31 and a metal layer 32 which are stacked, wherein the metal layer 32 is located on two opposite surfaces of the first dielectric sheet 31. In other words, the first substrate 3 is a sandwich structure of "metal layer-first dielectric sheet-metal layer", wherein the first dielectric sheet 31 is located in the middle, and the metal layers 32 are located on both sides, and the first dielectric sheet 31 separates the metal layers 32 on both sides.

[0179] The following description is made by taking an example that the first substrate 3 includes the first dielectric sheet 31 and the metal layers 32 on both sides, and the second substrate 4 includes only the second dielectric sheet 41 .

[0180] In some embodiments, providing the first substrate 3 includes preparing the first substrate 3, and preparing the first substrate 3 includes the following steps:

[0181] S11, provide metal foil, and pre-treat the metal foil. The metal foil is used to form the metal layer 32. Optionally, the metal foil includes at least one of copper foil, silver foil and gold foil. As an example, the metal foil is copper foil, and the mass content of copper in the copper foil is higher than 99.8wt%. Copper not only has good electrical conductivity and thermal conductivity, but also has stable chemical properties and is cheap. Copper foil is usually relatively thin. As an example, the thickness of the copper foil can be 0.5Oz, 1Oz, 2Oz or 4Oz. Pre-treating the metal foil includes but is not limited to at least one of cutting, degreasing, pickling, washing, pre-preg, browning and blackening the metal foil. As an example, pre-treating the metal foil includes cutting the metal foil, and the size of the metal foil obtained after cutting is slightly larger than the size of the first dielectric sheet 31 to ensure that the metal foil can completely cover the surface of one side of the first dielectric sheet 31.

[0182] S12, providing a first dielectric sheet 31, attaching metal foil to both sides of the first dielectric sheet 31, and performing a second hot pressing process to combine the metal foil with the first dielectric sheet 31. As an example, the second hot pressing process may include a vacuum lamination process, that is, using a vacuum laminator to press the upper and lower metal foils and the first dielectric sheet 31 together under vacuum conditions. Then, the excess part of the overflowed glue is cut off.

[0183] In some embodiments, step S2 specifically includes embedding a power device 13 in a first dielectric sheet 31 of at least one first substrate 3. For ease of distinction, the first substrate 3 for embedding the power device 13 is referred to as a first sub-substrate 301. That is, at least one first substrate 3 among the plurality of first substrates 3 is a first sub-substrate 301. One power device 13 or multiple power devices 13 may be embedded in the first dielectric sheet 31.

[0184] In some embodiments, see Figure 6 The process of embedding the power device 13 in the first dielectric sheet 31 of the first substrate 3 (specifically the first sub-substrate 301) includes the following steps:

[0185] S211, providing a power device 13. As an example, the power device 13 includes at least one of a power diode, a thyristor (SCR), an insulated gate bipolar transistor (IGBT), a metal oxide semiconductor field effect transistor (MOSFET), a silicon carbide (SiC) power device, and a gallium nitride (GaN) power device.

[0186] S212, see Figure 6 (a) Figure and Figure 6In the middle (b) figure, a first mounting groove 33 is provided on the first substrate 3, and the first mounting groove 33 at least extends into the first dielectric sheet 31. As an example, the first mounting groove 33 can be obtained by locally thinning the first substrate 3 along the thickness direction of the first substrate 3 by laser etching or mechanical processing. As an example, the first mounting groove 33 can be obtained by grooving. Since the metal layer 32 is very thin, in order to ensure that the first mounting groove 33 has sufficient depth to accommodate the power device 13, at least part of the first mounting groove 33 will extend into the first dielectric sheet 31, that is, at least part of the first dielectric sheet 31 will be etched away. The first mounting groove 33 may penetrate the first dielectric sheet 31, or may not penetrate the first dielectric sheet 31, but the first mounting groove 33 at least penetrates the metal layer 32 on one side of the first dielectric sheet 31.

[0187] S213, see Figure 6 Figure (c) and Figure 6 In the middle (d) figure, the power device 13 is placed in the first mounting groove 33, and the dielectric material is backfilled in the first mounting groove 33 to obtain the first packaging part 121b, and the power device 13 is embedded in the first packaging part 121b. The dielectric material backfilled in the first mounting groove 33 and the dielectric material in the first dielectric sheet 31 can be the same dielectric material or a different dielectric material. The dielectric material usually used to backfill the first mounting groove 33 is in liquid state, so that the dielectric material can better cover the power device 13, and then the dielectric material can be cured by adding a curing agent, heating or light to form the first packaging part 121b, and the power device 13 will be embedded in the first packaging part 121b. As an example, the dielectric material includes epoxy resin. Optionally, the top surface of the first packaging part 121b is kept flush or substantially flush with the surface of the first dielectric sheet 31.

[0188] S214, see Figure 6 Figure (e) and Figure 6In the middle (f) figure, a first hole 34 is opened on the first packaging part 121b to conduct the power device 13, metal is deposited in the first hole 34 to form a first electrode connection layer 131, and the metal layer 32 is restored on the surface of the first packaging part 121b. The first electrode connection layer 131 electrically connects the power device 13 and the metal layer 32. As an example, the first packaging part 121b can be etched by laser etching to obtain the first hole 34. The depth of the first hole 34 is based on the conduction of the power device 13. Conducting the power device 13 refers to exposing the electrical connection part of the power device 13; when the power device 13 is a bare chip, the electrical connection part of the power device 13 is the surface electrode 133. The first hole 34 is filled with metal by metal deposition, thereby forming a metal deposition layer filling the first hole 34. The metal deposition layer is the first electrode connection layer 131, and the first electrode connection layer 131 is electrically connected to the power device 13. Since the metal layer 32 on one side of the first dielectric sheet 31 has been partially etched away when the first mounting groove 33 is formed, the surface of the first packaging portion 121b formed thereafter no longer has the metal layer 32, and therefore the metal layer 32 needs to be further restored on the surface of the first packaging portion 121b.

[0189] It can be understood that in the first substrate 3 after the power device 13 is embedded, the power device 13 is connected to the first electrode connection layer 131 and both are located in the first dielectric sheet 31 . The first electrode connection layer 131 is also connected to the metal layer 32 on one side of the first dielectric sheet 31 .

[0190] Optionally, in order to dissipate heat for the power device 13, a heat sink 132 is further embedded in the first dielectric sheet 31 of the first substrate 3, and step S2 further includes:

[0191] In step S211 , a heat sink 132 is provided, and the power device 13 is disposed on the heat sink 132 . For example, the power device 13 is soldered on the heat sink 132 .

[0192] In step S212 , the first installation groove 33 is set to penetrate the first dielectric sheet 31 , so that the bottom wall of the first installation groove 33 is the metal layer 32 , that is, the metal layer 32 on the side of the first substrate 3 away from the opening of the first installation groove 33 .

[0193] In step S213, the power device 13 and the heat sink 132 are placed together in the first mounting groove 33, and the heat sink 132 is located on the metal layer 32. Then, the first packaging part 121b is arranged in the first mounting groove 33, and the heat sink 132 is also buried in the first packaging part 121b, and the heat sink 132 is thermally connected to the metal layer 32.

[0194] Combination Figure 2 and Figure 6In order to explain in more detail the process of embedding the power device 13 and the heat sink 132 into the first substrate 3 , the following description will be made by taking the power device 13 as a metal oxide semiconductor field effect transistor as an example.

[0195] In detail, the first sub-surface electrodes 133 a and the second sub-surface electrodes 133 b are distributed at intervals on the first surface 13 a of the power device 13 , and the third sub-surface electrodes 133 c are distributed on the second surface 13 b of the power device 13 .

[0196] A heat sink 132 is provided, and the area of ​​the heat sink 132 is larger than the area of ​​the power device 13. The heat sink 132 includes an insulating body 132a and a conductive layer 132b and a heat conductive layer 132c located on two opposite surfaces of the insulating body 132a. The heat sink 132 and the power device 13 are hot-pressed together by vacuum hot pressing, so that the third sub-surface electrode 133c is connected to the conductive layer 132b on the heat sink 132.

[0197] The heat sink 132 and the power device 13 which are heat pressed together are placed in the first mounting groove 33, and the heat conductive layer 132c of the heat sink 132 contacts the metal layer 32 of the bottom wall of the first mounting groove 33 to achieve heat conductive connection.

[0198] The first packaging part 121b is etched to obtain three first holes 34 that respectively connect the first sub-surface electrode 133a, the second sub-surface electrode 133b and the conductive layer 132b. Metal is deposited in the three first holes 34 to obtain three sub-electrode connection layers, namely the first sub-electrode connection layer 131a, the second sub-electrode connection layer 131b and the third sub-electrode connection layer 131c. Finally, another layer of metal is deposited on the surface of the first packaging part 121b to restore the metal layer 32. The first sub-electrode connection layer 131a directly connects the metal layer 32 and the first sub-surface electrode 133a, the second sub-electrode connection layer 131b directly connects the metal layer 32 and the second sub-surface electrode 133b, and the third sub-electrode connection layer 131c directly connects the metal layer 32 and the conductive layer 132b.

[0199] S215, see Figure 6In the middle (h) figure, the metal layer 32 connected to the power device 13 is etched into the first circuit layer 111. That is, before the first substrate 3 and the second substrate 4 are stacked into the stacked structure 1, the metal layer 32 connected to the power device 13 on the first substrate 3 needs to be etched into a patterned circuit layer 11 (i.e., the first circuit layer 111) in advance, especially in the stacked structure 1, the circuit layer 11 is used to be arranged toward the second substrate 4, because the circuit layer 11 facing the second substrate 4 in the stacked structure 1 will be blocked, and if the metal layer 32 is not etched in advance, the patterning process cannot be performed. As an example, the excess part of the metal layer 32 can be etched away by wet etching to obtain the patterned circuit layer 11, and the wet etching process includes: film pasting, development exposure, etching and film stripping.

[0200] In order to improve the alignment effect between the first substrate 3 and the second dielectric sheet 41 in the stacked structure 1, optionally, see Figure 6 In the middle (g) figure, step S2 also includes drilling a first positioning hole 37 and a first mounting hole 38 on the first substrate 3 (specifically the first sub-substrate 301), the first positioning hole 37 can be used to assist in alignment when preparing the stacked structure 1, and the first mounting hole 38 can be used to penetrate the conductive column 17. Usually, the first positioning hole 37 is set on the invalid area at the edge of the first substrate 3, and the invalid area can be removed after the packaging structure 10 is prepared.

[0201] In some embodiments, step S2 further includes: embedding a second device 14 in a first dielectric sheet 31 of at least one first substrate 3, and the first substrate 3 in which the second device 14 is embedded is different from the first substrate 3 in which the power device 13 is embedded. For the sake of distinction, the first substrate 3 for embedding the second device 14 is referred to as a second sub-substrate 302. That is, at least one of the plurality of first substrates 3 is a second sub-substrate 302. The second sub-substrate 302 is not the same first substrate 3 as the first sub-substrate 301. One second device 14 or a plurality of second devices 14 may be embedded in the first dielectric sheet 31.

[0202] In some embodiments, see Figure 7 The process of embedding the second device 14 in the first dielectric sheet 31 of the first substrate 3 (specifically the second sub-substrate 302) includes the following steps:

[0203] S221. Provide a second device 14. The second device 14 refers to other devices except the power device. Optionally, the second device 14 includes at least one of a passive device and a control chip. As an example, the passive device includes at least one of a temperature control element, a temperature sensing element, a strain gauge, a resistor and a capacitor. The control chip includes a processor.

[0204] S222, see Figure 7 (a) Figure and Figure 7 In the middle (b) figure, a second mounting groove 35 is provided on the first substrate 3, and the second mounting groove 35 at least extends into the first dielectric sheet 31. As an example, the first substrate 3 can be locally thinned along the thickness direction of the first substrate 3 by laser etching or mechanical processing to obtain the second mounting groove 35. As an example, the second mounting groove 35 can be prepared by grooving. Since the metal layer 32 is very thin, in order to ensure that the second mounting groove 35 has sufficient depth to accommodate the second device 14, at least part of the second mounting groove 35 will extend into the first dielectric sheet 31, that is, at least part of the first dielectric sheet 31 will be etched away. The second mounting groove 35 may penetrate the first dielectric sheet 31, or may not penetrate the first dielectric sheet 31, but the second mounting groove 35 at least penetrates the metal layer 32 on one side of the first dielectric sheet 31.

[0205] S223, see Figure 7 Figure (c) and Figure 7 In the middle (d) figure, the second device 14 is placed in the second mounting groove 35, and the dielectric material is backfilled in the second mounting groove 35 to obtain the second packaging part 123b, and the second device 14 is embedded in the second packaging part 123b. The dielectric material backfilled in the second mounting groove 35 can be the same dielectric material or a different dielectric material from the dielectric material in the first dielectric sheet 31. The dielectric material usually used to backfill the second mounting groove 35 is in liquid state, so that the dielectric material can better cover the second device 14, and then the dielectric material can be cured by adding a curing agent, heating or light to form the second packaging part 123b, and the second device 14 will be embedded in the second packaging part 123b. As an example, the dielectric material includes epoxy resin. Optionally, the top surface of the second packaging part 123b is kept flush or substantially flush with the surface of the first dielectric sheet 31.

[0206] S224, see Figure 7 Figure (e) and Figure 7In the middle (f) figure, a second hole 36 is opened on the second packaging part 123b to conduct the second device 14, metal is deposited in the second packaging part 123b to form a second electrode connection layer 141, and the metal layer 32 is restored on the surface of the second packaging part 123b. The second electrode connection layer 141 electrically connects the second device 14 and the metal layer 32. As an example, the second packaging part 123b can be etched by laser etching to obtain the second hole 36. The depth of the second hole 36 is based on conducting the second device 14. Conducting the second device 14 refers to exposing the electrical connection part of the second device 14. The second hole 36 is filled with metal by metal deposition, thereby forming a metal deposition layer filling the second hole 36. The metal deposition layer is the second electrode connection layer 141, and the second electrode connection layer 141 is electrically connected to the second device 14. Since the metal layer 32 on one side of the first dielectric sheet 31 has been partially etched away when the second mounting groove 35 is formed, the surface of the second packaging portion 123b formed thereafter no longer has the metal layer 32, and therefore it is necessary to further restore the metal layer 32 on the surface of the second packaging portion 123b. Alternatively, the metal layer 32 may be restored on the surface of the second packaging portion 123b by metal deposition, and the restored metal layer 32 is also electrically connected to the second electrode connection layer 141.

[0207] S225, see Figure 7 In the middle (h) figure, the metal layer 32 connected to the second electrode connection layer 141 is etched to form the third circuit layer 113. That is, before the first substrate 3 and the second substrate 4 are stacked into the stacked structure 1, the metal layer 32 connected to the second device 14 on the first substrate 3 needs to be etched into a patterned circuit layer 11 (i.e., the third circuit layer 113) in advance, especially in the stacked structure 1, the circuit layer 11 is used to be arranged toward the second substrate 4, because the circuit layer 11 facing the second substrate 4 in the stacked structure 1 will be blocked, and if the metal layer 32 is not etched in advance, the patterning process cannot be performed. As an example, the excess part of the metal layer 32 can be etched away by wet etching to obtain the patterned circuit layer 11, and the wet etching process includes: film pasting, development exposure, etching and film stripping.

[0208] In order to improve the alignment effect between the first substrate 3 and the second dielectric sheet 41 in the stacked structure 1, optionally, see Figure 7 In the middle (g) figure, step S2 also includes drilling a first positioning hole 37 and a first mounting hole 38 on the first substrate 3 (specifically the second sub-substrate 302), the first positioning hole 37 can be used to assist in alignment when preparing the stacked structure 1, and the first mounting hole 38 can be used to penetrate the conductive column 17. Usually, the first positioning hole 37 is set on the invalid area at the edge of the first substrate 3, and the invalid area can be removed after the packaging structure 10 is prepared.

[0209] In some embodiments, the method for preparing the packaging structure 10 further includes: before preparing the stacked structure 1, providing a heat insulation structure 15 in at least one second dielectric sheet 41. The number of heat insulation structures 15 provided in one second dielectric sheet 41 may be one or more. When the number of second dielectric sheets 41 is multiple, the heat insulation structure 15 may be provided in one or more of the second dielectric sheets 41, or the heat insulation structure 15 may be provided in each of the second dielectric sheets 41.

[0210] Specifically, see Figure 8 The process of providing the heat insulation structure 15 in the second dielectric sheet 41 includes:

[0211] S231, see Figure 8 (a) Figure and Figure 8 In the middle (b), a third mounting groove 44 is provided on the second dielectric sheet 41. As an example, the second dielectric sheet 41 can be partially thinned along the thickness direction of the second dielectric sheet 41 by laser etching or mechanical processing to obtain the third mounting groove 44. As an example, the third mounting groove 44 can be prepared by a gong groove method. Optionally, the depth of the third mounting groove 44 is less than the thickness of the second dielectric sheet 41. Of course, in some embodiments, the depth of the third mounting groove 44 is equal to the thickness of the second dielectric sheet 41, that is, the third mounting groove 44 penetrates the second dielectric sheet 41.

[0212] S232, see Figure 8 In the middle (d) figure, the third installation groove 44 is filled with a heat insulating material to obtain a heat insulating core layer 151. As an example, the heat insulating material includes at least one of asbestos, aerogel, rock wool, vacuum board and graphite felt.

[0213] S233, see Figure 8 Figure (c) and Figure 8 In the middle (e) figure, an insulating medium is filled into the third installation groove 44, and the insulating medium is cured to obtain an insulating cover layer 152. The thermal insulation structure 15 includes a thermal insulation core layer 151 and an insulating cover layer 152. As an example, the insulating medium includes a resin.

[0214] It should be noted here that when the depth of the third mounting groove 44 is less than the thickness of the second dielectric sheet 41, the third mounting groove 44 can be directly filled with insulation material after the third mounting groove 44 is excavated, and then filled with insulation medium until the surface of the insulation medium is flush with the surface of the second dielectric sheet 41. In this way, the insulation structure 15 obtained after curing includes an insulation core layer 151 and an insulation covering layer 152, and the insulation covering layer 152 covers one side surface of the insulation core layer 151.

[0215] When the depth of the third mounting groove 44 is equal to the thickness of the second dielectric sheet 41, the third mounting groove 44 is a through groove. The third mounting groove 44 can be sealed with adhesive tape at one end, and then the insulating dielectric part can be added into the third mounting groove 44 from the other end (see Figure 8 (c) in the figure), and then continue to add insulation materials after the insulation medium solidifies (see Figure 8 Finally, an insulating medium is added until the surface of the insulating medium is flush with the surface of the second dielectric sheet 41 (see Figure 8 In (d) figure), the thermal insulation structure 15 obtained after curing also includes a thermal insulation core layer 151 and an insulating covering layer 152, but the insulating covering layer 152 is composed of two layers, an upper layer and an lower layer, which respectively cover the two side surfaces of the thermal insulation core layer 151.

[0216] In some cases, the thermal insulation material can be molded and fixed before being added into the third mounting groove 44, so that the radial and axial dimensions of the final thermal insulation core layer 151 are smaller than the radial and axial dimensions of the third mounting groove 44. In this way, in the resulting thermal insulation structure 15, the thermal insulation core layer 151 can also be completely wrapped by the insulating covering layer 152.

[0217] In order to improve the alignment effect of the first substrate 3 and the second dielectric sheet 41 in the stacked structure 1, optionally, step S2 further includes drilling a second positioning hole 42 and a second mounting hole 43 on the second dielectric sheet 41, the second positioning hole 42 can be used to assist in alignment when preparing the stacked structure 1, and the second mounting hole 43 can be used to drill the conductive column 17. Usually, the second positioning hole 42 is set on the invalid area at the edge of the second dielectric sheet 41, and the invalid area can be removed after the packaging structure 10 is prepared.

[0218] In some embodiments, stacking the first substrate 3 and the second substrate 4 together includes: stacking the first substrate 3 and the second substrate 4 together alternately.

[0219] See also Fig. 9 , step S31 includes the following sub-steps:

[0220] S311, see Fig. 9 (a) Figure and Fig. 9In the middle (b) figure, the first substrate 3 and the second substrate 4 are alternately stacked together, and the second substrate 4 is located between the two first substrates 3, and the first circuit layer 111 and the third circuit layer 113 in the first substrate 3 are both facing the second substrate 4, so as to obtain a pre-stacked structure. As can be seen from the above, there are at least two first substrates 3 and at least one second substrate 4. As an example, two first substrates 3 and one second substrate 4 (i.e., the second dielectric sheet 41) are stacked together, and the second dielectric sheet 41 is sandwiched between the two first substrates 3. During the stacking process, the circuit layers 11 (the first circuit layer 111 and the third circuit layer 113, respectively) on the two first substrates 3 are kept facing the second dielectric sheet 41, and the unpatterned metal layers 32 on the two first substrates 3 are used as the surface layer of the stacked structure 1. When a thermal insulation structure 15 is provided in the second dielectric sheet 41, the thermal insulation structure 15 is kept corresponding to the power device 13 in the first substrate 3 as much as possible.

[0221] Optionally, when a first positioning hole 37 is formed on the first substrate 3 and a second positioning hole 42 is formed on the second substrate 4, the first substrate 3 and the second substrate 4 are positioned using the first positioning hole 37 and the second positioning hole 42 to improve the alignment effect of the first substrate 3 and the second substrate 4.

[0222] Optionally, a first mounting hole 38 is formed on the first substrate 3, a second mounting hole 43 is formed on the second dielectric sheet 41, the first mounting hole 38 is aligned with the second mounting hole 43, and a conductive column 17 is inserted into the first mounting hole 38 and the second mounting hole 43. Optionally, the conductive column 17 is electrically connected to the first circuit layer 111, the second circuit layer 112, and the third circuit layer 113. The conductive column 17 is a metal column, and the conductive column 17 runs through the stacked structure 1. The conductive column 17 can serve not only as a conductive channel, but also as a heat conduction channel, thereby improving the current carrying capacity and heat dissipation capacity of the packaging structure 10.

[0223] S312, performing a first hot pressing treatment on the pre-laminated structure to obtain a laminated structure 1. In the pre-laminated structure, the first substrate 3 and the second substrate 4 are only stacked and not yet combined together, and further treatment is required to combine the first substrate 3 and the second dielectric sheet 41 together. Specifically, the pre-laminated structure is subjected to a first hot pressing treatment to obtain the laminated structure 1. As an example, the first hot pressing treatment is a vacuum lamination treatment.

[0224] S313, see Fig. 9In the middle (c), a through hole is opened on the stacked structure 1 and penetrates the stacked structure 1, and the through hole is metallized to obtain a metallized through hole 16. The metallization method includes but is not limited to electroplating. Optionally, the metallized through hole 16 is electrically connected to the first circuit layer 111, the second circuit layer 112 and the third circuit layer 113. The metallized through hole 16 can realize electrical connection between the multi-layer circuit layers 11 of the stacked structure 1.

[0225] Third, see Figure 1 The embodiment of the present application further provides a circuit board 100 on which the above-mentioned packaging structure 10 is disposed.

[0226] For the fourth aspect, please see Figure 1 , an embodiment of the present application further provides an electronic device 1000 , and the electronic device 1000 includes the above-mentioned circuit board 100 .

[0227] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0228] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0229] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0230] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. Although the descriptions of various embodiments in the present application have different focuses, for parts not described in detail in a certain embodiment, reference can be made to the relevant contents of other embodiments. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A packaging structure (10), characterized in that: The invention comprises a stacked structure (1), wherein the stacked structure (1) comprises a dielectric layer (12), wherein the dielectric layer (12) comprises a first dielectric layer (121) and a second dielectric layer (122); the second dielectric layer (122) is arranged on at least one side of the first dielectric layer (121), a power device (13) is embedded in the first dielectric layer (121), a heat insulation structure (15) is embedded in the second dielectric layer (122), the heat insulation structure (15) comprises an insulating covering layer (152) and a heat insulation core layer (151), the insulating covering layer (152) covers the surface of the heat insulation core layer (151); the dielectric layer (12) further comprises a third dielectric layer (123), the third dielectric layer (123) is located on one side of the first dielectric layer (121), a second device (14) is embedded in the third dielectric layer (123), and the second dielectric layer (122) is located between the first dielectric layer (121) and the third dielectric layer (123).

2. The packaging structure (10) according to claim 1, characterized in that: The packaging structure (10) further comprises protective layers (2) located on opposite sides of the stacked structure (1), at least one layer of the protective layers (2) being provided with a soldering pad (21), and the second dielectric layer (122) being located between the first dielectric layer (121) and the protective layer (2) provided with the soldering pad (21).

3. The packaging structure (10) according to claim 1, characterized in that: The heat insulation structure (15) corresponds to the power device (13).

4. The packaging structure (10) according to claim 1, characterized in that: The thermal insulation core layer (151) comprises a thermal insulation material, wherein the thermal insulation material comprises at least one of asbestos, aerogel, rock wool, vacuum board and graphite felt.

5. The packaging structure (10) according to claim 2, characterized in that: The stacked structure (1) further comprises a circuit layer (11), the power device (13) is electrically connected to the circuit layer (11), and the pad (21) is electrically connected to the circuit layer (11).

6. The packaging structure (10) according to claim 5, characterized in that: The circuit layer (11) comprises a first circuit layer (111) and a second circuit layer (112); the first circuit layer (111) is adjacent to the first dielectric layer (121), the power device (13) is electrically connected to the first circuit layer (111), the second circuit layer (112) is adjacent to the protective layer (2), and the pad (21) is electrically connected to the second circuit layer (112).

7. The packaging structure (10) according to any one of claims 1 to 6, characterized in that: A heat sink (132) is also embedded in the first dielectric layer (121), the power device (13) is arranged on the heat sink (132), and the heat dissipation end surface of the heat sink (132) extends out of the first dielectric layer (121).

8. The packaging structure (10) according to any one of claims 1 to 6, characterized in that: The stacked structure (1) further comprises a first circuit layer (111); a first electrode connection layer (131) is also embedded in the first dielectric layer (121), and the power device (13) is connected to the first circuit layer (111) via the first electrode connection layer (131).

9. The packaging structure (10) according to claim 8, characterized in that: The first dielectric layer (121) comprises a first body portion (121a) and a first packaging portion (121b), and the power device (13) and the first electrode connection layer (131) are buried in the first packaging portion (121b).

10. The packaging structure (10) according to claim 8, characterized in that: The power device (13) has a surface electrode (133), the surface electrode (133) comprises three independent sub-surface electrodes; the first electrode connection layer (131) comprises three independent sub-electrode connection layers; the sub-surface electrodes are connected to the sub-electrode connection layers in a one-to-one correspondence.

11. The packaging structure (10) according to claim 10, characterized in that: A heat sink (132) is also embedded in the first dielectric layer (121), and the heat sink (132) comprises an insulating body (132a) and a conductive layer (132b) and a heat-conducting layer (132c) located on two opposite surfaces of the insulating body (132a); the power device (13) has a first surface (13a) and a second surface (13b) that are opposite to each other, one of the three sub-surface electrodes is distributed on the second surface (13b), and the other two are distributed on the first surface (13a) at intervals; the sub-surface electrode located on the second surface (13b) is connected to the conductive layer (132b), and the conductive layer (132b) is also connected to a sub-electrode connecting layer; the heat-conducting layer (132c) partially extends out of the first dielectric layer (121).

12. The packaging structure (10) according to claim 1, characterized in that: The stacked structure (1) further comprises a third circuit layer (113), wherein the third circuit layer (113) is adjacent to the third dielectric layer (123) and is electrically connected to the second device (14).

13. The packaging structure (10) according to claim 1, characterized in that: The second device (14) includes at least one of a passive device and a control chip.

14. The packaging structure (10) according to claim 12, characterized in that: A second electrode connection layer (141) is also embedded in the third dielectric layer (123), and the second device (14) is connected to the third circuit layer (113) via the second electrode connection layer (141).

15. The packaging structure (10) according to claim 14, characterized in that: The third dielectric layer (123) comprises a second body portion (123a) and a second packaging portion (123b), and the second device (14) and the second electrode connection layer (141) are buried in the second packaging portion (123b).

16. The packaging structure (10) according to claim 5 or 6, characterized in that: The packaging structure (10) is provided with a metallized through hole (16), the metallized through hole (16) passes through the stacked structure (1) and is electrically connected to the circuit layer (11); and / or the packaging structure (10) further includes a conductive column (17), the conductive column (17) passes through the stacked structure (1) and is electrically connected to the circuit layer (11).

17. The packaging structure (10) according to claim 5 or 6, characterized in that: The dielectric layer (12) is an organic dielectric layer (12), the organic dielectric layer (12) comprises a resin and a reinforcing material, the resin comprises at least one of epoxy resin, polytetrafluoroethylene, phenolic resin, polyphenylene ether and bismaleimide triazine resin, the reinforcing material comprises at least one of a paper base, glass cloth and a metal core; and / or the thickness of the circuit layer (11) is 17.5 μm to 140 μm; and / or the circuit layer (11) comprises at least one of copper, silver and gold; and / or the power device comprises a silicon carbide power device.

18. A method for preparing a packaging structure (10), characterized in that: include: A plurality of first substrates (3) and at least one second substrate (4) are provided, wherein the first substrate (3) comprises a first dielectric sheet (31), and the second substrate (4) comprises a second dielectric sheet (41); the number of the first substrates (3) is one more than the number of the second substrates (4); A power device (13) is embedded in the first dielectric sheet (31) of at least one of the first substrates (3); A second device (14) is embedded in the first dielectric sheet (31) of at least one of the first substrates (3), and the first substrate (3) in which the second device (14) is embedded is different from the first substrate (3) in which the power device (13) is embedded; A third installation groove (44) is provided on the second dielectric sheet (41); Filling the third installation groove (44) with a heat insulating material to obtain a heat insulating core layer (151); Filling the third installation groove (44) with an insulating medium, solidifying the insulating medium to obtain an insulating covering layer (152), thereby obtaining a thermal insulation structure (15), wherein the thermal insulation structure (15) comprises the thermal insulation core layer (151) and the insulating covering layer (152); The first substrate (3) and the second substrate (4) are alternately stacked together and subjected to a first heat pressing process to obtain a packaging structure (10).

19. A circuit board (100), characterized in that: It comprises a packaging structure (10) according to any one of claims 1 to 17 or a packaging structure (10) prepared by the preparation method according to claim 18.

20. An electronic device (1000), characterized in that: Comprising the circuit board (100) according to claim 19.

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