Instruction tracking method, device, equipment and medium
By following instructions to multiple central processors in the microcontroller unit and compressing data, the problem of insufficient storage space in the multi-CPU environment is solved, and the resource utilization rate of on-chip memory is improved.
Patent Information
- Application Number
- CN202411162385.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-23
- Publication Date
- 2024-12-17
- Estimated Expiration
- 2044-08-23
AI Technical Summary
The existing instruction tracking technology has the problem of insufficient on-chip memory due to the increase in memory space requirements in multi-CPU environments.
By introducing an instruction tracking controller in the microcontroller unit, multiple central processors are instructed to track instruction data within a specified range, and the storage space requirement is reduced using data compression technology.
It realizes instruction tracking data storage in multi-CPU environments, improves resource utilization of on-chip memory, and avoids the problem of insufficient storage space.
Smart Images
Figure CN118672662B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of instruction tracing, and in particular to an instruction tracing method, device, equipment and medium. Background Art
[0002] Instruction tracing technology is an advanced CPU (Central Processing Unit) debugging technology. Compared with traditional single-step debugging, breakpoints and other methods, instruction tracing technology can continuously record the CPU's working status over a period of time, and record the instructions running over a period of time, program register addresses, running results, and whether interruptions and exceptions occur during the CPU operation. By analyzing these records, programmers can quickly find problems and discover application performance bottlenecks to optimize the design.
[0003] Current instruction tracing technology usually performs instruction tracing on a single CPU in a chip, and instruction tracing technology requires designing a larger on-chip memory inside the chip to store instruction tracing data; however, as the number of CPU cores increases, the required storage space will become larger and larger, causing the problem of insufficient on-chip memory. Summary of the invention
[0004] In view of this, the purpose of the present invention is to provide an instruction tracing method, device, equipment and medium, which can not only perform instruction tracing on multiple central processing units at the same time, but also realize the storage of instruction tracing data within a specified range, and improve the resource utilization of on-chip memory through data compression. The specific scheme is as follows:
[0005] In a first aspect, the present application provides an instruction tracking method, which is applied to an instruction tracking controller in a microcontroller unit, wherein the microcontroller unit also includes an on-chip memory and several central processing units; wherein the method includes:
[0006] Performing instruction tracing on each of the central processors, and obtaining a target program counter count value corresponding to a currently executed instruction sent by the traced central processor; the currently executed instruction is an instruction currently executed by the traced central processor;
[0007] determining whether the target program counter count value is within a target program counter count range corresponding to the traced central processor;
[0008] If the target program counter count value is within the target program counter count range, the instruction tracing data is compressed and the compressed data is stored in the on-chip memory; the instruction tracing data is the tracing data corresponding to the currently executed instruction obtained after instruction tracing is performed on the traced central processor.
[0009] Optionally, the instruction tracking controller includes sub-controllers corresponding to the plurality of central processing units respectively, and the sub-controllers are used to perform instruction tracking on the corresponding central processing units.
[0010] Optionally, before performing instruction tracing on each of the central processors, the method further includes:
[0011] Obtaining a controller setting instruction sent by a host computer that performs data communication with the microcontroller unit, and writing each processor information to be tracked contained in the controller setting instruction into each local register; wherein each processor information to be tracked includes a processor identifier to be tracked and a corresponding program counter count range;
[0012] The sub-controllers corresponding to the processor identifiers to be tracked send a start-of-work instruction to the corresponding central processor to drive the corresponding central processor to start working, and perform instruction tracking on the corresponding central processor.
[0013] Optionally, the determining whether the target program counter count value is within a target program counter count range corresponding to the traced central processor includes:
[0014] Determining, by a target sub-controller corresponding to the traced CPU and based on a target register, whether the target program counter count value is within a target program counter count range corresponding to the traced CPU;
[0015] The target register is a register corresponding to the target sub-controller, and the target register stores the counting range of the target program counter.
[0016] Optionally, after determining whether the target program counter count value is within a target program counter count range corresponding to the traced central processor, the step further includes:
[0017] If the target sub-controller determines that the count value of the target program counter reaches the upper limit value of the target program counter count range, or the storage space corresponding to the tracked central processor in the on-chip memory is full, a stop working instruction is sent to the tracked central processor to drive the tracked central processor to stop working, and end the instruction tracking of the tracked central processor.
[0018] Optionally, the method further includes:
[0019] When a data read instruction is obtained from a host computer that communicates data with the microcontroller unit, the storage controller is called to control the on-chip memory to send the target compressed data corresponding to the data read instruction stored in itself to the data decompression module, so that the data decompression module decompresses the target compressed data and sends the decompressed data to the host computer; wherein the storage controller and the data decompression module are both located in the microcontroller unit.
[0020] Optionally, compressing the instruction trace data and storing the compressed data in the on-chip memory includes:
[0021] A data compression module is called to compress the instruction tracing data, and the compressed data is stored in the storage space corresponding to the traced central processor in the on-chip memory through the storage controller; wherein the data compression module is located in the microcontroller unit.
[0022] In a second aspect, the present application provides an instruction tracking device, which is applied to an instruction tracking controller in a microcontroller unit, wherein the microcontroller unit also includes an on-chip memory and several central processing units; wherein the device includes:
[0023] An instruction tracking module is used to perform instruction tracking on each of the central processors, and obtain a target program counter count value corresponding to a currently executed instruction sent by the tracked central processor; the currently executed instruction is the instruction currently executed by the tracked central processor;
[0024] A count value determination module, used for determining whether the count value of the target program counter is within the count range of the target program counter corresponding to the traced central processor;
[0025] A data compression storage module is used to compress instruction tracing data if the target program counter count value is within the target program counter count range, and store the compressed data in the on-chip memory; the instruction tracing data is the tracing data corresponding to the currently executed instruction obtained after instruction tracing is performed on the traced central processor.
[0026] In a third aspect, the present application provides an electronic device, including:
[0027] Memory, used to store computer programs;
[0028] A processor is used to execute the computer program to implement the aforementioned instruction tracing method.
[0029] In a fourth aspect, the present application provides a computer-readable storage medium for storing a computer program, wherein the computer program implements the aforementioned instruction tracking method when executed by a processor.
[0030] The instruction tracing method of the present application is applied to an instruction tracing controller in a microcontroller unit, wherein the microcontroller unit also includes an on-chip memory and a plurality of central processing units; wherein the method includes: performing instruction tracing on each of the central processing units respectively, and obtaining a target program counter count value corresponding to a currently executed instruction sent by the traced central processing unit; the currently executed instruction is an instruction currently executed by the traced central processing unit; determining whether the target program counter count value is within a target program counter count range corresponding to the traced central processing unit; if the target program counter count value is within the target program counter count range, compressing instruction tracing data, and storing the compressed data in the on-chip memory; the instruction tracing data is tracing data corresponding to the currently executed instruction obtained after performing instruction tracing on the traced central processing unit. It can be seen that the present application performs instruction tracking on multiple central processing units in a microcontroller unit through an instruction tracking controller, optimizes the usage scenarios of instruction tracking, and meets the user's needs for simultaneous instruction tracking on multiple central processing units; and, the present application sets a program counter count range, so that when the program counter count value corresponding to the instruction currently executed by the central processing unit is within the corresponding program counter count range, the instruction tracking data corresponding to the instruction currently executed by the central processing unit is stored, thereby realizing the storage of instruction tracking data within the specified range; further, the present application compresses the instruction tracking data to reduce the storage space required for the instruction tracking data, thereby reducing the resource consumption of the on-chip memory and improving the resource utilization of the on-chip memory. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.
[0032] Figure 1 A flow chart of an instruction tracking method disclosed in this application;
[0033] Figure 2 This is an architecture diagram of a micro control unit disclosed in this application;
[0034] Figure 3 A schematic diagram of the structure of an instruction tracking device disclosed in this application;
[0035] Figure 4 This is a structural diagram of an electronic device disclosed in this application. DETAILED DESCRIPTION
[0036] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0037] The current instruction tracking technology usually performs instruction tracking on a single CPU in a chip, and the instruction tracking technology requires a large on-chip memory to be designed inside the chip to store instruction tracking data; however, when the number of CPU cores increases, the required storage space will become larger and larger, thereby causing the problem of insufficient on-chip memory. To this end, the present application provides an instruction tracking method, which can not only perform instruction tracking on multiple central processing units at the same time, but also realize the storage of instruction tracking data within a specified range, and can reduce the storage space required for instruction tracking data through data compression, thereby improving the resource utilization of on-chip memory.
[0038] See also Figure 1 As shown, an embodiment of the present invention discloses an instruction tracking method, which is applied to an instruction tracking controller in a microcontroller unit, wherein the microcontroller unit also includes an on-chip memory and a plurality of central processing units; wherein the method includes:
[0039] Step S11, performing instruction tracing on each of the central processors respectively, and obtaining a target program counter count value corresponding to a currently executed instruction sent by the traced central processor; the currently executed instruction is the instruction currently executed by the traced central processor.
[0040] In this embodiment, the instruction tracking controller in the microcontroller unit (MCU) performs instruction tracking on each central processor in the microcontroller unit, and obtains the program counter count value corresponding to the instruction currently executed by the traced central processor and sent by the traced central processor. The program counter (ProgramCounter, PC) is a register in the central processor, which is used to store the instruction address. If the count value of the program counter is the address of the currently executed instruction, after completing the instruction fetch operation of the currently executed instruction, the count value of the program counter will automatically increase by one, thereby pointing to the address of the next instruction to be executed.
[0041] In addition, the instruction tracking controller includes sub-controllers corresponding to the plurality of central processing units, that is, one central processing unit corresponds to one sub-controller, and the sub-controller is used to perform instruction tracking on the corresponding central processing unit. In other words, the instruction tracking controller specifically performs instruction tracking on the corresponding central processing unit according to the sub-controllers corresponding to each central processing unit, and obtains the program counter count value corresponding to the currently executed instruction sent by the corresponding central processing unit.
[0042] In this embodiment, before the instruction tracking controller performs instruction tracking on each central processor respectively, it also includes: obtaining a controller setting instruction sent by a host computer that performs data communication with the microcontroller, and writing each processor information to be tracked contained in the controller setting instruction into each local register; wherein each processor information to be tracked includes a processor identifier to be tracked and a corresponding program counter count range. Then, a start-of-work instruction is sent to the corresponding central processor through a sub-controller corresponding to each processor identifier to be tracked to drive the corresponding central processor to start working, and instruction tracking is performed on the corresponding central processor.
[0043] It should be noted that each central processing unit corresponds to a sub-controller and a register in the instruction tracking controller, the sub-controller is used to perform instruction tracking on the corresponding central processing unit, and the register is used to store the processor identifier and the program counter count range. In addition, one processor identifier corresponds to one central processing unit and one sub-controller at the same time; and the processor identifier can be a processor number, etc. Further, one central processing unit corresponds to one program counter count range.
[0044] Among them, the controller setting instruction is specifically an instruction sent to the instruction tracking controller by the host computer that communicates data with the microcontroller unit based on the preset debugging interface. The preset debugging interface is located in the microcontroller unit, that is, the host computer communicates data with the instruction tracking controller through the preset debugging interface.
[0045] Step S12: determine whether the target program counter count value is within the target program counter count range corresponding to the traced CPU.
[0046] In this embodiment, after obtaining the target program counter count value corresponding to the currently executed instruction sent by the traced CPU, it is determined whether the target program counter count value is within the target program counter count range corresponding to the traced CPU.
[0047] Specifically, the instruction tracking controller performs instruction tracking on the corresponding central processing unit according to the sub-controllers corresponding to each central processing unit. For any target sub-controller corresponding to the tracked central processing unit, after obtaining the target program counter count value corresponding to the currently executed instruction sent by the tracked central processing unit, based on the target program counter count range corresponding to the tracked central processing unit stored in the target register, it is determined whether the target program counter count value is within the target program counter count range; wherein the target register is the register corresponding to the target sub-controller.
[0048] Step S13: If the target program counter count value is within the target program counter count range, the instruction tracing data is compressed and the compressed data is stored in the on-chip memory; the instruction tracing data is the tracing data corresponding to the currently executed instruction obtained after instruction tracing is performed on the traced central processor.
[0049] In this embodiment, if the target program counter count value is within the target program counter count range, the instruction tracing data corresponding to the currently executed instruction obtained after instruction tracing of the traced central processor is compressed, and the compressed data is stored in the on-chip memory.
[0050] Specifically, if the target sub-controller corresponding to the CPU being tracked determines that the target program counter count value is within the target program counter count range, the data compression module is called to compress the instruction tracking data corresponding to the currently executed instruction obtained after the CPU being tracked, and the compressed data is stored in the storage space corresponding to the CPU being tracked in the on-chip memory through the storage controller. It should be noted that the on-chip memory is used to store compressed instruction tracking data, and the on-chip memory includes storage space evenly allocated to several CPUs, that is, each CPU corresponds to a storage space in the on-chip memory.
[0051] It should also be noted that the data compression module and the storage controller are both located in the microcontroller unit. The data compression module is used to compress the instruction tracking data, and the data compression algorithm can adopt the LZMA algorithm (Lempel-Ziv-Markov chain-Algorithm, a compression algorithm improved and optimized by Deflate and LZ77 algorithms); the storage controller can receive various working instructions sent by the instruction tracking controller, receive the compressed data sent by the data compression module, and drive the on-chip memory to perform data read and write operations.
[0052] Furthermore, if the target sub-controller corresponding to the tracked central processor determines that the target program counter count value has not reached the lower limit value of the target program counter count range, it continues to perform instruction tracking on the tracked central processor, and continues to obtain the target program counter count value corresponding to the currently executed instruction sent by the tracked central processor until the target program counter count value is within the target program counter count range, and then compresses and stores the instruction tracking data corresponding to the currently executed instruction obtained by instruction tracking.
[0053] In this embodiment, if the target sub-controller corresponding to the tracked central processor determines that the target program counter count value reaches the upper limit value of the target program counter count range, or the storage space corresponding to the tracked central processor in the on-chip memory is full, a stop working instruction is sent to the tracked central processor to drive the tracked central processor to stop working and end the instruction tracking of the tracked central processor. At the same time, information that the instruction tracking of the tracked central processor has ended can also be sent to the host computer so that the host computer knows which central processors have ended instruction tracking.
[0054] It should be noted that when the instruction tracing controller performs instruction tracing on the central processing unit, the on-chip memory will be used as a specific memory to store compressed instruction tracing data; and when the instruction tracing controller ends instruction tracing for all traced central processing units, the on-chip memory can be used as a general memory for designers to use.
[0055] In this embodiment, when the instruction tracking controller obtains the data reading instruction sent by the host computer through the preset debugging interface, the storage controller is called to control the on-chip memory to send the target compressed data corresponding to the data reading instruction stored in itself to the data decompression module, so that the data decompression module decompresses the target compressed data and sends the decompressed data to the host computer through the preset debugging interface. Among them, the storage controller, the data decompression module and the preset debugging interface are all located in the micro control unit.
[0056] It should be noted that the working state of the instruction tracking controller may include an idle state, a setting state, and a tracking state, etc. Specifically, with respect to the working state of the instruction tracking controller, before the instruction tracking controller obtains the controller setting instruction sent by the host computer, the instruction tracking controller is in an idle state; after the instruction tracking controller obtains the controller setting instruction sent by the host computer and before performing instruction tracking on each central processing unit, the instruction tracking controller is in a setting state; during the process of the instruction tracking controller performing instruction tracking on each central processing unit, the instruction tracking controller is in a tracking state, and when the instruction tracking controller ends instruction tracking on all tracked central processing units, the instruction tracking controller is in an idle state.
[0057] It can be seen that the present application performs instruction tracking on multiple central processing units in a microcontroller unit through an instruction tracking controller, optimizes the usage scenarios of instruction tracking, and meets the user's needs for simultaneous instruction tracking on multiple central processing units; and, the present application sets a program counter count range, so that when the program counter count value corresponding to the instruction currently executed by the central processing unit is within the corresponding program counter count range, the instruction tracking data corresponding to the instruction currently executed by the central processing unit is stored, thereby realizing the storage of instruction tracking data within the specified range; further, the present application compresses the instruction tracking data to reduce the storage space required for the instruction tracking data, thereby reducing the resource consumption of the on-chip memory and improving the resource utilization of the on-chip memory.
[0058] See also Figure 2 As shown, an embodiment of the present invention discloses an instruction tracking method, which is applied to an instruction tracking controller in a micro control unit, wherein the micro control unit is a control unit composed of an instruction tracking controller, a preset debugging interface, a data compression module, a storage controller, an on-chip memory, a data decompression module and several central processing units, and a host computer communicates data with the instruction tracking controller and the data decompression module through the preset debugging interface; the specific instruction tracking method includes:
[0059] Obtain the controller setting instruction sent by the host computer through the preset debugging interface, and write the information of each processor to be tracked contained in the controller setting instruction into each local register; wherein each processor to be tracked information includes the processor to be tracked identifier and the corresponding program counter count range. Then, the sub-controller corresponding to each processor identifier to be tracked sends a start-of-work instruction to the corresponding central processor to drive the corresponding central processor to start working, and performs instruction tracking on the corresponding central processor. wherein, one central processor corresponds to one sub-controller and one register in the instruction tracking controller.
[0060] For any traced central processor, instruction tracing is performed on the traced central processor through the target sub-controller corresponding to the traced central processor, and a target program counter count value corresponding to the instruction currently executed by the traced central processor and sent by the traced central processor is obtained. Then, based on the target program counter count range corresponding to the traced central processor stored in the target register corresponding to the target sub-controller, it is determined whether the target program counter count value is within the target program counter count range.
[0061] If the target sub-controller corresponding to the tracked central processor determines that the target program counter count value is within the target program counter count range, the data compression module is called to compress the instruction tracking data corresponding to the currently executed instruction obtained after instruction tracking of the tracked central processor, and store the compressed data in the storage space corresponding to the tracked central processor in the on-chip memory through the storage controller.
[0062] If the target sub-controller corresponding to the tracked central processor determines that the target program counter count value reaches the upper limit value of the target program counter count range, or the storage space corresponding to the tracked central processor in the on-chip memory is full, a stop working instruction is sent to the tracked central processor to drive the tracked central processor to stop working and end the instruction tracking of the tracked central processor. At the same time, the information that the instruction tracking of the tracked central processor has ended can also be sent to the host computer so that the host computer knows which central processors have ended instruction tracking.
[0063] Furthermore, the data read instruction sent by the host computer through the preset debugging interface is obtained, and the storage controller is called to control the on-chip memory to send the target compressed data corresponding to the data read instruction stored in itself to the data decompression module, so that the data decompression module decompresses the target compressed data and sends the decompressed data to the host computer through the preset debugging interface, so that the host computer can view the decompressed instruction tracking data.
[0064] It can be seen that the present application performs instruction tracking on multiple central processing units in a microcontroller unit through an instruction tracking controller, optimizes the usage scenarios of instruction tracking, and meets the user's needs for simultaneous instruction tracking on multiple central processing units; and, the present application sets a program counter count range, so that when the program counter count value corresponding to the instruction currently executed by the central processing unit is within the corresponding program counter count range, the instruction tracking data corresponding to the instruction currently executed by the central processing unit is stored, thereby realizing the storage of instruction tracking data within the specified range; further, the present application compresses the instruction tracking data to reduce the storage space required for the instruction tracking data, thereby reducing the resource consumption of the on-chip memory and improving the resource utilization of the on-chip memory.
[0065] See also Figure 3 As shown, an embodiment of the present invention discloses an instruction tracking device, which is applied to an instruction tracking controller in a microcontroller unit, wherein the microcontroller unit also includes an on-chip memory and a plurality of central processing units; wherein the device includes:
[0066] The instruction tracking module 11 is used to perform instruction tracking on each of the central processors, and obtain the target program counter count value corresponding to the currently executed instruction sent by the tracked central processor; the currently executed instruction is the instruction currently executed by the tracked central processor;
[0067] A count value determination module 12, used for determining whether the count value of the target program counter is within the count range of the target program counter corresponding to the traced CPU;
[0068] The data compression storage module 13 is used to compress the instruction tracing data if the target program counter count value is within the target program counter count range, and store the compressed data in the on-chip memory; the instruction tracing data is the tracing data corresponding to the currently executed instruction obtained after instruction tracing is performed on the traced central processor.
[0069] It can be seen that the present application performs instruction tracking on multiple central processing units in a microcontroller unit through an instruction tracking controller, optimizes the usage scenarios of instruction tracking, and meets the user's needs for simultaneous instruction tracking on multiple central processing units; and, the present application sets a program counter count range, so that when the program counter count value corresponding to the instruction currently executed by the central processing unit is within the corresponding program counter count range, the instruction tracking data corresponding to the instruction currently executed by the central processing unit is stored, thereby realizing the storage of instruction tracking data within the specified range; further, the present application compresses the instruction tracking data to reduce the storage space required for the instruction tracking data, thereby reducing the resource consumption of the on-chip memory and improving the resource utilization of the on-chip memory.
[0070] In some specific embodiments, the instruction tracking controller includes sub-controllers corresponding to the plurality of central processing units, respectively, and the sub-controllers are used to perform instruction tracking on the corresponding central processing units.
[0071] In some specific embodiments, the instruction tracking device further includes:
[0072] A tracing information writing unit, used for acquiring a controller setting instruction sent by a host computer that performs data communication with the microcontroller unit, and writing each processor information to be traced contained in the controller setting instruction into each local register; wherein each processor information to be traced includes a processor identifier to be traced and a corresponding program counter counting range;
[0073] The start instruction sending unit is used to send a start work instruction to the corresponding central processor through the sub-controller corresponding to each of the processor identifiers to be tracked to drive the corresponding central processor to start working, and to track instructions for the corresponding central processor.
[0074] In some specific embodiments, the counting value determination module 12 includes:
[0075] a count value determination unit, configured to determine, through a target sub-controller corresponding to the traced CPU and based on a target register, whether the count value of the target program counter is within a count range of the target program counter corresponding to the traced CPU;
[0076] The target register is a register corresponding to the target sub-controller, and the target register stores the target program counter counting range.
[0077] In some specific embodiments, the instruction tracking device further includes:
[0078] A stop instruction sending unit is used to send a stop working instruction to the tracked central processor to drive the tracked central processor to stop working and end the instruction tracking of the tracked central processor if the target sub-controller determines that the count value of the target program counter reaches the upper limit value of the target program counter count range, or the storage space corresponding to the tracked central processor in the on-chip memory is full.
[0079] In some specific embodiments, the instruction tracking device further includes:
[0080] A data reading unit is used to call a storage controller to control the on-chip memory to send the target compressed data corresponding to the data reading instruction stored in the on-chip memory to a data decompression module when a data reading instruction is obtained from a host computer that communicates data with the microcontroller unit, so that the data decompression module can decompress the target compressed data and send the decompressed data to the host computer; wherein the storage controller and the data decompression module are both located in the microcontroller unit.
[0081] In some specific embodiments, the data compression storage module 13 includes:
[0082] A data compression storage unit is used to call a data compression module to compress the instruction tracking data, and store the compressed data in the storage space corresponding to the tracked central processor in the on-chip memory through the storage controller; wherein the data compression module is located in the micro control unit.
[0083] Furthermore, the present application also discloses an electronic device. Figure 4 This is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content in the diagram cannot be regarded as any limitation on the scope of use of the present application.
[0084] Figure 4 A schematic diagram of the structure of an electronic device 20 provided in an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 is used to store a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the instruction tracking method disclosed in any of the aforementioned embodiments. In addition, the electronic device 20 in this embodiment may specifically be an electronic computer.
[0085] In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.
[0086] In addition, the memory 22, as a carrier for storing resources, can be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon can include an operating system 221, a computer program 222, etc., and the storage method can be temporary storage or permanent storage.
[0087] The operating system 221 is used to manage and control the hardware devices and computer programs 222 on the electronic device 20, and may be Windows Server, Netware, Unix, Linux, etc. In addition to computer programs that can be used to complete the instruction tracing method performed by the electronic device 20 disclosed in any of the aforementioned embodiments, the computer program 222 may further include computer programs that can be used to complete other specific tasks.
[0088] Furthermore, the present application also discloses a computer-readable storage medium for storing a computer program; wherein the computer program, when executed by a processor, implements the aforementioned disclosed instruction tracing method. For the specific steps of the method, reference may be made to the corresponding contents disclosed in the aforementioned embodiments, and no further description will be given here.
[0089] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.
[0090] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.
[0091] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
[0092] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.
[0093] The technical solution provided by the present application is introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for general technicians in this field, according to the idea of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.
Claims
1. An instruction tracking method, characterized in that: An instruction tracking controller applied to a microcontroller unit, wherein the microcontroller unit also includes an on-chip memory and a plurality of central processing units; wherein the method comprises: Performing instruction tracing on each of the central processors, and obtaining a target program counter count value corresponding to a currently executed instruction sent by the traced central processor; the currently executed instruction is an instruction currently executed by the traced central processor; determining whether the target program counter count value is within a target program counter count range corresponding to the traced central processor; If the target program counter count value is within the target program counter count range, the instruction tracing data is compressed and the compressed data is stored in the on-chip memory; the instruction tracing data is the tracing data corresponding to the currently executed instruction obtained after instruction tracing is performed on the traced central processor; The instruction tracking controller includes sub-controllers corresponding to the plurality of central processing units respectively, and the sub-controllers are used to perform instruction tracking on the corresponding central processing units.
2. The instruction tracing method according to claim 1, characterized in that: Before the instruction tracking is performed on each of the central processors, the method further includes: Obtaining a controller setting instruction sent by a host computer that performs data communication with the microcontroller unit, and writing each processor information to be tracked contained in the controller setting instruction into each local register; wherein each processor information to be tracked includes a processor identifier to be tracked and a corresponding program counter count range; The sub-controllers corresponding to the processor identifiers to be tracked send a start-of-work instruction to the corresponding central processor to drive the corresponding central processor to start working, and perform instruction tracking on the corresponding central processor.
3. The instruction tracing method according to claim 2, characterized in that: The determining whether the target program counter count value is located within a target program counter count range corresponding to the traced central processor comprises: Determining, by a target sub-controller corresponding to the traced CPU and based on a target register, whether the target program counter count value is within a target program counter count range corresponding to the traced CPU; The target register is a register corresponding to the target sub-controller, and the target register stores the target program counter counting range.
4. The instruction tracing method according to claim 3, characterized in that: After determining whether the target program counter count value is within the target program counter count range corresponding to the traced central processor, the method further includes: If the target sub-controller determines that the count value of the target program counter reaches the upper limit value of the target program counter count range, or the storage space corresponding to the tracked central processor in the on-chip memory is full, a stop working instruction is sent to the tracked central processor to drive the tracked central processor to stop working, and end the instruction tracking of the tracked central processor.
5. The instruction tracking method according to any one of claims 1 to 4, characterized in that: Also includes: When a data read instruction is obtained from a host computer that communicates data with the microcontroller unit, the storage controller is called to control the on-chip memory to send the target compressed data corresponding to the data read instruction stored in itself to the data decompression module, so that the data decompression module decompresses the target compressed data and sends the decompressed data to the host computer; wherein the storage controller and the data decompression module are both located in the microcontroller unit.
6. The instruction tracing method according to claim 5, characterized in that: The compressing the instruction trace data and storing the compressed data in the on-chip memory comprises: A data compression module is called to compress the instruction tracing data, and the compressed data is stored in the storage space corresponding to the traced central processor in the on-chip memory through the storage controller; wherein the data compression module is located in the microcontroller unit.
7. An instruction tracking device, characterized in that: An instruction tracking controller applied to a microcontroller unit, wherein the microcontroller unit also includes an on-chip memory and a plurality of central processing units; wherein the device includes: An instruction tracking module is used to perform instruction tracking on each of the central processors, and obtain a target program counter count value corresponding to a currently executed instruction sent by the tracked central processor; the currently executed instruction is the instruction currently executed by the tracked central processor; A count value determination module, used for determining whether the count value of the target program counter is within the count range of the target program counter corresponding to the traced central processor; a data compression storage module, for compressing instruction tracing data if the target program counter count value is within the target program counter count range, and storing the compressed data in the on-chip memory; the instruction tracing data is tracing data corresponding to the currently executed instruction obtained after instruction tracing is performed on the traced central processor; The instruction tracking controller includes sub-controllers corresponding to the plurality of central processing units respectively, and the sub-controllers are used to perform instruction tracking on the corresponding central processing units.
8. An electronic device, characterized in that: include: Memory, used to store computer programs; A processor, configured to execute the computer program to implement the instruction tracing method according to any one of claims 1 to 6.
9. A computer-readable storage medium, characterized in that: Used to store a computer program, which, when executed by a processor, implements the instruction tracing method according to any one of claims 1 to 6.