Step-size correction method for digital-to-time converter in ADPLL
By receiving the phase information to be delayed in the ADPLL and calculating the correction coefficients, dynamically switching the gain coefficients, the instability problem of DTC step size under voltage and temperature changes is solved, and high-precision step size correction and phase noise spectrum stability are achieved.
Patent Information
- Application Number
- CN202411160766.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-22
- Publication Date
- 2024-12-10
- Estimated Expiration
- 2044-08-22
AI Technical Summary
Existing digital time converters (DTCs) cannot correct the step length in real time with high accuracy when facing voltage and temperature changes, resulting in unstable clock signal delay, resulting in bumps or spikes on the phase noise spectrum, reducing clock performance. .
By receiving the phase information to be delayed, combining the phase error and gain coefficients in the ADPLL, the correction coefficients are calculated, and the gain coefficients are dynamically switched when the jitter of the ADPLL output clock changes, adaptive correction of the DTC step size is achieved.
High-precision step size correction is achieved, with a step size error of less than 1%, which can track real-time changes, prevent jitter caused by changes in the external environment, maintain the stable phase noise spectrum, and avoid degradation in clock performance caused by changes in voltage and temperature.
Smart Images
Figure CN118677448B_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of clock chips, and in particular to a step length correction method for a digital time converter in an ADPLL. Background Art
[0002] In some all digital phase locked loop (ADPLL) circuits, a digital to time converter (DTC) may be used to delay the clock signal to obtain a clock signal with a required phase.
[0003] DTCs are often used in digital systems, communication systems, control systems, and other applications. They can be used to generate precise time delays, timing control signals, pulse generation, and other tasks. In digital systems, DTCs can be used for clock synchronization, data sampling, sequential logic control, and other aspects.
[0004] The design of DTC can be based on components or modules such as counters, clock generators, and delay lines. Among them, counters are usually used to calculate the period or duration of a specific event, while clock generators can generate clock signals with a specific frequency, and delay lines can achieve precise time delay.
[0005] The performance of these digital time converters depends on factors such as their accuracy, resolution, stability, etc. In applications with high accuracy and high stability, it is usually necessary to use specially designed DTC circuits or devices to ensure that the time intervals they output meet the requirements.
[0006] Since the digital time converter is greatly affected by the process, voltage and temperature, the unit delay value of the digital time converter, that is, the step size, is not a fixed value, but may fluctuate within a certain range. If the step size is not corrected, the delay of the clock signal will be unexpectedly advanced or delayed, resulting in bumps or spikes on the phase noise spectrum, reducing the clock performance.
[0007] The existing foreground correction technology cannot perform real-time correction according to voltage and temperature changes, while the background correction technology is not accurate and cannot prevent jitter caused by drastic changes in the external environment, such as voltage and temperature.
[0008] How to calibrate the step length of DTC with high precision in the background has become a difficult problem in the art. Summary of the invention
[0009] In order to alleviate or partially alleviate the above technical problems, the solution of the present invention is as follows:
[0010] A step correction method for a digital time converter in an ADPLL comprises the following steps: receiving phase information to be delayed; obtaining a correction coefficient according to the phase information to be delayed, a phase error output by a phase detector in the ADPLL and a gain coefficient set; multiplying the phase information to be delayed and the correction coefficient, and rounding down the multiplication result to obtain a DTC code value; in addition, when the jitter of the output clock of the ADPLL is not lower than a preset threshold value, applying the gain coefficient set under a first setting; when the jitter of the output clock of the ADPLL is lower than the preset threshold value, applying the gain coefficient set under a second setting; and the gain coefficient set comprises a first gain coefficient and a second gain coefficient; the first gain coefficient and the second gain coefficient in the gain coefficient set under the first setting are respectively greater than the first gain coefficient and the second gain coefficient in the gain coefficient set under the second setting.
[0011] Furthermore, the correction coefficient is obtained, comprising the following steps: multiplying the delayed phase information by -1, and then adding 0.5 to obtain a first result; multiplying the first result and the phase error to obtain a second result, and the second result and the first gain coefficient After multiplication, the third result is obtained; the third result and the previous value of the fourth result are added to obtain the fourth result; the fourth result and After multiplication, the fifth result is obtained, where is the second gain coefficient.
[0012] Further, the obtaining of the correction coefficient further comprises the following steps: After multiplication, a seventh result is obtained; the seventh result and the previous value of the sixth result are added to obtain an eighth result; after adding the fifth result and the eighth result, a sixth result is obtained; after performing a reciprocal process on the sixth result, the correction coefficient is obtained.
[0013] Further, the previous value of the fourth result is the fourth result after a unit delay; the previous value of the sixth result is the sixth result after a unit delay; and the unit delay is a delay of one clock cycle.
[0014] Further, before applying the gain coefficient set under the first setting or the gain coefficient set under the second setting, it is first determined whether the phase-locked loop of the ADPLL is preliminarily locked.
[0015] Furthermore, after the phase-locked loop of the ADPLL is preliminarily locked, it is determined whether the jitter of the output clock of the ADPLL is lower than a preset threshold value.
[0016] The technical solution of the present invention has one or more of the following beneficial technical effects:
[0017] (1) The DTC correction coefficient can be adaptively calculated in the background without affecting normal operation.
[0018] (2) High accuracy. In a specific example, the step error of DTC is less than 1%.
[0019] (3) It can track real-time changes without any additional correction process and does not take up any extra time.
[0020] (4) The glitches on the phase noise spectrum are few and low in amplitude.
[0021] (5) It can prevent jitter caused by drastic changes in the external environment. When the voltage and temperature change, the step size of the DTC will also change with the actual step size; when the voltage and temperature change drastically or there is a sudden introduction of noise, the step size of the DTC will not change abruptly, and the phase noise spectrum can remain stable.
[0022] In addition, other beneficial effects of the present invention will be mentioned in the specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 It is a flow chart of a step length correction method of a digital time converter in an ADPLL of the present invention;
[0024] Figure 2 is a schematic diagram of a step correction device for a digital time converter;
[0025] Figure 3 is a schematic diagram of a correction execution module;
[0026] Figure 4 is a schematic diagram of a correction coefficient acquisition module;
[0027] Figure 5 It is an overall working flow chart of the present invention when applied in a fully digital phase-locked loop. DETAILED DESCRIPTION
[0028] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0029] In order to clearly describe the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, words such as "first" and "second" are used to distinguish the same or similar items with substantially the same functions and effects. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order.
[0030] Figure 1 The flowchart of the step length correction method of the digital time converter in the ADPLL of the present invention is as follows. A step length correction method of the digital time converter in the ADPLL comprises the following steps:
[0031] Receive phase information to be delayed.
[0032] A correction coefficient is obtained according to the phase information to be delayed, a phase error output by a phase detector in the ADPLL, and a set of gain coefficients.
[0033] The phase information to be delayed is multiplied by the correction coefficient, and the result of the multiplication is rounded down to obtain a DTC code value.
[0034] In addition, when the jitter of the output clock of the ADPLL is not lower than the preset threshold value, the gain coefficient set under the first setting is applied; when the jitter of the output clock of the ADPLL is lower than the preset threshold value, the gain coefficient set under the second setting is applied.
[0035] In the present invention, the gain coefficient set includes a first gain coefficient and a second gain coefficient. The gain coefficient set has two different settings: the first gain coefficient and the second gain coefficient in the gain coefficient set under the first setting are respectively greater than the first gain coefficient and the second gain coefficient in the gain coefficient set under the second setting.
[0036] Furthermore, the ADPLL in the present invention includes a phase detector and a digital time converter. The phase error output by the phase detector is sent to the digital time converter, and the digital time converter includes a step correction device of the digital time converter. The purpose of the ADPLL is to obtain a stable output clock.
[0037] Since different all-digital phase-locked loops have different structures, the present invention only shows several modules in the all-digital phase-locked loop that are most relevant to the present invention. The present invention is not limited to a specific phase-locked loop structure. The specific implementation of the above steps will be described in detail below.
[0038] Figure 2 The step length correction device of the digital time converter of the present invention comprises a correction execution module and a correction coefficient acquisition module.
[0039] The step correction device of the digital time converter is configured to perform: receiving the phase information to be delayed, and outputting the DTC code value after correction processing.
[0040] Specifically, the correction processing step is performed by the correction execution module, and the correction coefficient k required by the correction execution module is dtc The correction coefficient acquisition module obtains it according to the input information to be delayed.
[0041] Figure 3 is a schematic diagram of the correction execution module. After receiving the phase information to be delayed, the correction execution module converts the phase information to be delayed and the correction coefficient k dtc The DTC code value is obtained by multiplying the multiplication result and rounding it down through a rounding-down module.
[0042] Figure 4 is a schematic diagram of a correction coefficient acquisition module, which discloses how to obtain the correction coefficient k according to the phase information to be delayed dtc .
[0043] In the present invention, the correction coefficient k is obtained according to the phase information to be delayed, the phase error output by the phase detector in the ADPLL and the gain coefficient set. dtc .
[0044] Specifically, the delayed phase information is first multiplied by -1, and then 0.5 is added to obtain a first result. The first result is multiplied by the phase error to obtain a second result, and the second result is multiplied by the first gain coefficient. After multiplication, the third result is obtained.
[0045] The third result is added to the fourth result after a unit delay (for example, one clock cycle) to obtain a fourth result. The fourth result after the unit delay is also the previous value of the fourth result.
[0046] The fourth result and After multiplication, the fifth result is obtained, where is the second gain coefficient.
[0047] In addition, the sixth result and A seventh result is obtained after multiplication; the seventh result and the sixth result after unit delay are added to obtain an eighth result.
[0048] The fifth result and the eighth result are added to obtain the sixth result. The sixth result is processed by the reciprocal module to obtain the correction coefficient k. dtc In other words, the sixth result is 1 / k dtc , the sixth result after unit delay, that is, the previous value of the sixth result.
[0049] In summary, in the present invention, the average step length of DTC is equal to the correction coefficient k dtc / Frequency value of the output clock of the fully digital phase-locked loop.
[0050] Figure 5 It is an overall working flow chart of the present invention when applied in a fully digital phase-locked loop.
[0051] First, the ADPLL is powered on and then initialized. After that, the full digital phase-locked loop operating mode is selected and it is determined whether the DTC will be used.
[0052] If DTC will not be used, there is no need to calibrate the step size of DTC; if DTC is needed, determine whether the ADPLL phase-locked loop is preliminarily locked. If the preliminarily locked is not completed, do not start the calibration temporarily and do not enter the calibration process.
[0053] After the ADPLL phase-locked loop is initially locked, the calibration is started and the calibration process is entered. Then, it is determined whether the jitter of the ADPLL output clock is lower than a preset threshold value. If it is not lower than the threshold value, the larger first gain coefficient and second gain coefficient are used, that is, the gain coefficient set under the first setting is applied at this time to perform the step length calibration of the DTC.
[0054] When the jitter of the output clock of the ADPLL is lower than the preset threshold value, it is considered that the corrected result is equivalent to the step length of the real DTC, and only the smaller first gain coefficient and the second gain coefficient need to be used, that is, the gain coefficient set under the second setting is applied at this time to perform the step length correction of the DTC. At the same time, the output clock of the ADPLL can be used normally.
[0055] In order to better illustrate the present invention, numerous specific details are provided in the above specific embodiments. It should be understood by those skilled in the art that the present invention can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present invention.
[0056] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.
Claims
1. A step length correction method for a digital time converter in an ADPLL, characterized in that: The steps include: receiving phase information to be delayed; Obtaining a correction coefficient according to the phase information to be delayed, a phase error output by a phase detector in the ADPLL, and a set of gain coefficients; Multiplying the phase information to be delayed and the correction coefficient, and rounding down the result of the multiplication to obtain a DTC code value; When the jitter of the output clock of the ADPLL is not lower than the preset threshold value, the gain coefficient set under the first setting is applied; when the jitter of the output clock of the ADPLL is lower than the preset threshold value, the gain coefficient set under the second setting is applied; and, The gain coefficient set includes a first gain coefficient and a second gain coefficient; the first gain coefficient and the second gain coefficient in the gain coefficient set under the first setting are respectively greater than the first gain coefficient and the second gain coefficient in the gain coefficient set under the second setting; The step of obtaining the correction coefficient comprises the following steps: Multiply the delayed phase information by -1, and then add 0.5 to obtain the first result; The first result and the phase error are multiplied to obtain the second result, and the second result and the first gain coefficient are multiplied to obtain the second result. After multiplication, the third result is obtained; Adding the previous values of the third result and the fourth result to obtain a fourth result; The fourth result and After multiplication, the fifth result is obtained, where is the second gain coefficient; By adding the previous value of the sixth result and After multiplication, the seventh result is obtained; adding the seventh result and the previous value of the sixth result to obtain an eighth result; After adding the fifth result and the eighth result, a sixth result is obtained; After performing the inverse processing on the sixth result, the correction coefficient is obtained; wherein, The previous value of the fourth result is the fourth result after a unit delay; the previous value of the sixth result is the sixth result after a unit delay; and the unit delay is a delay of one clock cycle.
2. The step length correction method of the digital time converter in the ADPLL according to claim 1, characterized in that: Before applying the gain coefficient set under the first setting or the gain coefficient set under the second setting, it is first determined whether the phase-locked loop of the ADPLL is preliminarily locked.
3. The step length correction method of the digital time converter in the ADPLL according to claim 2, characterized in that: When the phase-locked loop of the ADPLL is initially locked, it is determined whether the jitter of the output clock of the ADPLL is lower than a preset threshold value.