A multifunctional power management chip

Abstract

The present application is applicable to the field of semiconductor device technology, and provides a multifunctional power management chip, which includes: a linear voltage regulator circuit, a negative voltage power supply generation circuit, a drive circuit and an operational amplifier circuit; the linear voltage regulator circuit is used to convert the built-in reference voltage into the output voltage required by the chip; the negative voltage power supply generation circuit is used to adjust the output voltage of the chip; the operational amplifier circuit is used to amplify the chip input signal; the drive circuit is used to drive PMOSFET. The present application can provide a multifunctional power management chip with the characteristics of controllable timing, high integration and low static power consumption, and performs complete power supply modulation around the application of the power amplifier, realizing one-chip control of power supply, gate voltage control and drain voltage modulation.

Description

Technical Field

[0001] The present application belongs to the technical field of semiconductor devices, and in particular, relates to a multifunctional power management chip. Background Art

[0002] With the development of science and technology, power management chips are increasingly used in various fields. Power management chips are responsible for controlling, managing, and protecting the supply of power. They are responsible for the conversion, distribution, detection, and other management of electric energy in the entire control system, ensuring the normal operation of the equipment, and have a vital impact on the overall performance of the equipment. The application of power management chips covers consumer electronics, automotive electronics, wearable devices, industrial control, and new energy. In the future, power management chips will play a more important role in more fields, bringing greater convenience and value to people's lives and work.

[0003] The voltage regulator, driver, negative power supply and operational amplifier constructed with discrete devices all have the defects of large size, low static power consumption and difficulty in control, and cannot achieve the goals of low static power consumption and high integration. Summary of the invention

[0004] In order to overcome the problems existing in the related technology, the embodiment of the present application provides a multifunctional power management chip with the characteristics of controllable timing, high integration and low static power consumption. It performs complete power modulation around the application of the power amplifier and realizes one-chip control of power supply, gate voltage control and leakage voltage modulation.

[0005] This application is implemented through the following technical solutions:

[0006] In a first aspect, an embodiment of the present application provides a multifunctional power management chip, including a linear voltage regulator circuit, a negative voltage power supply generating circuit, a driving circuit and an operational amplifier circuit;

[0007] The first end of the linear voltage regulator circuit is connected to the first enable control port; the second end of the linear voltage regulator circuit is respectively connected to the first end of the negative voltage power supply generating circuit and the second working power supply; the third end of the linear voltage regulator circuit is respectively connected to the third end of the negative voltage power supply generating circuit, the second end of the driving circuit, the fourth end of the operational amplifier circuit and the first power supply; the linear voltage regulator circuit is used to convert the built-in reference voltage into the output voltage required by the chip;

[0008] The second end of the negative voltage power supply generating circuit is respectively connected to the second enable control port and the first end of the operational amplifier circuit; the fourth end of the negative voltage power supply generating circuit is the first output port of the negative voltage power supply generating circuit; the fifth end of the negative voltage power supply generating circuit is the second output port of the negative voltage power supply generating circuit; the sixth end of the negative voltage power supply generating circuit is the third output port of the negative voltage power supply generating circuit; the negative voltage power supply generating circuit is used to adjust the output voltage of the chip;

[0009] The second end of the operational amplifier circuit is connected to the second input signal interface; the third end of the operational amplifier circuit is connected to; the fifth end of the operational amplifier circuit is the output port of the operational amplifier circuit; the operational amplifier circuit is used to amplify the chip input signal;

[0010] The first end of the driving circuit is connected to the first input signal interface; the third end of the driving circuit is connected to the output port of the driving circuit; the driving circuit is used to drive the PMOSFET.

[0011] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0012] In the embodiment of the present application, the built-in reference voltage is converted into the required output voltage through a linear voltage regulator circuit; the output voltage is regulated by a negative voltage power supply generating circuit to drive the gate of the power amplifier; the PMOSFET is driven by a driving circuit; the input signal is amplified by an operational amplifier circuit, and the voltage controlled oscillator (VCO) is frequency modulated, so that the multifunctional power management chip has the characteristics of controllable timing, high integration and low static power consumption, and complete power supply modulation is performed around the application of the power amplifier to achieve one-chip control of power supply, gate voltage control and leakage voltage modulation.

[0013] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0015] Figure 1 is a schematic diagram of the structure of a multifunctional power management chip provided in one embodiment of the present application;

[0016] Figure 2 is a structural diagram of a first enabling control module provided in an embodiment of the present application;

[0017] Figure 3 is a structural schematic diagram of a pre-voltage stabilization module provided in an embodiment of the present application;

[0018] Figure 4 is a schematic structural diagram of a bandgap reference voltage source module provided in an embodiment of the present application;

[0019] Figure 5is a structural diagram of a feedback module provided in an embodiment of the present application;

[0020] Figure 6 is a structural schematic diagram of a negative voltage power supply generating circuit provided in one embodiment of the present application;

[0021] Figure 7 is a structural diagram of a second enabling control module provided in an embodiment of the present application;

[0022] Figure 8 is a schematic diagram of the structure of a reference module provided in an embodiment of the present application;

[0023] Fig. 9 is a schematic diagram of the structure of a comparator module provided in an embodiment of the present application;

[0024] Fig.10 is a structural diagram of an oscillator module provided in one embodiment of the present application;

[0025] Fig.11 is a structural diagram of a non-overlapping clock module provided in an embodiment of the present application;

[0026] Fig.12 It is a structural schematic diagram of a negative pressure charge pump power tube module provided in an embodiment of the present application;

[0027] Fig.13 is a schematic diagram of the structure of a driving circuit provided in an embodiment of the present application;

[0028] Fig.14 Schematic diagram of the structure of an operational amplifier circuit provided in one embodiment of the present application. DETAILED DESCRIPTION

[0029] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0030] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0031] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0032] In addition, in the description of the present application specification and the attached claims, the terms "first", "second", "third", or "first", "second", "third", or "first branch", "second branch", "third branch", etc. are only used to distinguish the description and shall not be understood as indicating or implying relative importance.

[0033] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0034] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0035] Figure 1 is a schematic diagram of the structure of a multifunctional power management chip provided in an embodiment of the present application, referring to Figure 1 , the multi-function power management chip is described in detail as follows:

[0036] An embodiment of the present application provides a multifunctional power management chip, including a linear voltage regulator circuit 100 , a negative voltage power supply generating circuit 200 , a driving circuit 300 and an operational amplifier circuit 400 .

[0037] The first end of the linear voltage regulator circuit 100 is connected to the first enable control port ENB; the second end of the linear voltage regulator circuit 100 is respectively connected to the first end of the negative voltage power supply generating circuit 200 and the second working power supply VDD2; the third end of the linear voltage regulator circuit 100 is respectively connected to the third end of the negative voltage power supply generating circuit 200, the second end of the driving circuit 300, the fourth end of the operational amplifier circuit 400 and the first power supply VB; the linear voltage regulator circuit 100 is used to convert the built-in reference voltage into the output voltage required by the chip.

[0038] The second end of the negative voltage power supply generating circuit 200 is respectively connected to the second enable control port ENA and the first end of the operational amplifier circuit 400; the fourth end of the negative voltage power supply generating circuit 200 is the first output port NADJ of the negative voltage power supply generating circuit 200; the fifth end of the negative voltage power supply generating circuit 200 is the second output port NOUT of the negative voltage power supply generating circuit 200; the sixth end of the negative voltage power supply generating circuit 200 is the third output port NMID of the negative voltage power supply generating circuit 200; the negative voltage power supply generating circuit 200 is used to adjust the output voltage of the chip.

[0039] The second end of the operational amplifier circuit 400 is connected to the second input signal interface PINB; the third end of the operational amplifier circuit 400 is connected to the second enable control port ENA; the fifth end of the operational amplifier circuit 400 is the output port POUTB of the operational amplifier circuit 400; the operational amplifier circuit 400 is used to amplify the chip input signal.

[0040] A first terminal of the driving circuit 300 is connected to the first input signal interface PINA; a third terminal of the driving circuit 300 is connected to the output port POUTA of the driving circuit 300; and the driving circuit 300 is used to drive the PMOSFET.

[0041] Among them, the peripheral interfaces of the multi-functional power management chip, such as the first enable control port ENB, the second enable control port ENA, the first input signal interface PINA, the second input signal interface PINB, the second working power supply VDD2, the first output port NADJ of the negative voltage power supply generating circuit 200, the second output port NOUT of the negative voltage power supply generating circuit 200, the third output port NMID of the negative voltage power supply generating circuit 200, the first power supply VB, etc. can all be grounded GND.

[0042] Exemplarily, the connection relationship between the peripheral interface of the multifunctional power management chip and the peripheral simplified model is as follows: Figure 1 The first output port NADJ of the negative voltage power supply generating circuit 200 is connected to the resistor R ADJ The first end of the negative voltage power supply generating circuit 200 is connected to the second output port NOUT of the resistor R ADJ The second end of the diode, the anode.

[0043] Exemplarily, the built-in reference voltage is converted into the required output voltage by the linear voltage regulator circuit 100, and multiple outputs of the negative voltage power supply generating circuit 200 are combined with the adjustable resistor R ADJAnd capacitors, etc., to achieve output voltage regulation. The output voltage is not only used for internal power supply, but also can provide stable voltage for corresponding low-voltage devices, such as single-chip microcomputers, common anode three-color lamps and other devices, to drive the gate of the power amplifier Q1 in the peripheral simplified model; drive the power field effect transistor (PMOSFET) Q2 through the driving circuit 300; amplify the 0-2V input signal through the operational amplifier circuit 400, and modulate the frequency of the VCO, so that the multi-functional power management chip has the characteristics of controllable timing, high integration and low static power consumption, and performs complete power supply modulation around the application of the power amplifier, realizing one-chip control of power supply, gate voltage control and leakage voltage modulation.

[0044] In one embodiment, see Figure 2-Figure 5 The linear voltage stabilization circuit 100 includes a first enabling control module 101 , a pre-stabilization module 102 , a bandgap reference voltage source module 103 and a feedback module 104 .

[0045] The input end of the first enabling control module 101 is connected to the first end of the linear voltage regulator circuit 100, that is, connected to the first enabling control port ENB; the first output end ENB_P of the first enabling control module 101 is connected to the first input end of the pre-voltage regulator module 102; the first output end ENB_P of the first enabling control module 101 is in phase with the input end of the first enabling control module 101; the second output end ENB_N of the first enabling control module 101 is connected to the second input end of the pre-voltage regulator module 102; the second output end ENB_N of the first enabling control module 101 is in anti-phase with the input end of the first enabling control module 101.

[0046] The enabling control function of the first enabling control module 101 can control the timing of each circuit, so that the product can be controlled by the single chip microcomputer to complete the startup, standby and shutdown functions, and reduce the power consumption in the standby and shutdown states.

[0047] The first output end of the pre-regulator module 102 is connected to the power supply input end of the bandgap reference voltage source module 103; the reference output end of the bandgap reference voltage source module 103 is connected to the first input end of the feedback module 104; the first output end of the feedback module 104 outputs the voltage input VDD2 as the second working power supply.

[0048] For example, see Figure 2 The first enabling control module 101 specifically includes a second hysteresis protection module SCHMIDT2, a second reset resistor RSET2, a first PMOS transistor MPH1, a second PMOS transistor MPH2, a third PMOS transistor MPH3, a first NMOS transistor MNH1, a second NMOS transistor MNH2 and a third NMOS transistor MNH3.

[0049] The first end of the second hysteresis protection module SCHMIDT2 is respectively connected to the input end of the first enable control module 101 and the second end of the second reset resistor RSET2; the second end of the second hysteresis protection module SCHMIDT2 is respectively connected to the gate of the first PMOS transistor MPH1 and the gate of the first NMOS transistor MNH1.

[0050] The first end of the second reset resistor RSET2, the source of the first PMOS tube MPH1, the source of the second PMOS tube MPH2 and the source of the third PMOS tube MPH3 are all connected to the first power supply VB; the drain of the first PMOS tube MPH1 is respectively connected to the drain of the first NMOS tube MNH1, the gate of the second PMOS tube MPH2 and the gate of the second NMOS tube MNH2; the source of the first NMOS tube MNH1, the source of the second NMOS tube MNH2 and the source of the third NMOS tube MNH3 are all grounded; the drain of the second PMOS tube MPH2, the drain of the second NMOS tube MNH2, the gate of the third PMOS tube MPH3 and the gate of the third NMOS tube MNH3 are all connected to the second output terminal ENB_N of the first enable control module 101; the drain of the third PMOS tube MPH3 and the drain of the third NMOS tube MNH3 are both connected to the first output terminal ENB_P of the first enable control module 101.

[0051] For example, see Figure 3 The pre-regulator module 102 includes a fourth NMOS transistor MNH4, a fifth NMOS transistor MNH5, a sixth NMOS transistor MNH6, a seventh NMOS transistor MNH7, a first resistor R1, a second resistor R2, a first diode D1, a second diode D2, a third capacitor C3 and a fourth capacitor C4.

[0052] The first diode D1 and the second diode D2 are both Zener diodes.

[0053] The gate of the fourth NMOS tube MNH4 is connected to the first input terminal of the pre-regulator module 102, that is, the first output terminal ENB_P of the first enable control module 101 is used as input. The drain of the fourth NMOS tube MNH4 is connected to the second end of the first resistor R1; the first end of the first resistor R1 and the first end of the second resistor R2 are both connected to the first power supply VB. The source of the fourth NMOS tube MNH4 is respectively connected to the drain of the fifth NMOS tube MNH5, the cathode of the first diode D1, the first end of the third capacitor C3 and the gate of the seventh NMOS tube MNH7. The second end of the second resistor R2 is connected to the drain of the seventh NMOS tube MNH7.

[0054] The gate of the fifth NMOS transistor MNH5 is connected to the second input terminal of the pre-regulator module 102, that is, the second output terminal ENB_N of the first enable control module 101 is used as input. The source of the fifth NMOS transistor MNH5, the anode of the first diode D1, the second end of the third capacitor C3, the source of the sixth NMOS transistor MNH6, the anode of the second diode D2 and the second end of the fourth capacitor C4 are all grounded.

[0055] The gate of the sixth NMOS transistor MNH6 is connected to the second input terminal of the pre-regulator module 102, that is, the second output terminal ENB_N of the first enable control module 101 is used as input. The drain of the sixth NMOS transistor MNH6, the cathode of the second diode D2, the first terminal of the fourth capacitor C4 and the source of the seventh NMOS transistor MNH7 are all connected to the first output terminal of the pre-regulator module 102.

[0056] For example, see Figure 4 The bandgap reference voltage source module 103 includes a first low voltage PMOS transistor MP1, a second low voltage PMOS transistor MP2, a first low voltage NMOS transistor MN1, a second low voltage NMOS transistor MN2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first NPN transistor NPN1 and a second NPN transistor NPN2.

[0057] The source of the first low-voltage PMOS tube MP1, the source of the second low-voltage PMOS tube MP2 and the first end of the fifth resistor are all connected to the power supply input end of the bandgap reference voltage source module 103; the drain of the first low-voltage PMOS tube MP1 is respectively connected to the gate of the first low-voltage PMOS tube MP1, the gate of the second low-voltage PMOS tube MP2, the drain of the second low-voltage NMOS tube MN2 and the collector of the first NPN-type transistor NPN1; the drain of the second low-voltage PMOS tube MP2 and the third resistor R3 are both connected to the reference output end VREF of the bandgap reference voltage source module 103.

[0058] The second end of the fifth resistor R5 is respectively connected to the drain of the first low-voltage NMOS transistor MN1 and the gate of the second low-voltage NMOS transistor MN2; the gate of the first low-voltage NMOS transistor MN1 is connected to the reference output end of the bandgap reference voltage source module 103; the source of the first low-voltage NMOS transistor MN1, the source of the second low-voltage NMOS transistor MN2, the emitter of the first NPN transistor NPN1 and the emitter of the second NPN transistor NPN2 are all grounded. The base of the first NPN transistor NPN1 is respectively connected to the collector of the second NPN transistor NPN2 and the second end of the fourth resistor R4; the first end of the fourth resistor R4 is respectively connected to the second end of the third resistor R3 and the base of the second NPN transistor NPN2.

[0059] For example, see Figure 5The feedback module 104 includes a first operational amplifier OP1, a fourth PMOS transistor MPH4, a sixth resistor R6 and a seventh resistor R7.

[0060] The negative input terminal of the first operational amplifier OP1 is connected to the first input terminal of the feedback module 104, that is, the reference output voltage VREF of the reference output terminal of the bandgap reference voltage source module 103 is used as input. The output terminal of the first operational amplifier OP1 is connected to the gate of the fourth PMOS tube MPH4; the positive electrode of the working power supply of the first operational amplifier OP1 and the source of the fourth PMOS tube MPH4 are both connected to the first power supply VB; the negative electrode of the working power supply of the first operational amplifier OP1 and the second end of the sixth resistor R6 are both grounded; the positive input terminal of the first operational amplifier OP1 is respectively connected to the first end of the sixth resistor R6 and the second end of the seventh resistor R7; the drain of the fourth PMOS tube MPH4 and the first end of the seventh resistor R7 are both connected to the first output terminal of the feedback module 104, and the output is the voltage VDD2 as the second working power supply.

[0061] Among them, MPH1~MPH4 are high-voltage PMOS devices, MNH1~MNH7 are high-voltage NMOS devices, MN1 and MN2 are low-voltage NMOS devices, and MP1 and MP2 are low-voltage PMOS devices.

[0062] For example, the linear voltage regulator circuit converts the 5-12V power supply voltage into a 3.3V output voltage, which is used to provide power for the control module of the negative voltage power supply generation circuit and external devices (such as a common anode tricolor lamp, etc.). The enable control function is used to control the timing of each circuit, so that the product can be controlled by the single-chip microcomputer to complete the power-on, standby and shutdown functions, and reduce the power consumption in the standby and shutdown states.

[0063] The linear voltage stabilization circuit 100 is provided with a reference voltage by a bandgap reference voltage source module 103. The first operational amplifier OP1, each PMOS tube, and a resistor form a negative feedback loop. The voltage conversion function is completed through the negative feedback loop, and the 6-12V power supply voltage is converted into a 3.3V output voltage. The output voltage is not only used for internal power supply, but also can provide a stable voltage for corresponding low-voltage devices. At the same time, the circuit integrates an enable control function, which is controlled by the first enable control module 101, and is internally set to a high level. The function is to work when connected to the first power supply VB at a high level, and stop working when connected to the ground at a low level.

[0064] In one embodiment, see Figure 6 , negative voltage power supply generating circuit 200 second enabling control module 201, reference module 202, comparator module 203, oscillator module 204, non-overlapping clock module 205 negative voltage charge pump power tube module 206, eighth resistor R8, adjustable resistor R ADJ, a first capacitor C1, a second capacitor C2, a third diode D3 and a fourth diode D4.

[0065] The input end of the second enable control module 201 is connected to the second end of the negative voltage power supply generating circuit 200; the first output end ENA_P of the second enable control module 201 is respectively connected to the first input end of the comparator module 203 and the first input end of the oscillator module 204; the second output end ENA_N of the second enable control module 201 is respectively connected to the second input end of the comparator module 203, the second input end of the oscillator module 204 and the first input end of the non-overlapping clock module 205.

[0066] The enabling control function of the second enabling control module 201 can control the timing of each circuit, so that the product can be controlled by the single chip microcomputer to complete the startup, standby and shutdown functions, and reduce the power consumption in the standby and shutdown states.

[0067] The third input terminal of the comparator module 203 is connected to the second output terminal VREF2 of the reference module 202; the first output terminal CTRL1 of the comparator module 203 is connected to the first input terminal of the negative charge pump power tube module 206; the second output terminal NOUFFB of the comparator module 203 is respectively connected to the second end of the eighth resistor R8 and the adjustable resistor R ADJ The first end of the adjustable resistor R ADJ The second end of is respectively connected to the second end of the second capacitor C2, the anode of the third diode D3 and the second output port NOUT of the negative voltage power supply generating circuit 200; the first end of the second capacitor C2 is grounded.

[0068] The reference voltage at the input end of the reference module 202 is the same as the voltage VREF at the reference output end of the bandgap reference voltage source module 103 ; the first output end VREF1 of the reference module 202 is connected to the first end of the eighth resistor R8 .

[0069] The first output terminal OUT1 of the oscillator module 204 is connected to the second input terminal of the non-overlapping clock module 205; the second output terminal OUT2 of the oscillator module 204 is connected to the third input terminal of the non-overlapping clock module 205; the third output terminal OUT3 of the oscillator module 204 is connected to the fourth input terminal of the non-overlapping clock module 205.

[0070] The first output terminal CTRL2 of the non-overlapping clock module 205 is connected to the second input terminal of the negative charge pump power tube module 206 ; the second output terminal CTRL3 of the non-overlapping clock module 205 is connected to the third input terminal of the negative charge pump power tube module 206 .

[0071] The output terminal NMID of the negative charge pump power tube module 206 is connected to the first end of the first capacitor C1; the second end of the first capacitor C1 is respectively connected to the cathode of the third diode D3 and the anode of the fourth diode D4; the cathode of the fourth diode D4 is grounded.

[0072] The ring oscillator module 204, the non-overlapping clock module 205, the negative voltage charge pump power tube module 206 and the comparator module 203, combined with the external diodes D3, D4 and the capacitors C1, C2, realize the negative voltage power generation function, converting the 5~12V power supply voltage into a negative voltage of -0.6~-3.3V, which is used to provide negative power for external devices.

[0073] For example, see Figure 7 The second enabling control module 201 includes a third hysteresis protection module SCHMIDT3, a third reset resistor RSET3, a third low voltage PMOS transistor MP3, a fourth low voltage PMOS transistor MP4, a fifth low voltage PMOS transistor MP5, a third low voltage NMOS transistor MN3, a fourth low voltage NMOS transistor MN4 and a fifth low voltage NMOS transistor MN5.

[0074] The first end of the third hysteresis protection module SCHMIDT3 is respectively connected to the input end of the second enable control module 201 and the second end of the third reset resistor RSET3; the second end of the third hysteresis protection module SCHMIDT3 is respectively connected to the gate of the third low-voltage PMOS tube MP3 and the gate of the third low-voltage NMOS tube MN3.

[0075] The first end of the third reset resistor RSET3, the source of the third low-voltage PMOS tube MP3, the source of the fourth low-voltage PMOS tube MP4 and the source of the fifth low-voltage PMOS tube MP5 are all connected to the second working power supply VDD2; the drain of the third low-voltage PMOS tube MP3 is respectively connected to the drain of the third low-voltage NMOS tube MN3, the gate of the fourth low-voltage PMOS tube MP4 and the gate of the fourth low-voltage NMOS tube MN4; the source of the third low-voltage NMOS tube MN3, the source of the fourth low-voltage NMOS tube MN4 and the source of the fifth low-voltage NMOS tube MN5 are all grounded; the drain of the fourth low-voltage PMOS tube MP4, the drain of the fourth low-voltage NMOS tube MN4, the gate of the fifth low-voltage PMOS tube MP5 and the gate of the fifth low-voltage NMOS tube MN5 are all connected to the second output terminal ENA_N of the second enable control module 201; the drain of the fifth low-voltage PMOS tube MP5 and the drain of the fifth low-voltage NMOS tube MN5 are both connected to the first output terminal ENA_P of the second enable control module 201.

[0076] For example, see Figure 8The reference module 202 includes a reference amplification module 2021 and a reference reduction module 2022; the reference amplification module 2021 includes a second operational amplifier OP2, a sixth low-voltage PMOS tube MP6, a ninth resistor R9 and a tenth resistor R10; the reference reduction module 2022 includes a third operational amplifier OP3, a seventh low-voltage PMOS tube MP7, an eleventh resistor R11 and a twelfth resistor R12.

[0077] The negative input terminal of the second operational amplifier OP2 is connected to the input terminal of the reference module 202, that is, the reference output terminal VREF of the bandgap reference voltage source module 103 is used as input; the positive input terminal of the second operational amplifier OP2 is respectively connected to the second terminal of the ninth resistor R9 and the first terminal of the tenth resistor R10; the positive electrode of the working power supply of the second operational amplifier OP2 and the source electrode of the sixth low-voltage PMOS tube MP6 are both connected to the second working power supply VDD2; the negative electrode of the second operational amplifier OP2 and the second terminal of the tenth resistor R10 are both grounded; the output terminal of the second operational amplifier OP2 is connected to the gate electrode of the sixth low-voltage PMOS tube MP6; the drain electrode of the sixth low-voltage PMOS tube MP6 and the first terminal of the ninth resistor R9 are both connected to the first output terminal VREF1 of the reference module 202.

[0078] The negative input terminal of the third operational amplifier OP3 is connected to the input terminal of the reference module 202, that is, the reference output terminal VREF of the bandgap reference voltage source module 103 is used as input; the positive input terminal of the third operational amplifier OP3 is respectively connected to the first terminal of the eleventh resistor R11 and the drain of the seventh low-voltage PMOS tube MP7; the positive electrode of the working power supply of the third operational amplifier OP3 and the source of the seventh low-voltage PMOS tube MP7 are both connected to the second working power supply VDD2; the negative electrode of the third operational amplifier OP3 and the second terminal of the twelfth resistor R12 are both grounded; the output terminal of the third operational amplifier OP3 is connected to the gate of the seventh low-voltage PMOS tube MP7; the second terminal of the eleventh resistor R11 and the first terminal of the twelfth resistor R12 are both connected to the second output terminal VREF2 of the reference module 202.

[0079] For example, see Fig. 9The comparator module 203 includes an eighth low-voltage PMOS tube MP8, a ninth low-voltage PMOS tube MP9, a tenth low-voltage PMOS tube MP10, an eleventh low-voltage PMOS tube MP11, a twelfth low-voltage PMOS tube MP12, a thirteenth low-voltage PMOS tube MP13, a twenty-fifth low-voltage NMOS tube MN25, a sixth low-voltage NMOS tube MN6, a seventh low-voltage NMOS tube MN7, an eighth low-voltage NMOS tube MN8, a ninth low-voltage NMOS tube MN9, a tenth low-voltage NMOS tube MN10, an eleventh low-voltage NMOS tube MN11, a twelfth low-voltage NMOS tube MN12, a thirteenth low-voltage NMOS tube MN13, a first inverter INV1, a second inverter INV2 and a first current source.

[0080] The source of the eighth low voltage PMOS tube MP8, the source of the ninth low voltage PMOS tube MP9, the source of the tenth low voltage PMOS tube MP10, the source of the eleventh low voltage PMOS tube MP11, the drain of the eleventh low voltage NMOS tube MN11, the positive electrode of the working power supply of the first inverter INV1 and the positive electrode of the working power supply of the second inverter INV2 are all connected to the second working power supply VDD2.

[0081] The drain of the eighth low-voltage PMOS transistor MP8 is respectively connected to the gate of the eighth low-voltage PMOS transistor MP8, the gate of the ninth low-voltage PMOS transistor MP9, the gate of the tenth low-voltage PMOS transistor MP10, the gate of the eleventh low-voltage PMOS transistor MP11, and the drain of the twenty-fifth low-voltage NMOS transistor MN25. The gate of the twenty-fifth low-voltage NMOS transistor MN25 is connected to the first input terminal of the comparator module 203, that is, the first output terminal ENA_P of the second enable control module 201 is used as an input. The source of the twenty-fifth low-voltage NMOS tube MN25 is connected to the negative electrode of the first current source; the positive electrode of the first current source, the source of the sixth low-voltage NMOS tube MN6, the source of the seventh low-voltage NMOS tube MN7, the source of the eighth low-voltage NMOS tube MN8, the source of the ninth low-voltage NMOS tube MN9, the source of the tenth low-voltage NMOS tube MN10, the source of the twelfth low-voltage NMOS tube MN12, the source of the thirteenth low-voltage NMOS tube MN13, the negative electrode of the working power supply of the first inverter INV1 and the negative electrode of the working power supply of the second inverter INV2 are all grounded.

[0082] The gate of the twelfth low-voltage PMOS transistor MP12 is connected to the third input terminal of the comparator module 203, that is, the second output terminal VREF2 of the reference module 202 is used as input; the source of the twelfth low-voltage PMOS transistor MP12 is respectively connected to the drain of the ninth low-voltage PMOS transistor MP9 and the source of the thirteenth low-voltage PMOS transistor MP13; the drain of the twelfth low-voltage PMOS transistor MP12 is respectively connected to the drain of the sixth low-voltage NMOS transistor MN6 and the gate of the eighth low-voltage NMOS transistor MN8. The gate of the sixth low-voltage NMOS transistor MN6 is respectively connected to the gate of the seventh low-voltage NMOS transistor MN7, the drain of the seventh low-voltage NMOS transistor MN7 and the drain of the thirteenth low-voltage PMOS transistor MP13; the gate of the thirteenth low-voltage PMOS transistor MP13 is connected to the second output terminal of the comparator module 203. The drain of the eighth low-voltage NMOS transistor MN8 is respectively connected to the drain of the ninth low-voltage NMOS transistor MN9 , the drain of the tenth low-voltage PMOS transistor MP10 , and the gate of the eleventh low-voltage NMOS transistor MN11 .

[0083] The gate of the ninth low-voltage NMOS transistor MN9 is connected to the first input terminal of the comparator module 203, that is, the output of the second output terminal ENA_N of the second enable control module 201 is used as input. The drain of the eleventh low-voltage PMOS transistor MP11 is respectively connected to the drain of the tenth low-voltage NMOS transistor MN10, the gate of the tenth low-voltage NMOS transistor MN10 and the gate of the twelfth low-voltage NMOS transistor MN12; the drain of the twelfth low-voltage NMOS transistor MN12 is respectively connected to the source of the eleventh low-voltage PMOS transistor MP11, the drain of the thirteenth low-voltage NMOS transistor MN13 and the input terminal of the first inverter INV1; the output terminal of the first inverter INV1 is connected to the input terminal of the second inverter INV2; the output terminal of the second inverter INV2 is connected to the first output terminal CTRL1 of the comparator module 203.

[0084] The comparator module 203 detects and samples the negative voltage output value and compares it with the reference voltage to control the opening and closing of the negative voltage charge pump power tube module. When the voltage reaches a predetermined value, the charging and discharging of the external capacitor C1 is stopped. When the discharge amount exceeds a certain level, the comparator reopens the switch tube to charge and discharge the capacitor C1.

[0085] For example, see Fig.10 The oscillator module 204 includes a second current source, oscillators ① to ⑦, a fourteenth low voltage PMOS transistor MP14, a fourteenth low voltage NMOS transistor MN14, a fifteenth low voltage NMOS transistor MN15, a sixteenth low voltage NMOS transistor MN16 and a seventeenth low voltage NMOS transistor MN17.

[0086] Each of the oscillator paths ① to ⑦ has the same structure. Taking oscillator path ① as an example, oscillator path ① includes the fifteenth low-voltage PMOS transistor MP15, the sixteenth low-voltage PMOS transistor MP16, the eighteenth low-voltage NMOS transistor MN18, the nineteenth low-voltage NMOS transistor MN19 and the fifth capacitor C5. The connection relationship of oscillators ① to ⑦ is the same. The output end of oscillator path ① is connected to the input end of oscillator path ②, which are connected in series in sequence. The output end of oscillator path ⑦ is connected to the input end of oscillator path ①. Among them, oscillators ⑤, oscillators ⑥ and oscillators ⑦ output signals OUT3, OUT2 and OUT1 respectively.

[0087] The gate of the fourteenth low-voltage NMOS tube MN14 is connected to the first input terminal of the oscillator module 204, that is, the output of the first output terminal ENA_P of the second enable control module 201 is used as input; the drain of the fourteenth low-voltage NMOS tube MN14 is connected to the positive electrode of the second current source; the source of the fourteenth low-voltage NMOS tube MN14 is respectively connected to the drain of the fifteenth low-voltage NMOS tube MN15, the drain of the sixteenth low-voltage NMOS tube MN16, the gate of the sixteenth low-voltage NMOS tube MN16, the gate of the seventeenth low-voltage NMOS tube MN17 and the gate of the nineteenth low-voltage NMOS tube MN19 of each group of oscillators ① to ⑦.

[0088] The gate of the fifteenth low-voltage NMOS transistor MN15 is connected to the second input terminal of the oscillator module 204, that is, the output of the second output terminal ENA_N of the second enable control module 201 is used as input. The source of the fifteenth low-voltage NMOS transistor MN15, the source of the sixteenth low-voltage NMOS transistor MN16, the source of the seventeenth low-voltage NMOS transistor MN17, and the source of the nineteenth low-voltage NMOS transistor MN19 of each group of oscillators ① to ⑦ are all grounded. The drain of the seventeenth low-voltage NMOS transistor MN17 is respectively connected to the drain of the fourteenth low-voltage PMOS transistor MP14, the gate of the fourteenth low-voltage PMOS transistor MP14, and the gate of the fifteenth low-voltage PMOS transistor MP15 of each group of oscillators ① to ⑦; the source of the fourteenth low-voltage PMOS transistor MP14 and the source of the fifteenth low-voltage PMOS transistor MP15 of each group of oscillators ① to ⑦ are all connected to the second working power supply VDD2.

[0089] The drain of the fifteenth low-voltage PMOS tube MP15 of each group of oscillators ① to ⑦ is connected to the source of the sixteenth low-voltage PMOS tube MP16 of each group of oscillators ① to ⑦; the gate of the sixteenth low-voltage PMOS tube MP16 of each group of oscillators ① to ⑦ is connected to the gate of the eighteenth low-voltage NMOS tube MN18 of each group of oscillators ① to ⑦; the source of the eighteenth low-voltage NMOS tube MN18 of each group of oscillators ① to ⑦ is connected to the drain of the nineteenth low-voltage NMOS tube MN19 of each group of oscillators ① to ⑦; the gate of the sixteenth low-voltage PMOS tube MP16 in the oscillator ① serves as the input end of the oscillator ①, and the gate of the tenth low-voltage PMOS tube MP16 in the oscillator ⑤ serves as the input end of the oscillator ①. The drain of the six low-voltage PMOS tube MP16 is used as the output end of the oscillator ⑤, and the output end of the oscillator ⑤ is connected to the third output end OUT3 of the oscillator module 204, and the output signal OUT3 is output; the drain of the sixteenth low-voltage PMOS tube MP16 in the oscillator ⑥ is used as the output end of the oscillator ⑥, and the output end of the oscillator ⑥ is connected to the second output end OUT2 of the oscillator module 204, and the output signal OUT2 is output; the drain of the sixteenth low-voltage PMOS tube MP16 in the oscillator ⑦ is used as the output end of the oscillator ⑦, and the output end of the oscillator ⑦ is connected to the first output end OUT1 of the oscillator module 204, and the output signal OUT1 is output. The oscillation signal is generated by the oscillator module 204, and can be shaped to form a TTL (Transistor-Transistor Logic, transistor-transistor logic integrated circuit) signal with a frequency of 300KHz, which is used to control the opening and closing of the final stage switch tube.

[0090] For example, see Fig.11 The non-overlapping clock module 205 includes a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, a seventh inverter INV7, an eighth inverter INV8, a ninth inverter INV9, a tenth inverter INV10, an eleventh inverter INV11, a twelfth inverter INV12, a thirteenth inverter INV13, a first NAND gate NAND1, a first NOR gate NOR1 and a second NOR gate NOR2.

[0091] The input end of the third inverter INV3 is connected to the fourth input end of the non-overlapping clock module 205; the output end of the third inverter INV3 is connected to the A port of the first NAND gate NAND1; the input end of the fourth inverter INV4 is connected to the second input end of the non-overlapping clock module 205; the output end of the fourth inverter INV4 is connected to the B port of the first NAND gate NAND1; the output port of the first NAND gate NAND1 is connected to the input end of the fifth inverter INV5; the output end of the fifth inverter INV5 is connected to the B port of the first NOR gate NOR1; the A port of the first NOR gate NOR1 is connected to the first input end of the non-overlapping clock module 205; the output port of the first NOR gate NOR1 is connected to the input end of the sixth inverter INV6; the output end of the sixth inverter INV6 is connected to the input end of the seventh inverter INV7; the output end of the seventh inverter INV7 is connected to the first output end CTRL2 of the non-overlapping clock module 205.

[0092] The input end of the eighth inverter INV8 is connected to the third input end of the non-overlapping clock module 205; the output end of the eighth inverter INV8 is connected to the input end of the ninth inverter INV9; the output end of the ninth inverter INV9 is connected to the input end of the tenth inverter INV10; the output end of the tenth inverter INV10 is connected to the input end of the eleventh inverter INV11; the output end of the eleventh inverter INV11 is connected to the B port of the second NOR gate NOR2; the A port of the second NOR gate NOR2 is connected to the first input end of the non-overlapping clock module 205; the output port of the second NOR gate NOR2 is connected to the input end of the twelfth inverter INV12; the output end of the twelfth inverter INV12 is connected to the input end of the thirteenth inverter INV13; the output end of the thirteenth inverter INV13 is connected to the second output end CTRL3 of the non-overlapping clock module 205.

[0093] For example, see Fig.12 The negative pressure charge pump power tube module 206 includes a seventeenth low voltage PMOS tube MP17, an eighteenth low voltage PMOS tube MP18, a nineteenth low voltage PMOS tube MP19, a twentieth low voltage PMOS tube MP20, a twentieth low voltage NMOS tube MN20, a twenty-first low voltage NMOS tube MN21, a twenty-second low voltage NMOS tube MN22, a twenty-third low voltage NMOS tube MN23, a twenty-fourth low voltage NMOS tube MN24, a thirteenth resistor R13 and a fourteenth resistor R14.

[0094] The source of the seventeenth low voltage PMOS tube MP17, the source of the eighteenth low voltage PMOS tube MP18, the source of the nineteenth low voltage PMOS tube MP19 and the source of the twentieth low voltage PMOS tube MP20 are all connected to the first power supply VB; the drain of the seventeenth low voltage PMOS tube MP17 is respectively connected to the gate of the seventeenth low voltage PMOS tube MP17, the gate of the eighteenth low voltage PMOS tube MP18 and the drain of the twentieth low voltage NMOS tube MN20.

[0095] The gate of the twentieth low-voltage NMOS tube MN20 is connected to the first input end of the negative-voltage charge pump power tube module 206; the source of the twentieth low-voltage NMOS tube MN20 is connected to the first end of the thirteenth resistor R13; the second end of the thirteenth resistor R13, the source of the twenty-first low-voltage NMOS tube MN21, the source of the twenty-second low-voltage NMOS tube MN22, the second end of the fourteenth resistor R14 and the source of the twenty-fourth low-voltage NMOS tube MN24 are all grounded.

[0096] The gate of the twenty-first low-voltage NMOS tube MN21 is connected to the second input end of the negative voltage charge pump power tube module 206; the drain of the twenty-first low-voltage NMOS tube MN21 is respectively connected to the drain of the twenty-second low-voltage NMOS tube MN22, the gate of the twenty-second low-voltage NMOS tube MN22, the drain of the eighteenth low-voltage PMOS tube MP18 and the gate of the twenty-fourth low-voltage NMOS tube MN24.

[0097] The gate of the twenty-third low-voltage NMOS tube MN23 is connected to the third input terminal of the negative-voltage charge pump power tube module 206; the drain of the twenty-third low-voltage NMOS tube MN23 is respectively connected to the drain of the nineteenth low-voltage PMOS tube MP19, the gate of the nineteenth low-voltage PMOS tube MP19 and the gate of the twentieth low-voltage PMOS tube MP20; the source of the twenty-third low-voltage NMOS tube MN23 is connected to the first end of the fourteenth resistor R14; the drain of the twentieth low-voltage PMOS tube MP20 and the drain of the twenty-fourth low-voltage NMOS tube MN24 are both connected to the output terminal NMID of the negative-voltage charge pump power tube module 206. Among them, the twentieth low-voltage PMOS tube MP20 and the twenty-fourth low-voltage NMOS tube MN24 are used as the final-stage power tubes.

[0098] Exemplarily, the linear voltage regulator circuit provides a low-voltage power supply and a bandgap reference voltage for the comparator module. By detecting the negative voltage output value and comparing it with the reference voltage provided by the reference module, the negative voltage charge pump power tube module is controlled to be turned on and off, thereby controlling the negative voltage output voltage. The output voltage value is controlled by the external resistors R8 and R ADJControl, the output voltage range can reach -3.3V ~ -0.6V, and the circuit also integrates an enable control function, which is controlled by the second enable control module and is internally set to a low level. The function is that the wiring voltage regulator circuit output voltage VDD2 works at a high level and stops working when it is grounded at a low level.

[0099] In one embodiment, see Fig.13 The driving circuit 300 includes an undervoltage lockout module 301, a first hysteresis protection module SCHMIDT1, a second NAND gate NAND2 and a buffer module BUFFER, a first reset resistor RSET1, a fourteenth inverter INV14 and a fifteenth inverter INV15.

[0100] Exemplarily, the undervoltage lockout module 301 is set to start when the power supply voltage reaches 5V, which can filter out false trigger signals at low voltage, and is set to stop working when it is lower than 4.5V, eliminating jitter on the power supply through a hysteresis voltage of about 0.5V.

[0101] The input end of the first hysteresis protection module SCHMIDT1 is respectively connected to the first end of the driving circuit 300 and the first end of the first reset resistor RSET1; the second end of the first reset resistor RSET1 is grounded; the output end of the first hysteresis protection module SCHMIDT1 is connected to the first end of the fourteenth inverter INV14; the second end of the fourteenth inverter INV14 is connected to the second input port B of the second NAND gate NAND2.

[0102] The undervoltage lockout module 301 is connected to the first end of the fifteenth inverter INV15; the second end of the fifteenth inverter INV15 is connected to the first input port A of the second NAND gate NAND2; and the output port of the second NAND gate NAND2 is connected to the input end of the buffer module BUFFER.

[0103] The first hysteresis protection module SCHMIDT1 is used to eliminate the jitter of the input signal, and the hysteresis voltage is also set to about 0.5V. The second NAND gate NAND2 is used to process the undervoltage lockout and the signal output by the first hysteresis protection module SCHMIDT1, so that it can output a control signal to the BUFFER module.

[0104] The output end of the buffer module BUFFER is connected to the output port POUTA of the driving circuit 300 .

[0105] Exemplarily, the buffer module BUFFER is formed by a plurality of inverters connected in series. For example, the buffer module BUFFER may include a sixteenth inverter INV16, a seventeenth inverter INV17, an eighteenth inverter INV18, and a nineteenth inverter INV19.

[0106] Exemplarily, the cache module BUFFER is a NOT gate-push-NOT gate structure with gradually increasing size, which is used to quickly drive the external PMOSFET. Its enable function can be controlled by TTL, and the internal position is set to GND. The TTL is inverted with the drive circuit output, so that the drive circuit 300 generates an inverted TTL signal with driving capability to drive the external PMOSFET.

[0107] In one embodiment, see Fig.14 The operational amplifier circuit 400 includes an IBIAS module 401 and an operational amplifier core module 402 .

[0108] The first end of the IBIAS module 401 is respectively connected to the first end of the operational amplifier core module 402 and the fourth end of the operational amplifier circuit 400, that is, connected to the first power supply VB; the second end of the IBIAS module 401 is respectively connected to the second end of the operational amplifier core module; the third end of the IBIAS module 401 is respectively connected to the third end of the operational amplifier core module and is grounded.

[0109] The fourth end of the operational amplifier core module 402 and the fifth end of the operational amplifier core module 402 are both connected to the first end of the operational amplifier circuit 400; the sixth end of the operational amplifier core module 402 is connected to the second end of the operational amplifier circuit 400; the seventh end of the operational amplifier core module 402 is connected to the third end of the operational amplifier circuit 400; and the eighth end of the operational amplifier core module 402 is connected to the fifth end of the operational amplifier circuit 400.

[0110] The IBIAS module 401 includes a fifth PMOS transistor MPH5, a sixth PMOS transistor MPH6, a seventh PMOS transistor MPH7, an eighth PMOS transistor MPH8, a ninth PMOS transistor MPH9, an eighth NMOS transistor MNH8, a ninth NMOS transistor MNH9, a third NPN-type transistor NPN3, a fourth NPN-type transistor NPN4, a fifth NPN-type transistor NPN5, a fifteenth resistor R15, a sixteenth resistor R16 and a seventeenth resistor R17.

[0111] The operational amplifier core module 402 includes a tenth PMOS tube MPH10, an eleventh PMOS tube MPH11, a twelfth PMOS tube MPH12, a thirteenth PMOS tube MPH13, a fourteenth PMOS tube MPH14, a fifteenth PMOS tube MPH15, a sixteenth PMOS tube MPH16, a tenth NMOS tube MNH10, an eleventh NMOS tube MNH11, a twelfth NMOS tube MNH12, a thirteenth NMOS tube MNH13, a first PNP-type transistor PNP1, a second PNP-type transistor PNP2, an eighteenth resistor R18, a nineteenth resistor R19, a twentieth resistor R20, a twenty-first resistor R21, a twenty-second resistor R22, a twenty-third resistor R23, a twenty-fourth resistor R24, a twenty-fifth resistor R25 and a sixth capacitor C6.

[0112] The sources of the fifth PMOS tube MPH5, the sixth PMOS tube MPH6, the seventh PMOS tube MPH7, the eighth PMOS tube MPH8 and the ninth PMOS tube MPH9 are all connected to the first end of the IBIAS module 401; the sources of the tenth PMOS tube MPH10, the eleventh PMOS tube MPH11, the twelfth PMOS tube MPH12, the thirteenth PMOS tube MPH13, the fourteenth PMOS tube MPH14, the fifteenth PMOS tube MPH15 and the sixteenth PMOS tube MPH16 are all connected to the first end of the operational amplifier core module 402; the first end of the IBIAS module 401 and the first end of the operational amplifier core module 402 are both connected to the fourth end of the operational amplifier circuit 400, that is, both are connected to the first power supply VB.

[0113] The drain of the fifth PMOS tube MPH5 is respectively connected to the first end of the fifteenth resistor R15, the gate of the fifth PMOS tube MPH5, the gate of the sixth PMOS tube MPH6 and the gate of the seventh PMOS tube MPH7; the drain of the sixth PMOS tube MPH6 is respectively connected to the base of the third NPN type transistor NPN3, the collector of the third NPN type transistor NPN3 and the base of the fourth NPN type transistor NPN4; the drain of the seventh PMOS tube MPH7 is respectively connected to the drain of the eighth NMOS tube MNH8, the gate of the eighth NMOS tube MNH8 and the gate of the ninth NMOS tube MPN9; the source of the eighth NMOS tube MNH8 is respectively connected to the collector of the fourth NPN type transistor NPN4 and the base of the fifth NPN type transistor NPN5; The drain of the eighth PMOS tube MPH8 is respectively connected to the drain of the ninth NMOS tube MPN9, the gate of the eighth PMOS tube MPH8 and the gate of the ninth PMOS tube MPH9 to the second end of the IBIAS module; the source of the ninth NMOS tube MPN9 is connected to the collector of the fifth NPN type transistor NPN5; the emitter of the fourth NPN type transistor NPN4 is connected to the first end of the sixteenth resistor R16; the emitter of the third NPN type transistor NPN3 is respectively connected to the emitter of the fifth NPN type transistor NPN5, the first end of the seventeenth resistor R17 and the drain of the ninth PMOS tube MPH9; the second end of the fifteenth resistor R15, the second end of the sixteenth resistor R16 and the second end of the seventeenth resistor R17 are all connected to the third end of the IBIAS module, that is, grounded.

[0114] The gate of the tenth PMOS tube MPH10, the drain of the eleventh PMOS tube MPH11 and the gate of the twelfth PMOS tube MPH12 are all connected to the second end of the operational amplifier core module 402; the drain of the tenth PMOS tube MPH10 is respectively connected to the drain of the tenth NMOS tube MNH10, the gate of the tenth NMOS tube MNH10, the gate of the eleventh NMOS tube MNH11 and the gate of the twelfth NMOS tube MNH12; the source of the tenth NMOS tube MNH10 is connected to the first end of the eighteenth resistor R18. The gate of the eleventh PMOS tube MPH11 is connected to the fourth end of the operational amplifier core module 402, that is, connected to the second enable control port, where the output of the first output end ENA_P of the second enable control module 201 is used as input.

[0115] The drain of the twelfth PMOS transistor MPH12 is respectively connected to the emitter of the first PNP type transistor PNP1 and the emitter of the second PNP type transistor PNP2; the base of the first PNP type transistor PNP1 is connected to the sixth end of the operational amplifier core module 402, that is, the input signal of the second input signal interface PINB is used as input; the collector of the first PNP type transistor PNP1 is respectively connected to the second end of the twenty-first resistor R21 and the first end of the twenty-second resistor R22; the collector of the second PNP type transistor PNP2 is respectively connected to the second end of the nineteenth resistor R19 and the first end of the twentieth resistor R20; the base of the second PNP type transistor PNP2 is respectively connected to the second end of the twenty-third resistor R23 and the first end of the twenty-fourth resistor R24.

[0116] The drain of the thirteenth PMOS tube MPH13 is respectively connected to the drain of the eleventh NMOS tube MNH11, the gate of the thirteenth PMOS tube MPH13 and the gate of the fourteenth PMOS tube MPH14; the source of the eleventh NMOS tube MNH11 is connected to the first end of the nineteenth resistor R19; the drain of the fourteenth PMOS tube MPH14 is respectively connected to the drain of the twelfth NMOS tube MNH12, the first end of the twenty-fifth resistor R25, the drain of the fifteenth PMOS tube MPH15 and the gate of the sixteenth PMOS tube MPH16; the source of the twelfth NMOS tube MNH12 is connected to the first end of the twenty-first resistor R21; the gate of the fifteenth PMOS tube MPH15 is connected to the fifth end of the operational amplifier core module 402, that is, connected to the second enable control port, where the output of the first output end ENA_P of the second enable control module is used as input.

[0117] The gate of the thirteenth NMOS tube MNH13 is connected to the seventh terminal of the operational amplifier core module 402, that is, connected to the second enable control port, where the output of the second output terminal ENA_N of the second enable control module is used as input. The drain of the thirteenth NMOS tube MNH13 is respectively connected to the second end of the sixth capacitor C6, the drain of the sixteenth PMOS tube MPH16, the first end of the twenty-third resistor R23 and the eighth terminal of the operational amplifier core module 402. The first end of the sixth capacitor C6 is connected to the second end of the twenty-fifth resistor R25; the second end of the eighteenth resistor R18, the second end of the twentieth resistor R20, the second end of the twenty-second resistor R22, the source of the thirteenth NMOS tube MNH13 and the second end of the twenty-fourth resistor R24 ​​are all grounded.

[0118] Among them, MPH4~MPH16 are high-voltage PMOS devices, MNH8~MNH13 are high-voltage NMOS devices; MP3~MP21 are low-voltage PMOS devices, MN3~MN23 are low-voltage NMOS devices; high-voltage PMOS devices or high-voltage NMOS devices are generally connected to the first power supply VB, and low-voltage PMOS devices or low-voltage NMOS devices are generally connected to VDD1, VDD2 or ground.

[0119] The operational amplifier circuit 400 provides a frequency modulation signal for the VCO, and triples the 0-2V triangle wave input signal. The IBIAS module 401 can provide a stable current source that does not change with the power supply. The operational amplifier core module 402 is an operational amplifier with a triple closed-loop gain, which is used to amplify the input signal and provide a stable frequency modulation voltage for the VCO. It is controlled by the second enable control module 201 and is internally set to a low level. The function is that the wiring voltage regulator circuit output voltage VDD2 works at a high level and stops working when it is grounded at a low level.

[0120] The circuit design was realized based on 0.25um BCD process, and the circuit built with the above architecture was tested and verified after tape-out. The test results show that the multifunctional power management chip proposed by the present invention can provide a 3.3V positive power supply, a -0.6 to -3.3V negative power supply, a MOSFET driver, and a triangle wave modulation signal that can be used for VCO frequency modulation, and is particularly suitable for systems that require single-chip microcomputer control, low power consumption, and high integration.

[0121] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0122] It can be seen that the present invention adopts a low-dropout linear regulator structure through the linear voltage regulator circuit 100, and forms a negative feedback loop through the error amplifier and the feedback resistor to convert the built-in reference voltage into the required output voltage; the negative voltage power supply generation circuit 200 adopts a negative voltage charge pump structure and integrates a negative voltage feedback function to achieve output voltage regulation for driving the power amplifier gate; the drive circuit 300 adopts a half-bridge drive structure to generate a half-bridge driver with a phase opposite to TTL and a certain driving capability for driving PMOSFET; the operational amplifier circuit 400 adopts an operational amplifier with a high input range with a three-fold gain, which is used to amplify the input signal and modulate the frequency of the VCO, and the four modules are integrated with an enable control function. The circuit has the characteristics of controllable timing, high integration and low static power consumption, and performs complete power supply modulation around the application of the power amplifier, realizing power supply, gate voltage control and drain voltage modulation on a single chip, and providing a complete set of solutions for power amplifiers, VCOs and other related low-voltage devices. The product is small in size and can be packaged in a QFN24 plastic package. Through the circuit design in the above embodiment, the chip size can reach 4mm×4mm, which can save a lot of area. It has the advantages of low power consumption and high integration, which is conducive to miniaturized and low-power applications.

[0123] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0124] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A multifunctional power management chip, characterized in that: It includes a linear voltage stabilizing circuit, a negative voltage power supply generating circuit, a driving circuit and an operational amplifier circuit; The first end of the linear voltage regulator circuit is connected to the first enable control port; the second end of the linear voltage regulator circuit is respectively connected to the first end of the negative voltage power supply generating circuit and the second working power supply; the third end of the linear voltage regulator circuit is respectively connected to the third end of the negative voltage power supply generating circuit, the second end of the driving circuit, the fourth end of the operational amplifier circuit and the first power supply; the linear voltage regulator circuit is used to convert the built-in reference voltage into the output voltage required by the chip; The second end of the negative voltage power supply generating circuit is respectively connected to the second enable control port and the first end of the operational amplifier circuit; the fourth end of the negative voltage power supply generating circuit is the first output port of the negative voltage power supply generating circuit; the fifth end of the negative voltage power supply generating circuit is the second output port of the negative voltage power supply generating circuit; the sixth end of the negative voltage power supply generating circuit is the third output port of the negative voltage power supply generating circuit; the negative voltage power supply generating circuit is used to adjust the output voltage of the chip; The second end of the operational amplifier circuit is connected to the second input signal interface; the third end of the operational amplifier circuit is connected to the second enable control port; the fifth end of the operational amplifier circuit is the output port of the operational amplifier circuit; the operational amplifier circuit is used to amplify the chip input signal; The first end of the driving circuit is connected to the first input signal interface; the third end of the driving circuit is connected to the output port of the driving circuit; the driving circuit is used to drive the PMOSFET; The negative voltage power supply generating circuit includes a second enabling control module, an oscillator module, a reference module, a comparator module, a non-overlapping clock module, a negative voltage charge pump power tube module, an eighth resistor, an adjustable resistor, a first capacitor, a second capacitor, a third diode and a fourth diode; The input end of the second enable control module is connected to the second end of the negative voltage power supply generating circuit; the first output end of the second enable control module is respectively connected to the first input end of the comparator module and the first input end of the oscillator module; the second output end of the second enable control module is respectively connected to the second input end of the comparator module, the second input end of the oscillator module and the first input end of the non-overlapping clock module; The third input end of the comparator module is connected to the second output end of the reference module; the first output end of the comparator module is connected to the first input end of the negative voltage charge pump power tube module; the second output end of the comparator module is respectively connected to the second end of the eighth resistor and the first end of the adjustable resistor; the second end of the adjustable resistor is respectively connected to the second end of the second capacitor, the positive electrode of the third diode and the second output port of the negative voltage power supply generating circuit; the first end of the second capacitor is grounded; The first output terminal of the reference module is connected to the first terminal of the eighth resistor; The first output terminal of the oscillator module is connected to the second input terminal of the non-overlapping clock module; the second output terminal of the oscillator module is connected to the third input terminal of the non-overlapping clock module; the third output terminal of the oscillator module is connected to the fourth input terminal of the non-overlapping clock module; The first output end of the non-overlapping clock module is connected to the second input end of the negative pressure charge pump power tube module; the second output end of the non-overlapping clock module is connected to the third input end of the negative pressure charge pump power tube module; The output end of the negative voltage charge pump power tube module is connected to the first end of the first capacitor; the second end of the first capacitor is respectively connected to the cathode of the third diode and the anode of the fourth diode; the cathode of the fourth diode is grounded.

2. The multifunctional power management chip as claimed in claim 1, characterized in that: The linear voltage stabilization circuit comprises a first enabling control module, a pre-voltage stabilization module, a bandgap reference voltage source module and a feedback module; The input end of the first enabling control module is connected to the first end of the linear voltage stabilizing circuit; the first output end of the first enabling control module is connected to the first input end of the pre-voltage stabilizing module; the first output end of the first enabling control module is in phase with the input end of the first enabling control module; The second output terminal of the first enabling control module is connected to the second input terminal of the pre-voltage stabilization module; The first output end of the pre-voltage regulator module is connected to the power supply input end of the bandgap reference voltage source module; the reference output end of the bandgap reference voltage source module is connected to the first input end of the feedback module; the first output end of the feedback module outputs the voltage input as the second working power supply.

3. The multifunctional power management chip as claimed in claim 2, characterized in that: The reference voltage at the input end of the reference module is the same as the voltage at the reference output end of the bandgap reference voltage source module.

4. The multifunctional power management chip as claimed in claim 1, characterized in that: The driving circuit includes an undervoltage lockout module, a first hysteresis protection module, a second NAND gate and a cache module, a first reset resistor, a fourteenth inverter and a fifteenth inverter; The input end of the first hysteresis protection module is connected to the first end of the driving circuit and the first end of the first reset resistor respectively; the second end of the first reset resistor is grounded; the output end of the first hysteresis protection module is connected to the first end of the fourteenth inverter; the second end of the fourteenth inverter is connected to the second input port of the second NAND gate; The undervoltage lockout module is connected to the first end of the fifteenth inverter; the second end of the fifteenth inverter is connected to the first input port of the second NAND gate; the output port of the second NAND gate is connected to the input end of the cache module; The output end of the cache module is connected to the output port of the driving circuit.

5. The multifunctional power management chip as claimed in claim 1, characterized in that: The operational amplifier circuit includes an IBIAS module and an operational amplifier core module; The first end of the IBIAS module is connected to the first end of the operational amplifier core module and the fourth end of the operational amplifier circuit respectively; the second end of the IBIAS module is connected to the second end of the operational amplifier core module respectively; the third end of the IBIAS module is grounded to the third end of the operational amplifier core module respectively; The fourth end of the operational amplifier core module and the fifth end of the operational amplifier core module are both connected to the first end of the operational amplifier circuit; the sixth end of the operational amplifier core module is connected to the second end of the operational amplifier circuit; the seventh end of the operational amplifier core module is connected to the third end of the operational amplifier circuit; and the eighth end of the operational amplifier core module is connected to the fifth end of the operational amplifier circuit.

6. The multifunctional power management chip as claimed in claim 2, characterized in that: The first enabling control module includes a second hysteresis protection module, a second reset resistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor and a third NMOS transistor; The first end of the second hysteresis protection module is respectively connected to the input end of the first enable control module and the second end of the second reset resistor; the second end of the second hysteresis protection module is respectively connected to the gate of the first PMOS tube and the gate of the first NMOS tube; The first end of the second reset resistor, the source of the first PMOS tube, the source of the second PMOS tube and the source of the third PMOS tube are all connected to the first power supply; the drain of the first PMOS tube is respectively connected to the drain of the first NMOS tube, the gate of the second PMOS tube and the gate of the second NMOS tube; the source of the first NMOS tube, the source of the second NMOS tube and the source of the third NMOS tube are all grounded; the drain of the second PMOS tube, the drain of the second NMOS tube, the gate of the third PMOS tube and the gate of the third NMOS tube are all connected to the second output end of the first enable control module; the drain of the third PMOS tube and the drain of the third NMOS tube are both connected to the first output end of the first enable control module.

7. The multifunctional power management chip as claimed in claim 1, characterized in that: The reference module includes a reference enlargement module and a reference reduction module; The reference amplification module includes a second operational amplifier, a sixth low-voltage PMOS tube, a ninth resistor and a tenth resistor; the reference reduction module includes a third operational amplifier, a seventh low-voltage PMOS tube, an eleventh resistor and a twelfth resistor; The negative input terminal of the second operational amplifier is connected to the input terminal of the reference module; the positive input terminal of the second operational amplifier is respectively connected to the second terminal of the ninth resistor and the first terminal of the tenth resistor; the positive electrode of the working power supply of the second operational amplifier and the source electrode of the sixth low-voltage PMOS tube are both connected to the second working power supply; the negative electrode of the second operational amplifier is grounded; the output terminal of the second operational amplifier is connected to the gate electrode of the sixth low-voltage PMOS tube; the drain electrode of the sixth low-voltage PMOS tube and the first terminal of the ninth resistor are both connected to the first output terminal of the reference module; The negative input terminal of the third operational amplifier is connected to the input terminal of the reference module; the positive input terminal of the third operational amplifier is respectively connected to the first terminal of the eleventh resistor and the drain terminal of the seventh low-voltage PMOS tube; the positive terminal of the working power supply of the third operational amplifier and the source terminal of the seventh low-voltage PMOS tube are both connected to the second working power supply; the negative terminal of the third operational amplifier and the second terminal of the twelfth resistor are both grounded; the output terminal of the third operational amplifier is connected to the gate terminal of the seventh low-voltage PMOS tube; the second terminal of the eleventh resistor and the first terminal of the twelfth resistor are both connected to the second output terminal of the reference module.

8. The multifunctional power management chip as claimed in claim 1, characterized in that: The non-overlapping clock module includes a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a ninth inverter, a tenth inverter, an eleventh inverter, a twelfth inverter, a thirteenth inverter, a first NAND gate, a first NOR gate, and a second NOR gate; The input end of the third inverter is connected to the fourth input end of the non-overlapping clock module; the output end of the third inverter is connected to the A port of the first NAND gate; the input end of the fourth inverter is connected to the second input end of the non-overlapping clock module; the output end of the fourth inverter is connected to the B port of the first NAND gate; the output port of the first NAND gate is connected to the input end of the fifth inverter; the output end of the fifth inverter is connected to the B port of the first NOR gate; the A port of the first NOR gate is connected to the first input end of the non-overlapping clock module; the output port of the first NOR gate is connected to the input end of the sixth inverter; the output end of the sixth inverter is connected to the input end of the seventh inverter; the output end of the seventh inverter is connected to the first output end of the non-overlapping clock module; The input end of the eighth inverter is connected to the third input end of the non-overlapping clock module; the output end of the eighth inverter is connected to the input end of the ninth inverter; the output end of the ninth inverter is connected to the input end of the tenth inverter; the output end of the tenth inverter is connected to the input end of the eleventh inverter; the output end of the eleventh inverter is connected to the B port of the second NOR gate; the A port of the second NOR gate is connected to the first input end of the non-overlapping clock module; the output port of the second NOR gate is connected to the input end of the twelfth inverter; the output end of the twelfth inverter is connected to the input end of the thirteenth inverter; the output end of the thirteenth inverter is connected to the second output end of the non-overlapping clock module.

9. The multifunctional power management chip as claimed in claim 1, characterized in that: The negative pressure charge pump power tube module includes a seventeenth low voltage PMOS tube, an eighteenth low voltage PMOS tube, a nineteenth low voltage PMOS tube, a twentieth low voltage PMOS tube, a twentieth low voltage NMOS tube, a twenty-first low voltage NMOS tube, a twenty-second low voltage NMOS tube, a twenty-third low voltage NMOS tube, a twenty-fourth low voltage NMOS tube MN24, a thirteenth resistor and a fourteenth resistor; The source of the seventeenth low-voltage PMOS tube, the source of the eighteenth low-voltage PMOS tube, the source of the nineteenth low-voltage PMOS tube, and the source of the twentieth low-voltage PMOS tube are all connected to the first power supply; the drain of the seventeenth low-voltage PMOS tube is respectively connected to the gate of the seventeenth low-voltage PMOS tube, the gate of the eighteenth low-voltage PMOS tube, and the drain of the twentieth low-voltage NMOS tube; The gate of the 20th low-voltage NMOS tube is connected to the first input end of the negative voltage charge pump power tube module; the source of the 20th low-voltage NMOS tube is connected to the first end of the 13th resistor; the second end of the 13th resistor, the source of the 21st low-voltage NMOS tube, the source of the 22nd low-voltage NMOS tube, the second end of the 14th resistor and the source of the 24th low-voltage NMOS tube MN24 are all grounded; The gate of the twenty-first low-voltage NMOS tube is connected to the second input end of the negative voltage charge pump power tube module; the drain of the twenty-first low-voltage NMOS tube is respectively connected to the drain of the twenty-second low-voltage NMOS tube, the gate of the twenty-second low-voltage NMOS tube, the drain of the eighteenth low-voltage PMOS tube and the gate of the twenty-fourth low-voltage NMOS tube MN24; The gate of the twenty-third low-voltage NMOS tube is connected to the third input end of the negative voltage charge pump power tube module; the drain of the twenty-third low-voltage NMOS tube is respectively connected to the drain of the nineteenth low-voltage PMOS tube, the gate of the nineteenth low-voltage PMOS tube and the gate of the twentieth low-voltage PMOS tube; the source of the twenty-third low-voltage NMOS tube is connected to the first end of the fourteenth resistor; the drain of the 20th low-voltage PMOS tube and the drain of the 24th low-voltage NMOS tube MN24 are both connected to the output end of the negative voltage charge pump power tube module.

10. The multifunctional power management chip as claimed in claim 4, characterized in that: The cache module is formed by connecting a plurality of inverters in series.

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