A glass-based multi-chip heterogeneous integrated structure and preparation method thereof
By independently distributing lines on the glass plate and implanting chips, the RF chip integration problem and glass plate warping problems in traditional packaging technology are solved, and the RF signal loss and the glass plate strength are reduced.
Patent Information
- Application Number
- CN202411176760.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-26
- Publication Date
- 2025-01-10
- Estimated Expiration
- 2044-08-26
AI Technical Summary
In traditional semiconductor chip packaging technology, it is difficult to make a circuit layer in the sinker during the integration process of RF chips and other conventional chips, resulting in high RF signal loss and easy warping of the glass plate and insufficient strength.
The preparation method of glass-based multi-chip heterogeneous integrated structure is adopted. By independently distributing lines on the glass plate, RF chips and non-RF chips are implanted to reduce RF signal loss and reduce warping through a symmetrical thickness design.
The heterogeneous integration of RF chips and conventional chips is realized, reducing RF signal loss, increasing the strength of glass plates, reducing warping phenomenon, and simplifying the line production process.
Smart Images
Figure CN118692922B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor chip packaging, and in particular to a glass-based multi-chip heterogeneous integrated structure and a preparation method thereof. Background Art
[0002] RF chips and other conventional chips usually take into account the particularity of RF signals and their sensitivity to the environment when they are integrated and packaged. In traditional integrated circuit packaging technology, the process steps for packaging RF chips and other conventional chips together are as follows:
[0003] (1) First provide a substrate, and then make grooves and through holes on the surface of the substrate;
[0004] (2) Making circuit layers in the grooves and through holes and on the surface of the substrate;
[0005] (3) Attach the RF chip and other conventional chips to the circuit layer on the surface of the substrate and perform plastic sealing.
[0006] In this process, in order to reduce the RF loss of the RF chip, the RF chip is usually attached to the circuit layer in the sink. However, in this process, the main problem is that it is difficult to make the circuit layer in the sink. Summary of the invention
[0007] One of the purposes of the present invention is to provide a method for preparing a glass-based multi-chip heterogeneous integrated structure, which can realize the heterogeneous integration of RF chips and other non-RF chips, and the RF chips are close to the glass plate to reduce RF signal loss; the present invention does not require trenching for circuits, and the circuit production is simple.
[0008] The second object of the present invention is to provide a method for preparing a glass-based multi-chip heterogeneous integrated structure, which can realize the heterogeneous integration of radio frequency chips and other conventional chips, reduce the warping of the glass plate, and improve the strength of the glass plate.
[0009] A third object of the present invention is to provide a glass-based multi-chip heterogeneous integrated structure which has high strength and is not prone to warping.
[0010] To achieve this object, the present invention adopts the following technical solutions:
[0011] On the one hand, the present invention provides a method for preparing a glass-based multi-chip heterogeneous integrated structure, providing a glass plate, making a first redistribution layer on at least one side of the glass plate, dividing the first redistribution layer into a first area and a second area, and making a second redistribution layer on the first area, and then implanting chips in the pad area of the second area of the first redistribution layer and the pad area of the second redistribution layer, respectively, wherein the chip implanted in the pad area of the second area of the first redistribution layer is a radio frequency chip, and the chip implanted in the pad area of the second redistribution layer is a non-radio frequency chip.
[0012] As a further solution of the method for preparing a glass-based multi-chip heterogeneous integrated structure, the following steps are included:
[0013] S10, providing a glass plate, preparing a first redistribution layer on one side of the glass plate, and dividing the first redistribution layer into a first area and a second area;
[0014] S20, pressing a dielectric layer on the surface of the first redistribution layer;
[0015] S30, performing a hole-opening process on the dielectric layer to form a first window that exposes a portion of the first redistribution layer located in the first area and a second window that exposes both the first redistribution layer and a portion of the glass plate located in the second area;
[0016] S40, preparing a conductive pillar electrically connected to the first redistribution layer in the first window, and preparing a second redistribution layer connected to the conductive pillar on the surface of the dielectric layer;
[0017] S50, respectively pressing a second solder resist layer on the exposed surface of the first redistribution layer and pressing a first solder resist layer on the exposed surface of the second redistribution layer, and exposing pad regions of the first redistribution layer and the second redistribution layer;
[0018] S60. Provide a plurality of first chips and a plurality of second chips, implant the first chips into the pad area of the second redistribution layer and implant the second chips into the pad area of the second area of the first redistribution layer, the first chips are non-RF chips and the second chips are RF chips.
[0019] In another optional embodiment of the present invention, the present invention provides a method for preparing a glass-based multi-chip heterogeneous integrated structure, comprising the following steps:
[0020] S10, providing a glass plate, preparing a first redistribution layer on one side of the glass plate, preparing a second redistribution layer on the other side, and connecting the first redistribution layer and the second redistribution layer via a first conductive column penetrating the glass plate, so as to divide the first redistribution layer into a first area and a second area;
[0021] S20, pressing a first dielectric layer on the surface of the first redistribution layer and pressing a second dielectric layer on the surface of the second redistribution layer;
[0022] S30, performing a hole-opening process on the first dielectric layer to form a first window for exposing a portion of the first redistribution layer in the first area and a second window for exposing both the first redistribution layer and a portion of the glass plate in the second area;
[0023] S40, preparing a second conductive pillar electrically connected to the first redistribution layer in the first window, and preparing a third redistribution layer electrically connected to the second conductive pillar on the surface of the first dielectric layer;
[0024] S50, respectively pressing a second solder resist layer on the exposed surface of the first redistribution layer and pressing a first solder resist layer on the exposed surface of the third redistribution layer, and exposing pad areas of the first redistribution layer and the third redistribution layer;
[0025] S60. Provide a plurality of first chips and a plurality of second chips, implant the first chips into the pad area of the third redistribution layer and implant the second chips into the pad area of the second area of the first redistribution layer, the first chips are non-RF chips and the second chips are RF chips.
[0026] As a further solution of the method for preparing a glass-based multi-chip heterogeneous integrated structure, the sum of the thicknesses of the first redistribution layer, the first dielectric layer and the first solder resist layer is equal to the sum of the thicknesses of the second redistribution layer and the second dielectric layer.
[0027] As a further solution of the method for preparing a glass-based multi-chip heterogeneous integrated structure, step S10 specifically includes:
[0028] S10a, providing a glass plate, and performing laser modification on a region of the glass plate to be opened;
[0029] S10b, etching the glass plate to form a through hole penetrating the glass plate;
[0030] S10c, forming a seed layer on the surface of the through hole and the surface of the glass plate;
[0031] S10d, pressing a photosensitive film on the surface of the seed layer located on the surface of the glass plate;
[0032] S10e, exposing and developing the photosensitive film to form a window that exposes a portion of the seed layer;
[0033] S10f, forming a first conductive column in the through hole, forming a first redistribution layer in a window adjacent to one side of the glass plate, and forming a second redistribution layer in a window adjacent to the other side of the glass plate;
[0034] S10g, removing the remaining photosensitive film and etching away the exposed seed layer.
[0035] As a further solution of the method for preparing a glass-based multi-chip heterogeneous integrated structure, step S40 specifically includes:
[0036] S40a, forming a seed layer on the inner wall of the first window of the first dielectric layer and on the surface of the first dielectric layer;
[0037] S40b, pressing a photosensitive film on the surface of the seed layer located on the surface of the first dielectric layer;
[0038] S40c, exposing and developing the photosensitive film to form a third window exposing a portion of the seed layer;
[0039] S40d, forming a second conductive column in the first window and forming a third redistribution layer in the third window;
[0040] S40e, removing the remaining photosensitive film and etching away the exposed seed layer.
[0041] As a further solution of the method for preparing a glass-based multi-chip heterogeneous integrated structure, step S50 specifically includes:
[0042] S50a, respectively pressing a second solder resist layer on the exposed surface of the first redistribution layer and pressing a first solder resist layer on the exposed surface of the third redistribution layer;
[0043] S50b, exposing and developing the second solder resist layer to form a first hole position that exposes the pad area of the first redistribution layer, and exposing and developing the first solder resist layer to form a second hole position that exposes the pad area of the first redistribution layer.
[0044] In another aspect, the present invention provides a glass-based multi-chip heterogeneous integrated structure prepared by the method for preparing the glass-based multi-chip heterogeneous integrated structure, comprising:
[0045] A glass plate, at least one side of which has a first redistribution layer, wherein the first redistribution layer is divided into a first region and a second region;
[0046] A second redistribution layer is located in a first region of the first redistribution layer on one side of the glass plate and is connected to the first redistribution layer;
[0047] A plurality of chips are respectively implanted in the pad area of the second region of the first redistribution layer and the pad area of the second redistribution layer, and the chips implanted in the pad area of the second region of the first redistribution layer are radio frequency chips.
[0048] As a further solution for glass-based multi-chip heterogeneous integration structure, it also includes:
[0049] A dielectric layer is located between the first region of the first redistribution layer and the second redistribution layer, and the first redistribution layer and the second redistribution layer are connected via a conductive column embedded in the dielectric layer;
[0050] The first solder resist layer covers the second redistribution layer, and the pad area of the second redistribution layer is exposed from the first solder resist layer.
[0051] In another optional embodiment of the present invention, the present invention provides a glass-based multi-chip heterogeneous integrated structure prepared by the method for preparing the glass-based multi-chip heterogeneous integrated structure, comprising:
[0052] A glass plate, wherein a first redistribution layer is disposed on one side of the glass plate, and a second redistribution layer is disposed on the other side of the glass plate, and the first redistribution layer is connected to the second redistribution layer via a first conductive column embedded in the glass plate, and the first redistribution layer is divided into a first area and a second area;
[0053] A first dielectric layer covering a first region of the first redistribution layer;
[0054] a second dielectric layer, covering the second redistribution layer;
[0055] a third redistribution layer, located on the first dielectric layer and electrically connected to the first redistribution layer via a second conductive column embedded in the first dielectric layer;
[0056] A first solder resist layer covers the third redistribution layer, and a pad area of the third redistribution layer is exposed from the first solder resist layer;
[0057] A second solder resist layer covers a second area of the first redistribution layer, and a pad area of the first redistribution layer is exposed from the second solder resist layer;
[0058] A plurality of first chips that are non-RF chips and a plurality of second chips that are RF chips, wherein the first chips are flipped on the third redistribution layer, and the I / O ports of the first chips are connected to the pad areas of the third redistribution layer, and the second chips are flipped on the second area of the first redistribution layer, and the I / O ports of the second chips are connected to the pad areas of the first redistribution layer.
[0059] As a further solution of the glass-based multi-chip heterogeneous integrated structure, the sum of the thicknesses of the first redistribution layer, the first dielectric layer and the first solder resist layer is equal to the sum of the thicknesses of the second redistribution layer and the second dielectric layer.
[0060] Beneficial effects of the present invention: The present invention realizes glass-based multi-chip heterogeneous integration by independently multi-region differential wiring on a glass plate; the RF chip is installed on the first redistribution layer close to the glass plate, reducing RF signal loss; the thickness of both sides of the glass plate is symmetrical, reducing the warping phenomenon of the glass-based multi-chip heterogeneous integration structure and improving the strength of the glass-based multi-chip heterogeneous integration structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0061] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0062] Figure 1 It is a schematic diagram of the glass-based multi-chip heterogeneous integrated structure described in Example 1 of the present invention.
[0063] Figure 2 It is a schematic diagram of the glass-based multi-chip heterogeneous integrated structure described in Example 2 of the present invention.
[0064] Figure 1 middle:
[0065] 1. Glass plate; 2. First redistribution layer; 3. Dielectric layer; 4. Conductive column; 5. Second redistribution layer; 6. First solder resist layer; 7. Second solder resist layer; 8. First chip; 9. Second chip;
[0066] Figure 2 middle:
[0067] 10. Glass plate; 20. First conductive column; 30. First redistribution layer; 40. Second redistribution layer; 50. First dielectric layer; 60. Second dielectric layer; 70. Second conductive column; 80. Third redistribution layer; 90. First solder resist layer; 100. Second solder resist layer; 110. First chip; 120. Second chip. DETAILED DESCRIPTION
[0068] The technical solution of the present invention is further described below with reference to the accompanying drawings and through specific implementation methods.
[0069] Among them, the drawings are only used for illustrative explanations, and they only represent schematic diagrams rather than actual pictures, and should not be understood as limitations on this patent; in order to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of the actual product; for those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.
[0070] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "inner", "outer", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as a limitation on this patent. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.
[0071] In the description of the present invention, unless otherwise clearly specified and limited, if the term "connection" or the like appears to indicate the connection relationship between components, the term should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two components or the interaction relationship between two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0072] Embodiment 1
[0073] The present embodiment provides a method for preparing a glass-based multi-chip heterogeneous integrated structure: providing a glass plate, making a first redistribution layer on at least one side of the glass plate, dividing the first redistribution layer into a first area and a second area, and making a second redistribution layer on the first area, and then implanting chips in the pad area of the second area of the first redistribution layer and the pad area of the second redistribution layer, respectively, wherein the chip implanted in the pad area of the second area of the first redistribution layer is a RF chip, and the chip implanted in the pad area of the second redistribution layer is a non-RF chip.
[0074] In this embodiment, a second redistribution layer is fabricated on a partial area of the first redistribution layer, and a conventional chip (excluding the RF chip) is implanted into the pad area of the second redistribution layer, and an RF chip is implanted into a specific area of the first redistribution layer, thereby realizing differential heterogeneous integration of the RF chip and the conventional chip.
[0075] Furthermore, the method for preparing the glass-based multi-chip heterogeneous integrated structure of this embodiment includes the following steps:
[0076] S10, providing a glass plate, preparing a first redistribution layer on one side of the glass plate, and dividing the first redistribution layer into a first area and a second area;
[0077] S20, pressing a dielectric layer on the surface of the first redistribution layer;
[0078] S30, performing hole processing on the dielectric layer to form a first window for exposing a portion of the first redistribution layer located in the first area and a second window for exposing a portion of the glass plate and the first redistribution layer located in the second area at the same time;
[0079] S40, preparing a conductive pillar electrically connected to the first redistribution layer in the first window and preparing a second redistribution layer connected to the conductive pillar on the surface of the dielectric layer;
[0080] S50, respectively pressing the second solder resist layer on the exposed surface of the first redistribution layer and pressing the first solder resist layer on the exposed surface of the second redistribution layer, and exposing the pad areas of the first redistribution layer and the second redistribution layer;
[0081] S60, providing a plurality of first chips and a plurality of second chips, implanting the first chips into the pad area of the second redistribution layer and implanting the second chips into the pad area of the second region of the first redistribution layer, wherein the first chips are non-RF chips and the second chips are RF chips.
[0082] Furthermore, the glass-based multi-chip heterogeneous integrated structure includes:
[0083] A glass plate, at least one side of the glass plate having a first redistribution layer, the first redistribution layer being divided into a first region and a second region;
[0084] A second redistribution layer is located in a first region of the first redistribution layer on one side of the glass plate and is connected to the first redistribution layer;
[0085] A plurality of chips are respectively implanted in the pad area of the second region of the first redistribution layer and the pad area of the second redistribution layer, and the chips implanted in the pad area of the second region of the first redistribution layer are radio frequency chips.
[0086] Furthermore, the glass-based multi-chip heterogeneous integrated structure also includes:
[0087] A dielectric layer is located between the first region of the first redistribution layer and the second redistribution layer, and the first redistribution layer and the second redistribution layer are connected via a conductive column embedded in the dielectric layer;
[0088] The first solder resist layer covers the second redistribution layer, and the pad area of the second redistribution layer is exposed on the first solder resist layer.
[0089] Next, a specific embodiment is used to describe in detail the method for preparing the glass-based multi-chip heterogeneous integrated structure of this embodiment. In this embodiment, the method for preparing the glass-based multi-chip heterogeneous integrated structure is as follows:
[0090] 1) providing a glass plate 1, and forming a seed layer on one surface of the glass plate 1 by vacuum sputtering;
[0091] 2) Pressing a photosensitive film on the surface of the seed layer;
[0092] 3) Expose and develop the photosensitive film to form a window that exposes part of the seed layer;
[0093] 4) Making a first redistribution layer 2 in the window by electroplating, and dividing the first redistribution layer 2 into a first area and a second area according to the type of chip to be installed (RF chip and non-RF chip);
[0094] 5) Remove the remaining photosensitive film and etch away the exposed seed layer;
[0095] 6) Pressing a dielectric layer 3 on the surface of the first redistribution layer 2;
[0096] 7) Opening the dielectric layer 3 to form a first window for exposing the first redistribution layer 2 in the first area and a second window for exposing the first redistribution layer 2 and a part of the glass plate 1 in the second area;
[0097] 8) Making a seed layer on the surface of the dielectric layer 3 and in the first window by vacuum sputtering;
[0098] 9) preparing a photosensitive film on the seed layer, and exposing and developing the photosensitive film to form a third window that exposes part of the seed layer;
[0099] 10) Forming a conductive column 4 in the first window and a second redistribution layer 5 in the third window by electroplating;
[0100] 11) removing the remaining photosensitive film and etching away the seed layer exposed on the second redistribution layer 5;
[0101] 12) Coating a first solder resist layer 6 on the surface of the second redistribution layer 5 and coating a second solder resist layer 7 on the second area of the first redistribution layer 2 at the second window;
[0102] 13) Expose and develop the first solder resist layer 6 and the second solder resist layer 7 to expose the pad area of the second region of the first redistribution layer 2 and the pad area of the second redistribution layer 5;
[0103] 14) Provide a plurality of first chips 8 and a plurality of second chips 9, and implant the first chips 8 into the pad area of the second redistribution layer 5 and implant the second chips 9 into the pad area of the second region of the first redistribution layer 2, wherein the second chips 9 are RF chips and the first chips 8 are non-RF chips.
[0104] For the RF chip, this embodiment does not need to open a groove for wiring, and the RF chip can be installed on the first redistribution layer 2 on the surface of the glass plate 1, thereby realizing differential heterogeneous integration of the RF chip and the non-RF chip, reducing RF signal loss.
[0105] like Figure 1 As shown, the glass-based multi-chip heterogeneous integrated structure of this embodiment includes:
[0106] A glass plate 1, wherein at least one side of the glass plate 1 has a first redistribution layer 2, and the first redistribution layer 2 is divided into a first area and a second area;
[0107] A dielectric layer 3, located above the first region of the first redistribution layer 2;
[0108] A conductive column 4 is embedded in the dielectric layer 3;
[0109] A second redistribution layer 5 is located above the dielectric layer 3 and connected to the first redistribution layer 2 through a conductive column 4;
[0110] A first solder resist layer 6 covers the second redistribution layer 5, and a pad area of the second redistribution layer 5 is exposed from the first solder resist layer 6;
[0111] A second solder resist layer 7 covers the second area of the first redistribution layer 2, and the pad area of the second redistribution layer 5 is exposed on the second solder resist layer 7;
[0112] A plurality of first chips 8, which are non-RF chips, are flip-chip mounted on the pad area of the second redistribution layer 5, that is, the I / O ports of the first chips 8 are connected to the pad area of the second redistribution layer 5;
[0113] A plurality of second chips 9 , which are radio frequency chips, are flip-chip mounted on the pad area of the second region of the first redistribution layer 2 , that is, the I / O ports of the second chips 9 are connected to the pad area of the second region of the first redistribution layer 2 .
[0114] Embodiment 2
[0115] This embodiment is further improved on the basis of the above embodiment.
[0116] Furthermore, the method for preparing the glass-based multi-chip heterogeneous integrated structure of this embodiment comprises the following steps:
[0117] S10, providing a glass plate, preparing a first redistribution layer on one side of the glass plate, preparing a second redistribution layer on the other side, and connecting the first redistribution layer and the second redistribution layer through a first conductive column penetrating the glass plate, so as to divide the first redistribution layer into a first area and a second area;
[0118] S20, pressing a first dielectric layer on a surface of the first redistribution layer and pressing a second dielectric layer on a surface of the second redistribution layer;
[0119] S30, performing a hole-opening process on the first dielectric layer to form a first window for exposing a portion of the first redistribution layer in the first area and a second window for exposing a portion of the glass plate and the first redistribution layer in the second area at the same time;
[0120] S40, preparing a second conductive pillar electrically connected to the first redistribution layer in the first window and preparing a third redistribution layer electrically connected to the second conductive pillar on the surface of the first dielectric layer;
[0121] S50, respectively pressing a second solder resist layer on the exposed surface of the first redistribution layer and pressing a first solder resist layer on the exposed surface of the third redistribution layer, and exposing pad areas of the first redistribution layer and the third redistribution layer;
[0122] S60, providing a plurality of first chips and a plurality of second chips, implanting the first chips into the pad area of the third redistribution layer and implanting the second chips into the pad area of the second region of the first redistribution layer, the first chips being non-RF chips and the second chips being RF chips.
[0123] The corresponding glass-based multi-chip heterogeneous integration structure includes:
[0124] A glass plate, wherein a first redistribution layer is disposed on one side of the glass plate, and a second redistribution layer is disposed on the other side of the glass plate, and the first redistribution layer is connected to the second redistribution layer via a first conductive column embedded in the glass plate, and the first redistribution layer is divided into a first area and a second area;
[0125] A first dielectric layer covering a first region of the first redistribution layer;
[0126] a second dielectric layer covering the second redistribution layer;
[0127] a third redistribution layer, located on the first dielectric layer and electrically connected to the ground redistribution layer through a second conductive column embedded in the first dielectric layer;
[0128] A first solder resist layer covers the third redistribution layer, and a pad area of the third redistribution layer is exposed on the first solder resist layer;
[0129] The second solder resist layer covers the second area of the first redistribution layer, and the pad area of the first redistribution layer is exposed on the second solder resist layer.
[0130] Next, a specific implementation method is used to describe the glass-based multi-chip heterogeneous integrated structure of this embodiment (refer to Figure 2 ) is described in detail. In this embodiment, the preparation method of the glass-based multi-chip heterogeneous integrated structure is as follows:
[0131] 1) Providing a glass plate 10, and performing laser modification on a region of the glass plate 10 where a hole is to be opened;
[0132] 2) Etching the glass plate 10 to form a through hole penetrating the glass plate 10;
[0133] 3) Making a seed layer on the surface of the through hole and the surface of the glass plate 10 by vacuum sputtering;
[0134] 4) Pressing a photosensitive film on the surface of the seed layer located on the surface of the glass plate 10;
[0135] 5) Expose and develop the photosensitive film to form a window that exposes part of the seed layer;
[0136] 6) Making a first conductive column 20 in the through hole, making a first redistribution layer 30 in a window adjacent to one side of the glass plate 10, and making a second redistribution layer 40 in a window adjacent to the other side of the glass plate 10;
[0137] 7) Remove the remaining photosensitive film and etch away the exposed seed layer;
[0138] 8) Pressing a first dielectric layer 50 on the surface of the first redistribution layer 30 and pressing a second dielectric layer 60 on the surface of the second redistribution layer 40;
[0139] 9) Opening the first dielectric layer 50 to form a first window for exposing a portion of the first redistribution layer 30 in the first area and a second window for exposing the first redistribution layer 30 and a portion of the glass plate 10 in the second area (the second window corresponds to the second area of the first redistribution layer 30);
[0140] 10), forming a seed layer on the inner wall of the first window of the first dielectric layer 50 and on the surface of the first dielectric layer 50;
[0141] 11) Pressing a photosensitive film on the surface of the seed layer located on the surface of the first dielectric layer 50;
[0142] 12) exposing and developing the photosensitive film to form a third window that exposes part of the seed layer;
[0143] 13) Fabricating a second conductive column 70 in the first window and fabricating a third redistribution layer 80 connected to the second conductive column 70 in the third window;
[0144] 14) Remove the remaining photosensitive film and etch away the exposed seed layer;
[0145] 15) Pressing the second solder resist layer 100 on the exposed surface of the first redistribution layer 30 and pressing the first solder resist layer 90 on the exposed surface of the third redistribution layer 80, and making the sum of the thickness of the first redistribution layer 30, the first dielectric layer 50 and the first solder resist layer 90 equal to the sum of the thickness of the second redistribution layer 40 and the second dielectric layer 60;
[0146] 16) exposing and developing the second solder resist layer 100 to form a first hole for exposing the pad area of the first redistribution layer 30, and exposing and developing the first solder resist layer 90 to form a second hole for exposing the pad area of the third redistribution layer 80;
[0147] 17) Provide a plurality of first chips 110 and a plurality of second chips 120, implant the first chips 110 into the pad area of the third redistribution layer 80 and implant the second chips 120 into the pad area of the second region of the first redistribution layer 30, the first chips 110 are non-RF chips and the second chips 120 are RF chips, and obtain the following Figure 2 The glass-based multi-chip heterogeneous integration structure shown.
[0148] The method of this embodiment can realize differential heterogeneous integration of RF chips and non-RF chips, and the RF chip is installed on the first redistribution layer 30 close to the glass plate 10, reducing RF signal loss. At the same time, the sum of the thickness of the first redistribution layer 30, the first dielectric layer 50 and the first solder resist layer 90 is designed to be equal to the sum of the thickness of the second redistribution layer 40 and the second dielectric layer 60, reducing the warping phenomenon of the glass-based multi-chip heterogeneous integrated structure and improving the strength of the glass-based multi-chip heterogeneous integrated structure.
[0149] like Figure 2 As shown, the glass-based multi-chip heterogeneous integrated structure of the embodiment includes:
[0150] A glass plate 10, wherein a first conductive column 20 is embedded in the glass plate 10, and a first redistribution layer 30 is disposed on one side of the glass plate 10, and a second redistribution layer 40 is disposed on the other side, and the first redistribution layer 30 is connected to the second redistribution layer 40 through the first conductive column 20, and the first redistribution layer 30 is divided into a first area and a second area;
[0151] A first dielectric layer 50 covering a first region of the first redistribution layer 30;
[0152] A second dielectric layer 60 covering the second redistribution layer 40;
[0153] A second conductive column 70 embedded in the first dielectric layer 50;
[0154] A third redistribution layer 80 , located on the first dielectric layer 50 and electrically connected to the first redistribution layer 30 through the second conductive pillar 70 ;
[0155] A first solder resist layer 90 covers the third redistribution layer 80 , and a pad area of the third redistribution layer 80 is exposed outside the first solder resist layer 90 ;
[0156] The second solder resist layer 100 covers the second region of the first redistribution layer 30 , and the pad region of the first redistribution layer 30 is exposed on the second solder resist layer 100 ;
[0157] A plurality of first chips 110 that are non-RF chips and a plurality of second chips 120 that are RF chips, the first chips 110 are flipped on the third redistribution layer 80, and the I / O port of the first chip 110 is connected to the pad area of the third redistribution layer 80, the second chip 120 is flipped on the second area of the first redistribution layer 30, and the I / O port of the second chip 120 is connected to the pad area of the first redistribution layer 30,
[0158] The sum of the thicknesses of the first redistribution layer 30 , the first dielectric layer 50 , and the first solder resist layer 90 is equal to the sum of the thicknesses of the second redistribution layer 40 and the second dielectric layer 60 .
[0159] It should be noted that the above specific implementations are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art should understand that various modifications, equivalent substitutions, changes, etc. can be made to the present invention. However, as long as these changes do not deviate from the spirit of the present invention, they should be within the scope of protection of the present invention. In addition, some terms used in the specification and claims of this application are not restrictive, but are only for the convenience of description.
Claims
1. A method for preparing a glass-based multi-chip heterogeneous integrated structure, characterized in that: The following steps are involved: S10, providing a glass plate, preparing a first redistribution layer on one side of the glass plate, and dividing the first redistribution layer into a first area and a second area; S20, pressing a dielectric layer on the surface of the first redistribution layer; S30, performing a hole-opening process on the dielectric layer to form a first window that exposes a portion of the first redistribution layer located in the first area and a second window that exposes both the first redistribution layer and a portion of the glass plate located in the second area; S40, preparing a conductive pillar electrically connected to the first redistribution layer in the first window, and preparing a second redistribution layer connected to the conductive pillar on the surface of the dielectric layer; S50, respectively pressing a second solder resist layer on the exposed surface of the first redistribution layer and pressing a first solder resist layer on the exposed surface of the second redistribution layer, and exposing pad regions of the first redistribution layer and the second redistribution layer; S60. Provide a plurality of first chips and a plurality of second chips, implant the first chips into the pad area of the second redistribution layer and implant the second chips into the pad area of the second area of the first redistribution layer, the first chips are non-RF chips and the second chips are RF chips.
2. A method for preparing a glass-based multi-chip heterogeneous integrated structure, characterized in that: The following steps are involved: S10, providing a glass plate, preparing a first redistribution layer on one side of the glass plate, preparing a second redistribution layer on the other side, and connecting the first redistribution layer and the second redistribution layer via a first conductive column penetrating the glass plate, so as to divide the first redistribution layer into a first area and a second area; S20, pressing a first dielectric layer on the surface of the first redistribution layer and pressing a second dielectric layer on the surface of the second redistribution layer; S30, performing a hole-opening process on the first dielectric layer to form a first window for exposing a portion of the first redistribution layer in the first area and a second window for exposing both the first redistribution layer and a portion of the glass plate in the second area; S40, preparing a second conductive pillar electrically connected to the first redistribution layer in the first window, and preparing a third redistribution layer electrically connected to the second conductive pillar on the surface of the first dielectric layer; S50, respectively pressing a second solder resist layer on the exposed surface of the first redistribution layer and pressing a first solder resist layer on the exposed surface of the third redistribution layer, and exposing pad areas of the first redistribution layer and the third redistribution layer; S60. Provide a plurality of first chips and a plurality of second chips, implant the first chips into the pad area of the third redistribution layer and implant the second chips into the pad area of the second area of the first redistribution layer, the first chips are non-RF chips and the second chips are RF chips.
3. The method for preparing a glass-based multi-chip heterogeneous integrated structure according to claim 2, characterized in that: The sum of the thicknesses of the first redistribution layer, the first dielectric layer, and the first solder resist layer is equal to the sum of the thicknesses of the second redistribution layer and the second dielectric layer.
4. The method for preparing a glass-based multi-chip heterogeneous integrated structure according to claim 2, characterized in that: Step S10 specifically includes: S10a, providing a glass plate, and performing laser modification on a region of the glass plate to be opened; S10b, etching the glass plate to form a through hole penetrating the glass plate; S10c, forming a seed layer on the surface of the through hole and the surface of the glass plate; S10d, pressing a photosensitive film on the surface of the seed layer located on the surface of the glass plate; S10e, exposing and developing the photosensitive film to form a window that exposes a portion of the seed layer; S10f, forming a first conductive column in the through hole, forming a first redistribution layer in a window adjacent to one side of the glass plate, and forming a second redistribution layer in a window adjacent to the other side of the glass plate; S10g, removing the remaining photosensitive film and etching away the exposed seed layer.
5. The method for preparing a glass-based multi-chip heterogeneous integrated structure according to any one of claims 2 to 4, characterized in that: Step S40 specifically includes: S40a, forming a seed layer on the inner wall of the first window of the first dielectric layer and on the surface of the first dielectric layer; S40b, pressing a photosensitive film on the surface of the seed layer located on the surface of the first dielectric layer; S40c, exposing and developing the photosensitive film to form a third window exposing a portion of the seed layer; S40d, forming a second conductive column in the first window and forming a third redistribution layer in the third window; S40e, removing the remaining photosensitive film and etching away the exposed seed layer.
6. A glass-based multi-chip heterogeneous integrated structure, prepared by the method for preparing a glass-based multi-chip heterogeneous integrated structure according to claim 1, characterized in that: include: A glass plate, at least one side of which has a first redistribution layer, wherein the first redistribution layer is divided into a first region and a second region; A second redistribution layer is located in a first region of the first redistribution layer on one side of the glass plate and is connected to the first redistribution layer; A plurality of chips are respectively implanted in the pad area of the second region of the first redistribution layer and the pad area of the second redistribution layer, and the chips implanted in the pad area of the second region of the first redistribution layer are radio frequency chips.
7. The glass-based multi-chip heterogeneous integrated structure according to claim 6, characterized in that: Also includes: A dielectric layer is located between the first region of the first redistribution layer and the second redistribution layer, and the first redistribution layer and the second redistribution layer are connected via a conductive column embedded in the dielectric layer; The first solder resist layer covers the second redistribution layer, and the pad area of the second redistribution layer is exposed from the first solder resist layer.
8. A glass-based multi-chip heterogeneous integrated structure, prepared by the method for preparing a glass-based multi-chip heterogeneous integrated structure according to any one of claims 2 to 5, characterized in that: include: A glass plate, wherein a first redistribution layer is disposed on one side of the glass plate, and a second redistribution layer is disposed on the other side of the glass plate, and the first redistribution layer is connected to the second redistribution layer via a first conductive column embedded in the glass plate, and the first redistribution layer is divided into a first area and a second area; A first dielectric layer covering a first region of the first redistribution layer; a second dielectric layer, covering the second redistribution layer; a third redistribution layer, located on the first dielectric layer and electrically connected to the first redistribution layer via a second conductive column embedded in the first dielectric layer; A first solder resist layer covers the third redistribution layer, and a pad area of the third redistribution layer is exposed from the first solder resist layer; A second solder resist layer covers a second area of the first redistribution layer, and a pad area of the first redistribution layer is exposed from the second solder resist layer; A plurality of first chips that are non-RF chips and a plurality of second chips that are RF chips, wherein the first chips are flipped on the third redistribution layer, and the I / O ports of the first chips are connected to the pad areas of the third redistribution layer, and the second chips are flipped on the second area of the first redistribution layer, and the I / O ports of the second chips are connected to the pad areas of the first redistribution layer.
9. The glass-based multi-chip heterogeneous integrated structure according to claim 8, characterized in that: The sum of the thicknesses of the first redistribution layer, the first dielectric layer, and the first solder resist layer is equal to the sum of the thicknesses of the second redistribution layer and the second dielectric layer.
Citation Information
Patent Citations
Module comprising semiconductor-based component and method of manufacturing same
CN116564923A