Packaging structure and manufacturing method thereof

Abstract

The invention relates to a packaging structure and a manufacturing method thereof, the packaging structure comprises a circuit board, an adapter plate, a rewiring layer and a chip layer which are stacked, and the chip layer comprises a plurality of first chips; the rewiring layer comprises a dielectric layer and a metal interconnection line arranged in the dielectric layer; the circuit board is electrically connected with the first chips through the adapter plate and the metal interconnection lines; a groove is formed in the side, close to the rewiring layer, of the adapter plate, and part of the dielectric layer is located in the groove. The first chip and the circuit board can be electrically interconnected through the adapter plate and the metal interconnection line, so that chip interconnection and fan-out packaging are realized, the process steps are saved, and the manufacturing cost is reduced. Besides, one side, close to the rewiring layer, of the adapter plate is provided with a groove, and a part of the dielectric layer is located in the groove, so that the binding force between the dielectric layer and the adapter plate is effectively improved, the dielectric layer is prevented from being separated from the adapter plate, meanwhile, the size of the adapter plate is reduced due to the arrangement of the groove, the warping of the adapter plate is reduced, and the packaging reliability is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a packaging structure and a manufacturing method thereof. Background Art

[0002] In recent years, with the growing demand for high-density, high-speed and low-latency chip interconnection, in order to improve the integration of chip input and output ports and power supply ports, the fan-out chip on substrate (FOCOS) packaging structure with substrate as the carrier is often used to reorganize multiple chips into fan-out modules and then place them on the substrate to achieve system integration at the packaging level.

[0003] However, using existing packaging structures to achieve fan-out packaging and chip interconnection has problems such as complex process flow, low packaging reliability, and high manufacturing cost. Summary of the invention

[0004] In order to overcome the problems existing in the related art, the present disclosure provides a packaging structure and a manufacturing method thereof.

[0005] According to a first aspect of an embodiment of the present disclosure, there is provided a packaging structure, the packaging structure comprising a circuit board, a transfer board, a redistribution layer and a chip layer that are stacked, wherein the chip layer comprises a plurality of first chips;

[0006] The redistribution layer includes a dielectric layer and metal interconnection lines arranged in the dielectric layer, and the metal interconnection lines are electrically interconnected with each of the first chips;

[0007] The circuit board is electrically interconnected with each of the first chips through the adapter board and the metal interconnection wire;

[0008] A groove is provided on one side of the adapter plate close to the redistribution layer, and part of the dielectric layer is located in the groove.

[0009] In some embodiments of the present disclosure, the groove is provided in plurality;

[0010] The plurality of grooves include at least one first groove group, each of which includes a plurality of first grooves arranged at intervals along a first preset direction; and / or the plurality of grooves include at least one second groove group, each of which includes a plurality of second grooves arranged at intervals along a second preset direction;

[0011] Wherein, the first preset direction and the second preset direction are arranged at an angle.

[0012] In some embodiments of the present disclosure, when the plurality of grooves include a plurality of first groove groups, the plurality of first groove groups are arranged at intervals along a second preset direction, and each of the first grooves extends along the first preset direction;

[0013] When the plurality of grooves include a plurality of second groove groups, the plurality of second groove groups are arranged at intervals along the first preset direction, and each of the second grooves extends along the second preset direction.

[0014] In some embodiments of the present disclosure, the adapter board includes a first plastic packaging material layer and a plurality of metal conductive pillars arranged in an array and penetrating the first plastic packaging material layer, the plurality of metal conductive pillars include a plurality of columns of metal conductive pillars arranged at intervals along a first preset direction, each column of metal conductive pillars includes a plurality of metal conductive pillars arranged at intervals along a second preset direction, each of the first grooves and each of the second grooves are arranged between adjacent metal conductive pillars, one end of the metal conductive pillar is electrically interconnected with the metal interconnect line, and the other end of the metal conductive pillar is electrically interconnected with the circuit board.

[0015] In some embodiments of the present disclosure, in each column of metal conductive pillars, the distance between adjacent metal conductive pillars in the second preset direction is a first preset distance, and the width of the first groove is less than half of the first preset distance;

[0016] The distance between adjacent rows of the metal conductive pillars in the first preset direction is a second preset distance, and the width of the second groove is less than half of the second preset distance.

[0017] In some embodiments of the present disclosure, the projection of the groove on the surface of the adapter plate is a mesh structure.

[0018] In some embodiments of the present disclosure, the adapter plate includes a first plastic packaging material layer and a plurality of metal conductive pillars arranged in an array and penetrating the first plastic packaging material layer, and each grid of the mesh structure has at least one metal conductive pillar.

[0019] In some embodiments of the present disclosure, the material of the dielectric layer includes polyimide.

[0020] According to a second aspect of an embodiment of the present disclosure, a method for manufacturing a packaging structure is provided, the method for manufacturing the packaging structure comprising:

[0021] providing a substrate;

[0022] A transfer plate is arranged on the substrate, wherein a metal conductive column is arranged in the transfer plate, and a groove is arranged on the top of the transfer plate;

[0023] forming a redistribution layer on the adapter plate, the redistribution layer comprising a dielectric layer and metal interconnection lines, and a portion of the dielectric layer is located in the groove;

[0024] Disposing a chip layer on the redistribution layer, wherein the chip layer includes a plurality of first chips;

[0025] removing the substrate;

[0026] The side of the adapter board away from the redistribution layer is welded to the circuit board.

[0027] In some embodiments of the present disclosure, the step of providing a transfer plate on the substrate includes:

[0028] forming a plurality of metal conductive pillars arranged in an array on the substrate;

[0029] forming a first plastic encapsulation material layer on the substrate, wherein a top surface of the first plastic encapsulation material layer is higher than a top surface of the metal conductive column;

[0030] forming the groove on the top of the first plastic packaging material layer, wherein the groove is arranged between adjacent metal conductive pillars;

[0031] Filling a first dielectric material layer in the groove, wherein the top surface of the first dielectric material layer is flush with the top surface of the first plastic encapsulation material layer;

[0032] Grinding the first plastic encapsulation material layer and the first dielectric material layer until they are flush with the top surface of the metal conductive column, so that the top surface of the metal conductive column is exposed, the first plastic encapsulation material layer and the metal conductive column constitute the adapter board, and the first dielectric material layer constitutes part of the dielectric layer; or,

[0033] The step of arranging a transfer plate on the substrate comprises:

[0034] forming a first plastic encapsulation material layer on the substrate;

[0035] forming a plurality of through holes arranged in an array in the first plastic encapsulation material layer;

[0036] Filling the through holes with metal material to form a plurality of metal conductive pillars, wherein the top surfaces of the metal conductive pillars are flush with the top surface of the first plastic encapsulation material layer;

[0037] forming the groove on the top of the first plastic packaging material layer, wherein the groove is arranged between adjacent metal conductive pillars;

[0038] A first dielectric material layer is filled in the groove, the top surface of the first dielectric material layer is flush with the top surface of the first plastic encapsulation material layer, the first plastic encapsulation material layer and the metal conductive column constitute the adapter plate, and the first dielectric material layer constitutes part of the dielectric layer.

[0039] The technical solution provided by the embodiments of the present disclosure may include the following beneficial effects: by stacking the circuit board, adapter board, redistribution layer and chip layer, multiple first chips in the chip layer can be electrically interconnected with the circuit board through the metal interconnection lines in the adapter board and the redistribution layer, thereby realizing chip interconnection and fan-out packaging, saving process steps and reducing manufacturing costs. In addition, a groove is provided on one side of the adapter board close to the redistribution layer, so that part of the dielectric layer is located in the groove, thereby effectively improving the bonding force between the dielectric layer and the adapter board, avoiding separation of the dielectric layer and the adapter board, and at the same time, the provision of the groove reduces the volume of the adapter board, reduces the warping of the adapter board, and improves the packaging reliability.

[0040] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0042] Figure 1 It is a schematic diagram of a packaging structure.

[0043] Figure 2 is a schematic diagram of a packaging structure according to an exemplary embodiment.

[0044] Figure 3 is a top view of an adapter plate according to an exemplary embodiment.

[0045] Figure 4 is a top view of an adapter plate according to another exemplary embodiment.

[0046] Figure 5 is a top view of an adapter plate according to another exemplary embodiment.

[0047] Figure 6 is a top view of an adapter plate according to another exemplary embodiment.

[0048] Figure 7 The figure is a flow chart of a method for manufacturing a packaging structure according to an exemplary embodiment.

[0049] Figure 8 is a schematic diagram of a substrate according to an exemplary embodiment.

[0050] Fig. 9 is a schematic diagram showing a transfer plate disposed on a substrate according to an exemplary embodiment.

[0051] Fig.10The diagram is a schematic diagram showing a method of forming a redistribution layer on a transfer board according to an exemplary embodiment.

[0052] Fig.11 The diagram is a schematic diagram showing a chip layer disposed on a redistribution layer according to an exemplary embodiment.

[0053] Fig.12 is a schematic diagram showing removal of a substrate according to an exemplary embodiment.

[0054] Fig.13 The invention is a flow chart showing a method of disposing an adapter plate on a substrate according to an exemplary embodiment.

[0055] Fig.14 is a schematic diagram showing a plurality of metal conductive pillars arranged in an array formed on a substrate according to an exemplary embodiment.

[0056] Fig.15 is a schematic diagram showing forming a first molding material layer on a substrate according to an exemplary embodiment.

[0057] Fig.16 is a schematic diagram showing forming a groove on the top of the first molding material layer according to an exemplary embodiment.

[0058] Fig.17 is a schematic diagram showing filling a first dielectric material layer in a trench according to an exemplary embodiment.

[0059] Fig.18 The diagram is a schematic diagram showing grinding the first molding material layer and the first dielectric material layer until they are flush with the top surface of the metal conductive pillar according to an exemplary embodiment.

[0060] Fig.19 is a flow chart showing a method of disposing an adapter plate on a substrate according to another exemplary embodiment.

[0061] Fig. 20 is a schematic diagram showing forming a first molding material layer on a substrate according to an exemplary embodiment.

[0062] Fig.21 is a schematic diagram showing a plurality of array-arranged through holes formed in a first molding material layer according to an exemplary embodiment.

[0063] Fig. 22 The diagram is a schematic diagram showing a method of filling a metal material in a through hole to form a plurality of metal conductive pillars according to an exemplary embodiment.

[0064] Fig.23 is a schematic diagram showing forming a groove on the top of the first molding material layer according to an exemplary embodiment.

[0065] In the figure:

[0066] 10-circuit board; 11-second metal pad; 20-adapter board; 21-first plastic encapsulation material layer; 22-metal conductive column; 23-through hole; 24-ball grid array; 30-rewiring layer; 31-dielectric layer; 32-metal interconnection line; 33-first dielectric material layer; 34-second dielectric material layer; 35-first metal pad; 40-chip layer; 41-first chip; 42-columnar bump; 43-second plastic encapsulation material layer; 44-bottom filling layer; 5 0-groove; 51-first groove group; 52-first groove; 53-second groove group; 54-second groove; 55-first groove portion; 56-second groove portion; 60-second chip; 70-capacitor; 80-base; 90-chip; 100-substrate; 110-bump; L1-first preset distance; L2-second preset distance; W1-width of the first groove; W2-width of the second groove; W3-width of the first groove portion; W4-width of the second groove portion. DETAILED DESCRIPTION

[0067] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Instead, they are merely examples of devices and methods consistent with some aspects of the present invention as detailed in the appended claims.

[0068] In related technologies, as the demand for high-density, high-speed and low-latency chip interconnection continues to grow, in order to improve the integration of chip input and output ports and power supply ports, the following are often used: Figure 1 The fan-out packaging structure shown uses a substrate 100 (Substrate) as a carrier, interconnects different chips 90 through a redistribution layer 30, and then leads the signal to the substrate 100 through a bump 110 (C4 bump), and then leads the signal out through a ball grid array 24 (Ball Grid Array, BGA) to achieve system integration at the packaging level.

[0069] However, the existing packaging structure is used to realize fan-out packaging and chip 90 interconnection, which requires the redistribution layer 30 and the substrate 100 to transmit signals to the ball grid array 24 and the circuit board 10. Due to the high manufacturing cost of the substrate 100, the complex process of manufacturing the substrate 100 and welding the bumps 110, and the insufficient overall bonding strength between the substrate 100 and the redistribution layer 30, the packaging structure will have complex process flow, low packaging reliability, high manufacturing cost and other problems.

[0070] Based on this, the exemplary embodiment of the present disclosure provides a packaging structure, which can make multiple first chips in the chip layer electrically interconnected with the circuit board through the metal interconnection lines in the adapter board and the redistribution layer by stacking the circuit board, thereby realizing chip interconnection and fan-out packaging, saving process steps and reducing manufacturing costs. In addition, a groove is provided on one side of the adapter board close to the redistribution layer, so that part of the dielectric layer is located in the groove, thereby effectively improving the bonding force between the dielectric layer and the adapter board, avoiding separation of the dielectric layer and the adapter board, and at the same time, the provision of the groove reduces the volume of the adapter board, reduces the warping of the adapter board, and improves the packaging reliability.

[0071] In an exemplary embodiment, reference Figure 2 As shown, a packaging structure is provided, which includes a stacked circuit board 10, an adapter board 20, a redistribution layer 30 and a chip layer 40, wherein the chip layer 40 includes a plurality of first chips 41; the redistribution layer 30 includes a dielectric layer 31 and metal interconnections 32 arranged in the dielectric layer 31, and the metal interconnections 32 are electrically interconnected with each first chip 41; the circuit board 10 is electrically interconnected with each first chip 41 through the adapter board 20 and the metal interconnections 32; a groove 50 is provided on one side of the adapter board 20 close to the redistribution layer 30, and part of the dielectric layer 31 is located in the groove 50.

[0072] The packaging structure includes a stacked printed circuit board 10 (Printed Circuit Board, PCB), an adapter board 20, a redistribution layer 30 (Re Distribution Layer, RDL) and a chip layer 40. The chip layer 40 includes a plurality of first chips 41. The first chip 41 may be, for example, a high bandwidth memory (High Bandwidth Memory, HBM) chip or an application-specific integrated circuit (Application Specific Integrated Circuit, ASIC) chip. The redistribution layer 30 includes a dielectric layer 31 and metal interconnects 32 disposed in the dielectric layer 31. The material of the metal interconnects 32 may be, for example, copper. Each first chip 41 may be electrically interconnected with the metal interconnects 32 in the redistribution layer 30 through, for example, columnar bumps 42, and the fan-out of the input and output ports and the power supply port of the first chip 41 may be achieved by changing the distance between the pins of the metal interconnects 32.

[0073] The adapter board 20 is used to transmit the signal of the metal interconnection line 32 to the circuit board 10. For example, Figure 2As shown, the adapter board 20 can continue to transmit the signal transmitted to the metal interconnection line 32 to the ball grid array 24 connecting the adapter board 20 and the circuit board 10, that is, the circuit board 10 realizes electrical interconnection with each first chip 41 through the adapter board 20 and the metal interconnection line 32. A groove 50 is provided on the side of the adapter board 20 close to the redistribution layer 30, and the groove depth of the groove 50 can be less than the thickness of the adapter board 20. Part of the dielectric layer 31 of the redistribution layer 30 is located in the groove 50, and another part of the dielectric layer 31 of the redistribution layer 30 is located above the adapter board 20, that is, the adapter board 20 and the dielectric layer 31 of the redistribution layer 30 form a mutually embedded integral structure, which can prevent the adapter board 20 and the redistribution layer 30 from separating and the adapter board 20 from warping.

[0074] In this embodiment, by stacking the circuit board 10, the adapter board 20, the redistribution layer 30 and the chip layer 40, the multiple first chips 41 in the chip layer 40 can be electrically interconnected with the circuit board 10 through the adapter board 20 and the metal interconnection lines 32 in the redistribution layer 30. The chip interconnection and fan-out packaging are also achieved by abandoning the substrate with higher cost, saving process steps and reducing the manufacturing cost. In addition, a groove 50 is provided on the side of the adapter board 20 close to the redistribution layer 30, so that part of the dielectric layer 31 is located in the groove 50, thereby effectively improving the bonding force between the dielectric layer 31 and the adapter board 20, avoiding the separation of the dielectric layer 31 and the adapter board 20, and at the same time, the provision of the groove 50 reduces the volume of the adapter board 20, reduces the warping of the adapter board 20, and improves the packaging reliability.

[0075] It should be noted that a second chip 60 or a capacitor 70 or other components may be disposed on one side of the circuit board 10 close to the adapter board 20 . The second chip 60 may be, for example, an integrated circuit (IC) chip.

[0076] In some embodiments, reference Figure 3 As shown, a plurality of grooves 50 are provided, and the plurality of grooves 50 include at least one first groove group 51, and each first groove group 51 includes a plurality of first grooves 52 arranged at intervals along a first preset direction, and the first preset direction is arranged at an angle to the second preset direction.

[0077] There are multiple grooves 50, and the multiple grooves 50 include at least one first groove group 51. The number of first groove groups 51 can be, for example, 1, 2, ..., m, where m is a positive integer greater than 2. Each first groove group 51 includes a plurality of first grooves 52 arranged at intervals along a first preset direction, and the first preset direction is, for example, the X direction in the figure. The same number of first grooves 52 can be set in each first groove group 51, and the number of first grooves 52 in each first groove group 51 can be, for example, 2, 3, ..., n, where n is a positive integer greater than three. Exemplarily, the groove length, groove width and groove depth of each first groove 52 are the same, and the distance between adjacent first groove groups 51 and the distance between adjacent first grooves 52 in each first groove group 51 are the same. If m first groove groups 51 are provided, and n first grooves 52 are provided in each first groove group 51, the number of grooves 50 is m*n.

[0078] In this embodiment, by setting at least one first groove group 51, each first groove group 51 includes a plurality of first grooves 52 arranged at intervals along a first preset direction, a plurality of grooves 50 can be obtained on the adapter board 20, thereby achieving that part of the dielectric layer 31 is located in the groove 50, and the plurality of grooves 50 are arranged at intervals, so that the dielectric layer 31 of the adapter board 20 and the redistribution layer 30 form an overall structure embedded in each other at multiple positions, thereby effectively improving the bonding force between the dielectric layer 31 and the adapter board 20, avoiding separation of the dielectric layer 31 and the adapter board 20, and at the same time, the setting of the groove 50 reduces the volume of the adapter board 20, reduces the warping of the adapter board 20, and improves the packaging reliability.

[0079] In other embodiments, reference Figure 4 As shown, the plurality of grooves 50 include at least one second groove group 53, each second groove group 53 includes a plurality of second grooves 54 arranged at intervals along a second preset direction, and the first preset direction is arranged at an angle to the second preset direction.

[0080] There are multiple grooves 50, and the multiple grooves 50 include at least one second groove group 53. The number of second groove groups 53 can be, for example, 1, 2, ..., p, where p is a positive integer greater than 2. Each second groove group 53 includes a plurality of second grooves 54 arranged at intervals along a second preset direction, and the second preset direction is, for example, the Y direction in the figure. The same number of second grooves 54 can be arranged in each second groove group 53, and the number of second grooves 54 in each second groove group 53 can be, for example, 2, 3, ..., q, where q is a positive integer greater than three. Exemplarily, the groove length, groove width and groove depth of each second groove 54 are the same, and the distance between adjacent second groove groups 53 and the distance between adjacent second grooves 54 in each second groove group 53 are the same. If p second groove groups 53 are provided, and q second grooves 54 are provided in each second groove group 53, the number of grooves 50 is p*q.

[0081] In this embodiment, by setting at least one second groove group 53, each second groove group 53 includes a plurality of second grooves 54 arranged at intervals along a second preset direction, a plurality of grooves 50 can be obtained on the adapter board 20, thereby achieving that part of the dielectric layer 31 is located in the groove 50, and the plurality of grooves 50 are arranged at intervals, so that the dielectric layer 31 of the adapter board 20 and the redistribution layer 30 form an overall structure embedded in each other at multiple positions, thereby effectively improving the bonding force between the dielectric layer 31 and the adapter board 20, avoiding separation of the dielectric layer 31 and the adapter board 20, and at the same time, the setting of the groove 50 reduces the volume of the adapter board 20, reduces the warping of the adapter board 20, and improves the packaging reliability.

[0082] In other embodiments, reference Figure 5 As shown, the multiple grooves 50 include at least one first groove group 51 and at least one second groove group 53, each first groove group 51 includes a plurality of first grooves 52 arranged at intervals along a first preset direction, and each second groove group 53 includes a plurality of second grooves 54 arranged at intervals along a second preset direction, and the first preset direction is set at an angle to the second preset direction.

[0083] There are multiple grooves 50, and the multiple grooves 50 include at least one first groove group 51 and at least one second groove group 53. The number of first groove groups 51 can be, for example, 1, 2, ..., m, and m is a positive integer greater than 2. Each first groove group 51 includes a plurality of first grooves 52 arranged at intervals along a first preset direction, and the first preset direction is, for example, the X direction in the figure. The same number of first grooves 52 can be set in each first groove group 51, and the number of first grooves 52 in each first groove group 51 can be, for example, 2, 3, ..., n, and n is a positive integer greater than three. Exemplarily, the groove length, groove width and groove depth of each first groove 52 are the same, and the distance between adjacent first groove groups 51 and the distance between adjacent first grooves 52 in each first groove group 51 are the same. The number of second groove groups 53 can be, for example, 1, 2, ..., p, and p is a positive integer greater than 2. Each second groove group 53 includes a plurality of second grooves 54 arranged at intervals along a second preset direction, the second preset direction is, for example, the Y direction in the figure, and the same number of second grooves 54 can be provided in each second groove group 53, and the number of second grooves 54 in each second groove group 53 can be, for example, 2, 3, ..., q, where q is a positive integer greater than three. Exemplarily, the groove length, groove width and groove depth of each second groove 54 are the same, the distance between adjacent second groove groups 53 and the distance between adjacent second grooves 54 in each second groove group 53 are the same, if there are m first groove groups 51 and p second groove groups 53, each first groove group 51 is provided with n first grooves 52, and each second groove group 53 is provided with q second grooves 54, then the number of grooves 50 is m*n+p*q.

[0084] In this embodiment, by setting at least one second groove group 53 and at least one second groove group 53, each first groove group 51 includes a plurality of first grooves 52 arranged at intervals along a first preset direction, and each second groove group 53 includes a plurality of second grooves 54 arranged at intervals along a second preset direction, a plurality of grooves 50 can be obtained on the adapter board 20, thereby achieving that part of the dielectric layer 31 is located in the groove 50, and the plurality of grooves 50 are arranged at intervals, so that the dielectric layer 31 of the adapter board 20 and the redistribution layer 30 form an integral structure embedded in each other at multiple positions, thereby effectively improving the bonding force between the dielectric layer 31 and the adapter board 20, avoiding separation of the dielectric layer 31 and the adapter board 20, and at the same time, the provision of the groove 50 reduces the volume of the adapter board 20, reduces the warping of the adapter board 20, and improves the packaging reliability.

[0085] In some embodiments, reference Figures 3 to 5As shown, when the multiple grooves 50 include multiple first groove groups 51, the multiple first groove groups 51 are arranged at intervals along the second preset direction, and each first groove 52 extends along the first preset direction; when the multiple grooves 50 include multiple second groove groups 53, the multiple second groove groups 53 are arranged at intervals along the first preset direction, and each second groove 54 extends along the second preset direction.

[0086] The angle between the first preset direction and the second preset direction may be, for example, 90°. When the plurality of grooves 50 include a plurality of first groove groups 51, the plurality of first groove groups 51 are arranged at intervals along the second preset direction, and each first groove 52 extends along the first preset direction, that is, the extension direction of the first groove 52 is the same as the spacing arrangement direction of the first grooves 52 in each first groove group 51. When the plurality of grooves 50 include a plurality of second groove groups 53, the plurality of second groove groups 53 are arranged at intervals along the first preset direction, and each second groove 54 extends along the second preset direction, that is, the extension direction of the second groove 54 is the same as the spacing arrangement direction of the second grooves 54 in each second groove group 53.

[0087] In this embodiment, by arranging a plurality of first groove groups 51 at intervals along the second preset direction and extending each first groove 52 along the first preset direction, a plurality of first grooves 52 arranged in an array and extending along the first preset direction are formed, and by arranging a plurality of second groove groups 53 at intervals along the first preset direction and extending each second groove 54 along the second preset direction, a plurality of second grooves 54 arranged in an array and extending along the second preset direction are formed. A plurality of grooves 50 can be obtained on the adapter board 20, thereby realizing that part of the dielectric layer 31 is located in the groove 50, and the plurality of grooves 50 are arranged in an array and the extension direction is fixed, so that the adapter board 20 and the dielectric layer 31 of the redistribution layer 30 form an integral structure mutually embedded in a plurality of positions arranged in an array, thereby effectively improving the bonding force between the dielectric layer 31 and the adapter board 20, avoiding the separation of the dielectric layer 31 and the adapter board 20, and at the same time, the provision of the grooves 50 reduces the volume of the adapter board 20, reduces the warping of the adapter board 20, and improves the packaging reliability.

[0088] The material of the adapter plate 20 may be, for example, silicon, glass, ceramic, dielectric material or plastic packaging material. Figures 2 to 5 As shown, the adapter board 20 includes a first plastic packaging material layer 21 and a plurality of metal conductive pillars 22 arranged in an array and penetrating the first plastic packaging material layer 21, the plurality of metal conductive pillars 22 include a plurality of columns of metal conductive pillars 22 arranged at intervals along a first preset direction, each column of metal conductive pillars 22 includes a plurality of metal conductive pillars 22 arranged at intervals along a second preset direction, each first groove 52 and each second groove 54 are arranged between adjacent metal conductive pillars 22, one end of the metal conductive pillar 22 is electrically interconnected with the metal interconnect line 32, and the other end of the metal conductive pillar 22 is electrically interconnected with the circuit board 10.

[0089] Among them, the adapter board 20 includes a first plastic packaging material layer 21 and a plurality of metal conductive columns 22 arranged in an array and penetrating the first plastic packaging material layer 21. The top surface of the metal conductive column 22 is flush with the top surface of the first plastic packaging material layer 21, and the bottom surface of the metal conductive column 22 is flush with the bottom surface of the first plastic packaging material layer 21. The material of the metal conductive column 22 can be copper, for example.

[0090] A plurality of columns of metal conductive pillars 22 are arranged at intervals along a first preset direction, and each column of metal conductive pillars 22 includes a plurality of metal conductive pillars 22 arranged at intervals along a second preset direction. Exemplarily, the height and diameter of each metal conductive pillar 22 can be set to 20-50 μm, and the distance between each column of metal conductive pillars 22 and the distance between adjacent metal conductive pillars 22 in each column of metal conductive pillars 22 can be determined according to the distance between the metal interconnects 32 in the redistribution layer 30 to correspond to the setting of the metal interconnects 32. The distance between the center lines of adjacent metal conductive pillars 22 can be set to be greater than 600 μm, for example.

[0091] Each first groove 52 is arranged between adjacent metal conductive pillars 22 along the first preset direction, and each second groove 54 is arranged between adjacent metal conductive pillars 22 along the second preset direction. One end of each metal conductive pillar 22 can be directly electrically interconnected with the metal interconnection line 32 of the redistribution layer 30, and the other end of each metal conductive pillar 22 can be electrically interconnected with the circuit board 10 through the ball grid array 24 arranged between the circuit board 10 and the adapter board 20, so as to realize the electrical interconnection between the circuit board 10 and each first chip 41.

[0092] In this embodiment, the adapter board 20 includes a first plastic encapsulation material layer 21 and a plurality of metal conductive pillars 22 penetrating the first plastic encapsulation material layer 21. The two ends of the metal conductive pillars 22 are electrically interconnected with the metal interconnection lines 32 and the circuit board 10, respectively, so as to realize the electrical interconnection between the circuit board 10 and each first chip 41. The plurality of metal conductive pillars 22 are arranged in an array so that each pin of the metal interconnection line 32 used for fan-out has a corresponding metal conductive pillar 22 electrically interconnected therewith, and the distance between adjacent metal conductive pillars 22 can be adjusted accordingly according to the distance between the metal interconnection lines 32. Each first groove 52 and each second groove 52 are arranged between adjacent metal conductive pillars 22 to avoid interference with the metal conductive pillars 22 caused by the arrangement of the grooves 50, thereby affecting the electrical interconnection between the circuit board 10 and the redistribution layer 30, while ensuring the overall strength of the adapter board 20 and improving the packaging reliability.

[0093] In some embodiments, reference Figure 5As shown, in each column of metal conductive pillars 22, the distance between adjacent metal conductive pillars 22 in the second preset direction is the first preset distance L1, and the width W1 of the first groove 52 is less than half of the first preset distance L1; the distance between adjacent columns of metal conductive pillars 22 in the first preset direction is the second preset distance L2, and the width W2 of the second groove 54 is less than half of the second preset distance L2.

[0094] Among them, Figure 5 As shown, the first preset distance L1 is the shortest distance between the sidewalls of adjacent metal conductive pillars 22 in each column of metal conductive pillars 22 in the second preset direction, and the width W1 of the first groove 52 is set to be less than half of the first preset distance L1, that is, the width W1 of the first groove 52 is less than the distance between adjacent metal conductive pillars 22 in the second preset direction. The second preset distance L2 is the shortest distance between the sidewalls of adjacent columns of metal conductive pillars 22 in the first preset direction, and the width W2 of the second groove 54 is less than half of the second preset distance L2, that is, the width W2 of the second groove 54 is less than the distance between adjacent columns of metal conductive pillars 22 in the first preset direction. The lengths of the first groove 52 and the second groove 54 can be set to be less than the diameter of the metal conductive pillar 22, or can be set to be greater than the diameter of the metal conductive pillar 22, and can be adjusted accordingly according to different stress simulation results under different groove 50 settings to ensure the overall strength of the adapter board 20.

[0095] In this embodiment, the width W1 of the first groove 52 is set to be less than half of the first preset distance L1, and the width W2 of the second groove 54 is set to be less than half of the second preset distance L2, so that the width of each groove 50 in one direction is less than half of the shortest distance between adjacent metal conductive pillars 22 in that direction, thereby avoiding interference with the metal conductive pillars 22 due to excessive width of the groove 50, thereby affecting the electrical interconnection between the circuit board 10 and the redistribution layer 30, and further improving the packaging reliability.

[0096] In some embodiments, reference Figure 6 As shown, the projection of the grooves 50 on the surface of the adapter plate 20 is a mesh structure.

[0097] Among them, the groove 50 can also be a connected groove 50 whose projection on the surface of the adapter plate 20 is a mesh structure. Exemplarily, the groove 50 can include a plurality of first groove portions 55 extending along a first preset direction and a plurality of second groove portions 56 extending along a second preset direction. The first groove portions 55 and the second groove portions 56 are interconnected at the intersection position. The first preset direction is, for example, the X direction in the figure, and the second preset direction is, for example, the Y direction in the figure. Two adjacent first groove portions 55 and two adjacent second groove portions 56 form a mesh edge, so that the projection of the entire groove 50 on the surface of the adapter plate 20 is a mesh structure.

[0098] In the present embodiment, by providing grooves 50 having a mesh-like projection on the surface of the adapter board 20, part of the dielectric layer 31 is located in the grooves 50. The grooves 50 are connected and arranged in a mesh, so that the dielectric layers 31 of the adapter board 20 and the redistribution layer 30 form a continuous and mutually embedded overall structure, thereby effectively improving the bonding force between the dielectric layer 31 and the adapter board 20 and avoiding separation of the dielectric layer 31 and the adapter board 20. At the same time, the provision of the grooves 50 reduces the volume of the adapter board 20, reduces the warping of the adapter board 20, and improves the packaging reliability.

[0099] In some embodiments, reference Figure 6 As shown, the adapter board 20 includes a first plastic packaging material layer 21 and a plurality of metal conductive pillars 22 arranged in an array and penetrating the first plastic packaging material layer 21 , and each grid of the mesh structure has at least one metal conductive pillar 22 .

[0100] The projection of the groove 50 on the surface of the adapter plate 20 is a mesh structure. The adapter plate 20 includes a first plastic encapsulation material layer 21 and a plurality of metal conductive pillars 22 arranged in an array and penetrating the first plastic encapsulation material layer 21. The top surface of the metal conductive pillar 22 is flush with the top surface of the first plastic encapsulation material layer 21, and the bottom surface of the metal conductive pillar 22 is flush with the bottom surface of the first plastic encapsulation material layer 21. The material of the metal conductive pillar 22 can be copper, for example. There is at least one metal conductive pillar 22 in each grid of the mesh structure, that is, the metal conductive pillar 22 is correspondingly arranged in the grid surrounded by two adjacent first groove portions 55 and two adjacent second groove portions 56. For example, one metal conductive pillar 22 is arranged in each grid. Since the groove 50 is arranged in a mesh structure, the metal conductive pillars 22 located in each grid are arranged in an array. The height and diameter of each metal conductive pillar 22 can be set to 20-50μm, and the distance between the center lines of adjacent metal conductive pillars 22 can be set to be greater than 600μm, for example.

[0101] In this embodiment, the adapter board 20 includes a first plastic encapsulation material layer 21 and a plurality of metal conductive pillars 22 that penetrate the first plastic encapsulation material layer 21. By electrically interconnecting the two ends of the metal conductive pillars 22 with the metal interconnection lines 32 and the circuit board 10, respectively, the circuit board 10 and each first chip 41 are electrically interconnected. At least one metal conductive pillar 22 is provided in each grid, so that each pin of the metal interconnection line 32 used for fan-out has a corresponding metal conductive pillar 22 electrically interconnected with it. The metal conductive pillar 22 is provided in each grid of the mesh structure of the groove 50 to avoid interference with the metal conductive pillar 22 caused by the provision of the groove 50, thereby affecting the electrical interconnection between the circuit board 10 and the redistribution layer 30, while ensuring the overall strength of the adapter board 20 and improving the packaging reliability.

[0102] It can be understood that when the first groove portion 55 extends along the first preset direction and the second groove portion 56 extends along the second preset direction, the distance between adjacent metal conductive pillars 22 in the second preset direction is the first preset distance L1, and the distance between adjacent metal conductive pillars 22 in the first preset direction is the second preset distance L2. Similarly, the width W3 of the first groove portion 55 is controlled to be less than half of the first preset distance L1, and the width W4 of the second groove portion 56 is controlled to be less than half of the second preset distance L2, so that the width of each groove 50 in one direction is less than half of the shortest distance between adjacent metal conductive pillars 22 in that direction, thereby avoiding interference with the metal conductive pillars 22 due to excessive width of the groove 50, thereby improving packaging reliability.

[0103] In some embodiments, the material of the dielectric layer 31 includes polyimide.

[0104] In this embodiment, the material of the dielectric layer 31 includes polyimide (PI), which is a type of polymer containing an imide ring (-CO-N-CO-) in the main chain, and has the characteristics of strong insulation and high temperature resistance. Using polyimide as the material of the dielectric layer 31 can make the dielectric layer 31 have low dielectric loss and adapt to high-temperature processing, and the polyimide has excellent bending resistance, which ensures the overall strength of the redistribution layer 30 composed of the dielectric layer 31 and the metal interconnection line 32.

[0105] In an exemplary embodiment, reference Figure 7 As shown, a method for manufacturing a packaging structure is provided, and the method for manufacturing the packaging structure includes:

[0106] S100: providing a substrate.

[0107] In step S100, provide Figure 8 The substrate 80 shown in the figure may be made of glass, for example, and the substrate 80 is used as a bottom carrier for manufacturing a packaging structure.

[0108] S200, a transfer plate is arranged on the substrate, a metal conductive column is arranged in the transfer plate, and a groove is arranged on the top of the transfer plate.

[0109] In step S200, Fig. 9 As shown, an adapter plate 20 is disposed on a substrate 80, and the side wall of the adapter plate 20 is flush with the side wall of the substrate 80. A metal conductive column 22 is disposed in the adapter plate 20, and the bottom of the metal conductive column 22 is in contact with the substrate 80, and the top of the metal conductive column 22 is flush with the first plastic encapsulation material layer 21. A groove 50 is disposed on the top of the adapter plate 20, and the groove 50 may be a plurality of grooves 50, or may be a connected groove 50 projected in a mesh structure.

[0110] S300, forming a redistribution layer on the transfer board, the redistribution layer including a dielectric layer and metal interconnection lines, and a portion of the dielectric layer is located in a plurality of grooves.

[0111] In step S300, Fig.10 As shown, a redistribution layer 30 including a dielectric layer 31 and metal interconnection lines 32 is formed on the adapter board 20. The dielectric layer 31 includes a first dielectric material layer 33 located in the groove 50 and a second dielectric material layer 34 located on the first plastic encapsulation material layer 21 and the first dielectric material layer 33. For example, the first dielectric material layer 33 can be first filled in the groove 50, and then the second dielectric material layer 34 can be formed on the first plastic encapsulation material layer 21 and the first dielectric material layer 33. The first dielectric material layer 33 and the second dielectric material layer 34 formed successively constitute the dielectric layer 31. The metal interconnection line 32 is arranged in the second dielectric material layer 34, and the bottom of the metal interconnection line 32 is connected to the metal conductive column 22. A first metal pad 35 electrically interconnected with the metal interconnection line 32 is formed at a position flush with the top surface of the second dielectric material layer 34 to achieve electrical interconnection with the first chip 41 formed subsequently, that is, the first chip 41 and the metal conductive column 22 are electrically interconnected through the metal interconnection line 32.

[0112] S400, disposing a chip layer on the redistribution layer, wherein the chip layer includes a plurality of first chips.

[0113] In step S400, Fig.11 As shown, a chip layer 40 is arranged on the top of the redistribution layer 30, and the chip layer 40 includes a plurality of first chips 41, and the first chip 41 may be, for example, a high-bandwidth memory chip or an integrated circuit chip for a special application. Exemplarily, the chip layer 40 may also include a pillar bump 42, a second plastic encapsulation material layer 43, and a bottom filling layer 44, wherein the pillar bump 42 is arranged on each first chip 41, and the first chip 41 is electrically interconnected with the metal interconnection line 32 by contacting the pillar bump 42 (pillar bump) on the first chip 41 with the first metal pad 35 in the redistribution layer 30. The bottom filling layer 44 is used to fill the gaps between the pillar bumps 42, and the second plastic encapsulation material layer 43 covers the bottom filling layer 44 and the plurality of first chips 41, and the top surface of the second plastic encapsulation material layer 43 is ground to be flush with the top surface of the first chip 41.

[0114] S500: removing the substrate.

[0115] In step S500, Fig.12 As shown, the substrate 80 is removed by debonding, so that one end of the metal conductive pillar 22 in the transfer board 20 away from the redistribution layer 30 is exposed.

[0116] S600, soldering the side of the adapter board away from the redistribution layer to the circuit board.

[0117] In step S600, the side of the adapter plate 20 away from the redistribution layer 30 is welded to the circuit board 10. For example, a ball grid array 24 is provided on the side of the adapter plate 20 away from the redistribution layer 30 corresponding to the exposed metal conductive pillars 22, a plurality of second metal pads 11 corresponding to the ball grid array 24 are formed on the circuit board 10, and the ball grid array 24 is welded to the second metal pads 11, so that the adapter plate 20 is welded to the circuit board 10 and the metal conductive pillars 22 are electrically interconnected with the circuit board 10, and finally a circuit board as shown in FIG. Figure 2 The packaging structure shown enables the circuit board 10 to be electrically interconnected with each first chip 41 through the adapter board 20 and the metal interconnection line 32 .

[0118] In this embodiment, by sequentially forming an adapter plate 20, a redistribution layer 30 and a chip layer 40 on a substrate 80, and welding the side of the adapter plate 20 away from the redistribution layer 30 to the circuit board 10 after the substrate 80 is removed, a packaging structure including a stacked circuit board 10, an adapter plate 20, a redistribution layer 30 and a chip layer 40 is formed, so that multiple first chips 41 in the chip layer 40 can be electrically interconnected with the circuit board 10 through the adapter plate 20 and the metal interconnection lines 32 in the redistribution layer 30, and the chip interconnection and fan-out packaging are also realized by abandoning the substrate with a higher cost, saving process steps and reducing the manufacturing cost. In addition, a groove 50 is provided on the side of the adapter plate 20 close to the redistribution layer 30, so that part of the dielectric layer 31 is located in the groove 50, thereby effectively improving the bonding force between the dielectric layer 31 and the adapter plate 20, avoiding the separation of the dielectric layer 31 and the adapter plate 20, and at the same time, the provision of the groove 50 reduces the volume of the adapter plate 20, reduces the warping of the adapter plate 20, and improves the packaging reliability.

[0119] In some embodiments, reference Fig.13 As shown, a transfer plate 20 is disposed on a substrate 80, comprising:

[0120] S201, forming a plurality of metal conductive pillars arranged in an array on a substrate.

[0121] In step S201, Fig.14 As shown, a plurality of metal conductive pillars 22 arranged in an array may be formed on the substrate 80 by an electroplating process. The material of the metal conductive pillars 22 may be copper, for example.

[0122] S202, forming a first plastic encapsulation material layer on the substrate, wherein a top surface of the first plastic encapsulation material layer is higher than a top surface of the metal conductive column.

[0123] In step S202, if Fig.15 As shown, a first molding material layer 21 can be formed on the substrate 80 by a filling or deposition process, and the top surface of the first molding material layer 21 is higher than the top surface of the metal conductive column 22.

[0124] S203 , forming a groove on the top of the first plastic packaging material layer, wherein the groove is arranged between adjacent metal conductive pillars.

[0125] In step S203, if Fig.16 As shown, a groove 50 may be formed on the top of the first molding material layer 21 by an etching process, and the groove 50 is disposed between adjacent metal conductive pillars 22 .

[0126] S204 , filling the groove with a first dielectric material layer, wherein the top surface of the first dielectric material layer is flush with the top surface of the first plastic encapsulation material layer.

[0127] In step S204, Fig.17 As shown, the first dielectric material layer 33 can be filled in the groove 50 by a filling process, and the top surface of the first dielectric material layer 33 is flush with the top surface of the first molding material layer 21 , and the top surface of the first dielectric material layer 33 is also higher than the top surface of the metal conductive column 22 .

[0128] S205, grinding the first plastic encapsulation material layer and the first dielectric material layer until they are flush with the top surface of the metal conductive column, so that the top surface of the metal conductive column is exposed, the first plastic encapsulation material layer and the metal conductive column constitute a transfer plate, and the first dielectric material layer constitutes a part of the dielectric layer.

[0129] In step S205, Fig.18 As shown, the first molding material layer 21 and the first dielectric material layer 33 can be ground to be flush with the top surface of the metal conductive column 22 through a grinding process, so that the top surface of the metal conductive column 22 is exposed, and the first molding material layer 21 and the metal conductive column 22 constitute the adapter board 20, and the first dielectric material layer 33 and the subsequently formed second dielectric material layer 34 constitute the dielectric layer 31 of the redistribution layer 30.

[0130] In this embodiment, the above steps are used to realize the setting of the adapter plate 20 on the substrate 80. The adapter plate 20 is provided with a metal conductive column 22. The two ends of the metal conductive column 22 can be electrically interconnected with the metal interconnection line 32 and the circuit board 10 respectively, so as to realize the electrical interconnection between the circuit board 10 and each first chip 41. Abandoning the substrate with higher cost also realizes chip interconnection and fan-out packaging, saves process steps and reduces manufacturing costs. In addition, a groove 50 is provided on one side of the adapter plate 20 close to the redistribution layer 30, so that part of the dielectric layer 31 is located in the groove 50, thereby effectively improving the bonding force between the dielectric layer 31 and the adapter plate 20, avoiding the separation of the dielectric layer 31 and the adapter plate 20, and at the same time, the provision of the groove 50 reduces the volume of the adapter plate 20, reduces the warping of the adapter plate 20, and improves the packaging reliability.

[0131] In other embodiments, reference Fig.19As shown, a transfer plate 20 is disposed on a substrate 80, comprising:

[0132] S211, forming a first plastic packaging material layer on the substrate.

[0133] In step S211, Fig. 20 As shown, the first molding material layer 21 is formed directly on the substrate 80 by a deposition process.

[0134] S212, forming a plurality of through holes arranged in an array in the first plastic packaging material layer.

[0135] In step S212, if Fig.21 As shown, a plurality of through holes 23 penetrating the first molding material layer 21 can be formed in the first molding material layer 21 by an etching process. The plurality of through holes 23 are arranged in an array and the arrangement corresponds to the arrangement of the metal conductive pillars 22 formed subsequently.

[0136] S213, filling the through holes with metal material to form a plurality of metal conductive pillars, wherein the top surfaces of the metal conductive pillars are flush with the top surface of the first plastic encapsulation material layer.

[0137] In step S213, if Fig. 22 As shown, a metal material may be filled in the through hole 23 through a filling process to form a plurality of metal conductive pillars 22 , wherein the plurality of metal conductive pillars 22 are arranged in an array, and the top surface of the metal conductive pillars 22 is flush with the top surface of the first plastic packaging material layer 21 .

[0138] S214 , forming a groove on the top of the first plastic packaging material layer, wherein the groove is arranged between adjacent metal conductive pillars.

[0139] In step S214, if Fig.23 As shown, a groove 50 may be formed on the top of the first molding material layer 21 by an etching process, and the groove 50 is disposed between adjacent metal conductive pillars 22 .

[0140] S215 , filling the groove with a first dielectric material layer, wherein the top surface of the first dielectric material layer is flush with the top surface of the first plastic encapsulation material layer, the first plastic encapsulation material layer and the metal conductive column constitute a transfer plate, and the first dielectric material layer constitutes a portion of the dielectric layer 31 .

[0141] In step S215, Fig.18 As shown, the first dielectric material layer 33 can be filled in the groove 50 through a filling process, the top surface of the first dielectric material layer 33 is flush with the top surface of the first plastic encapsulation material layer 21, the first plastic encapsulation material layer 21 and the metal conductive column 22 constitute the adapter board 20, and the first dielectric material layer 33 and the subsequently formed second dielectric material layer 34 constitute the dielectric layer 31 of the redistribution layer 30.

[0142] In this embodiment, the above steps are used to realize the setting of the adapter plate 20 on the substrate 80. The adapter plate 20 is provided with a metal conductive column 22. The two ends of the metal conductive column 22 can be electrically interconnected with the metal interconnection line 32 and the circuit board 10 respectively, so as to realize the electrical interconnection between the circuit board 10 and each first chip 41. Abandoning the substrate with higher cost also realizes chip interconnection and fan-out packaging, saves process steps and reduces manufacturing costs. In addition, a groove 50 is provided on one side of the adapter plate 20 close to the redistribution layer 30, so that part of the dielectric layer 31 is located in the groove 50, thereby effectively improving the bonding force between the dielectric layer 31 and the adapter plate 20, avoiding the separation of the dielectric layer 31 and the adapter plate 20, and at the same time, the provision of the groove 50 reduces the volume of the adapter plate 20, reduces the warping of the adapter plate 20, and improves the packaging reliability.

[0143] Those skilled in the art will readily appreciate other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses or adaptations of the present invention that follow the general principles of the present invention and include common knowledge or customary techniques in the art that are not disclosed in this disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present invention are indicated by the claims.

[0144] It should be understood that the present invention is not limited to the exact construction that has been described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

Claims

1. A packaging structure, characterized in that: The packaging structure comprises a circuit board, an adapter board, a redistribution layer and a chip layer which are stacked, wherein the chip layer comprises a plurality of first chips; The redistribution layer includes a dielectric layer and metal interconnection lines arranged in the dielectric layer, and the metal interconnection lines are electrically interconnected with each of the first chips; The circuit board is electrically interconnected with each of the first chips through the adapter board and the metal interconnection wire; A groove is provided on one side of the adapter plate close to the redistribution layer, and part of the dielectric layer is located in the groove.

2. The packaging structure according to claim 1, characterized in that: The grooves are provided in plurality; The plurality of grooves include at least one first groove group, and each of the first groove groups includes a plurality of first grooves arranged at intervals along a first preset direction; And / or, the plurality of grooves include at least one second groove group, and each of the second groove groups includes a plurality of second grooves arranged at intervals along a second preset direction; Wherein, the first preset direction and the second preset direction are arranged at an angle.

3. The packaging structure according to claim 2, characterized in that: When the plurality of grooves include a plurality of first groove groups, the plurality of first groove groups are arranged at intervals along the second preset direction, and each of the first grooves extends along the first preset direction; When the plurality of grooves include a plurality of second groove groups, the plurality of second groove groups are arranged at intervals along the first preset direction, and each of the second grooves extends along the second preset direction.

4. The packaging structure according to claim 2, characterized in that: The adapter board includes a first plastic packaging material layer and a plurality of metal conductive pillars arranged in an array and penetrating the first plastic packaging material layer, the plurality of metal conductive pillars include a plurality of columns of metal conductive pillars arranged at intervals along a first preset direction, each column of metal conductive pillars includes a plurality of metal conductive pillars arranged at intervals along a second preset direction, each of the first grooves and each of the second grooves are arranged between adjacent metal conductive pillars, one end of the metal conductive pillar is electrically interconnected with the metal interconnect line, and the other end of the metal conductive pillar is electrically interconnected with the circuit board.

5. The packaging structure according to claim 4, characterized in that: In each column of metal conductive pillars, the distance between adjacent metal conductive pillars in the second preset direction is a first preset distance, and the width of the first groove is less than half of the first preset distance; The distance between adjacent rows of the metal conductive pillars in the first preset direction is a second preset distance, and the width of the second groove is less than half of the second preset distance.

6. The packaging structure according to claim 1, characterized in that: The projection of the groove on the surface of the adapter plate is a mesh structure.

7. The packaging structure according to claim 6, characterized in that: The adapter plate includes a first plastic packaging material layer and a plurality of metal conductive pillars arranged in an array and penetrating the first plastic packaging material layer. There is at least one metal conductive pillar in each grid of the mesh structure.

8. The packaging structure according to any one of claims 1 to 7, characterized in that: The material of the dielectric layer includes polyimide.

9. A method for manufacturing a packaging structure, characterized in that: The manufacturing method of the packaging structure comprises: providing a substrate; A transfer plate is arranged on the substrate, wherein a metal conductive column is arranged in the transfer plate, and a groove is arranged on the top of the transfer plate; forming a redistribution layer on the adapter plate, the redistribution layer comprising a dielectric layer and metal interconnection lines, and a portion of the dielectric layer is located in the groove; Disposing a chip layer on the redistribution layer, wherein the chip layer includes a plurality of first chips; removing the substrate; The side of the adapter board away from the redistribution layer is welded to the circuit board.

10. The method for manufacturing a packaging structure according to claim 9, characterized in that: The step of arranging a transfer plate on the substrate comprises: forming a plurality of metal conductive pillars arranged in an array on the substrate; forming a first plastic encapsulation material layer on the substrate, wherein a top surface of the first plastic encapsulation material layer is higher than a top surface of the metal conductive column; forming the groove on the top of the first plastic packaging material layer, wherein the groove is arranged between adjacent metal conductive pillars; Filling a first dielectric material layer in the groove, wherein the top surface of the first dielectric material layer is flush with the top surface of the first plastic encapsulation material layer; Grinding the first plastic encapsulation material layer and the first dielectric material layer until they are flush with the top surface of the metal conductive column, so that the top surface of the metal conductive column is exposed, the first plastic encapsulation material layer and the metal conductive column constitute the adapter board, and the first dielectric material layer constitutes part of the dielectric layer; or, The step of arranging a transfer plate on the substrate comprises: forming a first plastic encapsulation material layer on the substrate; forming a plurality of through holes arranged in an array in the first plastic encapsulation material layer; Filling the through holes with metal material to form a plurality of metal conductive pillars, wherein the top surfaces of the metal conductive pillars are flush with the top surface of the first plastic encapsulation material layer; forming the groove on the top of the first plastic packaging material layer, wherein the groove is arranged between adjacent metal conductive pillars; A first dielectric material layer is filled in the groove, the top surface of the first dielectric material layer is flush with the top surface of the first plastic encapsulation material layer, the first plastic encapsulation material layer and the metal conductive column constitute the adapter plate, and the first dielectric material layer constitutes part of the dielectric layer.

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