Semiconductor device and method for manufacturing the same
By forming trench structures and recesses on the substrate of semiconductor devices and depositing polysilicon gates, the polysilicon residues and insufficient CD process windows in the transition areas of high-voltage and medium-voltage devices are solved, and a more efficient etching process is achieved and more efficient Competitive products.
Patent Information
- Application Number
- CN202411204248.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-30
- Publication Date
- 2024-12-27
- Estimated Expiration
- 2044-08-30
AI Technical Summary
During semiconductor manufacturing, the problems of polysilicon residues in the transition areas of high-voltage and medium-voltage devices and insufficient CD process windows make it difficult to achieve overetching processes, and it is easy to have the risk of insufficient overetching or insufficient process windows, especially at process nodes The smaller the problem is more obvious.
By forming a trench structure and isolation oxide layer on the substrate, and depositing a polysilicon gate in the depression, the polysilicon layer on the substrate is removed by using a dry etching process to form a sinking polysilicon gate, reducing the device The step height of the interval avoids polysilicon residue and ensures sufficient CD process window.
It effectively reduces the problem of polysilicon residue and insufficient CD process window, reduces the demand for overetch, improves process compatibility and economic benefits, and at the same time reduces the device size and enhances product competitiveness.
Smart Images
Figure CN118712131B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the same. Background Art
[0002] With the vigorous development of semiconductor manufacturing technology, the requirements for chip component density and integration are constantly increasing, and it is necessary to integrate multiple circuits on a single chip at the same time. These circuits need to rely on multiple MOS (Metal-Oxide-Semiconductor) transistors with different operating voltages to realize their functions. For example, it is necessary to integrate three devices, low voltage (LV), medium voltage (MV) and high voltage (HV), on the same chip. As the operating voltage of MOS transistors continues to increase, in order to ensure that they are not broken down, the thickness of the gate oxide layer needs to be increased accordingly. Therefore, for the usual manufacturing process, there will be a large height difference between different areas formed by MOS transistors with different operating voltages, and this height difference will cause insurmountable difficulties to the processes such as photolithography and etching of polysilicon gates (Poly). For example, the step height on the STI (shallow trench isolation structure) in the transition area between high-voltage devices and medium-voltage devices is relatively large, resulting in a thicker film stack here when polysilicon is deposited. In the subsequent etching process, if the conventional OE (over-etching) process is used, the over-etching amount may be insufficient, which may easily lead to the generation of polysilicon residues; if the OE amount is increased, there may be a risk of insufficient CD (critical dimension) process window. Moreover, as the process node advances, the smaller the process node, the more obvious the above phenomenon (polysilicon residues and insufficient CD process window) will be. For example, the film stack at the step of the 40nm process node is thicker than that of the 55nm process node, and the phenomenon will be more obvious. Summary of the invention
[0003] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, so as to solve the problems of polysilicon residue and insufficient CD process window in the transition region between the first device region and the second device region.
[0004] In order to achieve the above object and other related objects, the present invention provides a method for preparing a semiconductor device, comprising the following steps:
[0005] Providing a substrate, the substrate comprising a first device region and a second device region adjacent to the first device region;
[0006] forming a trench structure in the substrate of the first device region and extending the trench structure into the substrate of the second device region;
[0007] forming an isolation oxide layer in the trench structure, and etching the isolation oxide layer in the first device region to form a recess, wherein the recess is adjacent to the second device region, and the length of the recess is greater than or equal to one eighth of the length of the trench structure;
[0008] A polysilicon gate is formed in the recess.
[0009] Optionally, in the method for preparing the semiconductor device, the process for forming the trench structure and the process for forming the recess are both dry etching processes.
[0010] Optionally, in the method for preparing the semiconductor device, the first device region is a high-voltage device region, and the second device region is a medium-voltage device region or a low-voltage device region.
[0011] Optionally, in the method for preparing the semiconductor device, the length of the trench structure is greater than or equal to 0.48 μm, and the depth of the trench structure is greater than or equal to 0.31 μm.
[0012] Optionally, in the method for preparing the semiconductor device, the thickness of the isolation oxide layer between the sidewall of the recess and the first device region is greater than or equal to 0.21 μm.
[0013] Optionally, in the method for preparing the semiconductor device, the length of the polysilicon gate is greater than or equal to 0.06 μm.
[0014] Optionally, in the method for preparing the semiconductor device, the thickness of the isolation oxide layer under the polysilicon gate is greater than or equal to the thickness required for the breakdown voltage of the first device region.
[0015] Optionally, in the method for preparing the semiconductor device, the step of forming a polysilicon gate in the recess includes:
[0016] Depositing a polysilicon layer in the recess, wherein the polysilicon layer is also deposited on the substrate of the first device region and the second device region;
[0017] The polysilicon layer on the substrate outside the recess is removed by an etching process to form a polysilicon gate.
[0018] Optionally, in the method for preparing the semiconductor device, the step of removing the polysilicon layer on the substrate outside the recess by an etching process includes:
[0019] forming an anti-reflective coating, wherein the anti-reflective coating covers the polysilicon layer;
[0020] forming a patterned photoresist layer, wherein the patterned photoresist layer covers the anti-reflective coating above the recess;
[0021] Using the patterned photoresist layer as a mask, an etching process is sequentially performed on the anti-reflective coating and the polysilicon layer to remove the anti-reflective coating and the polysilicon layer on the substrate outside the recess.
[0022] In order to achieve the above object and other related objects, the present invention also provides a semiconductor device prepared by the above-mentioned method for preparing a semiconductor device, comprising:
[0023] A substrate comprising a first device region and a second device region adjacent to the first device region;
[0024] a trench structure located in the substrate of the first device region and extending into the substrate of the second device region;
[0025] An isolation oxide layer, located in the trench structure;
[0026] a recess, located in the isolation oxide layer of the first device region and adjacent to the second device region, wherein the length of the recess is greater than or equal to one eighth of the length of the trench structure;
[0027] The polysilicon gate is located in the recess.
[0028] Compared with the prior art, the technical solution of the present invention has the following unexpected beneficial effects:
[0029] The method for preparing a semiconductor device provided by the present invention forms a sunken polysilicon gate in the first device area, and the polysilicon gate is adjacent to the second device area, so that the thickness of the thin film stack in the transition area between the second device area and the first device area is reduced, that is, the step height between the second device area and the first device area is reduced, so that in the subsequent over-etching process, it is not necessary to increase the over-etching amount additionally, so that polysilicon residue can be avoided, and at the same time, sufficient CD process window can be guaranteed, and it has excellent compatibility with existing processes. In addition, the device size of the semiconductor device of the present invention is reduced, and the product is more competitive.
[0030] In addition, the method for preparing the semiconductor device of the present invention is easier to implement than the current process, can reduce the complexity of the process, and can achieve significant economic benefits. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] Figure 1 It is a schematic diagram of a product structure after executing step S01 in a method for preparing a semiconductor device;
[0032] Figure 2 is a schematic diagram of a product structure after executing step S04 in a method for preparing a semiconductor device;
[0033] Figure 3 The present invention is a schematic diagram of the product structure after a polysilicon layer is deposited in a method for preparing a semiconductor device;
[0034] Figure 4 is a schematic diagram of a product structure after executing step S052 in a method for preparing a semiconductor device;
[0035] Figure 5 is a schematic diagram of a product structure after executing step S053 in a method for preparing a semiconductor device;
[0036] Figure 6 is a schematic diagram of a product structure after executing step S1 in a method for preparing a semiconductor device according to an embodiment of the present invention;
[0037] Figure 7 is a schematic diagram of a product structure after executing step S2 in a method for preparing a semiconductor device according to an embodiment of the present invention;
[0038] Figure 8 It is a schematic diagram of the product structure after forming an isolation oxide layer in a method for preparing a semiconductor device according to an embodiment of the present invention;
[0039] Fig. 9 is a schematic diagram of a product structure after executing step S3 in a method for preparing a semiconductor device according to an embodiment of the present invention;
[0040] Fig.10 is a schematic diagram of a product structure after executing step S41 in a method for preparing a semiconductor device according to an embodiment of the present invention;
[0041] Fig.11 is a schematic diagram of a product structure after executing step S42 in a method for preparing a semiconductor device according to an embodiment of the present invention;
[0042] Figures 1 to 5 middle:
[0043] 01-substrate, 02-substrate oxide layer, 03-shallow trench isolation structure, 04-gate oxide layer, 05-polysilicon layer, 051-polysilicon residue, 06-anti-reflective coating, 07-patterned photoresist layer;
[0044] Figures 6 to 11 middle,
[0045] 10 - substrate, 20 - substrate oxide layer, 30 - trench structure, 40 - isolation oxide layer, 50 - recess, 60 - polysilicon gate, 60a - polysilicon layer. DETAILED DESCRIPTION
[0046] The semiconductor device and the method for manufacturing the same proposed by the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.
[0047] See also Figures 1 to 5 , a method for preparing a semiconductor device may include the following steps:
[0048] Step S01: providing a substrate 01, wherein the substrate 01 comprises a first device region and a second device region adjacent to the first device region;
[0049] Step S02: forming a shallow trench isolation structure 03 in a transition region between the first device region and the second device region;
[0050] Step S03: forming a gate oxide layer 04 on the substrate 01 and the shallow trench isolation structure 03;
[0051] Step S04: performing a first etching process to remove the gate oxide layer 04 of the second device region and remove a portion of the thickness of the shallow trench isolation structure 03 of the second device region to expose the substrate 01 and the shallow trench isolation structure 03 of the second device region;
[0052] Step S05: depositing a polysilicon layer 05 on the gate oxide layer 04 and the exposed substrate 01 and shallow trench isolation structure 03, and performing a second etching process to remove the polysilicon layer 05 in the second device region.
[0053] In step S01 , the first device region is an HV region (high voltage region), and the second device region is an MV region (medium voltage region).
[0054] In step S02 , the upper surface of the shallow trench isolation structure 03 is formed to be slightly higher than the upper surface of the substrate 01 .
[0055] Before executing step S02 , the preparation method may further include: forming a substrate oxide layer 02 on the substrate 01 .
[0056] In step S04, after removing the gate oxide layer 04 of the second device region, a portion of the thickness of the shallow trench isolation structure 03 is also removed so that the second device region can meet the process requirements. After step S04, there is a height difference between the surface of the gate oxide layer 04 on the shallow trench isolation structure of the first device region and the surface of the shallow trench isolation structure 03 exposed in the second device region, that is, an initial step is formed, and the initial step height h1 is greater than 100nm, which will cause the thin film stack at the step to be relatively thick when the polysilicon layer 05 is deposited.
[0057] In step S05, the second etching process may include:
[0058] Step S051: forming an anti-reflection coating 06, wherein the anti-reflection coating 06 covers the polysilicon layer 05;
[0059] Step S052: forming a patterned photoresist layer 07, wherein the patterned photoresist layer 07 covers the anti-reflective coating layer 06 in the first device region;
[0060] Step S053: Using the patterned photoresist layer 07 as a mask, the anti-reflective coating 06 and the polysilicon layer 05 are sequentially etched to remove the anti-reflective coating 06 and the polysilicon layer 05 of the second device region. The etching process of this step includes main etching and OE (over-etching). Since the step height h1 is relatively large, the thin film stack at the step is relatively thick when the polysilicon layer 05 is deposited. If conventional over-etching is used, the problem of insufficient over-etching will occur, which is likely to cause the generation of polysilicon residues 051. If the over-etching amount is increased additionally, there may be a risk of insufficient CD (critical dimension) process window.
[0061] In order to solve the problem of polysilicon residue or insufficient process window caused by the excessively high step height of the thin film in the transition area between the first device area and the second device area, the present invention provides a method for preparing a semiconductor device. Figures 6 to 11 , the method for preparing the semiconductor device may include the following steps:
[0062] Step S1: providing a substrate 10, wherein the substrate 10 comprises a first device region and a second device region adjacent to the first device region;
[0063] Step S2: forming a trench structure 30 in the substrate 10 in the first device region and extending the trench structure 30 into the substrate 10 in the second device region;
[0064] Step S3: forming an isolation oxide layer 40 in the trench structure 30, and etching the isolation oxide layer 40 in the first device region to form a recess 50, wherein the recess 50 is adjacent to the second device region, and the length of the recess 50 is greater than or equal to one eighth of the length of the trench structure 30;
[0065] Step S4 : forming a polysilicon gate in the recess 50 .
[0066] See also Figure 6 , perform step S1, and provide a substrate 10. In this embodiment, the substrate 10 may include a first device region and a second device region, and the second device region is adjacent to the first device region. The first device region may be a high voltage device region (HV region), and the second device region may be a medium voltage device region (MV region) or a low voltage device region (LV region). For example Figure 6 In the embodiment, the first device region is the HV region, and the second device region is the MV region. The substrate 10 may be one of single crystal silicon, polycrystalline silicon, and amorphous silicon. The substrate 10 may also be gallium arsenide, silicon gallium compound, etc. The substrate 10 may also have a silicon on insulating layer or an epitaxial layer on silicon structure. The substrate 10 may also be other semiconductor materials, which are not listed here. The first device region and the second device region are on the same wafer and are adjacent to each other.
[0067] In this embodiment, before performing step S2, the method for preparing the semiconductor device may further include: forming a substrate oxide layer 20 on the substrate 10. The substrate oxide layer 20 covers the entire upper surface of the substrate 10. The material of the substrate oxide layer 20 is preferably SiO2, but is not limited thereto. The substrate oxide layer 20 serves to isolate and protect the substrate 10, and the thickness of the substrate oxide layer 20 can be a conventionally set thickness, for example, 100Å~120Å.
[0068] See also Figure 7, perform step S2 to form a trench structure 30. In this embodiment, the number of the trench structure 30 is preferably one. The method for forming the trench structure 30 is preferably etching, and further preferably dry etching. The trench structure 30 is located in the substrate 10 of the first device region and extends to the substrate 10 of the second device region, and its length is preferably greater than or equal to 0.48μm. Further, the length of the trench structure 30 in the first device region is preferably greater than or equal to 0.27μm, and the length of the trench structure 30 extending to the second device region is preferably greater than or equal to 0.21μm, so as to ensure that the isolation oxide layer 40 formed subsequently has sufficient width, plays a relatively good isolation effect, and enables the polysilicon gate 60 to meet the requirements of the first device region. The depth of the trench structure 30 is preferably greater than or equal to 0.31μm, so as to ensure that the isolation oxide layer 40 formed subsequently has sufficient thickness, plays a relatively good isolation effect, and can also play the role of a shallow trench isolation structure together with the isolation oxide layer 40, and can also reduce the step height of the transition area between the first device region and the second device region. Furthermore, the depth of the trench structure 30 in the present embodiment can be set according to the thickness of the isolation oxide layer 40 below the recess 50 and the thickness of the polysilicon gate 60, and the length of the trench structure 30 in the present embodiment can be set according to the length of the polysilicon gate 60 and the thickness of the isolation oxide layer 40 on the side wall of the recess 50, and the setting of the trench structure 30 will not affect the functional effects of the first device area and the second device area.
[0069] See also Figure 8 , perform step S3 to form an isolation oxide layer 40 in the trench structure 30. The formation process of the isolation oxide layer 40 can be a thermal oxidation process or ALD (atomic layer deposition), but is not limited thereto. In this step, the isolation oxide layer 40 fills the trench structure 30. The material of the isolation oxide layer 40 is preferably SiO2, but is not limited thereto. The morphology of SiO2 in the trench structure 30 is preferably different from the morphology of SiO2 in the substrate oxide layer 20.
[0070] See also Fig. 9, after forming the isolation oxide layer 40, the isolation oxide layer 40 in the first device region is etched to form a recess 50. The etching process of this step is preferably a dry etching process, but is not limited thereto. In the present embodiment, the thickness of the isolation oxide layer 40 below the recess 50 (i.e., below the polysilicon gate) is preferably greater than or equal to the thickness required for the breakdown voltage of the first device region, and the thickness of the isolation oxide layer 40 between the sidewall of the recess 50 and the first device region is preferably greater than or equal to 0.21 μm to ensure the isolation effect between the polysilicon gate and the first device region and avoid breakdown. The thickness of the isolation oxide layer 40 between the sidewall of the recess 50 and the second device region is preferably greater than or equal to 0.21 μm to ensure the isolation effect between the polysilicon gate and the second device region. Further, the thickness of the isolation oxide layer 40 between the sidewall of the recess 50 and the second device region can be equal to the width of the shallow trench structure in the second device region in the prior art, the thickness of the isolation oxide layer 40 between the sidewall of the recess 50 and the first device region is equal to the thickness of the isolation oxide layer 40 between the sidewall of the recess 50 and the second device region, the thickness of the isolation oxide layer 40 below the recess 50 can be equal to the thickness required for the breakdown voltage of the first device region, and the length and depth of the recess 50 can be set according to the length and depth of the polysilicon gate required by the first device region. In this embodiment, the recess is only located in the first device region and is adjacent to the second device region, so that the polysilicon gate formed subsequently is adjacent to the second device region. That is, the isolation oxide layer 40 in the second device region will not be etched.
[0071] Executing step S4 to form a polysilicon gate 60 in the recess 50 may specifically include:
[0072] Step S41: depositing a polysilicon layer 60a in the recess 50, wherein the polysilicon layer 60a is also deposited on the substrate 10 in the first device region and the second device region;
[0073] Step S42 : removing the polysilicon layer 60 a on the substrate 10 outside the recess 50 by an etching process to form a polysilicon gate 60 .
[0074] See also Fig.10 , perform step S41 to form a polysilicon layer 60a. In this embodiment, the process for forming the polysilicon layer 60a may be a chemical deposition process, but is not limited thereto. In this embodiment, the polysilicon layer 60a is formed by depositing a polysilicon material, and the polysilicon layer 60a covers both the first device region and the second device region. Specifically, the polysilicon layer 60a covers the isolation oxide layer 40 and extends to cover the exposed substrate 10.
[0075] See also Fig.11, perform step S42, remove the polysilicon layer on the substrate outside the recess 50, specifically remove the polysilicon layer on the substrate of the second device region and part of the first device region. The step of removing the polysilicon layer on the substrate of the second device region by etching may include:
[0076] Step S421: forming an anti-reflective coating, wherein the anti-reflective coating covers the polysilicon layer;
[0077] Step S422: forming a patterned photoresist layer, wherein the patterned photoresist layer covers the anti-reflective coating above the recess 50;
[0078] Step S423 : using the patterned photoresist layer as a mask, sequentially performing an etching process on the anti-reflective coating layer and the polysilicon layer to remove the anti-reflective coating layer and the polysilicon layer outside the recess 50 .
[0079] Step S421 is executed to form an anti-reflective coating. The anti-reflective coating completely covers the polysilicon layer. The anti-reflective coating widely used in advanced semiconductor manufacturing processes is a silicon-based polymer, which is in liquid state and is formed by high-temperature curing after spin coating. The anti-reflective coating plays a certain anti-reflective role, can further reduce reflected light, help the exposure process, and ensure that the size of the pattern in the photoresist layer is consistent with the mask.
[0080] Step S422 is performed to form a patterned photoresist layer. Specifically, a photoresist material is spin-coated on the anti-reflective coating, soft-baked, exposed, baked, and developed to form a patterned photoresist layer, and the pattern in the photoresist layer exposes the anti-reflective coating. In this embodiment, the patterned photoresist layer covers the anti-reflective coating above the recess 50, exposing the anti-reflective coating on the substrate outside the recess 50.
[0081] Step S423 is performed, and the anti-reflective coating and the polysilicon layer are sequentially etched with the patterned photoresist layer as a mask to remove the anti-reflective coating and the polysilicon layer outside the recess 50, so as to form a polysilicon gate 60. The specific process may be: the anti-reflective coating is dry-etched with the patterned photoresist layer as a mask to form a patterned anti-reflective coating; then, the polysilicon layer is dry-etched with the patterned anti-reflective coating as a mask to form a polysilicon gate 60. In this embodiment, the etching of the polysilicon layer may include main etching and over-etching. Since the sunken polysilicon gate is formed in the first device region in this embodiment, the thickness of the thin film stack in the transition region between the first device region and the second device region is reduced, and conventional over-etching will not cause polysilicon residue in the subsequent over-etching process, and the problem of insufficient CD process window due to additional over-etching amount can also be avoided.
[0082] In this embodiment, while removing the polysilicon layer 60a in the second device region, the polysilicon layer 60a outside the recess in the first device region may also be removed.
[0083] In this embodiment, the polysilicon gate 60 is only located in the first device area, and the length of the polysilicon gate 60 is greater than or equal to one eighth of the length of the trench structure. Furthermore, the length of the polysilicon gate 60 can be specifically set according to the gate length requirement of the first device area, preferably greater than or equal to 0.06μm. The thickness of the polysilicon gate 60 can be set according to the gate thickness requirement of the first device area. The upper surface of the polysilicon gate 60 of this embodiment can be lower than the upper surface of the substrate of the second device area, or higher than the upper surface of the substrate of the second device area, or flush with the upper surface of the substrate of the second device area. Preferably, the upper surface of the polysilicon gate 60 is flush with the upper surface of the substrate of the second device area, that is, the polysilicon gate 60 just fills the recess 50.
[0084] In order to avoid polysilicon residue, the prior art generally increases the over-etching amount, which inevitably leads to the problem of insufficient CD process window, and the larger the additional over-etching amount, the larger the CD value. Compared with the prior art, the over-etching amount of the over-etching in this embodiment can be the amount commonly used in the semiconductor manufacturing process, and there is no need to increase the over-etching amount, which can avoid the appearance of polysilicon residue and ensure a sufficient CD process window.
[0085] In this embodiment, the method for preparing the semiconductor device may further include: removing the patterned photoresist layer and the patterned anti-reflective coating. In this embodiment, the step of removing the patterned photoresist layer and the patterned anti-reflective coating may be performed after the step of forming the polysilicon gate 60, or the step of removing the patterned photoresist layer may be performed after the step of forming the patterned anti-reflective coating, and the step of removing the patterned anti-reflective coating may be performed after the step of forming the polysilicon gate 60.
[0086] In summary, the method for preparing a semiconductor device provided by the present invention forms a sunken polysilicon gate in the first device region, so that the thickness of the thin film stack in the transition region between the second device region and the first device region is reduced, that is, the step height between the second device region and the first device region is reduced, so that in the subsequent over-etching process, it is not necessary to increase the over-etching amount additionally, so that polysilicon residue can be avoided, and sufficient CD process window can be ensured at the same time. Moreover, the device size of the semiconductor device of the present invention is reduced, and the product is more competitive.
[0087] Moreover, compared with the current process, the preparation method of the semiconductor device of the present invention is easier to implement, can reduce the complexity of the process, can achieve obvious economic benefits, and can effectively improve the device mismatch phenomenon caused by process program changes, increase the process manufacturing window, and has excellent compatibility with existing processes.
[0088] In addition, the present invention also provides a semiconductor device, which is prepared by the above-mentioned method for preparing a semiconductor device. Specifically, the semiconductor device may include:
[0089] A substrate 10, wherein the substrate 10 includes a first device region and a second device region adjacent to the first device region;
[0090] A trench structure 30, wherein the trench structure 30 is located in the substrate 10 of the first device region and extends into the substrate 10 of the second device region;
[0091] An isolation oxide layer 40 is located in the trench structure 30;
[0092] A recess 50 is located in the isolation oxide layer 40 of the first device region and is adjacent to the second device region, and the length of the recess 50 is greater than or equal to one eighth of the length of the trench structure 30;
[0093] The polysilicon gate 60 is located in the recess 50 .
[0094] The semiconductor device of this embodiment may further include a substrate oxide layer 20 . The substrate oxide layer 20 covers the upper surface of the substrate 10 to protect the substrate 10 .
[0095] The semiconductor device of the present invention may be an LCD driver, but is not limited thereto. The semiconductor device provided by the present invention forms a sunken polysilicon gate in the first device region, so that the thickness of the thin film stack in the transition region between the second device region and the first device region is reduced, that is, the step height between the second device region and the first device region is reduced, so that in the subsequent over-etching process, it is not necessary to increase the over-etching amount additionally, so that polysilicon residue can be avoided, and sufficient CD process window can be ensured at the same time. At the same time, the device size of the semiconductor device is reduced, and the product is more competitive.
[0096] In addition, it is understood that although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.
[0097] It should also be understood that the present invention is not limited to the specific methods, compounds, materials, manufacturing techniques, usages and applications described herein, which may vary. It should also be understood that the terms described herein are only used to describe specific embodiments, rather than to limit the scope of the present invention. It must be noted that the singular forms "one", "a kind" and "the" used herein and in the appended claims include plural references unless the context clearly indicates the opposite meaning. Thus, for example, a reference to "a step" means a reference to one or more steps, and may include secondary steps. All conjunctions used should be understood in the broadest sense. Therefore, the word "or" should be understood to have the definition of a logical "or", rather than a logical "exclusive or", unless the context clearly indicates the opposite meaning. The structure described herein will be understood to also quote the functional equivalent of the structure. Language that can be interpreted as approximate should be understood as such, unless the context clearly indicates the opposite meaning.
Claims
1. A method for preparing a semiconductor device, characterized in that: The following steps are involved: Providing a substrate, the substrate comprising a first device region and a second device region adjacent to the first device region, the first device region is a high voltage device region, and the second device region is a medium voltage device region or a low voltage device region; forming a trench structure in the substrate of the first device region and extending the trench structure into the substrate of the second device region; forming an isolation oxide layer in the trench structure, and etching the isolation oxide layer in the first device region to form a recess, wherein the recess is adjacent to the second device region, and the length of the recess is greater than or equal to one eighth of the length of the trench structure; A polysilicon gate is formed in the recess.
2. The method for preparing a semiconductor device according to claim 1, wherein: The process for forming the groove structure and the process for forming the recess are both dry etching processes.
3. The method for preparing a semiconductor device according to claim 1, wherein: The length of the groove structure is greater than or equal to 0.48 μm, and the depth of the groove structure is greater than or equal to 0.31 μm.
4. The method for preparing a semiconductor device according to claim 1, wherein: The thickness of the isolation oxide layer between the sidewall of the recess and the first device region is greater than or equal to 0.21 μm.
5. The method for preparing a semiconductor device according to claim 1, wherein: The length of the polysilicon gate is greater than or equal to 0.06 μm.
6. The method for preparing a semiconductor device according to claim 1, wherein: The thickness of the isolation oxide layer under the polysilicon gate is greater than or equal to the thickness required for the breakdown voltage of the first device region.
7. The method for preparing a semiconductor device according to claim 1, wherein: The step of forming a polysilicon gate in the recess comprises: Depositing a polysilicon layer in the recess, wherein the polysilicon layer is also deposited on the substrate of the first device region and the second device region; The polysilicon layer on the substrate outside the recess is removed by an etching process to form a polysilicon gate.
8. The method for preparing a semiconductor device according to claim 7, wherein: The step of removing the polysilicon layer on the substrate outside the recess by etching process comprises: forming an anti-reflective coating, wherein the anti-reflective coating covers the polysilicon layer; forming a patterned photoresist layer, wherein the patterned photoresist layer covers the anti-reflective coating above the recess; Using the patterned photoresist layer as a mask, an etching process is sequentially performed on the anti-reflective coating and the polysilicon layer to remove the anti-reflective coating and the polysilicon layer on the substrate outside the recess.
9. A semiconductor device manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 8, characterized in that: include: A substrate, comprising a first device region and a second device region adjacent to the first device region, wherein the first device region is a high voltage device region, and the second device region is a medium voltage device region or a low voltage device region; a trench structure located in the substrate of the first device region and extending into the substrate of the second device region; An isolation oxide layer, located in the trench structure; a recess, located in the isolation oxide layer of the first device region and adjacent to the second device region, wherein the length of the recess is greater than or equal to one eighth of the length of the trench structure; The polysilicon gate is located in the recess.