Silicon carbide power device terminal structure and manufacturing method thereof

Abstract

The present invention discloses a silicon carbide power device terminal structure and a manufacturing method thereof, wherein the silicon carbide power device terminal structure comprises a silicon carbide substrate, a silicon carbide epitaxial layer, a first conductive type doped region, an upper mesa, a lower mesa, a dielectric layer, an anode electrode and a cathode electrode. N upper mesas and lower mesas distributed at intervals are formed in the device terminal region, and the dielectric layer is filled in all the upper mesas and lower mesas. By controlling the dielectric distribution at different depth positions in the terminal region, the electric field distribution at the edge of the main junction is effectively modulated while significantly reducing the area of ​​the terminal region and thus reducing the chip area, thereby reducing the peak electric field near the main junction and ensuring the voltage resistance of the device. The present invention also discloses a manufacturing method of the device structure.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a silicon carbide power device terminal structure and a manufacturing method thereof. Background Art

[0002] Due to its larger bandgap, higher electron saturation drift velocity, stronger radiation resistance, higher breakdown electric field and thermal conductivity, SiC materials have considerable application prospects in the fields of new energy vehicles, rail transportation, aerospace systems, military electronic communication systems, etc. At present, power devices such as SiC diodes and SiC metal oxide semiconductor field effect transistors (MOSFETs) have been widely used in many fields.

[0003] The withstand voltage design of power devices includes two parts: active area design and terminal area design. Since the terminals of power devices are often spherical junctions or cylindrical junctions, if a special terminal structure design is not performed, the curvature effect will cause the breakdown voltage of the terminal area to be much lower than the breakdown voltage of the parallel plane junction in the cell area, causing the actual withstand voltage of the device to be much lower than the design value.

[0004] Common terminal structures for power devices include field limiting rings, field plates, and junction terminal extension structures. Field plate structures have been widely used in Si power devices. However, the critical breakdown field strength of SiC is much greater than that of Si, which means that the oxide layer in SiC power devices often breaks down prematurely. Therefore, surface depletion under the field plate cannot fully occur, and the protection effect cannot be fully reflected. The junction terminal extension structure is formed by an ion implantation process, forming one or more layers of the same type of doping region near the main junction to expand the main junction depletion region and ensure the device withstand voltage. However, the junction terminal extension structure is very sensitive to the ion implantation dose and interface charge. A slight difference will cause a sudden drop in withstand voltage, so the process window is very narrow.

[0005] At present, the common terminal design of SiC power devices is the field limiting ring structure, such as Figure 3 As shown. The structure forms N doping regions with the same doping type as the main junction and distributed at intervals in the terminal region 102 to achieve the purpose of expanding the main junction depletion region and reducing the peak electric field borne by the main junction. The process cost of the field limiting ring structure is low and the process window is relatively large, but there are also two problems. First, the chip area occupied by the structure is large. According to the different voltage levels, the number of field limiting rings ranges from more than ten to dozens, and the spacing between adjacent field limiting rings is generally increasing. Therefore, the chip area occupied by the entire field limiting ring structure is quite large. Second, the structure is more sensitive to interface charges, and the charge density of the SiC / SiO2 interface is 2 to 3 orders of magnitude higher than that of the Si / SiO2 interface. Therefore, the withstand voltage effect of the field limiting ring is often not as expected. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the terminal structure of SiC power devices, the present invention provides a terminal structure of silicon carbide power devices and a manufacturing method thereof. The purpose of the present invention is to achieve stable maintenance of the withstand voltage of the terminal area while minimizing the chip area of ​​the terminal area.

[0007] A silicon carbide power device terminal structure, comprising:

[0008] cathode electrode;

[0009] A silicon carbide substrate located on the cathode electrode, and a silicon carbide epitaxial layer located on the silicon carbide substrate;

[0010] A first conductivity type doped region located in the silicon carbide epitaxial layer;

[0011] N upper mesas distributed at intervals and penetrating the first conductive type doped region and extending into the silicon carbide epitaxial layer;

[0012] N lower mesas are located in the silicon carbide epitaxial layer and are spaced apart and connected to the upper mesas one by one; there are N upper mesas and N lower mesas; the width of the lower mesas is greater than the width of the upper mesas, and the difference between the two is 0.1µm to 1.0µm;

[0013] Completely fill the dielectric layer of the upper and lower surfaces;

[0014] An anode electrode located on one side of and above the dielectric layer.

[0015] A method for manufacturing a silicon carbide power device terminal structure, used for manufacturing the above-mentioned silicon carbide power device terminal structure, comprises the following steps:

[0016] Step 1, forming a silicon carbide epitaxial layer on a silicon carbide substrate;

[0017] Step 2, forming a first conductivity type doped region in the silicon carbide epitaxial layer;

[0018] Step 3, etching to form N upper mesas that penetrate the first conductive type doping region and extend into the silicon carbide epitaxial layer and are spaced apart from each other;

[0019] Step 4, etching in the silicon carbide epitaxial layer to form N lower mesas connected one by one with the bottoms of the N upper mesas; the width of the lower mesas is greater than the width of the upper mesas, and the difference between the two is 0.1µm to 1.0µm;

[0020] Step 5, forming a dielectric layer that completely fills the lower table and the upper table;

[0021] Step 6: grow an anode electrode on the first conductive type doping region and on one side and on the dielectric layer, and grow a cathode electrode on the bottom of the silicon carbide substrate.

[0022] The present invention adopts the above technical solution and has the following beneficial effects:

[0023] The present invention forms N spaced and connected upper and lower mesas in the terminal area, and fills the upper and lower mesas with dielectric layers, which greatly saves the chip area of ​​the terminal area compared to the traditional field-limiting ring terminal structure. The upper and lower mesas with different widths can construct different dielectric structures at different depths of the device, greatly alleviating the electric field concentration caused by the cylindrical junction or the spherical junction, and ensuring that the device withstand voltage meets the design target. The terminal protection structure proposed by the present invention is less affected by the interface charge, and the protective effect on the device withstand voltage is stable. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is a schematic diagram of the terminal structure of the silicon carbide power device of Example 1;

[0025] Figure 2 This is a schematic diagram of the terminal structure of the silicon carbide power device of Example 2;

[0026] Figure 3 This is a schematic diagram of the field limiting ring terminal structure of a silicon carbide power device commonly used in the prior art;

[0027] Figure 4~Figure 9 This is a schematic diagram of the preparation process of the silicon carbide power device terminal structure of Example 1;

[0028] Explanation of the reference numerals: 1. cathode electrode; 2. silicon carbide substrate; 3. silicon carbide epitaxial layer; 4. lower table; 5. upper table; 6. first conductive type doped region; 7. dielectric layer; 8. anode electrode; 9. passivation layer; 10. main junction; 11. field limiting ring; 101. main junction region; 102. terminal region. DETAILED DESCRIPTION

[0029] The present invention is further described below in conjunction with examples. The examples are only used to illustrate the present invention and do not constitute a limitation on the scope of the claims. Other alternative means that can be thought of by those skilled in the art are all within the scope of the claims of the present invention.

[0030] In addition, in the description of the present invention, it should be noted that the terms "central", "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance. Example 1

[0031] like Figure 1 As shown, a silicon carbide power device terminal structure of this embodiment includes:

[0032] Cathode electrode 1;

[0033] A silicon carbide substrate 2 is located on the cathode electrode 1, and a silicon carbide epitaxial layer 3 is located on the silicon carbide substrate 2. In this embodiment, the silicon carbide substrate 2 is a 4H-SiC substrate, the silicon carbide epitaxial layer 3 is a 4H-SiC epitaxial layer, and the doping concentration of the silicon carbide substrate 2 is 1e19cm -3 ~ 5e20cm -3 ; The doping concentration of the silicon carbide epitaxial layer 3 is 1e15cm -3 ~ 1e17cm -3 In other embodiments of the present invention, the silicon carbide substrate 2 and the silicon carbide epitaxial layer 3 are made of the same material, and the semiconductor material used may be 3C-SiC, 4H-SiC or 6H-SiC.

[0034] The first conductive type doping region 6 is located in the silicon carbide epitaxial layer 3, and the depth of the first conductive type doping region 6 ranges from 0.5µm to 1.3µm, and the doping concentration is 1e17cm -3 ~ 5e18cm -3 ;

[0035] N upper mesas 5 that are spaced apart and extend through the first conductive type doping region 6 and into the silicon carbide epitaxial layer 3, wherein the width of the upper mesas 5 ranges from 0.5µm to 2.0µm, and the depth of the upper mesas 5 ranges from 0.7µm to 2.5µm;

[0036] N lower terraces 4 are located in the silicon carbide epitaxial layer 3 and are distributed at intervals and connected to the upper terraces 5 one by one. The depth of the lower terraces ranges from 0.2µm to 1.5µm, and the width of the lower terraces ranges from 0.2µm to 2.5µm. There are N upper terraces and N lower terraces, and the value range of N is 3 to 50, which is a natural number.

[0037] A dielectric layer 7 located on the silicon carbide epitaxial layer 3 and between the upper mesa 5 and the lower mesa 4, wherein the dielectric layer 7 completely covers the upper mesa 5 and the lower mesa 4;

[0038] An anode electrode 8 is located on one side of and above the dielectric layer 7 .

[0039] The upper mesa closest to the active region, i.e., the main junction region 101, is the first upper mesa, the lower mesa closest to the active region is the first lower mesa, the upper mesa second closest to the active region is the second upper mesa, the lower mesa second closest to the active region is the second lower mesa, and so on, the upper mesa farthest from the active region is the Nth upper mesa, and the lower mesa farthest from the active region is the Nth lower mesa. The distance between the first upper mesa and the second upper mesa is D 11 , the distance between the first lower table and the second lower table is D 12 , the distance between the second upper table and the third upper table is D 21 , the distance between the second lower table surface and the second lower table surface is D 22 , and so on, the distance between the N-1th upper table and the Nth upper table is D （N-1）1 , the distance between the N-1th lower table and the Nth lower table is D （N-1）2 . D 11 , D 21 Even D （N-1）1 The size range is 0.5µm ~ 2.5µm, D 12 , D 22 Even D （N-1）2 The size range is 0.3µm ~ 3.0µm. 11 , D 21 Even D （N-1）1 The values ​​of D can be the same or different. 12 , D 22 Even D （N-1）2 The values ​​of can be the same or different.

[0040] A method for manufacturing a terminal structure of a silicon carbide power device in this embodiment is as follows: Figure 4~Figure 9 The specific process steps shown are described, including the following steps:

[0041] Step 1: forming a silicon carbide epitaxial layer 3 on a silicon carbide substrate 2; Figure 4 As shown, a silicon carbide epitaxial layer 3 is formed on a silicon carbide substrate 2 by epitaxial growth, and the doping concentration of the silicon carbide epitaxial layer 3 is 1e15cm -3 ~ 1e17cm -3 ;

[0042] Step 2: forming a first conductivity type doping region 6 in the silicon carbide epitaxial layer 3; Figure 5As shown, a patterned ion implantation mask layer is formed on the surface of the device prepared in step 1 by chemical vapor deposition, photolithography and etching processes, and ions are implanted into the device surface by using the ion implantation mask layer to form a first conductive type doping region 6 in the silicon carbide epitaxial layer 3. The depth of the first conductive type doping region 6 ranges from 0.5µm to 1.3µm, and the doping concentration is 1e17cm -3 ~5e18cm -3 , and then removing the ion implantation mask layer.

[0043] Step 3, forming N upper mesas 5 which penetrate the first conductive type doping region 6 and extend into the silicon carbide epitaxial layer 3 and are spaced apart from each other; Figure 6 As shown, a patterned etching mask layer is formed on the surface of the device prepared in step 2 by chemical vapor deposition, photolithography and etching processes, and the silicon carbide epitaxial layer 3 is etched by inductively coupled plasma using the patterned etching mask layer. The etching characteristic is anisotropy, forming N upper mesas 5 distributed at intervals, the width of the upper mesas 5 ranges from 0.5µm to 2.0µm, the depth of the upper mesas 5 ranges from 0.7µm to 2.5µm, and the spacing between adjacent upper mesas 5 can be the same or different, but the spacing ranges from 0.5µm to 2.5µm; wherein, the etching process can adopt an ICP (Inductive Coupled Plasma, inductively coupled plasma) etching process, and the etching gas adopted can be one or more combinations of gases such as SF6, HBr, Cl2, O2, Ar, etc., and the etching characteristic is anisotropy.

[0044] Step 4: forming N lower terraces 4 in the silicon carbide epitaxial layer 3, which are connected to the bottoms of the N upper terraces 5 one by one; Figure 7 As shown, the bottom of the upper table 5 formed in step 3 is etched by inductively coupled plasma, and the etching characteristic is isotropic, so as to form N lower table 4 connected with the upper table 5, and the spacing between adjacent lower table 4 can be the same or different, but the spacing ranges from 0.3µm to 2.0µm, the depth ranges from 0.2µm to 1.5µm, and the width ranges from 0.7µm to 2.5µm; wherein, the etching process can adopt ICP (Inductive Coupled Plasma, inductively coupled plasma) etching process, and the etching gas adopted can be one or more combinations of gases such as SF6, HBr, Ar, etc., and the etching characteristic is isotropic or anisotropic.

[0045] Step 5, forming a dielectric layer 7 located on the first conductive type doping region 6 and completely filling the lower mesa 4 and the upper mesa 5; Figure 8As shown, a dielectric layer 7 is formed on the surface of the device prepared in step 4 by a chemical vapor deposition process or a spin coating process, and the dielectric layer 7 is located on the first conductive type doping region 6 and completely fills the lower table 4 and the upper table 5; the dielectric constant of the dielectric layer 7 is determined by the depth and width of the upper table 5 and the lower table 4, and the greater the depth and the smaller the width of the upper table 5 and the lower table 4, the smaller the dielectric constant of the dielectric layer 7. Specifically, when the depth of the upper table 5 and the lower table 4 is greater than 1μm and the width is less than 1μm, the dielectric constant of the dielectric layer 7 can be less than 30, and the dielectric layer 7 completely fills the upper table 5 and the lower table 4; in this embodiment, the material of the dielectric layer 7 is selected from Al2O3. In other embodiments of the present application, the material of the dielectric layer can be one of SiO2, Si3N4, Al2O3, HfO2, HfSiON, AlON, TiN, TaN and the like.

[0046] Step 6: growing an anode electrode 8 on the first conductive type doping region 6 and on one side and on the dielectric layer 7, and growing a cathode electrode 1 on the bottom of the silicon carbide substrate 2; Fig. 9 As shown, an anode electrode 8 is grown on the first conductive type doping region 6 and on one side and on the dielectric layer 7, and the anode electrode 8 covers the first conductive type doping region 6, and a cathode electrode 1 is grown on the bottom of the silicon carbide substrate 2 to complete the electrode preparation. The electrode materials of the anode electrode 8 and the cathode electrode 1 can be one or more combinations of metals such as Ti, Al, Ni, and Pt.

[0047] In this embodiment, the first conductivity type is P type or N type. Example 2

[0048] A silicon carbide power device terminal structure of this embodiment, such as Figure 2 As shown, the difference from Example 1 is that the dielectric layer 7 is filled in the upper table 5 and the lower table 4, a passivation layer 9 is formed on the silicon carbide epitaxial layer 3, the passivation layer 9 covers the dielectric layer 7 and the silicon carbide epitaxial layer 3 between the adjacent upper table 5, and an anode electrode 8 is grown on the first conductive type doped region 6 and on one side and on the passivation layer 9; the material of the passivation layer 9 is Si3N4, which can further improve the isolation effect. In other embodiments of the present invention, the passivation layer material can be silicon oxide, silicon nitride, borophosphosilicate glass, aluminum oxide, sapphire or hafnium oxide.

[0049] In the manufacturing method of this embodiment, steps 1 to 4 refer to those of embodiment 1, except that:

[0050] Step 5, forming a dielectric layer 7 that completely fills the lower table 4 and the upper table 5, and forming a passivation layer 9 on the dielectric layer 7 and the silicon carbide epitaxial layer 3 between the adjacent upper table 5 by chemical vapor deposition process; the specific process of forming the dielectric layer refers to step 5 of Example 1.

[0051] Step 6, growing an anode electrode 8 on the first conductive type doping region 6 and on one side and on the passivation layer 9, and growing a cathode electrode 1 on the bottom of the silicon carbide substrate 2; for the specific process, refer to step 6 of embodiment 1.

[0052] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. A silicon carbide power device terminal structure, characterized in that: include: cathode electrode; A silicon carbide substrate located on the cathode electrode, and a silicon carbide epitaxial layer located on the silicon carbide substrate; A first conductivity type doped region located in the silicon carbide epitaxial layer; the first conductivity type is P type or N type; N upper mesas distributed at intervals and penetrating the first conductive type doped region and extending into the silicon carbide epitaxial layer; N lower mesas are located in the silicon carbide epitaxial layer and are spaced apart and connected to the upper mesas one by one; there are N upper mesas and N lower mesas; the width of the lower mesas is greater than the width of the upper mesas, and the difference between the two is 0.1µm to 1.0µm; Completely fill the dielectric layer of the upper and lower surfaces; An anode electrode located on one side of and above the dielectric layer.

2. A silicon carbide power device terminal structure according to claim 1, characterized in that: The spacing between adjacent lower mesas ranges from 0.3µm to 2.0µm, and the spacing between adjacent upper mesas ranges from 0.5µm to 2.5µm.

3. A silicon carbide power device terminal structure according to claim 2, characterized in that: The width of the upper mesa ranges from 0.5µm to 2.0µm, the depth of the upper mesa ranges from 0.7µm to 2.5µm, the depth of the lower mesa ranges from 0.2µm to 1.5µm, and the width of the lower mesa ranges from 0.7µm to 2.5µm.

4. A silicon carbide power device terminal structure according to claim 1, characterized in that: The value range of N is 3~50, which is a natural number.

5. A silicon carbide power device terminal structure according to claim 1, characterized in that: A dielectric layer is also located on the silicon carbide epitaxial layer.

6. A silicon carbide power device terminal structure according to claim 1, characterized in that: Also includes: A passivation layer covering the dielectric layer and the silicon carbide epitaxial layer between adjacent upper mesas is used to grow an anode electrode on the first conductive type doped region and on one side of the passivation layer.

7. A silicon carbide power device terminal structure according to claim 1, characterized in that: The dielectric constant of the dielectric layer is determined by the depth and width of the upper and lower mesas. The greater the depth and the smaller the width of the upper and lower mesas, the smaller the dielectric constant of the dielectric layer.

8. A method for manufacturing a silicon carbide power device terminal structure, used to manufacture a silicon carbide power device terminal structure according to any one of claims 1 to 7, characterized in that: The following steps are involved: Step 1, forming a silicon carbide epitaxial layer on a silicon carbide substrate; Step 2, forming a first conductivity type doped region in the silicon carbide epitaxial layer; Step 3, etching to form N upper mesas that penetrate the first conductive type doping region and extend into the silicon carbide epitaxial layer and are spaced apart from each other; Step 4, etching in the silicon carbide epitaxial layer to form N lower mesas connected one by one with the bottoms of the N upper mesas; the width of the lower mesas is greater than the width of the upper mesas, and the difference between the two is 0.1µm to 1.0µm; Step 5, forming a dielectric layer that completely fills the lower table and the upper table; Step 6: grow an anode electrode on the first conductive type doping region and on one side and on the dielectric layer, and grow a cathode electrode on the bottom of the silicon carbide substrate.

9. The method for manufacturing a terminal structure of a silicon carbide power device according to claim 8, characterized in that: Step 5 also includes forming a passivation layer on the dielectric layer and the silicon carbide epitaxial layer between the adjacent upper mesas by a chemical vapor deposition process.

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