Separated deep gate LDMOS device and manufacturing method, chip

Abstract

The present invention relates to the field of semiconductor technology, and provides a separated deep gate LDMOS device and a manufacturing method and a chip. The device comprises: a substrate, a body region, a drift region, a source region, a drain region, a separated deep gate structure and a field plate structure, wherein the body region, the drift region, the source region and the drain region are formed in the substrate, the body region is connected to the source region, and the drift region is connected to the drain region; the separated deep gate structure comprises a plurality of longitudinal deep gates embedded in the body region, and two adjacent longitudinal deep gates are isolated from each other by the body region; the field plate structure comprises a plurality of field oxide layers embedded in the drift region, and two adjacent field oxide layers are isolated from each other by the drift region; the body region between two adjacent longitudinal deep gates is connected to the drift region between two adjacent field oxide layers, and the plurality of longitudinal deep gates are respectively connected to the plurality of field oxide layers. The present invention adopts a separated longitudinal deep gate structure and a field plate structure to form a plurality of conductive channels, increase the control of the gate over the channel, increase the on-state current of the device, and thus reduce the on-state resistance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a separated deep-gate LDMOS device and a manufacturing method and a chip. Background Art

[0002] LDMOS (Lateral Double-diffusion Metal Oxide Semiconductor) is a typical power MOS device with the characteristics of high input impedance, simple driving, and fast switching speed. The on-resistance (Specific on-Resistance, Rsp) and breakdown voltage (Breakdown Voltage, BV) of LDMOS devices are two important indicators. In practical applications, LDMOS devices with high breakdown voltage and low on-resistance are required.

[0003] Generally, LDMOS devices use a field plate structure to increase the breakdown voltage. In the prior art, the gate of the LDMOS device is on the upper surface of the active region, and the field plate structure is designed below the gate. The field plate structure is usually formed by using Local Oxidation of Silicon (LOCOS) technology and Shallow Trench Isolation (STI) technology. In order to increase the breakdown voltage, it is necessary to increase the thickness of the field plate structure. However, when the LDMOS device is working, the current flows from the source to the drain along the lower surface of the field plate structure. The thicker the field plate structure, the longer the outflow path of the current from the source to the drain, and the greater the on-resistance. Therefore, it is difficult to obtain a lower on-resistance at a higher breakdown voltage. Summary of the invention

[0004] In order to solve the above technical defects, the present invention provides a separated deep gate LDMOS device and a manufacturing method thereof.

[0005] In one aspect, the present invention provides a separated deep gate LDMOS device, comprising: a substrate, a body region, a drift region, a source region, a drain region, a separated deep gate structure and a field plate structure;

[0006] The body region, the drift region, the source region and the drain region are formed in a substrate, the body region is connected to the source region, and the drift region is connected to the drain region;

[0007] The separated deep gate structure includes a plurality of longitudinal deep gates embedded in the body region, and two adjacent longitudinal deep gates are isolated from each other by the body region;

[0008] The field plate structure includes a plurality of field oxide layers embedded in the drift region, and two adjacent field oxide layers are isolated from each other by the drift region;

[0009] The body region between two adjacent longitudinal deep gates is connected to the drift region between two adjacent field oxide layers;

[0010] The body region at the bottom of the longitudinal deep gate is connected to the drift region at the bottom of the field oxide layer;

[0011] The plurality of longitudinal deep gates are respectively connected to the plurality of field oxide layers.

[0012] In an embodiment of the present invention, the split deep gate LDMOS device further comprises: a gate oxide layer;

[0013] The gate oxide layer is connected with the field oxide layer as a whole, and covers the side surface and bottom surface of the longitudinal deep gate.

[0014] In an embodiment of the present invention, the gate oxide layer is an oxide layer formed after the substrate is thermally oxidized;

[0015] The field oxide layer is an oxide layer formed after oxygen ions are implanted into the substrate.

[0016] In the embodiment of the present invention, the body region is connected to the side surface and bottom surface of each longitudinal deep gate through a gate oxide layer and a field oxide layer connected as one.

[0017] In the embodiment of the present invention, the drift region is directly connected to the side surface and the bottom surface of each field oxide layer.

[0018] In the embodiment of the present invention, when a positive voltage is applied to the vertical deep gates, the regions of the body region close to each vertical deep gate are inverted to form a plurality of conductive channels.

[0019] In the embodiment of the present invention, the depth at which the field oxide layer is embedded in the drift region is the same as the depth at which the vertical deep gate is embedded in the body region.

[0020] In an embodiment of the present invention, the depth of the source region is the same as the depth of the vertical deep gate embedded body region;

[0021] The depth of the drain region is the same as the depth of the drift region.

[0022] In the embodiment of the present invention, the interval between two adjacent longitudinal deep gates is 0.2-0.4 μm;

[0023] The depth of the vertical deep gate embedded in the body region is 0.2-0.4 μm.

[0024] In the embodiment of the present invention, the separated deep gate LDMOS device further comprises: an output terminal, the bottom of which is connected to the body region.

[0025] Another aspect of the present invention provides a method for manufacturing a separated deep-gate LDMOS device, comprising:

[0026] forming a plurality of mutually isolated longitudinal deep gates in a substrate;

[0027] Oxygen ion implantation is performed in a substrate region close to one side of the longitudinal deep gate to form a plurality of mutually isolated field oxide layers, wherein the plurality of field oxide layers are respectively connected to the plurality of longitudinal deep gates;

[0028] Ion implantation is performed in the substrate region between the field oxide layers and in the substrate region close to one side of the field oxide layer to form a drift region connected to the side and bottom surfaces of the field oxide layer;

[0029] Ion implantation is performed in the substrate region between each of the vertical deep gates to form a body region connected to the side and bottom surfaces of each of the vertical deep gates;

[0030] A source region is formed in the substrate region close to the other side of the vertical deep gate, and a drain region is formed in the substrate region close to one side of the drift region.

[0031] In an embodiment of the present invention, the step of forming a plurality of mutually isolated longitudinal deep gates in a substrate includes:

[0032] Etching the substrate to form a plurality of mutually isolated trenches in the substrate;

[0033] forming a gate oxide layer on inner walls of the plurality of trenches;

[0034] Polysilicon material is deposited in a plurality of trenches with a gate oxide layer to form a plurality of vertical deep gates isolated from each other.

[0035] In an embodiment of the present invention, the step of implanting oxygen ions in a substrate region close to one side of the vertical deep gate to form a plurality of mutually isolated field oxide layers includes:

[0036] Performing photolithography on the substrate to form a plurality of pattern windows on the substrate surface close to one side of the longitudinal deep gate;

[0037] High energy oxygen ion implantation is performed in a plurality of pattern windows, followed by annealing to form a field oxide layer.

[0038] In an embodiment of the present invention, the method further comprises: performing heavily doped P-type ion implantation in a substrate region close to a side of the source region to form an output terminal connected to the body region.

[0039] The present invention also provides a chip, which includes the above-mentioned separated deep-gate LDMOS device.

[0040] The present invention adopts a separated vertical deep gate structure and a field plate structure. When a positive voltage is applied to the vertical deep gate, the area of ​​the body region close to each vertical deep gate will be inverted to form an inversion layer, thereby forming multiple conductive channels in the body region between each vertical deep gate and the body region at the bottom of the vertical deep gate, which is equivalent to forming a three-dimensional conductive channel, increasing the control of the gate over the channel, reducing the leakage current of the device, increasing the on-current of the device, and thus reducing the on-resistance. Moreover, the thickness of the field plate structure of the present invention can be greatly increased, which can improve the breakdown voltage, but has very little effect on the on-resistance of the device.

[0041] Other features and advantages of the technical solution of the present invention will be described in detail in the specific implementation section below. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0043] Figure 1 is a schematic structural diagram of a lateral cross-section of a separated deep-gate LDMOS device provided by an embodiment of the present invention;

[0044] Figure 2 is a schematic structural diagram of a longitudinal cross section of a separated deep-gate LDMOS device provided by an embodiment of the present invention;

[0045] Figure 3 is a schematic structural diagram of a lateral cross-section of a separated deep-gate LDMOS device provided by another embodiment of the present invention;

[0046] Figure 4 is a schematic structural diagram of a longitudinal cross-section of a separated deep-gate LDMOS device provided by another embodiment of the present invention;

[0047] Figure 5 is a flow chart of a method for manufacturing a separated deep-gate LDMOS device provided by an embodiment of the present invention;

[0048] Figure 6a It is a schematic diagram of a trench and a gate oxide layer formed in the first step of a method for manufacturing a separated deep-gate LDMOS device provided by an embodiment of the present invention;

[0049] Figure 6b It is a schematic diagram of a vertical deep gate formed in the second step of the method for manufacturing a separated deep gate LDMOS device provided by an embodiment of the present invention;

[0050] Figure 6c is a schematic diagram of a field oxide layer formed in the third step of the method for manufacturing a split deep gate LDMOS device provided by an embodiment of the present invention;

[0051] Figure 6d It is a schematic diagram of a drift region and a body region formed in the fourth step of the method for manufacturing a split deep-gate LDMOS device provided by an embodiment of the present invention;

[0052] Figure 6e It is a schematic diagram of the source region and the drain region formed in the fifth step of the method for manufacturing a separated deep gate LDMOS device provided by an embodiment of the present invention.

[0053] Description of Reference Numerals

[0054] 10-substrate, 11-body region, 12-drift region, 13-vertical deep gate, 14-field oxide layer,

[0055] 15 - gate oxide layer, 16 - source region, 17 - drain region, 18 - connection terminal, 19 - trench. DETAILED DESCRIPTION

[0056] In order to make the technical solutions and advantages of the embodiments of the present invention more clearly understood, the exemplary embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.

[0057] In the description of the present invention, it should be understood that the terms "center", "upper", "lower", "front", "back", "left", "right", "side", "bottom", "surface", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. The terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first", "second", and "third" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0058] In the present invention, unless otherwise clearly specified and limited, the terms such as "interconnection", "connection", "connection" and the like should be understood in a broad sense, for example, it can be directly connected or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0059] In the process of realizing the present invention, the inventors found that the gate of the LDMOS device is on the upper surface of the active region, and the field plate structure is designed below the gate. In order to increase the breakdown voltage, it is necessary to increase the thickness of the field plate structure. However, when the LDMOS device is working, the current flows from the source end to the drain along the lower surface of the field plate structure. The thicker the field plate structure, the longer the outflow path of the current from the source to the drain, and the greater the on-resistance. Therefore, it is difficult to obtain a lower on-resistance at a higher breakdown voltage.

[0060] In view of the above problems, the embodiment of the present invention provides a separated deep gate LDMOS device, including: a substrate, a body region, a drift region, a source region, a drain region, a separated deep gate structure and a field plate structure, wherein the body region, the drift region, the source region and the drain region are formed in the substrate, the body region is connected to the source region, and the drift region is connected to the drain region; the separated deep gate structure includes a plurality of longitudinal deep gates embedded in the body region, and two adjacent longitudinal deep gates are isolated from each other by the body region; the field plate structure includes a plurality of field oxide layers embedded in the drift region, and two adjacent field oxide layers are isolated from each other by the drift region; and the plurality of longitudinal deep gates are respectively connected to the plurality of field oxide layers. The present invention adopts a separated longitudinal deep gate structure and a field plate structure, and when a positive voltage is applied to the longitudinal deep gate, the region of the body region close to each longitudinal deep gate will be inverted to form an inversion layer, thereby forming a plurality of conductive channels in the body region between each longitudinal deep gate and the body region at the bottom of the longitudinal deep gate, which is equivalent to forming a three-dimensional conduction channel, increasing the conduction current of the device, thereby reducing the conduction resistance. Furthermore, the thickness of the field plate structure of the present invention can be greatly increased, which can improve the breakdown voltage without almost increasing the on-resistance of the device.

[0061] like Figure 1 and Figure 2 As shown, a separated deep gate LDMOS device provided by an embodiment of the present invention includes: a substrate 10, a body region 11, a drift region 12, a source region 16, a drain region 17, a separated deep gate structure and a field plate structure. The body region 11, the drift region 12, the source region 16 and the drain region 17 are formed in the substrate 10, the body region 11 is connected to the source region 16, and the drift region 12 is connected to the drain region 17. The separated deep gate structure includes three longitudinal deep gates 13 embedded in the body region 11, and two adjacent longitudinal deep gates 13 are isolated from each other by the body region 11. The field plate structure includes three field oxide layers 14 embedded in the drift region 12, and two adjacent field oxide layers 14 are isolated from each other by the drift region 12. Multiple longitudinal deep gates 13 are respectively connected to multiple field oxide layers 14. The body region 11 between two adjacent longitudinal deep gates 13 is connected to the drift region 12 between two adjacent field oxide layers 14 , and the body region 11 at the bottom of the longitudinal deep gate 13 is connected to the drift region 12 at the bottom of the field oxide layer 14 .

[0062] In one embodiment, there is a gate oxide layer 15 between the source region 16 and each of the longitudinal deep gates 13, and the gate oxide layer 15 is connected to the field oxide layer 14 as a whole, covering the side and bottom surfaces of the longitudinal deep gates 13. The body region 11 is connected to the side and bottom surfaces of each of the longitudinal deep gates 13 through the gate oxide layer 15 and the field oxide layer 14 connected as a whole. The drift region 12 is directly connected to the side and bottom surfaces of each of the field oxide layers 14.

[0063] In an optional embodiment, the gate oxide layer 15 is formed in a different manner from the field oxide layer 14. The gate oxide layer 15 is an oxide layer formed after the substrate 10 is thermally oxidized. The field oxide layer 14 is an oxide layer formed after oxygen ions are implanted into the substrate 10. The gate oxide layer 15 formed by thermal oxidation is relatively thin, while the field oxide layer 14 formed by oxygen ion implantation is relatively thick, which can increase the breakdown voltage.

[0064] In a preferred embodiment, the depth of the field oxide layer 14 embedded in the drift region 12 is the same as the depth of the vertical deep gate 13 embedded in the body region 11. The depth of the source region 16 is the same as the depth of the vertical deep gate 13 embedded in the body region 11, and the depth of the drain region 17 is the same as the depth of the drift region 12. The interval between two adjacent vertical deep gates 13 is 0.2-0.4μm, and the depth of the vertical deep gate 13 embedded in the body region 11 is 0.2-0.4μm.

[0065] In the prior art, the gate of the LDMOS device is usually designed above the source region and the field plate, and the gate is a one-piece structure. When the device is working, the current flows from the source end to the drain end along the lower surface of the field plate. For devices with higher voltage resistance requirements, the field plate will be thicker, so the outflow path of the current from the source to the drain will be longer. The longer the current path, the greater the relative resistance.

[0066] The LDMOS device of the present invention adopts a separated deep gate structure and a field plate structure. The gate, field oxide layer, source and drain are designed to be arranged vertically in the substrate. Multiple longitudinal deep gates are separated by the body region, and multiple field oxide layers as field plates are separated by the drift region. When a positive voltage is applied to the gate, the gate carries a positive charge. The field oxide layer is equivalent to the dielectric layer of the capacitor. Since one side of the dielectric layer carries a positive charge (hole) and the other side carries a negative charge, a large amount of negative charge (electrons) will be induced in the body region. The original carriers in the P-type body region are holes. At this time, the holes are changed into electrons, so that the P-type silicon near the oxide layer in the body region is inverted to N-type, forming an inversion layer of a certain thickness. The N-type drift region will also induce a part of the electrons, which will accumulate at the interface with the body region, thereby conducting current. Since the inversion layer is conductive, its conductivity increases with the increase of the electric field, and the vertical deep gate is surrounded by the oxide layer and the body region outside the oxide layer, multiple conductive channels are formed in the body region between each vertical deep gate and the body region at the bottom of the vertical deep gate. The current can flow out from the conductive channel of the body region at the bottom of the vertical deep gate, and from the conductive channel of the body region between the vertical deep gates, which increases the control of the gate over the channel, reduces the leakage current of the device, increases the on-current of the device, and thus reduces the on-resistance of the device.

[0067] The bottom of the longitudinal deep gate of the LDMOS device of the present invention has a conductive channel, so it is impossible to design a field plate below the gate, but a field plate is made in the area between one side of the gate and the drift region, and the field plate is controlled by the gate to control the electric field distribution in the drift region. When the field plate is made on one side of the gate, the increase in the thickness of the field plate will increase the time of the thin film process. At the same time, considering the high temperature of the thin film process for a good interface state, this will cause a large amount of diffusion of the previously ion-implanted elements. The process of oxygen ion implantation and annealing in the area between the gate and the drift region can effectively solve this problem. By adjusting the range of oxygen ion implantation, the length of the field plate can be changed, and the breakdown voltage of the device can be changed. At the same time, the conduction path of the device does not change significantly. The current can flow out from the conductive channel of the body region at the bottom of the longitudinal deep gate, and can also flow out from the conductive channel of the body region between the longitudinal deep gates, so the on-resistance of the device is not greatly affected.

[0068] like Figure 3 and Figure 4As shown, another embodiment of the present invention provides a separated deep gate LDMOS device, comprising: a substrate 10, a body region 11, a drift region 12, a source region 16, a drain region 17, a separated deep gate structure and a field plate structure, wherein the body region 11, the drift region 12, the source region 16 and the drain region 17 are formed in the substrate 10, the body region 11 is connected to the source region 16, and the drift region 12 is connected to the drain region 17. The device also includes a connection terminal 18, the bottom of the connection terminal 18 is connected to the body region 11, and one side of the connection terminal 18 is connected to the source region 16. The separated deep gate structure includes three longitudinal deep gates 13 embedded in the body region 11, and two adjacent longitudinal deep gates 13 are isolated from each other by the body region 11. The field plate structure includes three field oxide layers 14 embedded in the drift region 12, and two adjacent field oxide layers 14 are isolated from each other by the drift region 12. Multiple longitudinal deep gates 13 are connected to multiple field oxide layers 14 respectively. The body region 11 between two adjacent longitudinal deep gates 13 is connected to the drift region 12 between two adjacent field oxide layers 14, and the body region 11 at the bottom of the longitudinal deep gate 13 is connected to the drift region 12 at the bottom of the field oxide layer 14. There is a gate oxide layer 15 between the source region 16 and each longitudinal deep gate 13, and the gate oxide layer 15 is connected to the field oxide layer 14 as a whole, covering the side and bottom surfaces of the longitudinal deep gate 13. Optionally, the depth of the field oxide layer 14 embedded in the drift region 12 is the same as the depth of the longitudinal deep gate 13 embedded in the body region 11. The depth of the source region 16 is the same as the depth of the longitudinal deep gate 13 embedded in the body region 11, and the depth of the drain region 17 is the same as the depth of the drift region 12. The interval between two adjacent longitudinal deep gates 13 is 0.2-0.4μm, and the depth of the longitudinal deep gate 13 embedded in the body region 11 is 0.2-0.4μm.

[0069] The separated deep gate LDMOS device of this embodiment has an additional connection terminal 18, and the connection terminal 18 has an ion doping type opposite to that of the source region 16 and the drain region 17, and has the same ion doping type as that of the body region 11. Since the potential of the body region 11 is constantly changing, which will cause the breakdown voltage of the LDMOS to change, the body region 11 below it is connected out through the connection terminal 18, and the connection terminal 18 is connected to the control potential to improve the potential stability of the body region 11.

[0070] Figure 5 FIG. 1 is a flow chart of a method for manufacturing a separated deep gate LDMOS device according to an embodiment of the present invention. Figure 5 As shown, the manufacturing method of the separated deep gate LDMOS device provided in this embodiment takes the NLDMOS device as an example, and the method comprises the following steps:

[0071] S501, forming a plurality of mutually isolated longitudinal deep gates in a substrate;

[0072] S502, performing oxygen ion implantation in a substrate region close to one side of the longitudinal deep gate to form a plurality of mutually isolated field oxide layers, wherein the plurality of field oxide layers are respectively connected to the plurality of longitudinal deep gates;

[0073] S503, performing N-type ion implantation in the substrate region between the field oxide layers and the substrate region close to one side of the field oxide layer to form an N-type drift region connected to the side and bottom surfaces of the field oxide layer;

[0074] S504, performing P-type ion implantation in the substrate region between each of the vertical deep gates to form a P-type body region connected to the side and bottom surfaces of each of the vertical deep gates;

[0075] S505 , forming a source region in the substrate region close to the other side of the vertical deep gate, and forming a drain region in the substrate region close to one side of the N-type drift region.

[0076] The following combination Figures 6a to 6e , the above manufacturing method is described in detail. It should be noted that, Figures 6a to 6e Only the cross-sectional view of the structure formed in each step is shown, which can be referred to Figure 1 The top view of the LDMOS device shown can be understood.

[0077] In the above step S501, a silicon wafer is selected as a substrate, and the substrate is photolithographically processed to form three pattern windows on the substrate surface using a photomask, and then the substrate is etched to form three mutually isolated trenches 19 in the substrate 10. Thermal oxidation is performed on the inner wall of the trench 19 to generate a layer of silicon oxide, which is used as the gate oxide layer 15 to form a gate oxide layer 15 as shown in FIG. Figure 6a The structure shown. Figure 6a This is a cross-sectional view, showing only a cutaway structure of a groove 19 .

[0078] After forming the gate oxide layer 15, polysilicon material is deposited in the three trenches 19 to form three Figure 6b A longitudinal deep grid 13 is shown.

[0079] In the above step S502, the substrate is photolithographically processed to form three pattern windows on the substrate surface near the right side of the vertical deep gate 13. High-energy oxygen ion implantation (the energy of oxygen ion implantation reaches 8 MeV) is performed in the three pattern windows, and annealing is performed. The oxygen element reacts with the substrate silicon to generate silicon oxide, forming three patterns such as Figure 6c The field oxide layer 14 shown. The field oxide layer 14 formed by oxygen ion implantation is relatively thick, which can improve the breakdown voltage. The gate oxide layer 15 formed by thermal oxidation in step S501 is relatively thin, and the thin gate oxide layer 15 is connected to the thick field oxide layer 14 as a whole, covering the side and bottom of the longitudinal deep gate 13. Figure 6c It is a cross-sectional view, which only shows a cutaway structure of a vertical deep gate 13 and a field oxide layer 14 .

[0080] In the above steps S503 to S504, if Figure 6dAs shown, N-type ion implantation is performed in the substrate region between each field oxide layer 14 and in the substrate region near the right side of the field oxide layer 14 to form an N-type drift region 12 connected to the side and bottom of the field oxide layer 14. P-type ion implantation is performed in the substrate region between each longitudinal deep gate 13 to form a P-type body region 11 connected to the side and bottom of the longitudinal deep gate 13.

[0081] In the above step S505, if Figure 6e As shown, heavily doped N-type ion implantation is performed in the substrate region near the left side of the longitudinal deep gate 13, and the doping concentration is greater than 10 18 / cm 3 , forming a source region 16. In the substrate region close to the right side of the N-type drift region 12, heavily doped N-type ions are implanted to form a drain region 17.

[0082] In another embodiment, after the source region 16 is formed, heavily doped P-type ion implantation is performed in the substrate region near the left side of the source region 16, with the doping concentration being greater than 10 18 / cm 3 , forming an outlet 18 connected to the body region 11. The position and structure of the outlet 18 can be referred to Figure 3 and Figure 4 To understand.

[0083] In the LDMOS device formed by the above method, the gate, field oxide layer, source and drain are arranged vertically in the substrate, and each longitudinal deep gate is separated by the body region. When a positive voltage is applied to the gate, the P-type silicon on the side close to the oxide layer in the body region is inverted to N-type, forming an inversion layer of a certain thickness. The N-type drift region will also induce a part of the electrons, which will accumulate at the interface with the body region, thereby conducting current. Since the inversion layer is conductive, its conductivity increases with the increase of the electric field, and the longitudinal deep gate is surrounded by the oxide layer and the body region outside the oxide layer, multiple conductive channels will be formed in the body region between each longitudinal deep gate and the body region at the bottom of the longitudinal deep gate. The current can flow out from the conductive channel in the body region at the bottom of the longitudinal deep gate, and can also flow out from the conductive channel in the body region between the longitudinal deep gates, which increases the conduction current and reduces the on-resistance of the device.

[0084] This method makes a field plate in the area between one side of the gate and the drift region, and controls the electric field distribution in the drift region by controlling the field plate through the gate. When the field plate is made on one side of the gate, the increase in the thickness of the field plate will increase the time of the thin film process. At the same time, considering the high temperature of the thin film process for a good interface state, this will cause a large amount of diffusion of the previously ion-implanted elements. This problem can be effectively solved by the process of oxygen ion implantation and annealing in the area between the gate and the drift region. By adjusting the range of oxygen ion implantation, the length of the field plate can be changed, and the breakdown voltage of the device can be changed. At the same time, the conduction path of the device does not change significantly. The current can flow out from the conductive channel of the body region at the bottom of the longitudinal deep gate, and can also flow out from the conductive channel of the body region between the longitudinal deep gates, so the on-resistance of the device is less affected.

[0085] An embodiment of the present invention further provides a chip, which includes the above-mentioned separated deep-gate LDMOS device.

[0086] The optional embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details in the above embodiments. Within the technical concept of the embodiments of the present invention, a variety of simple modifications can be made to the technical solutions of the embodiments of the present invention, and these simple modifications all belong to the protection scope of the embodiments of the present invention. It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction, and as long as the combination does not violate the concept of the embodiments of the present invention, it should also be regarded as the content disclosed in the embodiments of the present invention.

Claims

1. A split deep gate LDMOS device, characterized in that: include: Substrate, body region, drift region, source region, drain region, separated deep gate structure and field plate structure; The body region, the drift region, the source region and the drain region are formed in a substrate, the body region is connected to the source region, and the drift region is connected to the drain region; The separated deep gate structure includes a plurality of longitudinal deep gates embedded in the body region, and two adjacent longitudinal deep gates are isolated from each other by the body region; The field plate structure includes a plurality of field oxide layers embedded in the drift region, and two adjacent field oxide layers are isolated from each other by the drift region; The body region between two adjacent longitudinal deep gates is connected to the drift region between two adjacent field oxide layers; The body region at the bottom of the vertical deep gate is connected to the drift region at the bottom of the field oxide layer; The plurality of vertical deep gates are respectively connected to the plurality of field oxide layers.

2. The split deep gate LDMOS device according to claim 1, characterized in that: Also includes: A gate oxide layer is connected with the field oxide layer as a whole and covers the side surface and bottom surface of the longitudinal deep gate.

3. The split deep gate LDMOS device according to claim 2, characterized in that: The gate oxide layer is an oxide layer formed after the substrate is thermally oxidized; The field oxide layer is an oxide layer formed after oxygen ions are implanted into the substrate.

4. The split deep gate LDMOS device according to claim 2, characterized in that: The body region is connected to the side surface and bottom surface of each longitudinal deep gate through a gate oxide layer and a field oxide layer connected as one.

5. The split deep gate LDMOS device according to claim 2, characterized in that: The drift region is directly connected to the side surfaces and the bottom surfaces of each field oxide layer.

6. The split deep gate LDMOS device according to claim 1, characterized in that: When a positive voltage is applied to the vertical deep gates, the regions of the body region close to the vertical deep gates are inverted to form a plurality of conductive channels.

7. The split deep gate LDMOS device according to claim 1, characterized in that: The depth of the field oxide layer embedded in the drift region is the same as the depth of the vertical deep gate embedded in the body region.

8. The split deep gate LDMOS device according to claim 1, characterized in that: The depth of the source region is the same as the depth of the vertical deep gate embedded body region; The depth of the drain region is the same as the depth of the drift region.

9. The split deep gate LDMOS device according to claim 1, characterized in that: The interval between two adjacent longitudinal deep grids is 0.2-0.4 μm; The depth of the vertical deep gate embedded in the body region is 0.2-0.4 μm.

10. The split deep gate LDMOS device according to claim 1, characterized in that: Also includes: The outlet end has a bottom connected to the body region.

11. A method for manufacturing a split deep gate LDMOS device, characterized in that: include: forming a plurality of mutually isolated longitudinal deep gates in a substrate; Oxygen ion implantation is performed in a substrate region close to one side of the longitudinal deep gate to form a plurality of mutually isolated field oxide layers, wherein the plurality of field oxide layers are respectively connected to the plurality of longitudinal deep gates; Ion implantation is performed in the substrate region between the field oxide layers and in the substrate region close to one side of the field oxide layer to form a drift region connected to the side surface and the bottom surface of the field oxide layer; Ion implantation is performed in the substrate region between each of the vertical deep gates to form a body region connected to the side and bottom of each of the vertical deep gates, the body region between two adjacent vertical deep gates is connected to the drift region between two adjacent field oxide layers, and the body region at the bottom of the vertical deep gate is connected to the drift region at the bottom of the field oxide layer; A source region is formed in the substrate region close to the other side of the vertical deep gate, and a drain region is formed in the substrate region close to one side of the drift region.

12. The method for manufacturing a split deep gate LDMOS device according to claim 11, characterized in that: The method of forming a plurality of mutually isolated longitudinal deep gates in the substrate comprises: Etching the substrate to form a plurality of mutually isolated trenches in the substrate; forming a gate oxide layer on inner walls of the plurality of trenches; Polysilicon material is deposited in a plurality of trenches with a gate oxide layer to form a plurality of vertical deep gates isolated from each other.

13. The method for manufacturing a split deep gate LDMOS device according to claim 11, characterized in that: The oxygen ion implantation is performed in the substrate region near one side of the longitudinal deep gate to form a plurality of mutually isolated field oxide layers, including: Performing photolithography on the substrate to form a plurality of pattern windows on the substrate surface close to one side of the longitudinal deep gate; Oxygen ion implantation is performed in a plurality of pattern windows, followed by annealing to form a field oxide layer.

14. The method for manufacturing a split deep gate LDMOS device according to claim 11, characterized in that: The method further comprises: P-type ion implantation is performed in the substrate region close to the source region to form an output terminal connected to the body region.

15. A chip, characterized in that: The chip comprises the separated deep-gate LDMOS device according to any one of claims 1 to 10.

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