A transverse and longitudinal composite multi-junction TBC solar cell and its preparation method

Abstract

The present invention relates to the field of solar cells, and discloses a transverse and longitudinal composite multi-junction TBC solar cell and a preparation method thereof. The TBC solar cell comprises an N-type silicon wafer, the front side of which is provided with a pyramid velvet surface and a passivation layer in sequence; the back side of the N-type silicon wafer is provided with a deposition area A and a deposition area B distributed in a cross-finger shape; the gap between the deposition area A and the deposition area B is an isolation area, and the surface of the isolation area is provided with a pyramid velvet surface and a passivation layer in sequence; the surface of the deposition area A is provided with a boron diffusion layer A, a phosphorus diffusion layer A, a tunneling oxide layer A, a phosphorus diffusion layer B, a passivation layer and an electrode layer in sequence; the surface layer of the N-type silicon wafer located at the bottom of the deposition area B is a boron diffusion layer B, and the surface of the deposition area B is provided with a tunneling oxide layer B, a boron diffusion layer C, a passivation layer and an electrode layer in sequence. The TBC solar cell of the present invention has a transverse and longitudinal composite multi-junction structure, which is conducive to further improving the battery conversion efficiency of the battery, and at the same time reducing the battery preparation cost and technical difficulty.

Description

Technical Field

[0001] The invention relates to the field of solar cells, and in particular to a transverse and longitudinal composite multi-junction TBC solar cell and a preparation method thereof. Background Art

[0002] IBC cell is an interdigitated back contact solar cell. It is a structural technology that is compatible with various interface passivation technologies to form TBC, HBC, HPBC and other solar cells. Its biggest feature is that the metal cell contacts are placed on the back of the cell, and there is no metal electrode blocking the front, so it has a higher short-circuit current. J sc , while the back side can allow wider metal grid lines to reduce series resistance R s This increases the fill factor FF , so BC type cells tend to have higher conversion efficiency. In addition, IBC battery module packaging is more convenient and flexible, changing from conventional "Z" shaped welding to full back "I" shaped welding, avoiding the conventional complex packaging process, and can effectively improve the module's ability to resist hidden cracks. As TOPCon+ technology, TBC solar cells combine the excellent tunneling silicon oxide / doped amorphous silicon interface passivation technology of TOPCon cells, have higher conversion efficiency potential, and are expected to become the next generation of mass-produced cells.

[0003] Currently, the preparation of TBC solar cells generally requires high-temperature deposition of p + / n + -poly-Si layer with corresponding laser grooving and wet process steps to form a back-side cross-finger single-junction contact cell. Figure 8 As shown, currently, conventional TBC solar cells are generally single junction (pn junction) cells, and their theoretical limit is only ~29.43%. Patent CN118136703A discloses a TBC back contact structure crystalline silicon solar cell and its preparation method, the cell includes an N-type silicon substrate, a first tunneling oxide layer, a P-type polysilicon layer, a second tunneling oxide layer, an N-type polysilicon layer, a front passivation film, a back passivation film and an electrode assembly; the back of the N-type silicon substrate is distributed with a first and a second deposition area, the first deposition area and the side edge of the N-type silicon substrate have a first gap, and the first and second deposition intervals have a second gap; the first tunneling oxide layer and the P-type polysilicon layer are sequentially deposited in the first deposition area; the second tunneling oxide layer covers the second deposition area and part of the P-type polysilicon layer; the N-type polysilicon layer is arranged on the second tunneling oxide layer; the front and back passivation films are respectively arranged on the front and back of the N-type silicon substrate; the electrode assembly includes a first electrode, a second electrode and a third electrode.

[0004] In order to break through the efficiency limit of single-junction cells, stacked cell solutions are currently commonly used. The common mainstream stacked cell structure is a double-junction (pn junction) structure formed by perovskite cells + crystalline silicon solar cells, but there are many problems that need to be solved in this type of stacked cells. On the one hand, perovskite cells are ion crystal cells, and their long-term outdoor working stability is far inferior to atomic crystal silicon cells, resulting in poor reliability of the stacked cells. On the other hand, the preparation process of the cell is quite complicated, and the technical difficulty is high. The preparation cost is also expensive, which makes it difficult to use on a large scale.

[0005] In summary, in order to break through the efficiency limit of single-junction (pn-junction) TBC solar cells and reduce the preparation cost and technical difficulty, it is urgent to continuously develop TBC solar cells with new structures. Summary of the invention

[0006] In order to solve the above technical problems, the present invention provides a transverse and longitudinal composite multi-junction TBC solar cell and a preparation method thereof. The TBC solar cell of the present invention has a transverse and longitudinal composite multi-junction structure (pn junction), which is conducive to further improving the battery conversion efficiency of the battery and reducing the battery preparation cost and technical difficulty at the same time.

[0007] The specific technical scheme of the present invention is:

[0008] In a first aspect, the present invention provides a transverse and longitudinal composite multi-junction TBC solar cell, comprising an N-type silicon wafer, the front side of which is provided with a pyramid velvet surface and a passivation layer in sequence. The back side of the N-type silicon wafer is provided with a deposition area A and a deposition area B distributed in a cross-finger shape; the gap between the deposition area A and the deposition area B is an isolation area, and the surface of the isolation area is provided with a pyramid velvet surface and a passivation layer in sequence.

[0009] The surface of the deposition area A is provided with a boron diffusion layer A, a phosphorus diffusion layer A, a tunneling oxide layer A, a phosphorus diffusion layer B, a passivation layer and an electrode layer in sequence.

[0010] The surface layer of the N-type silicon wafer located at the bottom of the deposition area B is a boron diffusion layer B, and the surface of the deposition area B is provided with a tunneling oxide layer B, a boron diffusion layer C, a passivation layer and an electrode layer in sequence.

[0011] like Figure 1As shown, the above-mentioned TBC solar cell of the present invention has a horizontal and vertical composite multi-junction structure (pn junction). Among them, the first pn junction a is a horizontal structure, which is composed of a boron diffusion layer B (p-type region) and N-type silicon wafers on its left and right sides (the N-type silicon wafer substrate is an n-type region); the second pn junction b is a vertical structure, which is composed of a boron diffusion layer A and an N-type silicon wafer located at the bottom; the third pn junction c is a vertical structure, which is composed of a boron diffusion layer A and a phosphorus diffusion layer A (n-type region). First of all, compared with conventional single vertical single junction cells (PERC, TOPCon, HJT, etc.), the above-mentioned horizontal and vertical composite multi-junction TBC solar cell of the present invention can form a stacked structure on the silicon substrate itself, which can obtain higher V oc value, further improving the battery conversion efficiency; secondly, compared with the conventional perovskite + crystalline silicon stacked battery (preparation steps > 20 steps), the battery preparation steps are simpler (<16 steps), the preparation cost is lower, and the stacked structure is entirely composed of atomic crystals, which is more stable in long-term aging (light decay, humidity, heat, ultraviolet, etc.) environments.

[0012] Preferably, the thickness of the boron diffusion layer A is 200-1300 nm; the thickness of the boron diffusion layer B is 100-500 nm; the thickness of the boron diffusion layer C is 100-300 nm; the thickness of the phosphorus diffusion layer A is 50-400 nm; and the thickness of the phosphorus diffusion layer B is 100-300 nm.

[0013] In a second aspect, the present invention provides a method for preparing the above-mentioned transverse and longitudinal composite multi-junction TBC solar cell, comprising:

[0014] S1, N-type silicon wafer double-sided polishing.

[0015] S2, Boron diffusion, the concentration of boron atoms generated on the back of N-type silicon wafer is 1E+18~1E+19 cm -3 Boron diffusion layer A and BSG layer A.

[0016] After the first boron diffusion, a boron diffusion layer A and a BSG layer A can be sequentially generated on the back side of the N-type silicon wafer.

[0017] S3. Remove BSG layer A.

[0018] The BSG layer A on the back surface after boron diffusion can be removed by using a chain machine or other methods to pave the way for subsequent deposition steps.

[0019] S4. Depositing a tunneling oxide layer A and an intrinsic polysilicon layer A on the surface of the boron diffusion layer A in sequence.

[0020] The purpose of this step is to form an intrinsic polysilicon layer A, which provides conditions for subsequent conversion into a phosphorus diffusion layer B.

[0021] S5, phosphorus diffusion, so that the surface layer of the boron diffusion layer A, the inner layer and the surface layer of the intrinsic polysilicon layer A are transformed into phosphorus diffusion layer A (phosphorus atomic concentration is 5E+18~2E+20 cm -3 )、Phosphorus diffusion layer B (Phosphorus atomic concentration>1E+20 cm -3 ) and PSG layers.

[0022] In the phosphorus diffusion process, by controlling the phosphorus atom concentration on the phosphorus diffusion surface to be greater than the boron atom concentration on the first boron diffusion surface, the phosphorus atoms can pass through the tunneling oxide layer A, so that the surface portion of the boron diffusion layer A is transformed from a p-type region (i.e., a boron diffusion region) to an n-type region (i.e., a phosphorus diffusion region), while the deep portion of the boron diffusion layer A remains a p-type doped region. At the same time, the inner layer of the intrinsic polysilicon layer A is also transformed into a phosphorus diffusion layer B after phosphorus diffusion.

[0023] S6. Remove the PSG layer in the deposition area B and the isolation area on the back side of the N-type silicon wafer by laser patterning.

[0024] S7, alkaline cleaning to remove the deposition layers in the deposition area B and the isolation area (including the boron diffusion layer A, the phosphorus diffusion layer A, the tunneling oxide layer A and the phosphorus diffusion layer B).

[0025] After laser removal of the PSG layer in deposition area B and isolation area, the deposition areas at the bottom of the original PSG layer in this area can be removed during the alkaline cleaning process, thereby exposing the back side of the silicon wafer and providing conditions for subsequent deposition. The bottom deposition area of ​​deposition area A is retained due to the protection of PSG.

[0026] S8. Depositing a tunneling oxide layer B and an intrinsic polysilicon layer B on the surfaces of the deposition area A, the deposition area B and the isolation area in sequence.

[0027] The purpose of this step is to form an intrinsic polysilicon layer B, which provides conditions for subsequent conversion into a boron diffusion layer C.

[0028] S9, boron diffusion, so that the surface layer of the N-type silicon wafer in the deposition area B and the bottom of the isolation area, the inner layer and the surface layer of the intrinsic polysilicon layer B are transformed into the boron diffusion layer B (boron atomic concentration is 1E+19~2E+19 cm -3 )、boron diffusion layer C (boron atomic concentration is 1E+19~1E+20 cm -3 ) and BSG layer B.

[0029] In this boron diffusion process, the surface concentration of boron atoms can be controlled so that the boron atoms can pass through the tunneling oxide layer B in the deposition area B and the isolation area and enter the bottom of the N-type silicon wafer, so that the surface layer is transformed from n-type silicon to p-type silicon, that is, the boron diffusion layer B. Due to the presence of the intermediate PSG layer on the surface of the deposition area A, the boron atoms can be effectively blocked from entering the bottom area of ​​the PSG layer. At the same time, the inner layer and the surface layer of the intrinsic polysilicon layer B are transformed into the boron diffusion layer C and the BSG layer B respectively after this boron diffusion.

[0030] S10 , removing the BSG layer B in the deposition area A and the isolation area by laser patterning.

[0031] S11, removing the coating on the front and side surfaces of the N-type silicon wafer.

[0032] S12, cleaning and velveting.

[0033] In this process, since there is no coating layer on the front side of the silicon wafer, an effective light-trapping velvet surface (i.e., a pyramid velvet surface) can be formed under the action of an alkaline solution; and in the deposition area A area on the back side of the silicon wafer, since the protection of the BSG layer B is lost, the alkaline solution can effectively corrode and remove the deposition layers until the PSG layer, that is, the deposition layers formed after the PSG layer on the surface of the deposition area A on the back side of the N-type silicon wafer are removed by alkaline washing (due to the barrier of the PSG layer in the deposition area A, the deposition layers before the PSG can be prevented from being further corroded), and at the same time, the deposition layers at the junction of the deposition area A and the deposition area B (isolation area) are also removed after alkaline corrosion, thereby forming a gap (there is no deposition layer in the gap, that is, the back side of the N-type silicon wafer is exposed). On this basis, a pyramid velvet surface is formed at the gap after further corrosion by the alkaline solution. In addition, since the BSG layer B still exists in the deposition area B, the various parts of the deposition area B can be protected from being damaged during the cleaning and velveting process. Finally, the PSG layer on the back side of the silicon wafer (even if the boron diffusion layer B at the deposition area A is exposed) and the outermost BSG layer B of the deposition area B are removed by acid washing.

[0034] S13, double-sided coating.

[0035] S14, screen printing, sintering, and light injection to obtain a finished battery.

[0036] Preferably, in S1, the N-type silicon wafer is an N-type single crystal silicon wafer cut by diamond wire.

[0037] Preferably, in S2, the boron diffusion conditions are: boron diffusion temperature 900-950°C, diffusion time 10-50 min, BCl3 gas flow rate 50-500 sccm, O2 gas flow rate 500-2000 sccm; oxidation advancement temperature 1000-1050°C, O2 gas flow rate 3000-50000 sccm, advancement time 30-80 min, and the resulting BSG layer A has a thickness of 30-70 nm.

[0038] Preferably, in S4, the conditions for depositing the tunnel oxide layer A are: O2 gas flow rate 10000-80000 sccm, temperature 400-800°C, time 200-1000 s, and the thickness of the obtained tunnel oxide layer A is 1-10 nm.

[0039] Preferably, in S4, the conditions for depositing the intrinsic polysilicon layer A are: SiH4 gas flow rate 300~2000 sccm, temperature 500~700°C, time 2~4 h, working pressure 100~500 mTorr, and the thickness of the obtained intrinsic polysilicon layer A is 100~300 nm.

[0040] Preferably, in S5, the phosphorus diffusion conditions are: phosphorus diffusion temperature 750-850°C, diffusion time 5-30 min, POCl3 is carried by nitrogen with a flow rate of 500-2500 sccm, and O2 flow rate 500-3000 sccm; then oxidation is promoted at a temperature of 850-950°C, a promotion time of 5-60 min, and an O2 flow rate of 1000-10000 sccm; the thickness of the resulting PSG layer is 30-70 nm.

[0041] As a further preference, in S5, the conditions for the phosphorus diffusion are: phosphorus diffusion temperature 750-850°C, diffusion time 5-30 min, POCl3 carried by nitrogen with a flow rate of 500-2500 sccm, O2 flow rate 500-3000 sccm; then oxidation is promoted, and POCl3 carried by nitrogen is introduced again at a flow rate of 1000-5000 sccm for 2-10 min; oxidation promotion temperature 850-950°C, promotion time 5-20 min, O2 flow rate 5000-20000 sccm; the thickness of the obtained PSG layer is 30-70 nm.

[0042] In the above process, the "high surface doping concentration + short oxidation advancement time" method is adopted to make the PSG layer contain a higher concentration of phosphorus source. The advantage is that in the subsequent secondary boron diffusion high temperature process: on the one hand, the phosphorus atoms can pass through the tunneling oxide layer A again to form a phosphorus diffusion layer A with better diffusion effect; on the other hand, the phosphorus atom concentration in the phosphorus diffusion layer B can be maintained at a stable value and will not be greatly reduced.

[0043] Preferably, in S6, the conditions of the laser patterning treatment are: laser wavelength 400-600 nm, frequency 500-700 KHz, marking speed 40000-50000 mm / s, power 10-50 W, and treatment time 1-5 s.

[0044] Preferably, in S8, the conditions for depositing the tunnel oxide layer B are: O2 gas flow rate 10000-80000 sccm, temperature 400-800° C., time 200-1000 s, and the thickness of the obtained tunnel oxide layer B is 1-10 nm.

[0045] Preferably, in S8, the conditions for depositing the intrinsic polysilicon layer B are: SiH4 gas flow rate 300~2000 sccm, temperature 500~700°C, time 2~4 h, working pressure 100~500 mTorr, and the thickness of the obtained intrinsic polysilicon layer B is 100~300 nm.

[0046] Preferably, in S9, the boron diffusion conditions are: boron diffusion temperature 800-950°C, diffusion time 5-50 min, BCl3 gas flow rate 50-500 sccm, O2 gas flow rate 500-2000 sccm; oxidation advancement temperature 900-1050°C, O2 flow rate 5000-30000 sccm, advancement time 30-80 min, and the resulting BSG layer B has a thickness of 30-70 nm.

[0047] Preferably, in S10, the conditions of the laser patterning treatment are: laser wavelength 400-600 nm, frequency 500-700 KHz, marking speed 40000-50000 mm / s, power 10-50 W, and treatment time 1-5 s.

[0048] Compared with the prior art, the beneficial effects of the present invention are:

[0049] (1) The TBC solar cell of the present invention has a lateral and longitudinal composite multi-junction structure (pn junction), which can obtain higher V oc Value, is conducive to further improving battery conversion efficiency.

[0050] (2) The present invention successfully obtains a TBC solar cell with a transverse and longitudinal composite multi-junction structure through a series of ingenious process step designs, while reducing the cost and technical difficulty of cell preparation.

[0051] (3) The present invention strictly controls the phosphorus diffusion and the second boron diffusion processes respectively, so that phosphorus atoms and boron atoms can respectively pass through the tunneling oxide layer, and respectively transform the surface of the boron diffusion layer A and the surface of the N-type silicon wafer into the phosphorus diffusion layer A and the boron diffusion layer B, thereby successfully constructing a horizontal and vertical composite multi-junction structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 This is a schematic structural diagram of a transverse and longitudinal composite multi-junction TBC solar cell according to Example 1 of the present invention.

[0053] Figure 2 This is a schematic diagram of the structure of a silicon wafer after double-sided polishing S1 in Example 1 of the present invention.

[0054] Figure 3 This is a schematic diagram of the structure of a silicon wafer after S2 boron diffusion in Example 1 of the present invention.

[0055] Figure 4 This is a schematic diagram of the structure of a silicon wafer after S5 phosphorus diffusion in Example 1 of the present invention.

[0056] Figure 5 This is a schematic diagram of the structure of a silicon wafer after S7 alkaline cleaning in Example 1 of the present invention.

[0057] Figure 6 This is a schematic diagram of the structure of a silicon wafer after S9 boron diffusion in Example 1 of the present invention.

[0058] Figure 7 This is a schematic diagram of the structure of a silicon wafer after cleaning and texturing in S12 in Example 1 of the present invention.

[0059] Figure 8 This is a schematic diagram of the structure of a conventional back-side interdigitated single-junction contact cell.

[0060] The figures are marked as follows: N-type silicon wafer 1, boron diffusion layer A 2, phosphorus diffusion layer A 3, tunneling oxide layer A 4, phosphorus diffusion layer B5, PSG layer 6, tunneling oxide layer B 7, boron diffusion layer C 8, BSG layer B 9, pyramid velvet 10, passivation layer 11, electrode layer 12, boron diffusion layer B 13, first pn junction a, second pn junction b, third pn junction c. DETAILED DESCRIPTION

[0061] The present invention will be further described below in conjunction with the embodiments.

[0062] First, the present invention provides a transverse and longitudinal composite multi-junction TBC solar cell, comprising an N-type silicon wafer, the front side of which is provided with a pyramid velvet surface and a passivation layer in sequence. The back side of the N-type silicon wafer is provided with a deposition area A and a deposition area B distributed in a cross-finger shape; the gap between the deposition area A and the deposition area B is an isolation area, and the surface of the isolation area is provided with a pyramid velvet surface and a passivation layer in sequence.

[0063] The surface of the deposition area A is provided with a boron diffusion layer A, a phosphorus diffusion layer A, a tunneling oxide layer A, a phosphorus diffusion layer B, a passivation layer and an electrode layer in sequence. The surface layer of the N-type silicon wafer located at the bottom of the deposition area B is a boron diffusion layer B, and the surface of the deposition area B is provided with a tunneling oxide layer B, a boron diffusion layer C, a passivation layer and an electrode layer in sequence.

[0064] In some specific implementation cases, the thickness of the boron diffusion layer A is 200~1300 nm; the thickness of the boron diffusion layer B is 100~500 nm; the thickness of the boron diffusion layer C is 100~300 nm; the thickness of the phosphorus diffusion layer A is 50~400 nm; and the thickness of the phosphorus diffusion layer B is 100~300 nm.

[0065] Secondly, the present invention provides a method for preparing the above-mentioned transverse and longitudinal composite multi-junction TBC solar cell, which specifically comprises the following steps:

[0066] S1, N-type silicon wafer double-sided polishing.

[0067] In some specific implementation cases, N-type single crystal silicon wafers cut with diamond wire are selected, with a thickness of 100-200 μm and a size of 182.2 mm×186.7 mm. The cut N-type single crystal silicon wafers are placed in an alkaline polishing tank, the temperature is maintained at 75-85°C, the time is 6-8 min for double-sided polishing, the polishing thickness is 3-7 μm, and the thinning amount is 0.35-0.45 g.

[0068] S2, boron diffusion, forming a boron diffusion layer A and a BSG layer A on the back side of the N-type silicon wafer. After the first boron diffusion, a boron diffusion layer A and a BSG layer A can be formed in sequence on the back side of the N-type silicon wafer.

[0069] In some specific implementation cases, the boron diffusion conditions are: boron diffusion temperature 900-950°C, diffusion time 10-50 min, BCl3 gas flow rate 50-500 sccm, O2 gas flow rate 500-2000 sccm; oxidation push temperature 1000-1050°C, O2 gas flow rate 3000-50000 sccm, push time 30-80 min, the thickness of the obtained BSG layer A is 30-70 nm. The boron atomic concentration in the boron diffusion layer A is 1E+18-1E+19 cm -3 .

[0070] S3. Remove BSG layer A.

[0071] In some specific implementation cases, a chain machine is used to remove the BSG layer A on the back surface after boron diffusion, wherein the concentration of the HF solution in the chain machine is 20-80 wt % and the belt speed is 0.5-5 m / min.

[0072] S4, depositing a tunnel oxide layer A and an intrinsic polysilicon layer A in sequence on the surface of the boron diffusion layer A. The purpose of this step is to form the intrinsic polysilicon layer A, so as to provide conditions for subsequent conversion into the phosphorus diffusion layer B.

[0073] In some specific implementation cases, the conditions for depositing the tunnel oxide layer A are: O2 gas flow rate 10000~80000 sccm, temperature 400~800°C, time 200~1000 s, and the thickness of the obtained tunnel oxide layer A is 1~10 nm.

[0074] In some specific implementation cases, the conditions for depositing the intrinsic polysilicon layer A are: SiH4 gas flow rate 300~2000 sccm, temperature 500~700°C, time 2~4 h, working pressure 100~500 mTorr, and the thickness of the obtained intrinsic polysilicon layer A is 100~300 nm.

[0075] S5, phosphorus diffusion, so that the surface layer of the boron diffusion layer A, the inner layer and the surface layer of the intrinsic polysilicon layer A are transformed into phosphorus diffusion layer A (phosphorus atomic concentration is 5E+18~2E+20 cm -3 )、Phosphorus diffusion layer B (Phosphorus atomic concentration>1E+20 cm -3 ) and PSG layer. In the phosphorus diffusion process, by controlling the phosphorus atom concentration on the phosphorus diffusion surface to be greater than the boron atom concentration on the first boron diffusion surface, the phosphorus atoms can pass through the tunneling oxide layer A, so that the surface part of the boron diffusion layer A is transformed from a p-type region (i.e., a boron diffusion region) to an n-type region (i.e., a phosphorus diffusion region), while the deep part of the boron diffusion layer A remains a p-type doped region. At the same time, after phosphorus diffusion, the inner layer of the intrinsic polysilicon layer A is also transformed into a phosphorus diffusion layer B.

[0076] In some specific implementation cases, the conditions for the phosphorus diffusion are: phosphorus diffusion temperature 750~850℃, diffusion time 5~30 min, POCl3 is carried by nitrogen with a flow rate of 500~2500 sccm, and O2 flow rate 500~3000 sccm; then oxidation is promoted at a temperature of 850~950℃, a promotion time of 5~60 min, and an O2 flow rate of 1000~10000 sccm; the thickness of the resulting PSG layer is 30~70 nm.

[0077] In some more preferred implementation cases, the conditions for the phosphorus diffusion are: phosphorus diffusion temperature 750~850℃, diffusion time 5~30 min, POCl3 carried by nitrogen with a flow rate of 500~2500 sccm, O2 flow rate 500~3000 sccm; then oxidation is promoted, and POCl3 carried by nitrogen is introduced again at a flow rate of 1000~5000 sccm, and the introduction time is 2~10min; oxidation promotion temperature 850~950℃, promotion time 5~20 min, O2 flow rate 5000~20000 sccm; the thickness of the obtained PSG layer is 30~70 nm.

[0078] S6. Remove the PSG layer in the deposition area B and the isolation area on the back side of the N-type silicon wafer by laser patterning.

[0079] In some specific implementation cases, the conditions of the laser patterning treatment are: laser wavelength 400~600nm, frequency 500~700KHz, marking speed 40000~50000 mm / s, power 10~50W, and treatment time 1~5s.

[0080] S7, alkaline cleaning to remove the deposition layers in deposition area B and isolation area (including boron diffusion layer A, phosphorus diffusion layer A, tunneling oxide layer A and phosphorus diffusion layer B). After laser removal of the PSG layer in deposition area B and isolation area, the deposition areas at the bottom of the original PSG layer in this area can be removed during the alkaline cleaning process, thereby exposing the back side of the silicon wafer and providing conditions for subsequent deposition. Due to the protection of PSG, the bottom deposition area of ​​deposition area A is retained.

[0081] In some specific implementation cases, the conditions of the alkaline solution are: KOH solution concentration is 1.7~2.2 wt%, temperature is 75~85°C, time is 200~600 s, and corrosion depth is 1~5 μm.

[0082] S8, sequentially depositing a tunnel oxide layer B and an intrinsic polysilicon layer B on the surfaces of the deposition area A, the deposition area B and the isolation area. The purpose of this step is to form an intrinsic polysilicon layer B to provide conditions for subsequent conversion into a boron diffusion layer C.

[0083] In some specific implementation cases, the conditions for depositing the tunnel oxide layer B are: O2 gas flow rate 10000~80000 sccm, temperature 400~800°C, time 200~1000 s, and the thickness of the obtained tunnel oxide layer B is 1~10 nm.

[0084] In some specific implementation cases, the conditions for depositing the intrinsic polysilicon layer B are: SiH4 gas flow rate 300~2000 sccm, temperature 500~700°C, time 2~4 h, working pressure 100~500 mTorr, and the thickness of the obtained intrinsic polysilicon layer B is 100~300 nm.

[0085] S9, boron diffusion, so that the surface layer of the N-type silicon wafer in the deposition area B and the bottom of the isolation area, the inner layer and the surface layer of the intrinsic polysilicon layer B are transformed into the boron diffusion layer B (boron atomic concentration is 1E+19~2E+19 cm -3 )、boron diffusion layer C (boron atomic concentration is 1E+19~1E+20 cm -3) and BSG layer B. In this boron diffusion process, by controlling the surface concentration of boron atoms, boron atoms can pass through the tunneling oxide layer B in the deposition area B and the isolation area and enter the bottom of the N-type silicon wafer, so that its surface layer is transformed from n-type silicon to p-type silicon, that is, it becomes a boron diffusion layer B. Due to the presence of the intermediate PSG layer on the surface of the deposition area A, boron atoms can be effectively blocked from entering the bottom area of ​​the PSG layer. At the same time, the inner layer and the surface layer of the intrinsic polysilicon layer B are transformed into a boron diffusion layer C and a BSG layer B respectively after this boron diffusion.

[0086] In some specific implementation cases, the conditions for boron diffusion are: boron diffusion temperature 800-950°C, diffusion time 5-50 min, BCl3 gas flow rate 50-500 sccm, O2 gas flow rate 500-2000 sccm, oxidation advancement temperature 900-1050°C, O2 flow rate 5000-30000 sccm, advancement time 30-80 min, and the resulting BSG layer B thickness is 30-70 nm.

[0087] S10 , removing the BSG layer B in the deposition area A and the isolation area by laser patterning.

[0088] In some specific implementation cases, the conditions of the laser patterning treatment are: laser wavelength 400~600nm, frequency 500~700KHz, marking speed 40000~50000 mm / s, power 10~50W, and treatment time 1~5s.

[0089] S11, removing the coating on the front and side surfaces of the N-type silicon wafer.

[0090] In some specific implementation cases, a chain machine is used to remove the boron diffusion layer and the phosphorus diffusion layer coated on the front and side surfaces of the silicon wafer, wherein the volume ratio of the HF solution (concentration 45~55 wt%) and the HNO3 solution (concentration 65~75 wt%) in the acid tank is 1:2~1:8; the temperature is room temperature, and the belt speed is 1~10 m / min.

[0091] S12, cleaning and velveting.

[0092] In some specific implementation cases, the silicon wafer after the coating is removed is placed in an alkaline texturing tank for wet cleaning and texturing integrated treatment, wherein the concentration of KOH solution in the texturing tank is 1.5-1.8 wt%, the temperature is maintained at 80-85°C, and the time is 6-12 min. The subsequent acid (HF / HCl) cleaning tank of the texturing tank can further remove the residual PSG layer and BSG layer B of the silicon wafer.

[0093] In this process, since there is no coating layer on the front side of the silicon wafer, an effective light-trapping velvet surface (i.e., a pyramid velvet surface) can be formed under the action of an alkaline solution; and the deposition area A on the back side of the silicon wafer, due to the loss of the protection of the BSG layer B, the alkaline solution can effectively corrode and remove the deposition layers up to the PSG layer, that is, the deposition layers formed after the PSG layer on the surface of the deposition area A on the back side of the N-type silicon wafer are removed by alkaline washing (due to the barrier of the PSG layer in the deposition area A, the deposition layers before the PSG can be prevented from being further corroded), and at the same time, the deposition layers (including the bottom boron diffusion layer A) are removed after alkaline corrosion at the junction of the deposition area A and the deposition area B (isolation area), thereby forming a gap (there is no deposition layer in the gap, i.e., the back side of the N-type silicon wafer is exposed), and on this basis, a pyramid velvet surface is formed at the gap after further corrosion by the alkaline solution. In addition, since the BSG layer B still exists in the deposition area B, the various parts of the deposition area B can be protected from being damaged during the cleaning and velveting process. Finally, the PSG layer on the back side of the silicon wafer (ie, the boron diffusion layer B at the deposition area A is exposed) and the BSG layer B at the outermost layer of the deposition area B are removed by pickling.

[0094] S13, double-sided coating.

[0095] In some specific implementation cases, AlO is deposited on the front and back surfaces of the processed silicon wafer by ALD deposition. x The film is generated by the reaction of Al(CH3)3 and water vapor, with a thickness of 8~10 nm and a process temperature of 220~280℃. Then SiN is deposited on both sides using a tubular PECVD device. x Film, front SiN x The thickness of the film is 80~100 nm, and the refractive index is 2.0~2.1; the back SiN x The thickness of the film is 80~120 nm, and the refractive index is 1.9~2.1; the reaction gases in the tubular cavity are SiH4 and NH3, the working pressure is 1500~1700 mTorr, the power is 10000~15000 W, the temperature is 400~600℃, the SiH4 gas flow rate is 900~2000 sccm, the NH3 gas flow rate is 7000~12000 sccm, the silicon-nitrogen ratio is 0.1~0.3:1, and the deposition time is 5~20 min.

[0096] S14, screen printing, sintering, and light injection to obtain a finished battery.

[0097] In some specific implementation cases, the coated silicon wafer is screen-printed on the back to form a metal contact, and then sintered at 700~800℃ to form an Ag-Si ohmic contact, and finally repaired by light injection to obtain the final finished battery.

[0098] Specific examples and comparative examples.

[0099] Example 1

[0100] A method for preparing the above-mentioned transverse and longitudinal composite multi-junction TBC solar cell specifically comprises the following steps:

[0101] S1. Double-sided polishing of N-type silicon wafer: Select N-type single crystal silicon wafer cut by diamond wire, with a thickness of 150 μm and a size of 182.2 mm×186.7 mm. Put the cut N-type single crystal silicon wafer into the alkaline polishing tank, maintain the temperature at 75°C, and perform double-sided polishing for 6 min. The polishing thickness is 4 μm and the thinning amount is 0.42 g. Figure 2 Schematic diagram of the structure of a silicon wafer after double-sided polishing.

[0102] S2, boron diffusion, generating boron diffusion layer A and BSG layer A on the back of N-type silicon wafer. The conditions of boron diffusion are: boron diffusion temperature 930℃, diffusion time 25 min, BCl3 gas flow rate 200 sccm, O2 gas flow rate 1200 sccm, oxidation push temperature 1050℃, O2 gas flow rate 20000 sccm, push time 60 min, the thickness of BSG layer A is about 48 nm. The concentration of boron atoms in boron diffusion layer A is 4E+18 cm -3 . Figure 3 Schematic diagram of the structure of the silicon wafer after boron diffusion.

[0103] S3. Removal of BSG layer A: A chain machine is used to remove the BSG layer A on the back surface after boron expansion, wherein the concentration of the HF solution in the chain machine is 40 wt % and the belt speed is 3 m / min.

[0104] S4. Deposit tunnel oxide layer A and intrinsic polysilicon layer A on the surface of boron diffusion layer A in sequence. The conditions for depositing tunnel oxide layer A are: O2 gas flow rate 40000 sccm, temperature 600°C, time 600 s, and the thickness of the obtained tunnel oxide layer A is about 3 nm. The conditions for depositing intrinsic polysilicon layer A are: SiH4 gas flow rate 900 sccm, temperature 550°C, time 2.5 h, working pressure 300 mTorr, and the thickness of the obtained intrinsic polysilicon layer A is about 200 nm.

[0105] S5, phosphorus diffusion, so that the surface layer of the boron diffusion layer A, the inner layer and the surface layer of the intrinsic polysilicon layer A are transformed into the phosphorus diffusion layer A, the phosphorus diffusion layer B and the PSG layer respectively. The conditions for phosphorus diffusion are: phosphorus diffusion temperature 790℃, diffusion time 20 min, POCl3 is carried by nitrogen with a flow rate of 1100 sccm, O2 flow rate of 700 sccm, after the initial diffusion is completed, O2 is introduced for oxidation promotion, the oxidation promotion temperature is 890℃, the gas flow rate of O2 is 3000 sccm, and the promotion time is 40 min; the thickness of PSG is about 42 nm. In the phosphorus diffusion process, by controlling the phosphorus atom concentration on the phosphorus diffusion surface to be greater than the boron atom concentration on the first boron diffusion surface, the phosphorus atoms can pass through the tunneling oxide layer A, so that the surface part of the boron diffusion layer A is transformed from the p-type region (i.e., the boron diffusion region) to the n-type region (i.e., the phosphorus diffusion layer A, about 200 nm thick, with a phosphorus atom concentration of 5E+19 cm -3 ), while the deep part of the boron diffusion layer A remains a p-type doped region. At the same time, after phosphorus diffusion, the inner layer of the intrinsic polysilicon layer A is also transformed into a phosphorus diffusion layer B (phosphorus atomic concentration is 2E+20 cm -3 ). Figure 4 Schematic diagram of the structure of the silicon wafer after phosphorus diffusion.

[0106] S6. Remove the PSG layer in the deposition area B and the isolation area on the back of the N-type silicon wafer by laser patterning. The conditions of the laser patterning are: laser wavelength 532 nm, frequency 600 KHz, marking speed 45000 mm / s, power 25 W, and processing time 2.7 s.

[0107] S7, alkaline cleaning to remove the deposition layers (including boron diffusion layer A, phosphorus diffusion layer A, tunneling oxide layer A and phosphorus diffusion layer B) in deposition area B and isolation area. After laser removal of the PSG layer in deposition area B and isolation area, the deposition areas at the bottom of the original PSG layer in this area can be removed during the alkaline cleaning process, thereby exposing the back of the silicon wafer and providing conditions for subsequent deposition. Due to the protection of PSG, the bottom deposition area of ​​deposition area A is retained. The conditions of the alkaline solution are: KOH solution concentration of 2.0 wt%, temperature of 75°C, time of 400 s, and corrosion depth of 3 μm. Figure 5 Schematic diagram of the structure of the silicon wafer after alkaline cleaning.

[0108] S8, depositing tunnel oxide layer B and intrinsic polysilicon layer B on the surfaces of deposition area A, deposition area B and isolation area in sequence. The conditions for depositing tunnel oxide layer B are: O2 gas flow rate 50000 sccm, temperature 600°C, time 800 s, and the thickness of the obtained tunnel oxide layer B is about 5 nm. The conditions for depositing intrinsic polysilicon layer B are: SiH4 gas flow rate 920 sccm, temperature 550°C, time 3.4 h, working pressure 300 mTorr, and the thickness of the obtained intrinsic polysilicon layer B is about 295 nm.

[0109] S9, boron diffusion, so that the surface layer of the N-type silicon wafer in the deposition area B and the bottom of the isolation area, the inner layer and the surface layer of the intrinsic polysilicon layer B are transformed into the boron diffusion layer B (boron atomic concentration is 1.5E+19 cm -3 )、boron diffusion layer C (boron atomic concentration is 3E+19cm -3 ) and BSG layer B. The conditions for boron diffusion are: boron diffusion temperature 850℃, diffusion time 10 min, BCl3 gas flow rate 200 sccm, O2 gas flow rate 1200 sccm, oxidation push temperature 950℃, O2 flow rate 7000 sccm, push time 30 min, and BSG layer thickness of about 45 nm. In this boron diffusion process, by controlling the surface concentration of boron atoms, boron atoms can pass through the tunneling oxide layer B in the deposition area B and the isolation area to enter the bottom of the N-type silicon wafer, so that its surface layer is transformed from n-type silicon to p-type silicon, that is, it becomes a boron diffusion layer B. Due to the presence of the intermediate PSG layer on the surface of the deposition area A, boron atoms can be effectively blocked from entering the bottom area of ​​the PSG layer. At the same time, the inner layer and surface layer of the intrinsic polysilicon layer B are transformed into a boron diffusion layer C and a BSG layer B respectively after this boron diffusion. Figure 6 Schematic diagram of the structure of the silicon wafer after boron diffusion.

[0110] S10, removing the BSG layer B in the deposition area A and the isolation area by laser patterning. The conditions of the laser patterning are: laser wavelength 532 nm, frequency 600 KHz, marking speed 45000 mm / s, power 50 W, and processing time 3 s.

[0111] S11. Removal of coating layers on the front and side surfaces of N-type silicon wafers: Use a chain machine to remove the boron diffusion layer and phosphorus diffusion layer coated on the front and side surfaces of the silicon wafers, wherein the volume ratio of HF solution (concentration 49 wt%) and HNO3 solution (concentration 69 wt%) in the acid tank is 1:4; the temperature is room temperature, and the belt speed is 1.3 m / min.

[0112] S12, cleaning and texturing: The silicon wafer after the coating is removed is placed in an alkaline texturing tank for wet cleaning and texturing integrated treatment, wherein the concentration of KOH solution in the texturing tank is 1.7 wt%, the temperature is maintained at 82°C, and the time is 7 minutes. The subsequent acid (HF / HCl) cleaning tank of the texturing tank can further remove the residual PSG layer of the silicon wafer. In this process, since there is no coating layer on the front side of the silicon wafer, an effective light-trapping velvet surface (i.e., a pyramid velvet surface) can be formed under the action of an alkaline solution; and the deposition area A on the back side of the silicon wafer, due to the loss of the protection of the BSG layer B, the alkaline solution can effectively corrode and remove the deposition layers up to the PSG layer, that is, the deposition layers formed after the PSG layer on the surface of the deposition area A on the back side of the N-type silicon wafer are removed by alkaline washing (due to the barrier of the PSG layer in the deposition area A, the deposition layers before the PSG can be prevented from being further corroded), and at the same time, the deposition layers (including the bottom boron diffusion layer A) are removed after alkaline corrosion at the junction of the deposition area A and the deposition area B (isolation area), thereby forming a gap (there is no deposition layer in the gap, i.e., the back side of the N-type silicon wafer is exposed), and on this basis, a pyramid velvet surface is formed at the gap after further corrosion by the alkaline solution. In addition, since the BSG layer B still exists in the deposition area B, the various parts of the deposition area B can be protected from being damaged during the cleaning and velveting process. Finally, the PSG layer on the back side of the silicon wafer (ie, the boron diffusion layer B at the deposition area A is exposed) and the BSG layer B at the outermost layer of the deposition area B are removed by pickling. Figure 7 Schematic diagram of the structure of the silicon wafer after cleaning and texturing.

[0113] S13, double-sided coating: Atomic layer deposition (ALD) is used to deposit AlO on the front and back of the processed silicon wafer. x The film is generated by the reaction of Al(CH3)3 and water vapor, with a thickness of about 8 nm and a process temperature of 250°C. Then SiN is deposited on both sides of the silicon wafer using a tubular PECVD device. x Thin film, SiN x The film thickness is about 90 nm and the refractive index is 2.0. x During thin film deposition, the reaction gases in the tubular chamber are SiH4 and NH3, the working pressure is 1600 mTorr, the power is 12000 W, the temperature is 440℃, the flow rate of SiH4 gas is 980 sccm, the flow rate of NH3 gas is 8000 sccm, the silicon-nitrogen ratio is 1:5, and the deposition time is 10 min.

[0114] S14. The coated silicon wafer is screen-printed on the back to form a metal contact, and then sintered at 770°C to form an Ag-Si ohmic contact. Finally, the finished battery is obtained through light injection repair.

[0115] like Figure 1As shown, the TBC solar cell prepared in this embodiment includes an N-type silicon wafer 1, and the front side of the N-type silicon wafer 1 is provided with a pyramid velvet surface 10 and a passivation layer 11 in sequence; the back side of the N-type silicon wafer 1 is provided with a deposition area A and a deposition area B distributed in a cross-finger shape; the gap between the deposition area A and the deposition area B is an isolation area, and the isolation area is provided with a pyramid velvet surface 10 and a passivation layer 11 in sequence.

[0116] The surface of the deposition area A is provided with a boron diffusion layer A2 (thickness of about 800 nm), a phosphorus diffusion layer A3 (thickness of about 200 nm), a tunneling oxide layer A4, a phosphorus diffusion layer B5 (thickness of about 158 ​​nm), a passivation layer 11 and an electrode layer 12 in sequence.

[0117] The surface layer of the N-type silicon wafer 1 located at the bottom of the deposition area B is a boron diffusion layer B 13 (thickness is about 200 nm), and the surface of the deposition area B is provided with a tunneling oxide layer B 7, a boron diffusion layer C 8 (thickness is about 250 nm), a passivation layer 11 and an electrode layer 12 in sequence.

[0118] like Figure 1 As shown, the TBC solar cell prepared in this embodiment has a horizontal and vertical composite multi-junction structure (pn junction). Among them, the first pn junction a is a horizontal structure, consisting of a boron diffusion layer B (p-type region) and N-type silicon wafers on its left and right sides (the N-type silicon wafer base is an n-type region); the second pn junction b is a vertical structure, consisting of a boron diffusion layer A and an N-type silicon wafer located at the bottom; the third pn junction c is a vertical structure, consisting of a boron diffusion layer A and a phosphorus diffusion layer A (n-type region).

[0119] Example 2

[0120] The difference between Example 2 and Example 1 is that S5, that is, S5 of Example 2 adopts a phosphorus diffusion process of "high surface doping concentration + short oxidation advancement time", which is more conducive to phosphorus atoms passing through the tunneling oxide layer, as follows:

[0121] S5, phosphorus diffusion, so that the surface layer of the boron diffusion layer A, the inner layer and the surface layer of the intrinsic polysilicon layer A are transformed into phosphorus diffusion layer A (thickness of about 160 nm, phosphorus atomic concentration of 7E+19 cm -3 )、Phosphorus diffusion layer B (Phosphorus atomic concentration is 3.5E+20 cm -3) and PSG layer. The phosphorus diffusion conditions are: phosphorus diffusion temperature 790℃, diffusion time 20 min, POCl3 carried by nitrogen with a flow rate of 1100 sccm, O2 flow rate 700 sccm; then oxidation is promoted, and nitrogen containing POCl3 is introduced again at a flow rate of 2500 sccm for 5 min, oxidation promotion temperature 890℃, promotion time 10 min, O2 flow rate 8000 sccm, and a PSG layer with a thickness of about 35 nm is generated.

[0122] Comparative Example 1

[0123] S1. Select N-type single crystal silicon wafers cut with diamond wire, with a thickness of 150 μm and a size of 182.2 mm×186.7 mm. Put the cut silicon wafers into an alkaline polishing tank, maintain the temperature at 75°C, and perform double-sided polishing for 6 min. The polishing thickness is 4 μm and the thinning amount is 0.42 g.

[0124] S2, then the back surface of the polished silicon wafer is firstly grown by LPCVD tunneling SiO x layer, the O2 gas flow rate is 40000 sccm, the temperature is 600℃, the time is 600 s, and the tunneling SiO x The layer thickness is about 3 nm; then tunneling SiO x An i-poly-Si layer is grown again on the layer, with a SiH4 gas flow rate of 920 sccm, a temperature of 550 °C, a time of 3.3 h, a working gas pressure of 300 mTorr, and a thickness of the i-poly-Si layer of about 290 nm.

[0125] S3, then the high temperature boron diffusion method is used to transform the inner layer and the surface layer of the i-poly-Si layer into p + -poly-Si layer and BSG layer, boron diffusion temperature 850℃, diffusion time 10 min, BCl3 gas flow rate 200 sccm, O2 gas flow rate 1200 sccm, oxidation advancement temperature 950℃, O2 flow rate 7000 sccm, advancement time 30 min, BSG layer thickness is about 45 nm.

[0126] S4. Use picosecond laser to perform a patterned grooving of the BSG layer. The laser wavelength used is 532 nm, the frequency is 600 KHZ, the marking speed is 45000 mm / s, the power is 50 W, and the processing time is 3 s.

[0127] S5. The silicon wafer after laser patterning and slotting is placed in an alkaline solution for cleaning at a temperature of 75°C for 360 s and a corrosion depth of 1.7 μm.

[0128] S6, then use LPCVD to grow tunnel SiO x layer, the gas flow rate of O2 is 30000 sccm, the temperature is 600℃, the time is 450 s, and the tunneling SiO x The layer thickness is about 2.5 nm; then in the tunneling SiO x An i-poly-Si layer is grown again on the layer, with a SiH4 gas flow rate of 920 sccm, a temperature of 550 °C, a time of 1.5 h, a working gas pressure of 300 mTorr, and a thickness of the i-poly-Si layer of about 180 nm.

[0129] S7, using phosphorus diffusion method to transform the inner layer and surface layer of i-poly-Si layer into n + -poly-Si layer and PSG layer, phosphorus diffusion temperature 790℃, diffusion time 15 min, POCl3 is carried by nitrogen with a flow rate of 1000 sccm, O2 flow rate is 650 sccm, oxidation advancement temperature 890℃, O2 flow rate is 3000 sccm, advancement time is 20 min, PSG layer thickness is about 39 nm.

[0130] S8, then use picosecond laser to perform secondary patterning to open the PSG layer, so that p + -poly bottom corresponds to PSG layer and p + -poly and n + The PSG layer at the junction area of ​​-poly was loosened with a laser wavelength of 532 nm, a frequency of 600 KHz, a marking speed of 45000 mm / s, a power of 25 W, and a processing time of 2.7 s.

[0131] S9, using a chain machine to remove the n-plated silicon wafers on the front and side surfaces of the silicon wafers. + -poly-Si and p + -poly-Si layer, wherein the volume ratio of the hydrofluoric acid solution to the nitric acid solution in the acid tank is 1:4 (the concentration of the hydrofluoric acid solution is 49 wt %, and the concentration of the nitric acid solution is 69 wt %), and the belt speed is 1.3 m / min.

[0132] S10, put the silicon wafer that has been deplated into an alkaline texturing tank for wet cleaning of the laser slotted area on the back and integrated texturing of the front. The KOH solution concentration in the texturing tank is 1.7 wt%, the temperature is maintained at 82°C, the time is 7 min, and the weight is reduced by 0.36 g for cleaning and texturing. Since the silicon wafer has been deplated and there is no oxidation area on the front side, an effective light-trapping texture surface can be formed during the texturing process; and in the laser patterning area on the back side, the alkaline solution can effectively corrode the bottom poly-Si to form an isolated insulating structure. The subsequent acid (HF / HCl) cleaning tank of the texturing tank can further remove the residual PSG layer and BSG layer of the silicon wafer.

[0133] S11, using ALD deposition method to deposit AlO on the front and back sides of the processed silicon wafer x The film is generated by the reaction of Al(CH3)3 and water vapor, with a thickness of 8 nm and a process temperature of 250°C. Then, SiN is deposited on both sides using a tubular PECVD device. x Film, front SiN x The thickness of the film is about 82 nm, and the refractive index is 2.1; the back SiN x The thickness of the film is about 90 nm and the refractive index is 2.0; the reaction gases in the tubular cavity are SiH4 and NH3, the working pressure is 1600 mTorr, the power is 12000 W, the temperature is 440℃, the SiH4 gas flow rate is 980 sccm, the NH3 gas flow rate is 8000 sccm, the silicon-nitrogen ratio is 1:5, and the deposition time is 10 min.

[0134] S12. The coated sheet is screen-printed on the back to form a metal contact, and then sintered at 770°C to form an Ag-Si ohmic contact. Finally, the final TBC finished battery is obtained through light injection repair.

[0135] Comparative Example 2

[0136] The difference between Comparative Example 2 and Example 1 is that the S5 phosphorus diffusion process is different: the concentration of the POCl3 source is low and the time is short, resulting in insufficient phosphorus atoms passing through the tunneling oxide layer A to make the surface of the boron diffusion layer A unable to be fully inverted to n-type, as follows:

[0137] S5, phosphorus diffusion, so that the surface of the boron diffusion layer A and the intrinsic polysilicon layer A are transformed into the phosphorus diffusion layer A and the phosphorus diffusion layer B respectively, and a PSG layer is formed on the surface of the phosphorus diffusion layer B. The conditions for phosphorus diffusion are: phosphorus diffusion temperature 790℃, diffusion time 3.5 min, POCl3 is carried by nitrogen with a flow rate of 370 sccm, O2 flow rate is 400 sccm, after the initial diffusion is completed, O2 is introduced for oxidation promotion, the oxidation promotion temperature is 870℃, the gas flow rate of O2 is 1200 sccm, and the promotion time is 3.2 min; the thickness of PSG is about 25 nm.

[0138] Comparative Example 3

[0139] Compared with Example 1, Comparative Example 3 differs only in that: the second boron diffusion process in S9 is different: the concentration of the BCl3 source is low and the time is short, resulting in insufficient boron atoms passing through the tunneling oxide layer to convert the surface layer of the bottom N-type silicon wafer into p-type, resulting in the inability of boron atoms to fully penetrate the tunneling oxide layer B during the secondary boron diffusion, as follows:

[0140] S9. The conditions for boron diffusion are: boron diffusion temperature 830°C, diffusion time 4 min, BCl3 gas flow rate 40 sccm, O2 gas flow rate 450 sccm, oxidation advancement temperature 930°C, O2 flow rate 2000 sccm, advancement time 15 min, and the resulting BSG layer B thickness is about 32 nm.

[0141] Performance Testing

[0142] The electrical properties of the solar cells obtained in the embodiments and comparative examples were tested, and the results are shown in Table 1.

[0143] Table 1

[0144]

[0145] From the comparison of the data in Table 1, we can see that:

[0146] (1) From the comparison of the data of Example 1 and Comparative Example 1, it can be seen that the solar cell having the lateral and longitudinal composite multi-junction structure of the present invention has better performance.

[0147] (2) By comparing the data of Comparative Examples 2 and 3 with Example 1, it can be seen that Example 1 can optimize the process parameters of S5 phosphorus diffusion and S9 boron diffusion, so that phosphorus atoms and boron atoms can pass through the tunneling oxide layer more easily, thereby forming more ideal phosphorus diffusion layer A and boron diffusion layer B, respectively, and finally obtaining a higher performance battery.

[0148] (3) Compared with Example 1, Example 2 S5 adopts a more optimized "high surface doping concentration + short oxidation advancement time" phosphorus diffusion process, which can make the PSG layer contain a higher concentration of phosphorus source. Its advantages are: in the subsequent secondary boron diffusion high temperature process: on the one hand, the phosphorus atoms can pass through the tunneling oxide layer A again to form a phosphorus diffusion layer A with better diffusion effect; on the other hand, the phosphorus atom concentration in the phosphorus diffusion layer B can be maintained at a stable value and will not be greatly reduced, thereby ultimately obtaining a higher performance solar cell.

[0149] The raw materials and equipment used in the present invention, unless otherwise specified, are all commonly used raw materials and equipment in the art; the methods used in the present invention, unless otherwise specified, are all conventional methods in the art.

[0150] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any simple modification, change and equivalent transformation made to the above embodiment based on the technical essence of the present invention still falls within the protection scope of the technical solution of the present invention.

Claims

1. A transverse and longitudinal composite multi-junction TBC solar cell, comprising an N-type silicon wafer, the front side of which is provided with a pyramid velvet surface and a passivation layer in sequence; characterized in that: The back side of the N-type silicon wafer is provided with a deposition area A and a deposition area B which are distributed in a cross-finger shape; the gap between the deposition area A and the deposition area B is an isolation area, and the surface of the isolation area is provided with a pyramid velvet surface and a passivation layer in sequence; The surface of the deposition area A is provided with a boron diffusion layer A, a phosphorus diffusion layer A, a tunneling oxide layer A, a phosphorus diffusion layer B, a passivation layer and an electrode layer in sequence; The surface layer of the N-type silicon wafer located at the bottom of the deposition area B is a boron diffusion layer B, and the surface of the deposition area B is provided with a tunneling oxide layer B, a boron diffusion layer C, a passivation layer and an electrode layer in sequence; Wherein: the boron diffusion layer C is a boron-doped polysilicon layer, and the phosphorus diffusion layer B is a phosphorus-doped polysilicon layer.

2. The lateral and longitudinal composite multi-junction TBC solar cell according to claim 1, characterized in that: The thickness of the boron diffusion layer A is 200-1300 nm; The thickness of the boron diffusion layer B is 100-500 nm; The thickness of the boron diffusion layer C is 100-300 nm; The thickness of the phosphorus diffusion layer A is 50-400 nm; The thickness of the phosphorus diffusion layer B is 100-300 nm.

3. A method for preparing a transverse and longitudinal composite multi-junction TBC solar cell according to claim 1 or 2, characterized in that include: S1, N-type silicon wafer double-sided polishing; S2, boron diffusion, generating boron atomic concentration of 1E+18~1E+19 cm on the back side -3 Boron diffusion layer A and BSG layer A; S3, remove BSG layer A; S4, depositing a tunneling oxide layer A and an intrinsic polysilicon layer A on the surface of the boron diffusion layer A; S5, phosphorus diffusion, so that the surface layer of the boron diffusion layer A, the inner layer and the surface layer of the intrinsic polysilicon layer A are converted to phosphorus atomic concentrations of 5E+18~2E+20 cm -3 Phosphorus diffusion layer A, phosphorus atomic concentration> 1E+20 cm -3 Phosphorus diffusion layer B and PSG layer; S6, removing the PSG layer in the deposition area B and the isolation area by laser patterning; S7, alkali cleaning to remove the deposition layer in the deposition area B and the isolation area; S8, depositing a tunneling oxide layer B and an intrinsic polysilicon layer B on the surfaces of the deposition area A, the deposition area B and the isolation area in sequence; S9, boron diffusion, so that the surface layer of the N-type silicon wafer in the deposition area B and the bottom of the isolation area, the inner layer and the surface layer of the intrinsic polysilicon layer B are converted to boron atomic concentrations of 1E+19~2E+19 cm -3 The boron diffusion layer B has a boron atomic concentration of 1E+19~1E+20 cm -3 Boron diffusion layer C and BSG layer B; S10, removing the BSG layer B in the deposition area A and the isolation area by laser patterning; S11, removing the coating; S12, cleaning and velveting; S13, double-sided coating; S14, screen printing, sintering, light injection.

4. The preparation method according to claim 3, characterized in that: In S2, the conditions for boron diffusion are: boron diffusion temperature 900~950℃, diffusion time 10~50 min, BCl3 flow rate 50~500 sccm, O2 flow rate 500~2000 sccm; oxidation advancement temperature 1000~1050℃, O2 flow rate 3000~50000 sccm, advancement time 30~80 min, and the resulting BSG layer A has a thickness of 30~70 nm.

5. The preparation method according to claim 3, characterized in that: In S4, The conditions for depositing the tunnel oxide layer A are: O2 flow rate 10000~80000 sccm, temperature 400~800°C, time 200~1000s, and the thickness of the obtained tunnel oxide layer A is 1~10 nm; The conditions for depositing the intrinsic polysilicon layer A are: SiH4 flow rate 300~2000 sccm, temperature 500~700℃, time 2~4 h, working pressure 100~500 mTorr, and the thickness of the obtained intrinsic polysilicon layer A is 100~300 nm.

6. The preparation method according to claim 3, characterized in that: In S5, the phosphorus diffusion conditions are: phosphorus diffusion temperature 750~850℃, diffusion time 5~30 min, POCl3 is carried by nitrogen with a flow rate of 500~2500 sccm, and O2 flow rate 500~3000 sccm; then oxidation is promoted at a temperature of 850~950℃, a promotion time of 5~60 min, and an O2 flow rate of 1000~10000sccm; the thickness of the obtained PSG layer is 30~70 nm.

7. The preparation method according to claim 3, characterized in that: In S5, the conditions for phosphorus diffusion are: phosphorus diffusion temperature 750~850℃, diffusion time 5~30 min, POCl3 carried by nitrogen with a flow rate of 500~2500 sccm, O2 flow rate 500~3000 sccm; then oxidation is promoted, and POCl3 carried by nitrogen with a flow rate of 1000~5000 sccm is introduced again simultaneously, for 2~10 min, oxidation promotion temperature 850~950℃, promotion time 5~20 min, O2 flow rate 5000~20000sccm; the thickness of the obtained PSG layer is 30~70 nm.

8. The preparation method according to claim 3, characterized in that: In S8, The conditions for depositing the tunnel oxide layer B are: O2 flow rate 10000~80000 sccm, temperature 400~800°C, time 200~1000s, and the thickness of the obtained tunnel oxide layer B is 1~10 nm; The conditions for depositing the intrinsic polysilicon layer B are: SiH4 flow rate 300~2000 sccm, temperature 500~700℃, time 2~4 h, working pressure 100~500 mTorr, and the thickness of the obtained intrinsic polysilicon layer B is 100~300 nm.

9. The preparation method according to claim 3, characterized in that: In S9, the conditions for boron diffusion are: boron diffusion temperature 800-950°C, diffusion time 5-50 min, BCl3 flow rate 50-500 sccm, O2 flow rate 500-2000 sccm; oxidation advancement temperature 900-1050°C, O2 flow rate 3000-50000 sccm, advancement time 30-80 min, and the resulting BSG layer B has a thickness of 30-70 nm.

10. The preparation method according to claim 3, characterized in that: In S10, the conditions of the laser patterning treatment are: laser wavelength 400-600 nm, frequency 500-700 KHz, marking speed 40000-50000 mm / s, power 10-50 W, and treatment time 1-5 s.

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