Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a method for manufacturing the same, wherein the semiconductor device comprises: a substrate; a plurality of shallow trench isolation structures arranged in the substrate, wherein the plurality of shallow trench isolation structures divide a plurality of active areas in the substrate; a convex structure arranged in the substrate, and the convex structure is located between adjacent shallow trench isolation structures, wherein the height of the convex structure is less than the height of the shallow trench isolation structure; a doped region arranged in the substrate, and the doped region and the convex structure are distributed in adjacent active areas; a gate oxide layer arranged on the shallow trench isolation structure and the convex structure, and on the substrate; and a polysilicon layer arranged on the gate oxide layer, and the polysilicon layer covers the convex structure and part of the doped region. The present invention provides a semiconductor device and a method for manufacturing the same, which can improve the voltage resistance of semiconductor products without increasing the area occupied by the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit manufacturing, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] Increasing the area of ​​semiconductor products can improve the performance of semiconductor products, for example, enabling semiconductor products to withstand higher operating voltages. The higher the operating voltage that a semiconductor product can withstand, the less likely it is to break down under the same power and voltage conditions.

[0003] Increasing the area of ​​semiconductor products will also bring with it a series of problems such as difficulty in improving product yield, difficulty in controlling product costs, and difficulty in ensuring product packaging and heat dissipation technologies. In addition, increasing the area of ​​semiconductor products does not conform to the development trend of electronic devices that are light, thin, small, and high-performance. Therefore, increasing the area of ​​semiconductor products is also difficult to adapt to the upgrade of supporting electronic devices. Summary of the invention

[0004] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can improve the voltage resistance of the semiconductor product without increasing the area occupied by the semiconductor device.

[0005] In order to solve the above technical problems, the present invention is achieved through the following technical solutions:

[0006] The present invention provides a semiconductor device, comprising:

[0007] substrate;

[0008] A plurality of shallow trench isolation structures are arranged in the substrate, wherein the plurality of shallow trench isolation structures divide a plurality of active areas in the substrate;

[0009] A convex structure is disposed in the substrate, and the convex structure is located between adjacent shallow trench isolation structures, wherein the height of the convex structure is smaller than the height of the shallow trench isolation structure;

[0010] A doped region, disposed in the substrate, wherein the doped region and the convex structure are distributed in adjacent active regions;

[0011] a gate oxide layer, disposed on the shallow trench isolation structure, the convex structure, and the substrate; and

[0012] A polysilicon layer is disposed on the gate oxide layer, and the polysilicon layer covers the convex structure and a portion of the doped region.

[0013] In one embodiment of the present invention, there are a plurality of the convex structures, and the plurality of convex structures are arrayed and distributed in the active area.

[0014] In one embodiment of the present invention, the semiconductor device includes a first type active region and a second type active region, the first type active region is arranged between adjacent second type active regions, wherein the first type active region is the active region where the convex structure is located, and the second type active region is the active region where the doped region is located.

[0015] In an embodiment of the present invention, the semiconductor device comprises a channel, the channel is located in the coverage area of ​​the polysilicon layer, and two ends of the channel are connected to different doping regions.

[0016] In one embodiment of the present invention, the height of the protrusion structure is 1 / 2 to 1 / 3 of the height of the shallow trench isolation structure.

[0017] The present invention provides a method for manufacturing a semiconductor device, comprising the following steps:

[0018] providing a substrate;

[0019] Forming a shallow trench isolation structure and a convex structure in the substrate, wherein the shallow trench isolation structure divides a plurality of active areas in the substrate, the convex structure is located between adjacent shallow trench isolation structures, and the height of the convex structure is smaller than the height of the shallow trench isolation structure;

[0020] forming a doped region in the substrate, wherein the doped region and the convex structure are distributed in adjacent active regions;

[0021] forming a gate oxide layer on the shallow trench isolation structure, the convex structure and the substrate; and

[0022] A polysilicon layer is formed on the gate oxide layer, wherein the polysilicon layer covers the convex structure and a portion of the doped region.

[0023] In one embodiment of the present invention, before forming the protrusion structure, the shallow trench isolation structure is formed in the substrate.

[0024] In one embodiment of the present invention, the step of forming the convex structure or forming the shallow trench isolation structure includes:

[0025] Providing a mask layer and forming an etching window in the mask layer, wherein the ratio of the etching window width for forming the protrusion structure to the etching window width for forming the shallow trench isolation structure is 1:200-1:1;

[0026] Etching the substrate from the etching window to form a shallow trench or groove; and

[0027] The shallow trench or the recess is filled to form the shallow trench isolation structure or the convex structure.

[0028] In one embodiment of the present invention, the protrusion structure and the shallow trench isolation structure are formed in the substrate simultaneously.

[0029] In one embodiment of the present invention, the steps of forming the convex structure and the shallow trench isolation structure include:

[0030] Providing a mask layer, and forming a first etching window and a second etching window in the mask layer, wherein a width of the second etching window is less than half of a width of the first etching window;

[0031] Etching the substrate from the first etching window and the second etching window to simultaneously form shallow trenches and recesses; and

[0032] The shallow trench and the recess are filled simultaneously to form the shallow trench isolation structure and the convex structure respectively.

[0033] As described above, the present invention provides a semiconductor device and a method for manufacturing the same, and the unexpected technical effect is that the present invention is used to form a high-voltage semiconductor device, and can improve the voltage resistance of the device without increasing the device occupied area, and can ensure the process yield. According to different process requirements or cost requirements, the increased voltage resistance can be flexibly adjusted to balance the improvement of the device voltage resistance and the process efficiency.

[0034] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0036] Figure 1 Schematic diagram of the structure of a substrate, a nitride layer and a substrate oxide layer in one embodiment of the present invention.

[0037] Figure 2 Schematic diagram of the structure of the first etching window in one embodiment of the present invention.

[0038] Figure 3 FIG. 4 is a schematic diagram of the structure of a shallow trench in an embodiment of the present invention.

[0039] Figure 4 FIG. 1 is a schematic diagram of a structure for forming a liner oxide layer in one embodiment of the present invention.

[0040] Figure 5FIG. 4 is a schematic diagram of forming a shallow trench isolation structure according to an embodiment of the present invention.

[0041] Figure 6 FIG. 1 is a schematic diagram of a semiconductor device after the first type nitride layer is removed according to an embodiment of the present invention.

[0042] Figure 7 FIG. 4 is a schematic diagram of a second etching window in an embodiment of the present invention.

[0043] Figure 8 Schematic diagram of the cross-sectional structure of a groove in one embodiment of the present invention.

[0044] Fig. 9 FIG. 4 is a schematic diagram of the cross-sectional structure of a convex portion in one embodiment of the present invention.

[0045] Fig.10 FIG. 4 is a schematic diagram of the cross-sectional structure of a convex portion in one embodiment of the present invention.

[0046] Fig.11 FIG. 4 is a schematic diagram of a first etching window and a second etching window in another embodiment of the present invention.

[0047] Fig.12 Schematic diagram of the structure of shallow grooves and recesses in one embodiment of the present invention.

[0048] Fig.13 FIG. 1 is a schematic diagram of forming a shallow trench isolation structure and a convex structure in one embodiment of the present invention.

[0049] Fig.14 FIG. 1 is a schematic cross-sectional view of a protrusion and a shallow trench isolation structure in one embodiment of the present invention.

[0050] Fig.15 FIG. 4 is a schematic cross-sectional view of a polysilicon layer in one embodiment of the present invention.

[0051] Fig.16 FIG. 4 is a schematic top view of a semiconductor device according to an embodiment of the present invention.

[0052] Fig.17 FIG. 1 is a schematic top view of a convex structure in one embodiment of the present invention.

[0053] Fig.18 FIG. 1 is a schematic top view of a convex structure in one embodiment of the present invention.

[0054] Fig.19 FIG. 1 is a schematic top view of a convex structure in one embodiment of the present invention.

[0055] Fig. 20 FIG. 4 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

[0056] Fig.21 FIG. 4 is a schematic diagram of carrier concentration in a channel according to an embodiment of the present invention.

[0057] In the figure: 100, substrate; 101, shallow trench; 1011, pad oxide layer; 102, shallow trench isolation structure; 1021, first filling part; 1022, second filling part; 103, groove; 104, convex structure; 105, gate oxide layer; 106, polysilicon layer; 107, doping region; 108, metal contact column; 200, substrate oxide layer; 200a, first type substrate oxide layer; 200b, second type substrate oxide layer; 300, nitride layer; 300a, first type nitride layer; 300b, second type nitride layer; 400, first photoresist layer; 400a, first type photoresist pattern; 401a, first etching window; 400b, second type photoresist pattern; 401b, first etching window; 402b, second etching window; 500, second photoresist layer; 501, second etching window. DETAILED DESCRIPTION

[0058] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0059] According to the operating voltage range of semiconductor products, semiconductor products can be divided into low-voltage devices and high-voltage devices. The operating voltage of the high-voltage device is, for example, 8V, 15V, 28V, and 32V. In this embodiment, the semiconductor device is a high-voltage device, and specifically can be a semiconductor device based on a laterally diffused metal oxide semiconductor (LDMOS). In this embodiment, the semiconductor device may be, but is not limited to, a field effect transistor (FET), a metal-oxide-semiconductor field-effect transistor (MOSFET), a complementary metal oxide semiconductor (CMOS), an insulated gate bipolar transistor (IGBT), a fast recovery diode (FRD), a high-speed and high-efficiency rectifier diode (HED), a constant voltage diode, a high-frequency diode, a light-emitting diode (LED), a gate turn off thyristor (GTO), a light triggered thyristor (LTT), a thyristor (Thyristor), a charge coupled device (CCD image sensor), a digital signal processor (DSP), a photo relay (Photo Relay) or a microprocessor (Micro Processor) and other semiconductor devices or one or more thereof.

[0060] See also Figure 1 As shown, the present invention provides a method for manufacturing a semiconductor device. First, a substrate 100 is provided. The substrate 100 is, for example, a silicon substrate for forming a semiconductor device. The substrate 100 may include a substrate and a silicon layer disposed above the substrate. The substrate may be, for example, silicon (Si), silicon carbide (SiC), sapphire (Al 2 O 3 ), gallium arsenide (GaAs), lithium aluminate (LiAlO 2) and other semiconductor substrate materials, and a silicon layer is formed on the substrate. The present invention does not limit the material and thickness of the substrate 100. In this embodiment, the substrate 100 can be an intrinsic semiconductor, or ions can be implanted into the substrate 100 to form an N-type semiconductor or a P-type semiconductor, and the present invention does not specifically limit this. It should be noted that the substrate 100 provided by the present invention can be a silicon substrate, or it can include a silicon substrate and an epitaxial layer arranged on the substrate. And the present invention does not limit the epitaxial layer to be homoepitaxial or heteroepitaxial.

[0061] See also Figures 1 to 3 As shown, in one embodiment of the present invention, a shallow trench 101 is then formed on the substrate 100. In this embodiment, a substrate oxide layer 200 is first formed on the substrate 100, a nitride layer 300 is formed on the substrate oxide layer 200, and a first photoresist layer 400 is formed on the nitride layer 300. In this embodiment, silicon oxide is deposited on the surface of the substrate 100 by chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD) to form the substrate oxide layer 200. Then, silicon nitride is deposited on the substrate oxide layer 200 by chemical vapor deposition to form the nitride layer 300. The substrate oxide layer 200 and the nitride layer 300 can protect the surface of the substrate 100 from damage. Then, photoresist is spin-coated on the surface of the nitride layer 300 to form the first photoresist layer 400. Then, the first photoresist layer 400 is exposed and developed, so as to pattern the first photoresist layer 400 and form a first type photoresist pattern 400a. The first type photoresist pattern 400a includes a first etching window 401a. The first etching window 401a corresponds to the area where the shallow trench 101 is to be formed, so the width of the first etching window 401a can be set equal to the width of the shallow trench 101. Then, using the first type nitride layer 300a as a mask, the nitride layer 300, the substrate oxide layer 200 and the substrate 100 are patterned by dry etching to form the first type nitride layer 300a, the first type substrate oxide layer 200a and the shallow trench 101. Then, the first type photoresist pattern 400a is removed by an ashing process.

[0062] Please refer to 3 to Figure 5 As shown, in one embodiment of the present invention, the shallow trench 101 is filled to form a shallow trench isolation structure 102. In this embodiment, firstly, oxide is deposited on the groove wall of the shallow trench 101 by chemical vapor deposition to form a liner oxide layer 1011. The material of the liner oxide layer 1011 can be silicon oxide. In this embodiment, the liner oxide layer 1011 is connected to the first type substrate oxide layer 200a to form a completed thin film structure, such as Figure 4As shown. The thin film structure formed therein covers the surface of the substrate 100 and the surface of the shallow trench 101. Then, oxide is deposited in the shallow trench 101 by chemical vapor deposition, for example, silicon oxide is deposited. Figure 5 As shown, in this embodiment, the cross-sectional shape of the shallow trench 101 is a trapezoid, and the cross-sectional width of the shallow trench 101 increases along the direction close to the surface of the substrate 100. Among them, the shallow trench 101 has a rounded corner or an obtuse corner. In this embodiment, the shallow trench isolation structure 102 includes a first filling part 1021 and a second filling part 1022. Among them, the first filling part 1021 is filled in the shallow trench 101, the second filling part 1022 is connected to the first filling part 1021, and the second filling part 1022 is filled in the etching hole of the first type nitride layer 300a. Among them, the etching hole refers to the hole-like structure formed after the first type nitride layer 300a is etched. The present invention does not limit the specific shape of the hole-like structure, and the shape and position of the specific etching hole correspond to the first etching window 401a. In this embodiment, the surface of the second filling part 1022 can be higher than the surface of the first type nitride layer 300a, or lower than the surface of the first type nitride layer 300a, and the present invention does not limit this.

[0063] See 5 and Figure 6 As shown, in one embodiment of the present invention, the first type nitride layer 300a and the second filling portion 1022 are then removed. In this embodiment, the first type nitride layer 300a is removed by wet etching, wherein the first type substrate oxide layer 200a can prevent the etching solution from contaminating the active area. It should be noted that the substrate 100 can be an intrinsic semiconductor, and a variety of ions can be injected into the substrate 100 to form an N-type semiconductor or a P-type semiconductor. The shallow trench isolation structure 102 is partially disposed in the substrate 100, and a plurality of active areas are separated in the substrate 100. After removing the first type nitride layer 300a, the second filling portion 1022 and the first type substrate oxide layer 200a can be polished by chemical mechanical polishing (CMP). In this embodiment, the stop layer of the chemical mechanical polishing can be the surface of the substrate 100. After the chemical mechanical polishing, the first type substrate oxide layer 200a and the second filling portion 1022 are removed, thereby forming the shallow trench isolation structure 102 in the semiconductor device described in the present invention, as shown in FIG. Figure 6 shown.

[0064] See 6 and Figure 7 ,as well as Fig.10As shown, in one embodiment of the present invention, a second photoresist layer 500 is then formed on the substrate 100, the shallow trench isolation structure 102, and the pad oxide layer 1011. Specifically, a photoresist is spin-coated on the surface of the substrate 100, the surface of the shallow trench isolation structure 102, and the top surface of the pad oxide layer 1011, and then the spin-coated photoresist is exposed and developed to form the second photoresist layer 500. In this embodiment, the second photoresist layer 500 includes a plurality of second etching windows 501. The widths of the plurality of second etching windows 501 are equal, and the second etching windows 501 are d 1 The distance between adjacent shallow trench isolation structures 102 is d 1 It should be noted that due to the thickness of the liner oxide layer 1011 and the distance d between adjacent shallow trench isolation structures 102 1 The thickness of the liner oxide layer 1011 is much smaller than the distance d between the adjacent shallow trench isolation structures 102. 1 , so get the spacing d 1 The thickness of the pad oxide layer 1011 can be ignored. The number of the second etching windows 501 is, for example, n. Figure 7 Seven second etching windows 501 are shown. In this embodiment, the width d of the second etching window 501 is 1 The ratio of the spacing D is, for example, 1:200 to 1:1. And the number of the second etching windows 501 is at least 1. It should be noted that in the embodiments included in the present invention, the second etching window 501 can be, for example, 1, and the width d of the second etching window 501 is 1 and the spacing D are equal, at this time, the window edge of the second etching window 501 coincides with the edge of the shallow trench isolation structure 102, and the subsequently formed convex structure 104 can be connected to the shallow trench isolation structures 102 on both sides. This is an extreme case in the embodiment of the present invention, and can also play a role in improving the withstand voltage of the semiconductor device without increasing the area of ​​the semiconductor device. In other embodiments of the present invention, a plurality of second etching windows 501 can be arranged between adjacent shallow trench isolation structures 102 to form a plurality of convex structures 104 in subsequent steps, and take into account both ensuring the process yield and achieving the technical effect of improving the withstand voltage of the semiconductor device without changing the device area. Among them, the spacing d between adjacent shallow trench isolation structures 102 1 The value of is limited by the specific semiconductor device design, and the present invention does not limit this. Therefore, in this embodiment, the upper limit of the number of the second etching windows 501 is not limited.

[0065] Please refer to 7 to Fig. 9As shown, in one embodiment of the present invention, the second photoresist layer 500 is used as a mask to etch the substrate 100, form a plurality of grooves 103 on the substrate 100, and fill the grooves 103 to form a convex structure 104. In this embodiment, after filling the grooves 103, a gate oxide layer 105 is continuously formed on the substrate 100 and the convex structure 104, as well as on the shallow trench isolation structure 102. In this embodiment, the substrate 100 is etched by dry etching, and the plasma gas etches the surface of the substrate 100 through the second etching window 501, thereby forming the grooves 103. The width of the grooves 103 is equal to the width of the second etching window 501, and the depth of the grooves 103 is, for example, 1 / 2 to 1 / 3 of the height of the shallow trench isolation structure 102. The plurality of grooves 103 are located between adjacent shallow trench isolation structures 102, and the plurality of grooves 103 in this embodiment are distributed at equal intervals. After the grooves 103 are formed, the second photoresist layer 500 is removed. Then, the groove 103 is filled with oxide, such as silicon oxide, by chemical vapor deposition to form a convex structure 104. After the groove 103 is filled, the process of chemical vapor deposition of oxide is continued until a complete oxide film is formed on the substrate 100, and the oxide film is used as a gate oxide layer 105. The convex structure 104 and the gate oxide layer 105 are formed successively in the same deposition process, and the convex structure 104 is connected to the gate oxide layer 105. Specifically, the gate oxide layer 105 covers the convex structure 104, the shallow trench isolation structure 102, the surface of the substrate 100 and the pad oxide layer 1011.

[0066] See also Figure 1 , Fig. 9 and Fig.11 As shown, in another embodiment of the present invention, after forming the first photoresist layer 400, the first photoresist layer 400 is exposed and developed, so as to pattern the first photoresist layer 400 and form a second type of photoresist pattern 400b. The second type of photoresist pattern 400b includes a plurality of first etching windows 401b and a plurality of second etching windows 402b. The first etching window 401b corresponds to an area where the shallow groove 101 is to be formed, and the second etching window 402b corresponds to an area where the groove 103 is to be formed. The plurality of second etching windows 402b are located between adjacent first etching windows 401b. The plurality of second etching windows 402b are distributed at equal intervals. In this embodiment, the width of the second etching window 402b is d 1 , and the distance between adjacent second etching windows 402b is d 2 . The distance between adjacent first etching windows 401b is D. The number of second etching windows 402b is, for example, n. For example, Fig.11 Seven second etching windows 402b are shown. In this embodiment, the second etching window 402b has a width d 1The ratio of the spacing d to the spacing D is greater than, for example, 1:200, and less than, for example, 1:1. And the number of the second etching windows 402b is at least 1. 1 The value of is limited by the specific semiconductor device design, and the present invention does not limit this. Therefore, in this embodiment, there is no upper limit on the number of second etching windows 402b. In this embodiment, the spacing between adjacent second etching windows 402b is d 2 . See Figure 1 , Fig.11 and Fig.12 As shown, in another embodiment of the present invention, the second type of photoresist pattern 400b is used as a mask to etch the nitride layer 300, the substrate oxide layer 200 and the substrate 100 to form the second type of nitride layer 300b, the second type of substrate oxide layer 200b and the shallow trench 101, and the groove 103. In this embodiment, the nitride layer 300, the substrate oxide layer 200 and the substrate 100 are etched by dry etching. The shallow trench 101 corresponds to the first etching window 401b, and the groove 103 corresponds to the second etching window 402b. In this embodiment, the width of the second etching window 402b is much smaller than the width of the first etching window 401b, so the etching rate of forming the groove 103 is much lower than the etching rate of forming the shallow trench 101. When the shallow trench 101 reaches a preset depth, the depth of the groove 103 is much smaller than the depth of the shallow trench 101. Specifically, the width of the second etching window 402b is less than at least half of the width of the first etching window 401b. In this embodiment, the depth of the recess 103 is, for example, 1 / 2 to 1 / 3 of the depth of the shallow trench 101. After the etching of the substrate 100 is completed, the second type photoresist pattern 400b is removed.

[0067] See also Figure 1 , Figure 12 to Figure 14As shown, in another embodiment of the present invention, the shallow trench 101 and the groove 103 are filled to form a shallow trench isolation structure 102 and a convex structure 104. In this embodiment, oxide, such as silicon oxide, is deposited in the shallow trench 101 and the groove 103, and in the etching hole of the second type nitride layer 300b by chemical vapor deposition. Wherein, when forming the shallow trench isolation structure 102, the oxide is filled in the shallow trench 101 to form a first filling part 1021. Continue filling, the oxide is filled in the etching hole of the second type nitride layer 300b and the etching hole of the second type substrate oxide layer 200b, to form a second filling part 1022, wherein the second filling part 1022 is connected to the first filling part 1021. Wherein the second filling part 1022 may not fill the etching hole of the second type nitride layer 300b. When forming the second filling part 1022, an oxide accumulation structure is simultaneously formed on the convex structure 104. Then, the second type nitride layer 300b, the second filling part 1022, the oxide accumulation structure and the second type substrate oxide layer 200b are removed to expose the surface of the substrate 100, the surface of the shallow trench isolation structure 102 and the surface of the convex structure 104. The surface of the substrate 100, the surface of the shallow trench isolation structure 102 and the surface of the convex structure 104 are flush. In this embodiment, the second type nitride layer 300b is removed by wet etching, wherein in the process of removing the second type nitride layer 300b, the second type substrate oxide layer 200b can prevent the etching solution from contaminating the active area. Then, the second filling part 1022, the oxide accumulation structure and the second type substrate oxide layer 200b are removed by dry etching.

[0068] See also Figure 1 , Figures 13 to 15 As shown, in another embodiment of the present invention, a gate oxide layer 105 is then formed. In one embodiment, in the step of forming the gate oxide layer 105, after removing the second type of nitride layer 300b, the second filling portion 1022, the oxide accumulation structure and the second type of substrate oxide layer 200b, the gate oxide layer 105 is formed on the substrate 100, the shallow trench isolation structure 102 and the convex structure 104. In this embodiment, the gate oxide layer 105 can be formed by chemical vapor deposition, and the gate oxide layer 105 is an oxide, and specifically can be silicon oxide. In another embodiment, in the step of forming the gate oxide layer 105, the second type of nitride layer 300b is removed, and the oxide accumulation structure and the second type of substrate oxide layer 200b are used as the gate oxide layer 105. In this embodiment, the thickness of the gate oxide layer 105 on the convex structure 104 and the gate oxide layer 105 on the substrate 100 can be different. And specifically, as Fig.13 As shown, the thickness of the gate oxide layer 105 located on the protrusion structure 104 is less than or equal to, for example, 1000 angstroms, and the thickness of the gate oxide layer 105 located on the substrate 100 is less than or equal to, for example, 500 angstroms.

[0069] See also Figure 1 and Fig. 9 , Figures 14 to 19 As shown, in the present invention, after forming the gate oxide layer 105, a polysilicon layer 106 is formed on the gate oxide layer 105. In one embodiment of the present invention and another embodiment of the present invention, after forming the gate oxide layer 105, polysilicon is deposited on the gate oxide layer 105 by chemical vapor deposition to form a polysilicon layer, wherein the polysilicon layer covers the surface of the gate oxide layer 105. Then, with the assistance of the photoresist layer, the polysilicon layer is patterned to form a Fig.15 and Fig.16 The polysilicon layer 106 is shown. In the present invention, the polysilicon layer 106 covers the protrusion structure 104, and the polysilicon layer 106 covers a portion of the shallow trench isolation structure 102. Fig.16 As shown, Fig.16 FIG. 1 shows a schematic top view of the layout of the polysilicon layer 106 and the convex structure 104. The gate oxide layer 105 is on the surface of the substrate 100 and the shallow trench isolation structure 102. To facilitate the display of the shallow trench isolation structure 102, Fig.16 The position of the shallow trench isolation structure 102 is shown. In fact, the shallow trench isolation structure 102 is located under the gate oxide layer 105. The top view of the plurality of convex structures 104 is a long rectangular strip, and the plurality of convex structures 104 are arranged in a linear array. It should be noted that Fig.16 Only a schematic diagram of the top view distribution of a convex structure 104 is shown. For example, in an active area, along a direction parallel to the shallow trench isolation structure 102, the convex structure 104 can be a continuous rectangular strip or an elliptical strip, such as Fig.17 and Fig.18 As shown. For example, in an active area, along a direction parallel to the shallow trench isolation structure 102, the convex structure 104 can also be a plurality of rectangular strips distributed discontinuously, and gaps 1041 are set between adjacent convex structures 104. The present invention does not limit the top view structure of the convex structure 104, and the convex structure 104 can be any regular array shape. In the present invention, as Fig.16 As shown, the length of the protrusion structure 104 is less than or equal to the width of the polysilicon layer 106. The length of the protrusion structure 104 is the dimension of the protrusion structure 104 along a direction parallel to the shallow trench isolation structure 102. The width of the polysilicon layer 106 is the dimension of the polysilicon layer 106 along a direction parallel to the shallow trench isolation structure 102.

[0070] See also Figure 1 and Fig. 9 , Figures 14 to 16 ,as well as Fig. 20As shown, in the present invention, after forming the polysilicon layer 106, ions can be implanted into the active area to form a doped area 107. The doped area 107 can be used as a source area or a drain area. Then, a portion of the gate oxide layer 105 is etched to expose the surface of the doped area 107. Then, a metal contact column 108 is formed on the doped area 107. In the step of forming the metal contact column 108, a dielectric layer is first formed on the gate oxide layer 105 and the polysilicon layer 106, and then the dielectric layer is patterned to form an etching hole in the area where the metal contact column 108 is to be formed. Then, a metal material, such as aluminum or copper, is deposited in the etching hole to form a metal contact column 108. The present invention does not show the dielectric layer. The metal contact column 108 is formed on the doped area 107, and can also be formed on the doped area 107 and the polysilicon layer 106. In the present invention, the convex structure 104 and the doped area 107 are distributed in different active areas. The active region where the convex structure 104 is located is the first type of active region, and the active region where the doped region 107 is located is the second type of active region, wherein the first type of active region and the second type of active region are adjacent, and the first type of active region is arranged between adjacent second type of active regions. When a high voltage is applied to the polysilicon layer 106, the exchange of electrons between two adjacent doped regions 107 is completed through the gate oxide layer 105. In the present invention, the doped region 107 located on one side of the first type of active region has an acceptor impurity, and the doped region 107 located on the other side of the first type of active region has a donor impurity.

[0071] See also Fig. 20 and Fig.21 As shown, in the present invention, the semiconductor device includes a substrate 100, a shallow trench isolation structure 102, a convex structure 104, a doped region 107, a gate oxide layer 105, a polysilicon layer 106 and a metal contact column 108. The shallow trench isolation structure 102 and the convex structure 104 are arranged in the substrate 100, a plurality of convex structures 104 are arranged between adjacent shallow trench isolation structures 102, and a plurality of convex structures 104 are arranged in an array. The gate oxide layer 105 is arranged on the substrate 100 and on the shallow trench isolation structure 102, as well as on the convex structure 104. The polysilicon layer 106 is arranged on the gate oxide layer 105. According to the semiconductor device provided by the present invention, the carrier concentration of the saturation region channel is tested, and the concentration diagram obtained is as shown in FIG. Fig.21 As shown. The carrier concentration in the area corresponding to the convex structure 104 is significantly reduced. Specifically, the carrier concentration in the channel shows a phenomenon of alternating saturation and decline. In the channel, the concentration of free carriers is reduced, and the threshold voltage is significantly increased, so the voltage resistance of the semiconductor device is also improved, and the occupied area of ​​the semiconductor device remains unchanged.

[0072] The present invention provides a semiconductor device and a manufacturing method thereof, wherein the semiconductor device includes a substrate, a plurality of shallow trench isolation structures, a convex structure, a doped region, a gate oxide layer and a polysilicon layer. The plurality of shallow trench isolation structures are arranged in the substrate, and the plurality of shallow trench isolation structures divide a plurality of active regions in the substrate. The convex structure is arranged in the substrate, and the convex structure is located between adjacent shallow trench isolation structures, wherein the height of the convex structure is less than the height of the shallow trench isolation structure. The doped region is arranged in the substrate, wherein the doped region and the convex structure are distributed in adjacent active regions. The gate oxide layer is arranged on the shallow trench isolation structure and the convex structure, as well as on the substrate. The polysilicon layer is arranged on the gate oxide layer, and the polysilicon layer covers the convex structure and part of the doped region. The unexpected technical effect of the present invention is that the present invention is used to form a high-voltage semiconductor device, and can improve the voltage resistance of the device without increasing the area occupied by the device, and can ensure the process yield. According to different process requirements or cost requirements, the degree of voltage resistance can be flexibly adjusted to balance the improvement of the voltage resistance of the device and the process efficiency.

[0073] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A semiconductor device, characterized in that: include: substrate; A plurality of shallow trench isolation structures are arranged in the substrate, wherein the plurality of shallow trench isolation structures divide a plurality of active areas in the substrate; A convex structure is disposed in the substrate, and the convex structure is located between adjacent shallow trench isolation structures, wherein the height of the convex structure is smaller than the height of the shallow trench isolation structure; A doped region, disposed in the substrate, wherein the doped region and the convex structure are distributed in adjacent active regions; A gate oxide layer is disposed on the shallow trench isolation structure, the convex structure, and the substrate; as well as A polysilicon layer, disposed on the gate oxide layer, wherein the polysilicon layer covers the convex structure and a portion of the doped region; The semiconductor device comprises a first type active region and a second type active region, the first type active region is arranged between adjacent second type active regions, the first type active region is the active region where the convex structure is located, and the second type active region is the active region where the doped region is located; The semiconductor device comprises a channel, wherein the channel is located within the coverage range of the polysilicon layer, and the two ends of the channel are connected to different doping regions, wherein the doping region at one end of the channel is located on one side of the first type of active region, and the doping region at the other end of the channel is located on the other side of the first type of active region, wherein the doping region located on one side of the first type of active region has donor impurities, and the doping region located on the other side of the first type of active region has acceptor impurities, wherein the doping region is a source region or a drain region, one end of the channel is connected to the drain region, and the other end of the channel is connected to the source region.

2. A semiconductor device according to claim 1, characterized in that: There are a plurality of the convex structures, and the plurality of convex structures are arrayed and distributed in the active area.

3. A semiconductor device according to claim 1, characterized in that: The height of the convex structure is 1 / 2 to 1 / 3 of the height of the shallow trench isolation structure.

4. A method for manufacturing a semiconductor device, characterized in that: The following steps are involved: providing a substrate; Forming a shallow trench isolation structure and a convex structure in the substrate, wherein the shallow trench isolation structure divides a plurality of active areas in the substrate, the convex structure is located between adjacent shallow trench isolation structures, and the height of the convex structure is smaller than the height of the shallow trench isolation structure; forming a doped region in the substrate, wherein the doped region and the convex structure are distributed in adjacent active regions, wherein the semiconductor device comprises a first type of active region and a second type of active region, the first type of active region is arranged between adjacent second type of active regions, wherein the first type of active region is the active region where the convex structure is located, and the second type of active region is the active region where the doped region is located; forming a gate oxide layer on the shallow trench isolation structure, the convex structure and the substrate; and forming a polysilicon layer on the gate oxide layer, wherein the polysilicon layer covers the convex structure and a portion of the doped region; The semiconductor device comprises a channel, wherein the channel is located within the coverage range of the polysilicon layer, and the two ends of the channel are connected to different doping regions, wherein the doping region at one end of the channel is located on one side of the first type of active region, and the doping region at the other end of the channel is located on the other side of the first type of active region, wherein the doping region located on one side of the first type of active region has donor impurities, and the doping region located on the other side of the first type of active region has acceptor impurities, wherein the doping region is a source region or a drain region, one end of the channel is connected to the drain region, and the other end of the channel is connected to the source region.

5. The method for manufacturing a semiconductor device according to claim 4, characterized in that: Before forming the protrusion structure, the shallow trench isolation structure is formed in the substrate.

6. The method for manufacturing a semiconductor device according to claim 5, characterized in that: The steps of forming the convex structure or forming the shallow trench isolation structure include: Providing a mask layer and forming an etching window in the mask layer, wherein the ratio of the etching window width for forming the protrusion structure to the etching window width for forming the shallow trench isolation structure is 1:200-1:1; Etching the substrate from the etching window to form a shallow trench or groove; and The shallow trench or the recess is filled to form the shallow trench isolation structure or the convex structure.

7. The method for manufacturing a semiconductor device according to claim 4, characterized in that: The convex structure and the shallow trench isolation structure are formed in the substrate simultaneously.

8. The method for manufacturing a semiconductor device according to claim 7, characterized in that: The steps of forming the convex structure and the shallow trench isolation structure include: Providing a mask layer, and forming a first etching window and a second etching window in the mask layer, wherein a width of the second etching window is less than half of a width of the first etching window; Etching the substrate from the first etching window and the second etching window to simultaneously form shallow trenches and recesses; and The shallow trench and the recess are filled simultaneously to form the shallow trench isolation structure and the convex structure respectively.

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