Adaptive power supply circuit and power supply method for asynchronous successive approximation analog-to-digital converter

Abstract

The present invention discloses an adaptive power supply circuit and power supply method of an asynchronous successive approximation analog-to-digital converter, belonging to the field of integrated circuit technology, wherein the asynchronous successive approximation analog-to-digital converter includes a capacitor DAC, a comparator, a delay logic, a successive approximation logic and a counter, and the adaptive power supply circuit includes a reference voltage generating circuit and a digitally controlled LDO, wherein the reference voltage generating circuit is used to provide a reference analog voltage for the capacitor DAC, and the digitally controlled LDO is used to provide an adjustable voltage for the comparator, the delay logic, the successive approximation logic and the counter through the digitally controlled LDO control logic. The present invention can realize automatic calibration of the successive approximation ADC, and can generate a clock number that meets the number of DAC conversion bits at different process temperature angles.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an adaptive power supply circuit and a power supply method for an asynchronous successive approximation analog-to-digital converter. Background Art

[0002] The successive approximation analog-to-digital converter uses a sample-and-hold circuit to collect and hold the voltage of the input analog signal, uses a successive approximation register to gradually infer the value of the input signal, and then verifies the correctness of the inference through a comparator. In early successive approximation ADCs, a synchronous clock was usually relied on to ensure that each operation step was performed in a predetermined time sequence, and the conversion rate was low. However, with the advancement of semiconductor technology, the sampling rate of the successive approximation ADC has increased significantly. As the sampling rate reaches hundreds of MHz, if the synchronous clock continues to be used, the synchronous clock rate will reach GHz. This high-speed clock transmission will generate a lot of power consumption and increase the complexity and cost of the clock design.

[0003] In order to avoid the use of high-speed clocks, successive approximation analog-to-digital converters are often implemented using asynchronous architectures in deep submicron processes. That is, the clock circuit only needs to provide a sampling clock to the successive approximation ADC, and the successive approximation ADC uses logic delays to generate an asynchronous clock to provide a clock for each bit of the internal DAC approximation. Although asynchronous clocks can reduce power consumption, the delay logic has a large difference in delay at different process temperature angles even at the same voltage. Therefore, at the slowest process temperature angle, if the number of clocks generated by the delay just meets the conversion step requirements of the capacitor DAC, at the fastest process temperature angle, the number of asynchronous clocks is too large, resulting in a too short conversion time for each bit, which causes comparator judgment errors and ADC performance degradation. Summary of the invention

[0004] In order to improve the adaptability of ADC asynchronous clock generation circuit to process temperature angle, this scheme proposes an adaptive power supply circuit and power supply method for asynchronous successive approximation analog-to-digital converter. By dynamically adjusting the voltage, it is ensured that the comparator, delay logic, successive approximation logic and counter have appropriate voltage supply under different working conditions, thereby optimizing the overall performance of the asynchronous successive approximation analog-to-digital converter.

[0005] According to a first aspect of the present invention, an adaptive power supply circuit of an asynchronous successive approximation analog-to-digital converter is provided, wherein the asynchronous successive approximation analog-to-digital converter comprises a capacitor DAC, a comparator, a delay logic, a successive approximation logic and a counter.

[0006] The adaptive power supply circuit includes a reference voltage generating circuit and a digitally controlled LDO. The reference voltage generating circuit is used to provide a reference analog voltage for a capacitor DAC. The digitally controlled LDO is used to provide an adjustable voltage for a comparator, a delay logic, a successive approximation logic and a counter through a digitally controlled LDO control logic.

[0007] According to the above technical solution, by dynamically adjusting the voltage, it is ensured that the comparator, delay logic, successive approximation logic and counter have appropriate voltage supply under different working conditions, thereby reducing unnecessary power consumption and reducing the impact of power supply noise and voltage fluctuations on the performance of the analog-to-digital converter, thereby optimizing the overall performance of the analog-to-digital converter.

[0008] Optionally, in the adaptive power supply circuit of the asynchronous successive approximation analog-to-digital converter provided by the present invention, one end of the digitally controlled LDO control logic is connected to the counter, and the other end is connected to the digitally controlled LDO. The digitally controlled LDO control logic is used to adjust the output voltage of the digitally controlled LDO with the sampling clock of the successive approximation ADC as a period, read the count value of the counter at the end of each sampling clock cycle, and output the control word of the digitally controlled LDO.

[0009] In the above technical solution, by reading the count value of the counter at the end of each sampling period, the digital control LDO control logic can adjust the voltage of the digital control LDO in real time to adapt to actual working requirements and improve the accuracy and stability of the system.

[0010] Optionally, in the adaptive power supply circuit of the asynchronous successive approximation analog-to-digital converter provided by the present invention, the counter is used to read the bit sequence output by the comparator through the NAND gate, and count the bit sequence to obtain a count value; the target value of the counter is set to N+M1 / M2, where N is the number of bits of the successive approximation ADC, M1 and M2 are the values ​​of the margin, and M1 <M2。

[0011] The above technical solution, through precise voltage regulation and reasonable target value setting, helps to improve the overall stability of the system and reduce the impact of power supply noise and fluctuations on ADC performance.

[0012] Optionally, in the adaptive power supply circuit of the asynchronous successive approximation analog-to-digital converter provided by the present invention, the digitally controlled LDO includes multiple power units, and the digitally controlled LDO control logic is used to increase the output voltage by increasing the number of power units when the count value of the counter is less than N+M1; and to reduce the output voltage by reducing the number of power units when the count value of the counter is greater than N+M2.

[0013] The above technical solution can accurately control the output voltage of the LDO by dynamically adjusting the number of power units, ensuring that the power supply voltage can be adjusted in real time when the counter count value changes, thereby optimizing the performance of the ADC.

[0014] Optionally, in the adaptive power supply circuit of the asynchronous successive approximation analog-to-digital converter provided by the present invention, the reference voltage generating circuit uses an operational amplifier to form a buffer circuit.

[0015] Optionally, in the adaptive power supply circuit of the asynchronous successive approximation analog-to-digital converter provided by the present invention, the capacitor DAC includes multiple proportional capacitor units, and the number of capacitors of the high-order bit capacitor unit is twice the number of capacitors of the low-order bit capacitor unit; in the sampling stage, the upper plates of all capacitors of the capacitor DAC are connected to the input, and the lower plates are grounded, and the input voltage is sampled onto the capacitor; in the conversion stage, the comparator is used to compare the input voltage with the reference voltage and output the comparison result; the successive approximation logic connects the comparator and the capacitor DAC respectively, including the LATCH and switch of each bit capacitor unit, the LATCH is used to store the output of each bit, and the switch is used to control the capacitor of the corresponding bit to be connected to the reference voltage or ground according to the output of each bit.

[0016] Optionally, in the adaptive power supply circuit of the asynchronous successive approximation analog-to-digital converter provided by the present invention, the conversion cycle of each bit is asynchronously generated by delay logic, including comparator delay, LATCH delay, DAC switching time and DAC setup time.

[0017] Optionally, in the adaptive power supply circuit of the asynchronous successive approximation analog-to-digital converter provided by the present invention, in each bit conversion cycle, the comparator is used to compare the positive and negative terminal voltages of the input capacitor DAC and output a comparison result. The comparison result outputs a high level through the NAND gate, and the high level returns through the delay logic to reset the comparator. When the comparator is reset, both the positive and negative terminals output a high level, and after passing through the NAND gate, a low level is output, and after returning through the delay logic, the reset state of the comparator is released.

[0018] Optionally, in the adaptive power supply circuit of the asynchronous successive approximation analog-to-digital converter provided by the present invention, the asynchronous delay period generated by the delay logic is equal to the comparator delay plus twice the delay logic delay, and is greater than or equal to the sum of the comparator delay, LATCH delay, DAC switching time and DAC setup time.

[0019] The above technical solution ensures that each component of the system (comparator, LATCH, DAC, etc.) has enough time to complete the operation by setting the asynchronous delay period to be the comparator delay plus twice the delay logic delay, thereby avoiding system instability caused by timing mismatch.

[0020] According to a second aspect of the present invention, there is provided an adaptive power supply method for an asynchronous successive approximation analog-to-digital converter, which is implemented based on the adaptive power supply circuit of the asynchronous successive approximation analog-to-digital converter according to the first aspect of the present invention, and comprises:

[0021] Obtain the count value of the counter, and set the target value of the counter to N + M1 / M2, where N is the number of bits of the successive approximation ADC, and M1 and M2 are the values of the margins, and M1 < M2; when the count value of the counter is less than N + M1, increase the number of power units to increase the output voltage; when the count value of the counter is greater than N + M2, reduce the number of power units to reduce the output voltage until the count value of the counter is equal to the target value.

[0022] According to the adaptive power supply circuit and power supply method of the asynchronous successive approximation analog-to-digital converter provided by the present invention, by dynamically adjusting the voltage, it is ensured that the comparator, delay logic, successive approximation logic, and counter have appropriate voltage supplies in different working states. Since the delay is inversely proportional to the power supply voltage, it can ensure that each component (comparator, LATCH, DAC, etc.) of the successive approximation ADC has sufficient time to complete the operation, thereby avoiding system instability caused by timing mismatch.

[0023] Therefore, this solution can achieve automatic calibration of the successive approximation ADC, can generate the number of clocks that meet the DAC conversion bits at different process temperature corners, reduce unnecessary power consumption, reduce the influence of power supply noise and voltage fluctuations on the performance of the analog-to-digital converter, and thus optimize the overall performance of the analog-to-digital converter.

[0024] The above description is only an overview of the technical solution of the present invention. In order to be able to understand the technical means of the present invention more clearly, it can be implemented according to the content of the specification. And in order to make the above and other purposes, features and advantages of the present invention more obvious and understandable, the specific embodiments of the present invention are specifically listed below. Brief Description of the Drawings

[0025] By reading the detailed description of the preferred embodiments below, various other advantages and benefits will become clear to those of ordinary skill in the art. The drawings are only for the purpose of showing the preferred embodiments and are not considered to be a limitation of the present invention. And throughout the drawings, the same reference numerals are used to represent the same components. In the drawings:

[0026] Figure 1 Shows the structural schematic diagram of the successive approximation analog-to-digital converter;

[0027] Figure 2 Shows the schematic diagram of the adaptive power supply circuit of the asynchronous successive approximation analog-to-digital converter according to an embodiment of the present invention;

[0028] Figure 3 Shows the schematic diagram of the capacitor DAC reference voltage generation circuit according to an embodiment of the present invention;

[0029] Figure 4A timing diagram of an asynchronous successive approximation analog-to-digital converter according to an embodiment of the present invention is shown;

[0030] Figure 5 A schematic diagram of a digitally controlled LDO power supply logic of an asynchronous successive approximation analog-to-digital converter according to an embodiment of the present invention is shown;

[0031] Figure 6 A schematic diagram of the internal architecture of a digitally controlled LDO according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0032] The successive approximation register (SAR) samples the input analog signal to the capacitor DAC. The comparator starts to compare from the highest bit, and the output value of the capacitor DAC is gradually adjusted by the successive approximation logic to approximate the voltage of the input signal. The internal logic delay is used to generate an asynchronous clock to provide a clock for each internal bit. Once the successive approximation logic determines the state of all bits, the ADC will combine these bits into a digital value as a digital representation of the input signal. Since the delay logic has a large difference in delay at different process temperature angles, the ADC performance may be degraded. In order to make the asynchronous clock generate the number of clocks that just meet the DAC conversion bit number at different process temperature angles, this solution uses an adaptive power supply voltage to automatically adjust the delay of the asynchronous clock generation circuit to achieve automatic calibration of the successive approximation ADC.

[0033] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0034] Figure 1 Figure 2 shows a schematic diagram of the structure of a successive approximation analog-to-digital converter. Figure 1 As shown, the successive approximation analog-to-digital converter includes a capacitor DAC, a comparator and a successive approximation logic, wherein the capacitor DAC is composed of a plurality of proportional capacitor units, which is responsible for converting the digital signal into an analog voltage signal, and the bit positions increase from left to right, and the number of capacitor units in the high position is twice the number of capacitor units in the low position. The comparator is used to compare the analog voltage output by the capacitor DAC with the voltage of the input analog signal, and output the comparison result. The successive approximation logic includes LATCH and switches of each level of bits, LATCH is used to store the output of each bit, and the switch is used to control the capacitor of the corresponding bit to be connected to the reference voltage Vref or the ground GND according to the bit output.

[0035] Its working process is divided into the sampling stage and the conversion stage. In the sampling stage, the upper plates of all capacitors on the capacitor DAC are connected to the voltage Vin of the input signal, and the lower plates are grounded GND, so that the input voltage Vin is sampled to all capacitor units of the capacitor DAC. The main task of this stage is to capture and hold the voltage value of the input signal.

[0036] At the end of the sampling phase, all connections to the input signal are disconnected and the capacitor DAC enters the conversion phase. During the conversion phase, the comparator transmits the comparison result to the successive approximation logic, which is responsible for gradually adjusting the output of the capacitor DAC, starting from the highest bit, by adjusting the capacitor unit of each bit to approximate the voltage of the input signal. The matching accuracy of the capacitor DAC, the accuracy of the comparator, and the implementation of the successive approximation logic will affect the overall performance of the ADC.

[0037] In successive approximation ADCs, power supply design is critical, especially when dealing with high-speed and high-precision applications. Figure 2 FIG. 2 shows a schematic diagram of an adaptive power supply circuit of an asynchronous successive approximation analog-to-digital converter according to an embodiment of the present invention. Figure 2 As shown in the figure, the power supply circuit contains two power domains, one of which provides analog voltage reference for capacitor DAC with high precision requirements, and the other is a digitally controlled LDO (low dropout regulator) that provides power for comparators, delay logic, successive approximation logic, and counters. The digitally controlled LDO has good noise suppression performance and precise voltage regulation capabilities, and can adjust the output voltage to adapt to different working conditions and load changes to ensure the stability of the power supply.

[0038] Figure 3 FIG. 4 shows a schematic diagram of a capacitor DAC reference voltage generating circuit according to an embodiment of the present invention. Figure 3 As shown in the figure, since the reference voltage stability and noise level of the capacitor DAC directly determine the accuracy of the analog-to-digital converter, the reference voltage generation circuit of the capacitor DAC uses a high-performance operational amplifier to form a buffer circuit to stabilize the reference voltage. Since the total capacitance of the capacitor DAC is small, the load of the buffer circuit is relatively small. Even if the bandwidth of the buffer circuit is high, a high-precision voltage reference can still be achieved at a very low power consumption cost.

[0039] Except for the capacitor DAC with precision requirements, other circuit units of the successive approximation ADC are powered by digitally controlled LDOs. This is because other circuits of the successive approximation ADC, such as comparators, delay logic, successive approximation logic, and counters, have no requirements for the accuracy of the power supply voltage. Since the delay is inversely proportional to the power supply voltage, the delay of the asynchronous clock generation circuit can be adjusted by adjusting the LDO output voltage.

[0040] For an asynchronous successive approximation ADC, the conversion cycle of each bit is generated asynchronously by the delay logic. Figure 4 FIG. 2 shows a timing diagram of an asynchronous successive approximation analog-to-digital converter according to an embodiment of the present invention. Figure 4 As shown, the conversion cycle of each bit is asynchronously generated by the delay logic, and the conversion cycle of each bit includes comparator delay, LATCH delay, switching switch delay, and DAC setup time.

[0041] In each bit conversion cycle, the comparator compares the positive and negative voltages of the input capacitor DAC and outputs the comparison result. The comparator outputs 1 through the NAND gate, and 1 returns through the delay logic to reset the comparator. After the comparator is reset, both the positive and negative ends output level 1, and after the NAND gate, they output 0, and after the delay logic returns, the reset state of the comparator is released. At this time, the comparator is ready to compare the next bit.

[0042] Therefore, the asynchronous delay period is equal to the comparator delay plus twice the delay logic delay. This period needs to be greater than or equal to the sum of the comparator delay, LATCH delay, DAC switching time and DAC setup time. In other words, this period cannot be too short, otherwise the DAC will not be fully established, resulting in the input comparator voltage still in the process of establishment, not the final correct value, which will cause the comparator comparison to be wrong; this period cannot be too long, otherwise the sum of the conversion periods of all bits will be greater than the total allowed conversion time, resulting in the inability of all bits to complete the conversion within the total conversion time, resulting in a decrease in the effective number of bits.

[0043] In deep submicron technology, logic delay varies greatly with process angle, temperature angle and voltage angle. In design, if a fixed voltage value is used to power the successive approximation logic, the asynchronous logic rate will vary greatly at different process temperature angles. At the fastest process temperature angle, there may not be enough time to build the capacitor DAC; at the slowest process temperature angle, the conversion cycle of each bit is too long, so that the total conversion time cannot generate the conversion time of all bits, resulting in a significant reduction in the effective number of bits.

[0044] In order to make the successive approximation ADC maintain a stable conversion time at each process temperature angle, this solution uses a power supply circuit that is adaptive to the process temperature angle and performs automatic calibration by adjusting the supply voltage. Figure 5 FIG. 2 shows a schematic diagram of a digitally controlled LDO power supply logic of an asynchronous successive approximation analog-to-digital converter according to an embodiment of the present invention. Figure 5 As shown, the digital control LDO adjusts the output voltage through the digital control LDO control logic. One end of the digital control LDO control logic is connected to the counter, and the other end is connected to the digital control LDO. The digital control LDO control logic is used to adjust the output voltage of the digital control LDO with the sampling clock of the successive approximation ADC as the cycle, and reads the count value of the counter at the end of each sampling clock cycle.

[0045] The specific calibration principle is as follows: In each conversion cycle, the comparator outputs a comparison result, the NAND gate outputs a 0 / 1 conversion, and the counter counts the 0 / 1 sequence. If the number of bits of the ADC is N, ideally, the counter output result is N, indicating that the conversion time just meets the requirements of the conversion cycle. To ensure a certain margin, the target of the counter can be set to N + M1 / M2, where M1 and M2 are the values of the margin, and M1 < M2.

[0046] If the result of the counter is less than N + M1, the digital control LDO control logic increases the number of units of the digital control LDO, raises the voltage, increases the speed of the asynchronous delay logic, and increases the number of conversion cycles; if the result of the counter is greater than N + M2, the digital control LDO control logic reduces the number of units of the digital control LDO, lowers the voltage, reduces the speed of the asynchronous delay logic, and reduces the number of conversion cycles.

[0047] Figure 6 The internal architecture schematic diagram of the digital control LDO according to an embodiment of the present invention is shown. As Figure 6 shown, the digital control LDO includes a plurality of power units (power unit 1, 2......n). When the load current is the same, increasing the number of turned-on power units can increase the output voltage, and reducing the number of turned-on power units can reduce the output voltage. The digital control LDO control logic outputs a control word of bit1-n, which is adjusted at the sampling clock period of the ADC. At the end of each sampling period, the counter result is read. If the counting result is small, one power unit is added. If the counting result is large, one power unit is reduced. At the beginning of the next sampling period, the counter result is cleared and the next counting continues.

[0048] Through the above adaptive algorithm, it can be ensured that the digital control LDO provides a voltage that adapts to the process temperature angle, and at the same time, the input of the reference voltage is avoided, ensuring that the successive approximation ADC can achieve automatic calibration.

[0049] Based on the above adaptive power supply circuit of the asynchronous successive approximation analog-to-digital converter, an embodiment of the present invention further provides an adaptive power supply method for an asynchronous successive approximation analog-to-digital converter, including:

[0050] Obtaining the count value of the counter, the target value of the counter is set to N + M1 / M2, where N is the number of bits of the successive approximation ADC, and M1 and M2 are the values of the margin, and M1 < M2; when the count value of the counter is less than N + M1, the number of power units is increased to raise the output voltage; when the count value of the counter is greater than N + M2, the number of power units is reduced to lower the output voltage until the count value of the counter is equal to the target value.

[0051] According to the adaptive power supply circuit and power supply method of the asynchronous successive approximation analog-to-digital converter provided by the present invention, by dynamically adjusting the voltage, it is ensured that the comparator, delay logic, successive approximation logic and counter have appropriate voltage supply in different working states. Since the delay is inversely proportional to the power supply voltage, it can be ensured that each component of the successive approximation ADC (comparator, LATCH, DAC, etc.) has enough time to complete the operation, thereby avoiding system instability caused by timing mismatch.

[0052] Therefore, this scheme can realize automatic calibration of successive approximation ADC, can generate clock numbers that meet the DAC conversion bit number under different process temperature angles, reduce unnecessary power consumption, and reduce the impact of power supply noise and voltage fluctuations on the performance of the analog-to-digital converter, thereby optimizing the overall performance of the analog-to-digital converter.

[0053] In the description provided herein, a large number of specific details are described. However, it is understood that embodiments of the present invention can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0054] Those skilled in the art will appreciate that the modules or units or components of the devices in the examples disclosed herein may be arranged in the devices described in the embodiment, or alternatively may be located in one or more devices different from the devices in the examples. The modules in the foregoing examples may be combined into one module or may be divided into multiple submodules.

[0055] Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments may be combined into one module or unit or component, and furthermore may be divided into a plurality of submodules or subunits or subcomponents.

[0056] Furthermore, those skilled in the art will appreciate that although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features from different embodiments is meant to be within the scope of the present invention and to form different embodiments.

[0057] As used herein, unless otherwise specified, the use of ordinal numbers "first," "second," "third," etc. to describe common objects merely indicates that different instances of similar objects are involved, and is not intended to imply that the objects so described must have a given order in time, space, order, or in any other manner.

[0058] Although the present invention has been described according to a limited number of embodiments, it will be apparent to those skilled in the art, with the benefit of the above description, that other embodiments may be envisioned within the scope of the invention thus described. In addition, it should be noted that the language used in this specification is selected primarily for readability and teaching purposes, rather than for explaining or defining the subject matter of the present invention. Therefore, many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the appended claims. The disclosure of the present invention is illustrative and not restrictive with respect to the scope of the present invention, and the scope of the present invention is defined by the appended claims.

Claims

1. An adaptive power supply circuit for an asynchronous successive approximation analog-to-digital converter, the asynchronous successive approximation analog-to-digital converter comprising a capacitor DAC, a comparator, a delay logic, a successive approximation logic and a counter, characterized in that: The adaptive power supply circuit includes a reference voltage generation circuit and a digitally controlled LDO. The reference voltage generation circuit is used to provide a reference analog voltage for the capacitive DAC. The digitally controlled LDO is used to provide an adjustable voltage for the comparator, delay logic, successive approximation logic, and counter through the digitally controlled LDO control logic. One end of the digitally controlled LDO control logic is connected to the counter, and the other end is connected to the digitally controlled LDO. The digitally controlled LDO control logic is used to adjust the output voltage of the digitally controlled LDO with the sampling clock of the successive approximation ADC as the period, read the count value of the counter at the end of each sampling clock cycle, and output the control word of the digitally controlled LDO. The counter is used to read the bit sequence output by the comparator through the NAND gate, count the bit sequence to obtain a count value, and the target value of the counter is set to N + M1 / M2, where N is the number of bits of the successive approximation ADC, and M1 and M2 are the values of the margins, and M1 < M2. The digitally controlled LDO includes multiple power units. The digitally controlled LDO control logic is used to increase the output voltage by increasing the number of power units when the count value of the counter is less than N + M1, and decrease the output voltage by decreasing the number of power units when the count value of the counter is greater than N + M2.

2. The adaptive power supply circuit of the asynchronous successive approximation analog-to-digital converter according to claim 1, characterized in that: The reference voltage generation circuit uses an operational amplifier to form a buffer circuit.

3. The adaptive power supply circuit of the asynchronous successive approximation analog-to-digital converter according to claim 1, characterized in that: The capacitive DAC includes multiple proportional capacitive units. The number of capacitors in the high-order bit capacitive unit is twice that of the low-order bit capacitive unit. In the sampling stage, the upper plates of all the capacitors of the capacitive DAC are connected to the input, and the lower plates are grounded to sample the input voltage onto the capacitors. In the conversion stage, the comparator is used to compare the input voltage and the reference voltage and output a comparison result. The successive approximation logic is respectively connected to the comparator and the capacitive DAC, and includes LATCHes and switches of each bit capacitive unit. The LATCH is used to store the output of each bit, and the switch is used to control the corresponding bit capacitor to be connected to the reference voltage or grounded according to the output of each bit.

4. The adaptive power supply circuit of the asynchronous successive approximation analog-to-digital converter according to claim 3, characterized in that: The conversion period of each bit is generated asynchronously by the delay logic, including comparator delay, LATCH delay, DAC switch time, and DAC settling time.

5. The adaptive power supply circuit of the asynchronous successive approximation analog-to-digital converter according to claim 4, characterized in that: In the conversion period of each bit, the comparator is used to compare the positive and negative terminal voltages of the input capacitive DAC, output a comparison result. The comparison result passes through the NAND gate to output a high level. The high level returns through the delay logic to reset the comparator. When the comparator is reset, both the positive and negative terminals output a high level. After passing through the NAND gate, it outputs a low level and returns through the delay logic to release the reset state of the comparator.

6. The adaptive power supply circuit of the asynchronous successive approximation analog-to-digital converter according to claim 5, characterized in that: The asynchronous delay period generated by the delay logic is equal to the comparator delay plus twice the delay logic delay, and is greater than or equal to the sum of the comparator delay, LATCH delay, DAC switch time, and DAC settling time.

7. An adaptive power supply method for an asynchronous successive approximation analog-to-digital converter, implemented based on the adaptive power supply circuit for the asynchronous successive approximation analog-to-digital converter as claimed in any one of claims 1 to 6, characterized in that: Including: Obtain the count value of the counter, and set the target value of the counter to N + M1 / M2, where N is the number of bits of the successive approximation ADC, and M1 and M2 are the values of the margins, and M1 < M2. When the count value of the counter is less than N+M1, the number of power units is increased to improve the output voltage; when the count value of the counter is greater than N+M2, the output voltage is reduced by reducing the number of power units until the count value of the counter is equal to the target value.

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