A control circuit for clock signal delay

Abstract

The purpose of the present invention is to provide a control circuit for clock signal delay, the circuit comprising: a first variable delay line, a second variable delay line and a 1UI / 2UI calibration circuit; the input end of the first variable delay line is connected to the clock signal, and the output end is connected to the 1UI / 2UI calibration circuit; the input end of the second variable delay line is connected to the clock signal, and the output end is connected to the 1UI / 2UI calibration circuit; the 1UI / 2UI calibration circuit is calibrated according to the clock signals output by the first variable delay line and the second variable delay line. The present invention calibrates so that DQS samples the correct DQ, and obtains a delay line of the clock signal 1UI / 2UI through calibration, and is not affected by the setup time and hold time of the D flip-flop itself, thereby achieving a more accurate 1UI / 2UI calibration.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to a control circuit for clock signal delay. Background Art

[0002] With the development of integrated circuit technology, the speed of circuits is getting faster and faster, and the clock frequency is constantly increasing. The principle of clock sampling is based on the Nyquist sampling theorem, which states that in the sampling process, the sampling frequency must be greater than or equal to twice the highest frequency in the analog signal in order to completely restore the original analog signal. The clock sampling process mainly includes two steps: sampling and quantization. Sampling refers to the instantaneous sampling of the analog signal under the trigger of a given clock signal. Quantization is the conversion of the continuous analog signal value obtained by sampling into a discrete digital signal value. In clock sampling, the clock signal plays a vital role. The stability and accuracy of the clock signal directly affect the sampling accuracy and the quality of signal restoration. Usually, the clock signal is provided by a crystal oscillator, generated by a frequency-stable oscillator, and the frequency is adjusted by a frequency division circuit.

[0003] In the application of DDR IP, the unit time interval (UI, 1UI is half of the clock cycle) of data (DQ) and sampling clock (DQS) is getting smaller and smaller. The relative positions of DQ and DQS need to be trained so that DQS can sample the correct DQ and reserve enough spare time. In the DDR PHY circuit, it is necessary to obtain a delay line equal to the 1UI and 2UI times, and then adjust the relative position of DQS to complete the sampling of DQ. However, in the existing 1UI calibration circuit, it is greatly affected by the setup and hold time of the D flip-flop itself, resulting in inaccurate calibration. Figure 2 As shown in the figure, when the phase difference between CLK_DLY and CLK_NDLY is less than 1UI, FLAG0 is 0 and FLAG1 is 1. When variable delay line 2 gradually increases and CLK_DLY is pushed to a phase difference of 1UI with CLK_NDLY, FLAG0 jumps to 1 and FLAG1 jumps to 0. At this time, the phase difference between the two variable delay lines is 1UI. However, this result is affected by the setup and hold time of the D flip-flop itself. When CLK_DLY and CLK_NDLY sample each other, the two D flip-flops themselves have setup time and hold time, resulting in an inaccurate 1UI calibration result. The calibration result is essentially a superposition of the 1UI value of the clock signal and the setup time / hold time. Summary of the invention

[0004] The purpose of the present invention is to provide a control circuit for clock signal delay, which can realize the relative position training of DQ and DQS in DDR PHY IP through calibration, so that DQS samples the correct DQ and reserves enough margin. The delay line of the clock signal 1UI / 2UI is obtained through calibration, and it is not affected by the setup time and hold time of the D flip-flop itself, so as to realize more accurate 1UI / 2UI calibration.

[0005] A control circuit for clock signal delay, comprising: a first variable delay line, a second variable delay line and a 1UI / 2UI calibration circuit;

[0006] The input end of the first variable delay line is connected to the clock signal, and the output end is connected to the 1UI / 2UI calibration circuit;

[0007] The input end of the second variable delay line is connected to the clock signal, and the output end is connected to the 1UI / 2UI calibration circuit;

[0008] The 1UI / 2UI calibration circuit performs calibration according to the clock signals output by the first variable delay line and the second variable delay line.

[0009] Preferably, the 1UI / 2UI calibration circuit comprises: a first trigger, a second trigger, a third trigger, a fourth trigger, a fifth trigger, a first amplifier, a first signal selector, a second signal selector and a phase detection module;

[0010] The D terminal of the first trigger is connected to CAL EN, the Q terminal is connected to the input terminal of the first amplifier, and the CLK terminal is connected to CLKNDLY;

[0011] The D terminal of the second trigger is connected to the output terminal of the first amplifier, the Q terminal is connected to the 0 terminal of the first signal selector, and the CLK terminal is connected to CLK NDLY;

[0012] The D terminal of the third trigger is connected to CAL EN, the Q terminal is connected to the 1 terminal of the first signal selector, and the CLK terminal is connected to CLKNDLY;

[0013] The D terminal of the fourth trigger is connected to CAL EN, the Q terminal is connected to the 0 terminal of the second signal selector, and the CLK terminal is connected to CLKDLY;

[0014] The D terminal of the fifth trigger is connected to CAL EN, the Q terminal is connected to the 1 terminal of the second signal selector, and the CLK terminal is connected to CLKDLY;

[0015] The output ends of the first signal selector and the output end of the second signal selector are both connected to the input end of the phase detection module.

[0016] Preferably, the first variable delay line is a delay line with a fixed length.

[0017] Preferably, the length of the second variable delay line is adjusted according to an output of the calibration circuit.

[0018] Preferably, the phase detection module includes: a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube and a first NOT gate;

[0019] The gate of the first MOS tube is connected to the output end of the second signal selector, and the drain is connected to the drain of the second MOS tube and the drain of the fifth MOS tube;

[0020] The drain of the second MOS tube is connected to the gate of the third MOS tube;

[0021] The gate of the third MOS tube is connected to the gate of the sixth MOS tube, and the drain is connected to the input end of the first NOT gate;

[0022] The gate of the fourth MOS tube is connected to the output end of the first signal selector, and the drain is connected to the input end of the first NOT gate;

[0023] The drain of the fifth MOS tube is connected to the drains of the first MOS tube and the second MOS tube, and the source is connected to the drain of the seventh MOS tube;

[0024] The gate of the sixth MOS tube is connected to the drain of the first MOS tube, the drain of the second MOS tube is connected to the drain of the fifth MOS tube, the drain is connected to the input end of the first NOT gate, and the source is connected to the drain of the eighth MOS tube;

[0025] The gate of the seventh MOS tube is connected to the output end of the second signal selector, and the source is grounded;

[0026] The gate of the eighth MOS tube is connected to the output end of the first signal selector, and the source is grounded.

[0027] Preferably, the second trigger and the fourth trigger are 2UI paths;

[0028] The second trigger and the fourth trigger are rising edge triggered.

[0029] Preferably, the third trigger and the fifth trigger are 1UI paths;

[0030] The third trigger and the fifth trigger are falling edge triggered;

[0031] MOS CAP is used as a load to compensate for the delay from CLK to the D terminal of the third trigger and the fifth trigger triggered by the rising edge.

[0032] A training method for a control circuit of a clock signal delay, comprising:

[0033] Determining whether the clock signal needs to be calibrated according to the calibration enable signal;

[0034] When the calibration enable signal is 1, the clock signal is calibrated;

[0035] The output signals of the first variable delay line and the second variable delay line sample the calibration enable signal;

[0036] The first signal selector and the second signal selector select a calibration mode for calibration according to the sampled calibration enable signal;

[0037] The phase detection module verifies the calibration result.

[0038] Preferably, the first signal selector and the second signal selector select the calibration mode for calibration according to the sampled calibration enable signal, comprising:

[0039] When the signal selector output is 1, the 1UI path is selected and 1UI calibration is performed;

[0040] The falling edge of CLK_NDLY samples CAL_EN and outputs Q2, and the rising edge of CLK_DLY samples CLK_EN and outputs Q4;

[0041] When the first rising edge of CLK_DLY precedes the first falling edge of CLK_NDLY, the rising edge of Q4 will arrive earlier than Q2. At this time, the phase detector output is 0, and the code of the second variable delay line increases, pushing CLK_DLY until the first rising edge of CLK_DLY coincides with the first falling edge of CLK_NDLY. The order of the rising edges of Q2 and Q4 changes, and the rising edge of Q4 lags behind Q2. The phase detector output CAL_OUT jumps to 1. At this time, the code corresponding to the second variable delay line is the 1UI calibration result.

[0042] Preferably, the first signal selector and the second signal selector select the calibration mode for calibration according to the sampled calibration enable signal, comprising:

[0043] When the signal selector output is 0, the 2UI path is selected and 2UI calibration is performed;

[0044] The rising edge of CLK_NDLY samples CAL_EN and outputs Q0. When the next rising edge of CLK_NDLY arrives, Q1 is output. There is a phase difference of 2UI between Q1 and Q0.

[0045] The rising edge of CLK_DLY samples CLK_EN and outputs Q3. When the first rising edge of CLK_DLY precedes the second rising edge of CLK_NDLY, the rising edge of Q3 will arrive earlier than Q1. At this time, the phase detector output is 0, and the code of the second variable delay line increases, pushing CLK_DLY until the first rising edge of CLK_DLY coincides with the second rising edge of CLK_NDLY. The order of the rising edges of Q1 and Q3 changes, and the rising edge of Q3 will lag behind Q1. The phase detector output CAL_OUT jumps to 1. At this time, the code corresponding to the second variable delay line is the 2UI calibration result.

[0046] The beneficial effects of the present invention are as follows: 1. The present invention adopts a novel 1UI / 2UI calibration method, which can overcome the influence of the setup time and the hold time of the D flip-flop itself, and can more accurately obtain the 1UI / 2UI delay in the training of the DDR PHY IP; 2. The present invention integrates the 1UI and 2UI calibration into one circuit, which saves the circuit area and improves the operation efficiency of the circuit; 3. In the 1UI calibration path, the present invention adds load capacitance adjustment to the D flip-flop with rising edge sampling, and for the case where CAL_OUT jumps from 0 to 1, it is ensured that it has the same CLK to Q delay as the D flip-flop with falling edge sampling, thereby achieving accurate calibration. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0048] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0049] Figure 1 A schematic diagram of a control circuit structure for clock signal delay according to the present invention;

[0050] Figure 2 It is a schematic diagram of the structure of a 1UI calibration circuit in the prior art of the present invention;

[0051] Figure 3 It is a schematic diagram of the structure of the 1UI / 2UI calibration circuit of the present invention;

[0052] Figure 4 This is a 1UI calibration timing diagram of the present invention;

[0053] Figure 5 This is a 2UI calibration timing diagram of the present invention;

[0054] Figure 6 It is a schematic diagram of the circuit structure of the phase detection module of the present invention;

[0055] Figure 7 The figure is a schematic diagram of the circuit structure of the rising edge and falling edge triggered D flip-flop of the present invention. DETAILED DESCRIPTION

[0056] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0057] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0058] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0059] In the application of DDR IP, the unit time interval (UI, 1UI is half of the clock cycle) of data (DQ) and sampling clock (DQS) is getting smaller and smaller. The relative positions of DQ and DQS need to be trained so that DQS can sample the correct DQ and reserve enough spare time. In the DDR PHY circuit, it is necessary to obtain a delay line equal to the 1UI and 2UI times, and then adjust the relative position of DQS to complete the sampling of DQ. However, in the existing 1UI calibration circuit, it is greatly affected by the setup and hold time of the D flip-flop itself, resulting in inaccurate calibration. Figure 2As shown in the figure, when the phase difference between CLK_DLY and CLK_NDLY is less than 1UI, FLAG0 is 0 and FLAG1 is 1. When variable delay line 2 gradually increases and CLK_DLY is pushed to a phase difference of 1UI with CLK_NDLY, FLAG0 jumps to 1 and FLAG1 jumps to 0. At this time, the phase difference between the two variable delay lines is 1UI. However, this result is affected by the setup and hold time of the D flip-flop itself. When CLK_DLY and CLK_NDLY sample each other, the two D flip-flops themselves have setup time and hold time, resulting in an inaccurate 1UI calibration result. The calibration result is essentially a superposition of the 1UI value of the clock signal and the setup time / hold time.

[0060] The present invention adopts a novel 1UI / 2UI calibration method, which can overcome the influence of the setup time and hold time of the D flip-flop itself, and can more accurately obtain the 1UI / 2UI delay in the training of the DDR PHY IP; the present invention integrates the 1UI and 2UI calibration into one circuit, which saves the circuit area and improves the operation efficiency of the circuit; in the 1UI calibration path, the present invention adds load capacitance adjustment to the D flip-flop of rising edge sampling, and when CAL_OUT jumps from 0 to 1, it is ensured that it has the same CLK to Q delay as the D flip-flop of falling edge sampling, thereby realizing accurate calibration.

[0061] Example 1

[0062] A control circuit for clock signal delay, referring to Figure 1 , comprising: a first variable delay line, a second variable delay line and a 1UI / 2UI calibration circuit;

[0063] An input end of the first variable delay line is connected to a clock signal, and an output end is connected to a 1UI / 2UI calibration circuit;

[0064] The input end of the second variable delay line is connected to the clock signal, and the output end is connected to the 1UI / 2UI calibration circuit;

[0065] The 1UI / 2UI calibration circuit performs calibration according to the clock signals output by the first variable delay line and the second variable delay line.

[0066] The setup time and hold time of the trigger are two important timing parameters in digital circuit design. Together, they affect the time requirement for the data to remain stable before and after the clock signal is triggered, to ensure that the data can be correctly sampled and read. The setup time refers to the time that the data must remain stable before the rising edge of the trigger clock signal arrives. This time interval ensures that the input signal has enough time to reach the chip and can be correctly sampled on the rising edge of the clock. If the input signal does not meet the setup time requirement, the data cannot be entered into the trigger by the current clock, and can only be sampled at the next rising edge of the clock. The hold time refers to the time that the data must remain stable for a period of time after the rising edge of the trigger clock signal arrives, to ensure that the data can be stably read. The importance of the hold time is that it ensures that when the signal passes through the wiring and logic unit inside the device, due to the existence of delay, the data needs a certain transition time when the high and low levels are converted, so as to ensure that the data can be stably maintained for a period of time after the clock signal edge is triggered, so as to be effectively read and converted to output. If the hold time is insufficient, the data cannot be effectively read. Setup time and hold time are the time requirements between the input signal and the clock signal of the test chip. They characterize the time that the data needs to last at the input of the latch before and after the clock edge triggers, and are the characteristics of the chip itself. Failure to meet the setup time and hold time requirements will lead to metastable conditions, that is, the output value is in an uncertain state for a short time, which may affect the correct operation of the digital system.

[0067] Due to the existence of the setup time and hold time of the trigger, when the signal is sampled, the setup time and hold time of the trigger will affect the calibration result of the clock signal, resulting in inaccurate calibration of the clock signal. The present invention provides a control circuit for clock signal delay, including: a first variable delay line (variable delay line 1), a second variable delay line (variable delay line 2), and a 1UI / 2UI calibration circuit. The input is a clock signal CLK, a calibration enable signal CAL_EN, and a 1UI / 2UI calibration mode selection signal MODESEL, and the output is a standard signal CAL_OUT of a phase detection result.

[0068] Preferably, the 1UI / 2UI calibration circuit comprises: a first trigger, a second trigger, a third trigger, a fourth trigger, a fifth trigger, a first amplifier, a first signal selector, a second signal selector and a phase detection module;

[0069] The D terminal of the first trigger is connected to CAL EN, the Q terminal is connected to the input terminal of the first amplifier, and the CLK terminal is connected to CLKNDLY;

[0070] The D terminal of the second trigger is connected to the output terminal of the first amplifier, the Q terminal is connected to the 0 terminal of the first signal selector, and the CLK terminal is connected to CLK NDLY;

[0071] The D terminal of the third trigger is connected to CAL EN, the Q terminal is connected to the 1 terminal of the first signal selector, and the CLK terminal is connected to CLKNDLY;

[0072] The D terminal of the fourth trigger is connected to CAL EN, the Q terminal is connected to the 0 terminal of the second signal selector, and the CLK terminal is connected to CLKDLY;

[0073] The D terminal of the fifth trigger is connected to CAL EN, the Q terminal is connected to the 1 terminal of the second signal selector, and the CLK terminal is connected to CLKDLY;

[0074] The output ends of the first signal selector and the second signal selector are both connected to the input end of the phase detection module.

[0075] The basic modules of a trigger include: Input module: Triggers usually have one or more input signals, which can be changes in voltage or current. The input signal can be continuous or instantaneous. Logic gate circuit: The input signal is processed and decoded by the logic gate circuit. The logic gate circuit can generate a corresponding output signal according to the specific conditions of the input signal. Common logic gates include AND gate, OR gate, NOT gate, etc. Feedback loop: Triggers usually contain one or more feedback loops, which are used to record and store past input signals. The feedback loop can keep the state of the trigger until a certain condition is met. Output signal: The output signal of the trigger can be a level signal or a pulse signal. The form and characteristics of the output signal depend on the type and design of the trigger. The trigger can generate an output signal according to specific input conditions, thereby triggering corresponding operations or events in the system. Different types of triggers have different application scenarios, such as storing and transmitting data in digital circuits, or detecting and responding to external events in control systems. Monitoring conditions: Triggers constantly monitor specific conditions, such as specific data states, time intervals, or triggering of external events. ‌Condition Verification: When a trigger detects that a condition is met, further actions are triggered. ‌This usually involves validating the condition to ensure that specific requirements are met. ‌Trigger Action: Once the condition is verified to be correct, the trigger will initiate the defined action or procedure. ‌These actions can be pre-defined commands, scripts, functions, stored procedures, etc., in response to the triggering event. ‌Execution Logic: Trigger actions can execute corresponding logic as required. ‌For example, in a database, triggers can be used to automatically perform other actions when data is inserted, updated, or deleted, such as updating other tables or firing other triggers. ‌Optional Feedback: After the triggered action is completed, the trigger can choose to provide feedback to the user, such as displaying a message, logging an event, or triggering other notification mechanisms.

[0076] When CAL_EN is 1, calibration is performed, and the outputs CLK_DLY and CLK_NDLY of the variable delay lines 1 and 2 sample the high level CAL_EN. The phase detector compares the rising edges of the sampling results Q1, Q2, Q3, and Q4. When the rising edge of PH1 arrives before PH0, the value of the phase detector output CAL_OUT is 0. When the rising edge of PH1 arrives later than PH0, the value of the phase detector output CAL_OUT is 1.

[0077] Preferably, the first variable delay line is a delay line with a fixed length.

[0078] Preferably, the length of the second variable delay line is adjusted according to the output of the calibration circuit.

[0079] Delay line is an electronic device used for the transmission and processing of delayed signals. It can delay the arrival time of the input signal for a certain period of time before outputting it, and is often used in data communication, digital signal processing and measurement and other fields. Delay line is a device that can delay the arrival time of the signal. It introduces a specific delay element in the signal path so that the input signal needs a period of time to reach the output end. Delay line can achieve signal delay based on the principles of electromagnetic wave propagation, capacitive coupling or clock control. The main function of delay line is to solve problems such as signal synchronization, timing calibration, signal compensation and pulse shaping. For example, in communication systems, delay lines are often used to ensure that different signals arrive at the receiving end in the correct order, thereby achieving effective data transmission. Clock-controlled delay line is a device that uses clock signals to synchronize and control delay. It controls the delay time of the signal through precise clock pulses, and is used in scenarios such as timing calibration, synchronous data transmission and clock distribution. Clock-controlled delay lines are widely used in digital systems, high-speed communications and chip-level integrated circuits. Variable delay line can provide precise signal delay control. Delay line can delay the signal in a highly accurate and adjustable manner to meet the needs of different application scenarios. To achieve signal synchronization and timing calibration, the delay line can solve the data misalignment and timing problems caused by inconsistent signal arrival time, ensuring the normal operation of the system. Simplify signal processing and debugging: The delay line can be used for signal compensation, pulse shaping, and signal waveform correction, simplifying the system design and debugging process.

[0080] Variable delay line 1 is a delay line with a fixed length (initial length). Its purpose is to offset the inherent delay of variable delay line 2. The length of variable delay line 2 is controlled by code and is continuously adjusted according to the result of CAL_OUT, and the initial delay is continuously increased. When CAL_OUT jumps from 0 to 1, the variable delay line code at this time corresponds to a 1UI / 2UI delay length, and the calibration is completed. CAL_EN is the calibration enable signal. When it is 1, calibration can be performed; MODESEL is the 1UI / 2UI calibration mode selection signal. When it is 1, 1UI calibration is performed, and when it is 0, 2UI calibration is performed.

[0081] Preferably, reference Figure 5 The phase detection module includes: a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube and a first NOT gate;

[0082] The gate of the first MOS tube is connected to the output end of the second signal selector, and the drain is connected to the drain of the second MOS tube and the drain of the fifth MOS tube;

[0083] The drain of the second MOS tube is connected to the gate of the third MOS tube;

[0084] The gate of the third MOS tube is connected to the gate of the sixth MOS tube, and the drain is connected to the input end of the first NOT gate;

[0085] The gate of the fourth MOS tube is connected to the output end of the first signal selector, and the drain is connected to the input end of the first NOT gate;

[0086] The drain of the fifth MOS tube is connected to the drains of the first MOS tube and the second MOS tube, and the source is connected to the drain of the seventh MOS tube;

[0087] The gate of the sixth MOS tube is connected to the drain of the first MOS tube, the drain of the second MOS tube is connected to the drain of the fifth MOS tube, the drain is connected to the input end of the first NOT gate, and the source is connected to the drain of the eighth MOS tube;

[0088] The gate of the seventh MOS tube is connected to the output end of the second signal selector, and the source is grounded;

[0089] The gate of the eighth MOS tube is connected to the output end of the first signal selector, and the source is grounded.

[0090] When the rising edge of PH1 arrives earlier than PH0, CAL_OUT output is 0, and when the rising edge of PH1 arrives later than PH0, CAL_OUT output is 1.

[0091] The phase detector module is a device that can identify the phase difference of the input signal, so that the output voltage has a certain relationship with the phase difference between the two input signals. In the embodiment of the present invention, the phase detector module can determine whether the calibration result of the calibration circuit meets the standard, and the second variable delay line can adjust its own length according to the output of the phase detector module to adapt to the calibration of the next clock signal.

[0092] Preferably, reference Figure 7 , the second trigger and the fourth trigger are 2UI paths;

[0093] The second trigger and the fourth trigger are rising edge triggered.

[0094] "Rising edge" refers to the moment when the signal changes from a low level to a high level. In digital circuits and communication systems, the rising edge generally indicates the process of the signal state changing from 0 (low level) to 1 (high level), that is, the starting edge of the signal. For example, in a digital signal source, when the output signal changes from 0 to 1, it is said that a rising edge occurs at this time; the rising edge trigger refers to the moment when the signal changes from a low level (0V) to a high level (for example, above 3.5V). In digital circuits, this usually indicates the starting edge of the signal state, which can trigger many logic gates and triggers to complete specific functions. For example, in a digital signal source, when the output signal changes from 0 to 1, a rising edge occurs, which can be used for timing control, signal locking, and data synchronization.

[0095] Preferably, the third trigger and the fifth trigger are 1UI paths;

[0096] The third and fifth triggers are falling edge triggered;

[0097] MOS CAP is used as a load to compensate for the delay from CLK to the D end of the third and fifth triggers triggered by the rising edge.

[0098] "Falling edge" refers to the moment when a signal changes from a high level to a low level. In digital circuits and communication systems, a falling edge generally indicates the process of a signal state changing from 1 (high level) to 0 (low level), that is, the end edge of the signal. For example, in a digital signal source, when the output signal changes from 1 to 0, it is said that a falling edge has occurred. Rising edge triggering and falling edge triggering refer to the instantaneous change of a signal from a low level to a high level or from a high level to a low level, respectively.

[0099] Falling edge triggering refers to the moment when the signal changes from a high level (for example, greater than 3.5V) to a low level (below 0.3V). In digital circuits, this indicates the end edge of the signal state, and can also trigger logic gates and triggers to achieve specific functions. For example, when the output signal changes from 1 to 0, a falling edge occurs, which also plays an important role in timing control, signal locking, and data synchronization.

[0100] In the present invention, the D flip-flop for CLK_NDLY sampling under the 1UI path is triggered by the falling edge, and the other D flip-flops are all triggered by the rising edge. Since the delay from the CLK of the D flip-flop to the D end will directly affect the accuracy of the 1UI / 2UI calibration, under the 1UI path, MOS CAP is used as a load to compensate for the delay from the CLK of the D flip-flop triggered by the rising edge to the D end, ensuring that it is consistent with the delay of the D flip-flop triggered by the falling edge, such as Figure 7As shown. Since the present invention focuses on the state of the Q terminal (CAL_OUT) changing from 0 to 1, that is, the state of the Q1 terminal changing from 1 to 0, this state is driven by BCLK in the falling edge trigger and driven by ACLK in the rising edge trigger. Since BCLK has an additional inverter delay relative to ACLK, MOS CAP is used as loading to compensate the D flip-flop triggered by the rising edge.

[0101] Example 2

[0102] A training method for a control circuit of a clock signal delay comprises the steps of:

[0103] Step S100, judging whether the clock signal needs to be calibrated according to the calibration enable signal;

[0104] The calibration enable signal is a control signal used to enable or disable a specific function or operation. It usually indicates the enable or disable state in the form of a high level (logic 1) or a low level (logic 0). By changing the state of the enable signal, the working state of the corresponding module or device can be controlled. This signal is widely used in electronic systems and digital circuits, for example, it plays an important role in data storage, logic gates, and clock control. The enable signal not only helps control the system operation mode, but also saves power consumption. In practical applications, such as motor control, CNC machine tools, etc., the enable signal ensures the safe operation of the equipment and the precise control of the function. In an embodiment of the present invention, the calibration enable signal is used to turn on the calibration circuit.

[0105] Step S200, when the calibration enable signal is 1, calibrate the clock signal;

[0106] When the calibration enable signal is 1, it means that the current clock signal needs to be calibrated and the calibration circuit starts working.

[0107] Step S300, the output signals of the first variable delay line and the second variable delay line sample the calibration enable signal;

[0108] The first variable delay line and the second variable delay line discretize the continuous calibration enable signal in time. By taking the instantaneous value of the analog signal x(t) point by point at a certain time interval △t, the continuous analog signal is converted into a discrete time series. This process is achieved by multiplying the sampling pulse and the analog signal. Simply put, sampling is to capture the value of the analog signal at a specific time point, so that it changes from a continuous form to a series of separated time samples. These samples can then be used for digital signal processing and analysis.

[0109] Step S400, the first signal selector and the second signal selector select a calibration mode for calibration according to the sampled calibration enable signal;

[0110] In the embodiment of the present invention, the calibration circuit has two calibration modes, namely, 1UI calibration mode and 2UI calibration mode, 1UI is half of a clock cycle, 2UI is one clock cycle,

[0111] Step S500: The phase detection module checks the calibration result.

[0112] The phase detection module is based on phase comparison. By comparing the phase information of the two input signals, it outputs a voltage proportional to the phase difference. This voltage is then used to adjust the oscillator or frequency synthesizer in the loop to reduce the phase difference between the input signal and the output signal, and finally achieve frequency and phase synchronization. The demodulation principle of the phase detection module involves converting the change of the phase difference into the change of the output voltage. In this way, the phase detection module realizes the demodulation of the phase modulated wave and extracts the original information. The phase detection module generates an output voltage proportional to the phase difference by identifying the phase difference of the input signal, thereby realizing the demodulation of the phase modulated wave and the synchronous control of frequency and phase.

[0113] Preferably, in step S400, the first signal selector and the second signal selector select the calibration mode for calibration according to the sampled calibration enable signal, including:

[0114] Step S410A, when the signal selector output is 1, select the 1UI path and perform 1UI calibration;

[0115] The falling edge of CLK_NDLY samples CAL_EN and outputs Q2, and the rising edge of CLK_DLY samples CLK_EN and outputs Q4;

[0116] When the first rising edge of CLK_DLY precedes the first falling edge of CLK_NDLY, the rising edge of Q4 will arrive earlier than Q2. At this time, the phase detector output is 0, and the code of the second variable delay line increases, pushing CLK_DLY until the first rising edge of CLK_DLY coincides with the first falling edge of CLK_NDLY. The order of the rising edges of Q2 and Q4 changes, and the rising edge of Q4 lags behind Q2. The phase detector output CAL_OUT jumps to 1. At this time, the code corresponding to the second variable delay line is the 1UI calibration result.

[0117] Timing diagram Figure 4As shown in the figure, when MODESEL is 1, the 1UI path is selected for 1UI calibration. The falling edge of CLK_NDLY samples CAL_EN and outputs Q2. The rising edge of CLK_DLY samples CLK_EN and outputs Q4. When the first rising edge of CLK_DLY precedes the first falling edge of CLK_NDLY, the rising edge of Q4 will arrive before Q2. At this time, the phase detector output is 0, and the code of variable delay line 2 will continue to increase, thereby pushing CLK_DLY until the first rising edge of CLK_DLY coincides with the first falling edge of CLK_NDLY. The order of the rising edges of Q2 and Q4 changes, and the rising edge of Q4 will lag behind Q2. The phase detector output CAL_OUT jumps to 1. At this time, the code corresponding to variable delay line 2 is the 1UI calibration result.

[0118] Preferably, in step S400, the first signal selector and the second signal selector select the calibration mode for calibration according to the sampled calibration enable signal, including:

[0119] Step S410B, when the signal selector output is 0, select the 2UI path and perform 2UI calibration;

[0120] The rising edge of CLK_NDLY samples CAL_EN and outputs Q0. When the next rising edge of CLK_NDLY arrives, Q1 is output. There is a phase difference of 2UI between Q1 and Q0.

[0121] The rising edge of CLK_DLY samples CLK_EN and outputs Q3. When the first rising edge of CLK_DLY precedes the second rising edge of CLK_NDLY, the rising edge of Q3 will arrive earlier than Q1. At this time, the phase detector output is 0, and the code of the second variable delay line increases, pushing CLK_DLY until the first rising edge of CLK_DLY coincides with the second rising edge of CLK_NDLY. The order of the rising edges of Q1 and Q3 changes, and the rising edge of Q3 will lag behind Q1. The phase detector output CAL_OUT jumps to 1. At this time, the code corresponding to the second variable delay line is the 2UI calibration result.

[0122] Timing diagram Figure 5 As shown in the figure, when MODESEL is 0, the 2UI path is selected and 2UI calibration is performed. Figure 4As shown, the rising edge of CLK_NDLY samples CAL_EN and outputs Q0. When the next rising edge of CLK_NDLY arrives, Q1 is output. There is a phase difference of 2UI between Q1 and Q0. The rising edge of CLK_DLY samples CLK_EN and outputs Q3. When the first rising edge of CLK_DLY precedes the second rising edge of CLK_NDLY, the rising edge of Q3 will arrive earlier than Q1. At this time, the phase detector output is 0, and the code of variable delay line 2 will increase, thereby pushing CLK_DLY until the first rising edge of CLK_DLY coincides with the second rising edge of CLK_NDLY. The order of the rising edges of Q1 and Q3 changes, and the rising edge of Q3 will lag behind Q1. The phase detector output CAL_OUT jumps to 1. At this time, the code corresponding to variable delay line 2 is the 2UI calibration result.

[0123] The present invention adopts a novel 1UI / 2UI calibration method, which can overcome the influence of the setup time and hold time of the D flip-flop itself, and can more accurately obtain the 1UI / 2UI delay in the training of the DDR PHY IP; the present invention integrates the 1UI and 2UI calibration into one circuit, which saves the circuit area and improves the operation efficiency of the circuit; in the 1UI calibration path, the present invention adds load capacitance adjustment to the D flip-flop of rising edge sampling, and when CAL_OUT jumps from 0 to 1, it is ensured that it has the same CLK to Q delay as the D flip-flop of falling edge sampling, thereby realizing accurate calibration.

[0124] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A control circuit for clock signal delay, characterized in that: include: a first variable delay line, a second variable delay line, and a 1UI / 2UI calibration circuit; The input end of the first variable delay line is connected to the clock signal, and the output end is connected to the 1UI / 2UI calibration circuit; The input end of the second variable delay line is connected to the clock signal, and the output end is connected to the 1UI / 2UI calibration circuit; The 1UI / 2UI calibration circuit is calibrated according to the clock signals output by the first variable delay line and the second variable delay line; The 1UI / 2UI calibration circuit comprises: a first trigger, a second trigger, a third trigger, a fourth trigger, a fifth trigger, a first amplifier, a first signal selector, a second signal selector and a phase detection module; The D terminal of the first trigger is connected to CAL EN, the Q terminal is connected to the input terminal of the first amplifier, and the CLK terminal is connected to the signal (CLK NDLY) generated after the clock CLK passes through the first variable delay line of the initial code; The D terminal of the second trigger is connected to the output terminal of the first amplifier, the Q terminal is connected to the 0 terminal of the first signal selector, and the CLK terminal is connected to the signal (CLK NDLY) generated after the clock CLK passes through the first variable delay line of the initial code; The D terminal of the third trigger is connected to CAL EN, the Q terminal is connected to the 1 terminal of the first signal selector, and the CLK terminal is connected to the signal (CLK NDLY) generated after the clock CLK passes through the first variable delay line of the initial code; The D terminal of the fourth trigger is connected to CAL EN, the Q terminal is connected to the 0 terminal of the second signal selector, and the CLK terminal is connected to the signal (CLK DLY) generated after the clock CLK passes through the second variable delay line of the adjusted code; The D terminal of the fifth trigger is connected to CAL EN, the Q terminal is connected to the 1 terminal of the second signal selector, and the CLK terminal is connected to the signal (CLK DLY) generated after the clock CLK passes through the second variable delay line of the adjusted code; The output ends of the first signal selector and the output end of the second signal selector are both connected to the input end of the phase detection module.

2. A clock signal delay control circuit according to claim 1, characterized in that: The first variable delay line is a delay line with a fixed length.

3. The clock signal delay control circuit according to claim 1, characterized in that: The length of the second variable delay line is adjusted according to the output of the calibration circuit.

4. The clock signal delay control circuit according to claim 1, characterized in that: The phase detection module includes: a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube and a first NOT gate; The gate of the first MOS tube is connected to the output end of the second signal selector, and the drain is connected to the drain of the second MOS tube and the drain of the fifth MOS tube; The drain of the second MOS tube is connected to the gate of the third MOS tube; The gate of the third MOS tube is connected to the gate of the sixth MOS tube, and the drain is connected to the input end of the first NOT gate; The gate of the fourth MOS tube is connected to the output end of the first signal selector, and the drain is connected to the input end of the first NOT gate; The drain of the fifth MOS tube is connected to the drains of the first MOS tube and the second MOS tube, and the source is connected to the drain of the seventh MOS tube; The gate of the sixth MOS tube is connected to the drain of the first MOS tube, the drain of the second MOS tube is connected to the drain of the fifth MOS tube, the drain is connected to the input end of the first NOT gate, and the source is connected to the drain of the eighth MOS tube; The gate of the seventh MOS tube is connected to the output end of the second signal selector, and the source is grounded; The gate of the eighth MOS tube is connected to the output end of the first signal selector, and the source is grounded.

5. The clock signal delay control circuit according to claim 1, characterized in that: The second trigger and the fourth trigger are 2UI paths; The second trigger and the fourth trigger are rising edge triggered.

6. The clock signal delay control circuit according to claim 1, characterized in that: The third trigger and the fifth trigger are 1UI paths; The third trigger and the fifth trigger are falling edge triggered; MOS CAP is used as a load to compensate for the delay from CLK to the D terminal of the third trigger and the fifth trigger triggered by the rising edge.

7. A training method for a clock signal delay control circuit, applied to a clock signal delay control circuit according to any one of claims 1 to 6, characterized in that: include: Determining whether the clock signal needs to be calibrated according to the calibration enable signal; When the calibration enable signal is 1, the clock signal is calibrated; The output signals of the first variable delay line and the second variable delay line sample the calibration enable signal; The first signal selector and the second signal selector select a calibration mode for calibration according to the sampled calibration enable signal; The phase detection module verifies the calibration result.

8. The training method for a clock signal delay control circuit according to claim 7, characterized in that: The first signal selector and the second signal selector select the calibration mode for calibration according to the sampled calibration enable signal, comprising: When the signal selector output is 1, the 1UI path is selected and 1UI calibration is performed; The falling edge of CLK_NDLY samples the calibration enable signal (CAL_EN) and outputs Q2. The rising edge of CLK_DLY samples the calibration enable signal (CAL_EN) and outputs Q4. When the first rising edge of CLK_DLY precedes the first falling edge of CLK_NDLY, the rising edge of Q4 will arrive earlier than Q2. At this time, the phase detector output is 0, and the code of the second variable delay line increases, pushing CLK_DLY until the first rising edge of CLK_DLY coincides with the first falling edge of CLK_NDLY. The order of the rising edges of Q2 and Q4 changes, and the rising edge of Q4 lags behind Q2. The phase detector output CAL_OUT jumps to 1. At this time, the code corresponding to the second variable delay line is the 1UI calibration result.

9. The training method of a clock signal delay control circuit according to claim 7, characterized in that: The first signal selector and the second signal selector select the calibration mode for calibration according to the sampled calibration enable signal, comprising: When the signal selector output is 0, the 2UI path is selected and 2UI calibration is performed; The rising edge of CLK_NDLY samples the calibration enable signal (CAL_EN) and outputs Q0. When the next rising edge of CLK_NDLY arrives, Q1 is output. There is a phase difference of 2UI between Q1 and Q0. The rising edge of CLK_DLY samples the calibration enable signal (CAL_EN) and outputs Q3. When the first rising edge of CLK_DLY precedes the second rising edge of CLK_NDLY, the rising edge of Q3 will arrive earlier than Q1. At this time, the phase detector output is 0, and the code of the second variable delay line increases, pushing CLK_DLY until the first rising edge of CLK_DLY coincides with the second rising edge of CLK_NDLY. The order of the rising edges of Q1 and Q3 changes, and the rising edge of Q3 will lag behind Q1. The phase detector output CAL_OUT jumps to 1. At this time, the code corresponding to the second variable delay line is the 2UI calibration result.

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