Semiconductor device and method for manufacturing the same

Abstract

The present invention discloses a semiconductor device and a manufacturing method thereof, belonging to the field of semiconductor technology. The manufacturing method comprises: providing a substrate, the substrate comprising a channel region, a source region and a drain region, etching part of the substrate to form a plurality of recesses in the channel region; forming a continuous epitaxial compensation layer on the substrate in the recesses and the channel region, the surface of the epitaxial compensation layer having a plurality of protrusions along the length direction of the device, the length direction being the direction from the source region to the drain region; forming a gate on the epitaxial compensation layer; forming a source electrode in the source region on one side of the gate; and forming a drain electrode in the drain region on one side of the gate. The semiconductor device and the manufacturing method thereof provided by the present invention can reduce the area of ​​the semiconductor device, improve the utilization rate of the substrate, and improve the performance of the semiconductor device at the same time.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a semiconductor device and a manufacturing method thereof. Background Art

[0002] With the development of semiconductor devices, semiconductor devices are moving towards miniaturization and integration, which puts forward further requirements on the size of semiconductor devices. Therefore, how to reduce the size of semiconductor devices is becoming more and more challenging.

[0003] Metal-Oxide-Semiconductor Field-Effect Transistor (MOS) is the most basic device in semiconductor manufacturing, and is divided into NMOS transistors and PMOS transistors according to the carriers and doping types during manufacturing. MOS transistors are used for electronic switches, clock amplifiers, radio frequency amplifiers, and conversion of digital electrical signals, and are widely used in various integrated circuits. However, as the size of MOS transistors decreases, MOS transistors face a series of challenges, such as short channel effect (SCE), drain induced barrier lowering (DIBL), hot carrier injection (HCI), and gate oxide leakage. Summary of the invention

[0004] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same. The semiconductor device and the method for manufacturing the same provided by the present invention can reduce the area of ​​the semiconductor device, improve the utilization rate of the substrate, thereby reducing the cost, and at the same time adjust the electrical properties of the semiconductor device such as the threshold voltage, saturation current and leakage current, thereby improving the performance of the semiconductor device.

[0005] In order to solve the above technical problems, the present invention provides a method for manufacturing a semiconductor device, comprising:

[0006] providing a substrate, the substrate comprising a channel region, a source region and a drain region,

[0007] Etching a portion of the substrate to form a plurality of recesses in the channel region;

[0008] Forming a continuous epitaxial compensation layer on the substrate of the recess and the channel region, wherein the surface of the epitaxial compensation layer has a plurality of protrusions along the length direction of the device, and the length direction is the direction from the source region to the drain region;

[0009] forming a gate on the epitaxial compensation layer;

[0010] forming a source electrode in the source region on one side of the gate; and

[0011] A drain electrode is formed in the drain region at one side of the gate.

[0012] In one embodiment of the present invention, the method for forming the concave portion includes:

[0013] forming a sacrificial oxide layer and a sacrificial nitride layer in sequence on the substrate;

[0014] forming a first photoresist layer on the sacrificial nitride layer, wherein a plurality of first openings distributed equidistantly are formed on the first photoresist layer, and the opening widths of the plurality of first openings are equal;

[0015] The sacrificial nitride layer, the sacrificial oxide layer and a portion of the substrate are etched using the first photoresist layer as a mask to form a plurality of recesses.

[0016] In one embodiment of the present invention, the manufacturing method further includes:

[0017] After forming the recess, removing the sacrificial nitride layer and the sacrificial oxide layer on the channel region;

[0018] The continuous epitaxial compensation layer is formed on the substrate in the recess and the channel region by an epitaxial growth method.

[0019] In one embodiment of the present invention, in the length direction, the opening width of the concave portion is 2 nm to 200 nm, and the spacing between adjacent concave portions is 2 nm to 50 nm.

[0020] In one embodiment of the present invention, in the width direction of the device, the recesses are distributed in a strip shape, and the width direction is perpendicular to the length direction.

[0021] In one embodiment of the present invention, the substrate is a single material substrate or a stacked substrate, and the stacked substrate includes a first semiconductor layer, an insulating layer and a second semiconductor layer, and the insulating layer is arranged between the first semiconductor layer and the second semiconductor layer.

[0022] In one embodiment of the present invention, when the substrate is a stacked substrate, the recess is disposed in the second semiconductor layer, and a depth of the recess is less than or equal to a thickness of the second semiconductor layer.

[0023] In one embodiment of the present invention, the epitaxial compensation layer is a single crystal silicon, gallium nitride, gallium arsenide, silicon germanium, indium nitride, aluminum nitride or silicon carbide epitaxial layer.

[0024] In one embodiment of the present invention, when forming the epitaxial compensation layer, a triangular gap is formed at the bottom of the recess.

[0025] The present invention also provides a semiconductor device, comprising:

[0026] A substrate, comprising a channel region, a source region and a drain region, wherein the source region and the drain region are arranged on both sides of the channel region;

[0027] An epitaxial compensation layer is arranged on the channel region, and a surface of the epitaxial compensation layer has a plurality of protrusions along a length direction of the device, wherein the length direction is a direction from the source region to the drain region;

[0028] A gate, disposed on the epitaxial compensation layer;

[0029] a source electrode, disposed in the source region on one side of the gate; and

[0030] A drain electrode is arranged in the drain region at the other side of the gate.

[0031] In summary, the present invention provides a semiconductor device and a method for manufacturing the same, which can reduce the size of the semiconductor device in the length direction, thereby reducing the area of ​​the semiconductor device, improving the utilization rate of the substrate, and reducing the cost. It can reduce the distance between the source and the drain, thereby adjusting the threshold voltage, saturation current, leakage and other electrical properties of the semiconductor device, and improving the performance of the semiconductor device. It can reduce the interface state density, improve the carrier mobility, and improve the thermal stability of the semiconductor device. It can improve the integration of semiconductor devices and meet the development trend of semiconductor devices.

[0032] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0034] Figure 1 FIG. 1 is a schematic top view of an embodiment after forming an epitaxial compensation layer.

[0035] Figure 2 For along Figure 1 A cross-sectional view after a sacrificial oxide layer, a sacrificial nitride layer, a first photoresist layer and a first opening are formed in the XX direction.

[0036] Figure 3 For along Figure 1 A cross-sectional view after a recess is formed in the XX direction.

[0037] Figure 4 For along Figure 1 A cross-sectional view after a recess is formed in the YY direction.

[0038] Figure 5 For along Figure 1 A cross-sectional view of removing the sacrificial oxide layer and the sacrificial nitride layer in the channel region in the XX direction.

[0039] Figure 6 For along Figure 1 A cross-sectional view of removing the sacrificial oxide layer and the sacrificial nitride layer in the channel region in the YY direction.

[0040] Figure 7 For along Figure 1 A cross-sectional view of an epitaxial compensation layer formed in the XX direction.

[0041] Figure 8 For along Figure 1 A cross-sectional view of an epitaxial compensation layer formed in the YY direction.

[0042] Fig. 9 For along Figure 1 A cross-sectional view of removing the sacrificial oxide layer and the sacrificial nitride layer on the substrate in the XX direction.

[0043] Fig.10 For along Figure 1 A cross-sectional view of a gate dielectric layer formed in the XX direction.

[0044] Fig.11 For along Figure 1 A cross-sectional view of a gate material layer and a second photoresist layer formed in the XX direction.

[0045] Fig.12 For along Figure 1 A cross-sectional view of a gate and a lightly doped region is formed along the XX direction.

[0046] Fig.13 For along Figure 1 A cross-sectional view of a semiconductor device formed along the XX direction.

[0047] Fig.14 For along Figure 1 A cross-sectional view of a semiconductor device formed along the YY direction.

[0048] Fig.15 This is a simulation diagram of a semiconductor device provided in an embodiment and a comparative example in an embodiment of the present invention.

[0049] Fig.16 1 is a transfer characteristic curve of the semiconductor device of the embodiment and the comparative example in one embodiment of the present invention.

[0050] Fig.17 Graph 1 is a subthreshold swing of the semiconductor device of the embodiment and the comparative example in one embodiment of the present invention.

[0051] Description of labels:

[0052] 10. substrate; 101. first semiconductor layer; 102. insulating layer; 103. second semiconductor layer; 11. sacrificial oxide layer; 12. sacrificial nitride layer; 13. first photoresist layer; 131. first opening; 14. recess; 15. epitaxial compensation layer; 151. gap; 16. gate dielectric layer; 17. gate material layer; 18. second photoresist layer; 19. gate; 20. lightly doped region; 21. sidewall structure; 22. source; 23. drain; 100. channel region; 200. source region; 300. drain region. DETAILED DESCRIPTION

[0053] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0054] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0055] In the present invention, it should be noted that, if the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, if the terms "first" and "second" appear, they are only used for description and distinction purposes, and cannot be understood as indicating or implying relative importance.

[0056] See also Figures 1 to 14As shown, the present invention provides a semiconductor device, which at least includes a substrate 10, a gate 19, a source 22 and a drain 23. Among them, the substrate 10 includes a channel region 100, a source region 200 and a drain region 300, and the source region 200 and the drain region 300 are arranged on both sides of the channel region 100. The channel region 100 has a plurality of protrusions along the length direction of the device, and the length direction is the direction from the source region 200 to the drain region 300. By having a plurality of protrusions in the length direction, the area of ​​the semiconductor device can be reduced, and the electrical properties of the semiconductor device such as the threshold voltage, saturation current and leakage current can be adjusted, thereby improving the performance of the semiconductor device. The present invention also provides a method for manufacturing a semiconductor device, and describes the manufacturing process of the semiconductor device. The method for manufacturing a semiconductor device provided by the present invention can be widely used in the manufacture of various semiconductor devices with channels. For example, this application uses a MOS transistor as an example for description.

[0057] See also Figure 1 to Figure 2 As shown, in one embodiment of the present invention, Figure 2 for Figure 1 A cross-sectional view after forming a sacrificial oxide layer, a sacrificial nitride layer, a first photoresist layer and a first opening along the XX direction. First, a substrate 10 is provided, and the substrate 10 can be any material suitable for forming a semiconductor device. The substrate is, for example, a single material substrate or a stacked substrate, such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), silicon germanium (GeSi), sapphire or silicon wafer, etc., and also includes a stacked structure composed of these semiconductors, or silicon on insulator, stacked silicon on insulator, stacked silicon germanium on insulator, silicon germanium on insulator, and germanium on insulator. The present invention does not limit the type and thickness of the substrate 10, such as selecting a silicon wafer. In this embodiment, the substrate 10 is, for example, an SOI (Silicon On Insulator) substrate, and the SOI substrate includes, for example, a first semiconductor layer 101, an insulating layer 102 and a second semiconductor layer 103, and the materials of the second semiconductor layer 103 and the first semiconductor layer 101 are the same or different. Among them, the first semiconductor layer 101 is, for example, single crystal silicon, the insulating layer 102 is, for example, a silicon oxide layer, the second semiconductor layer 103 is, for example, single crystal silicon, and the second semiconductor layer 103 is, for example, N-type doping or P-type doping. The present application does not limit the thickness of the second semiconductor layer 103, as long as it meets the subsequent manufacturing requirements of the semiconductor device. In other embodiments, the substrate 10 is, for example, a silicon wafer substrate, etc., which can be selected specifically according to the type of semiconductor device. The substrate 10 includes a channel region 100, a source region 200 and a drain region 300, and the source region 200 and the drain region 300 are arranged on both sides of the channel region 100, wherein the direction from the source region 200 to the drain region 300 is the length direction of the device, and the direction in which the channel region 100, the source region 200 and the drain region 300 extend is the width direction of the device.

[0058] See also Figure 2 As shown, in one embodiment of the present invention, a sacrificial oxide layer 11 is formed on the substrate 10. The sacrificial oxide layer 11 is, for example, a dense silicon oxide or other material. For example, the sacrificial oxide layer 11 can be formed on the second semiconductor layer 103 by a thermal oxidation method or an in-situ water vapor growth method. In this embodiment, the substrate 10 is placed in a furnace tube at a temperature of, for example, 900°C to 1150°C, and oxygen is introduced into the furnace tube. The substrate 10 reacts with the oxygen at a high temperature to generate a dense sacrificial oxide layer 11, and the thickness of the sacrificial oxide layer 11 is, for example, 10nm to 30nm. After the sacrificial oxide layer 11 is formed, a sacrificial nitride layer 12 is formed on the sacrificial oxide layer 11. The sacrificial nitride layer 12 is, for example, silicon nitride or a mixed layer of silicon nitride and silicon oxide. In this embodiment, the sacrificial nitride layer 12 is, for example, silicon nitride. Among them, the sacrificial oxide layer 11 as a buffer layer can improve the stress between the substrate 10 and the sacrificial nitride layer 12. In the present invention, for example, the sacrificial nitride layer 12 can be formed on the sacrificial oxide layer 11 by low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). In some embodiments, the thickness of the sacrificial nitride layer 12 is, for example, 30 nm to 100 nm.

[0059] See also Figures 2 to 4 As shown, in one embodiment of the present invention, Figure 3 for Figure 1 A cross-sectional view of a concave portion formed along the XX direction, Figure 4 To form the concave rear edge Figure 1. A cross-sectional view of the YY direction. After forming the sacrificial nitride layer 12, a first photoresist layer 13 is formed on the sacrificial nitride layer 12. Through processes such as exposure and development, a plurality of first openings 131 are formed on the first photoresist layer 13. The plurality of first openings 131 are equidistantly arranged on the channel region 100, and the opening widths of the plurality of first openings 131 are equal. Using the first photoresist layer 13 as a mask, the sacrificial nitride layer 12 exposed by the first photoresist layer 13 is quantitatively removed by dry etching, wet etching, or a combination of dry etching and wet etching. Then, using the sacrificial nitride layer 12 as a mask, the sacrificial oxide layer 11 and a portion of the second semiconductor layer 103 are removed in situ to obtain a recess 14. The recess 14 is in the shape of a long strip and distributed in the second semiconductor layer 103, and the recess 14 is distributed along the width direction of the device, the depth of the recess 14 is, for example, less than or equal to the thickness of the second semiconductor layer 103, and the opening width of the recess 14 is required to form a continuous epitaxial compensation layer in the subsequent process, and the epitaxial compensation layer has a plurality of protrusions. In a specific embodiment, in the length direction, the opening width of the recess 14 is, for example, 2nm~200nm, and the spacing between adjacent recesses 14 is, for example, 2nm~50nm, to ensure that the epitaxial compensation layer in the recess 14 is continuous. In other embodiments, when the substrate 10 is a substrate of a single material, the depth of the recess 14 in the substrate 10 is, for example, 20nm~50nm. The present invention does not limit the number of recesses 14, which can be selected according to the design of the semiconductor device. In this embodiment, for example, dry etching is used to form the recess 14, and the etching gas is, for example, chlorine (Cl2), trifluoromethane (CHF3), difluoromethane (CH2F2), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6) or hydrogen bromide (HBr), etc., or a combination of several of them, or a mixed gas of them and oxygen (O2). After the etching is completed, the first photoresist layer 13 is removed, and the first photoresist layer 13 is removed, for example, by oxygen plasma removal or wet removal.

[0060] See also Figures 3 to 6 As shown, in one embodiment of the present invention, Figure 5 for Figure 1 A cross-sectional view of removing the sacrificial oxide layer and sacrificial nitride layer in the channel region along the XX direction, Figure 6 for Figure 1A cross-sectional view of the sacrificial oxide layer and the sacrificial nitride layer in the channel region removed along the YY direction. After the recess 14 is formed, the sacrificial nitride layer 12 and the sacrificial oxide layer 11 on the substrate 10 in the channel region 100 are removed. Specifically, a patterned photoresist layer (not shown in the figure) is formed on the substrate 10, and the patterned photoresist layer covers the source region 200 and the drain region 300. The sacrificial nitride layer 12 and the sacrificial oxide layer 11 are removed by dry etching or wet etching using the patterned photoresist layer as a mask. In the present embodiment, the sacrificial nitride layer 12 is removed by, for example, a wet process, and the wet etching solution is, for example, hot phosphoric acid, and the sacrificial oxide layer 11 is removed by, for example, wet etching, and the wet etching solution is, for example, hydrofluoric acid, and etching is performed at room temperature, and then the patterned photoresist layer is removed. In other embodiments, other etching methods may also be used, and selection is made according to specific manufacturing requirements.

[0061] See also Figures 5 to 8 As shown, in one embodiment of the present invention, Figure 7 for Figure 1 A cross-sectional view of an epitaxial compensation layer formed along the XX direction, Figure 8 for Figure 1 A cross-sectional view of an epitaxial compensation layer formed along the YY direction. After removing the sacrificial nitride layer 12 and the sacrificial oxide layer 11 on the channel region 100, an epitaxial compensation layer 15 is formed on the recess 14 on the channel region 100 and the second semiconductor layer remaining after etching to serve as a channel of the semiconductor device. The epitaxial compensation layer 15 is, for example, a semiconductor epitaxial layer such as single crystal silicon, gallium nitride, gallium arsenide, silicon germanium, indium nitride, aluminum nitride or silicon carbide, and the epitaxial compensation layer 15 is, for example, an intrinsic semiconductor layer. The epitaxial compensation layer 15 can also be an N-type or P-type doped epitaxial layer, and for example, the doping type is the same as the doping type of the second semiconductor layer 103. The epitaxial compensation layer 15 is, for example, formed by an epitaxial growth method, and during the epitaxial growth process, due to the presence of the sacrificial nitride layer 12 on the source region 200 and the drain region 300, the epitaxial compensation layer 15 is only formed on the channel region 100. The epitaxial growth temperature is, for example, 400°C to 900°C.

[0062] See also Figures 7 and 8As shown, in one embodiment of the present invention, during the epitaxial growth process, due to the presence of the concave portion 14, the surface of the formed epitaxial compensation layer 15 has multiple protrusions in the length direction, without changing the distance between the source and the drain, so as to increase the effective length of the channel, thereby reducing the area of ​​the semiconductor device under the same effective channel length, improving the utilization rate of the substrate, and reducing the cost. In one embodiment of the present invention, under the condition of the same device performance, the area of ​​the semiconductor device is reduced by 35% to 45%. At the same time, multiple protrusions are formed in the length direction, for example in a sawtooth shape, which can reduce the distance between the source and the drain, and can adjust the electrical properties of the semiconductor device such as the threshold voltage, saturation current and leakage, and improve the performance of the semiconductor device. A triangular gap 151 is formed at the bottom of the concave portion 14 to improve the isolation performance, thereby further improving the performance of the semiconductor device. The epitaxial compensation layer 15 is an epitaxially grown semiconductor layer with high crystal quality, which can increase the threshold voltage of the semiconductor device, reduce the on-resistance, and improve the performance of the semiconductor device.

[0063] See also Figures 7 to 9 As shown, in one embodiment of the present invention, Fig. 9 for Figure 1 A cross-sectional view of removing the sacrificial oxide layer and the sacrificial nitride layer on the substrate along the XX direction. After forming the epitaxial compensation layer 15, the sacrificial nitride layer 12 and the sacrificial oxide layer 11 on the substrate 10 are removed. Specifically, the sacrificial nitride layer 12 and the sacrificial oxide layer 11 are removed by, for example, dry etching or wet etching. In the present embodiment, the sacrificial nitride layer 12 is removed by, for example, a wet process, and the wet etching solution is, for example, hot phosphoric acid, and the sacrificial oxide layer 11 is removed by, for example, wet etching, and the wet etching solution is, for example, hydrofluoric acid, and etching is performed at room temperature, and then the patterned photoresist layer is removed. In other embodiments, other etching methods can also be used, which can be selected according to specific manufacturing requirements.

[0064] It is worth noting that in the present application, the formation method of the channel with the epitaxial compensation layer and the formed structure can be applied to different semiconductor devices to increase the effective length of the channel, reduce the area of ​​the semiconductor device, improve the utilization rate of the substrate, and reduce the cost. In this embodiment, the formation of a MOS transistor with an epitaxial compensation layer is taken as an example to illustrate the influence of the epitaxial compensation layer on the semiconductor device.

[0065] See also Figures 9 and 10 As shown, in one embodiment of the present invention, Fig.10 for Figure 1A cross-sectional view of a gate dielectric layer formed along the XX direction, after removing the sacrificial nitride layer and the sacrificial oxide layer, a gate dielectric layer 16 is formed on the substrate 10 and the epitaxial compensation layer 15, and the gate dielectric layer 16 can be formed of one of a high dielectric constant material, silicon oxide, silicon nitride and silicon oxynitride, or include multiple of high dielectric constant materials, silicon oxide, silicon nitride and silicon oxynitride. Among them, the high dielectric constant material can include at least one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide and lead zinc niobate.

[0066] See also Figure 10 to Figure 11 As shown, in one embodiment of the present invention, Fig.11 for Figure 1 A cross-sectional view of a gate material layer and a second photoresist layer formed along the XX direction. After forming the gate dielectric layer 16, a gate material layer 17 is formed on the gate dielectric layer 16. The gate material layer 17 is, for example, polysilicon or a metal material, and the polysilicon is doped polysilicon or undoped polysilicon. The metal material can be magnesium, aluminum, nickel, copper, gold, silver, TiAl-based alloy, titanium carbide, tantalum carbide or tungsten silicide, or an alloy of several materials. The gate material layer 17 is formed, for example, by chemical vapor deposition, physical vapor deposition or metal organic chemical vapor deposition, and the thickness of the gate material layer is, for example, 150nm~400nm. After forming the gate material layer 17, the gate material layer 17 is flattened, for example, by a flattening process such as chemical mechanical polishing (CMP), so that the surface of the gate material layer 17 is flattened to serve as a flat surface for subsequent structures, thereby reducing the difficulty of the process. After the gate material layer 17 is planarized, a second photoresist layer 18 is formed on the gate material layer 17 , and the second photoresist layer 18 on the channel region 100 is retained through processes such as exposure and development.

[0067] See also Figure 11 to Figure 12 As shown, in one embodiment of the present invention, Fig.12 for Figure 1 A cross-sectional view of a gate and a lightly doped region formed along the XX direction. After forming the second photoresist layer 18, the second photoresist layer 18 is used as a mask and the second semiconductor layer 103 is used as an etching stop layer. The gate material layer 17 and the gate dielectric layer 16 exposed by the second photoresist layer 18 are removed by dry etching, wet etching, or a combination of dry etching and wet etching. The remaining gate material layer 17 is defined as a gate 19, and the two sides of the gate 19 are aligned with the edge of the epitaxial compensation layer 15. After the etching is completed, the second photoresist layer 18 is removed, for example, by oxygen plasma removal or wet removal.

[0068] See also Fig.12As shown, in one embodiment of the present invention, after the gate 19 is formed, a lightly doped region 20 is formed in the substrate 10 on both sides of the gate 19. The doping ions in the lightly doped region 20 are formed, for example, by ion implantation, and the type of the implanted ions is opposite to the type of ions in the second semiconductor layer 103. In this embodiment, when the semiconductor device is a PMOS transistor, the doping ions in the lightly doped region 20 are, for example, P-type impurities such as boron or gallium, and when the semiconductor device is an NMOS transistor, the doping ions in the lightly doped region 20 are, for example, N-type impurities such as phosphorus or arsenic.

[0069] See also Figure 12 to Figure 14 As shown, in one embodiment of the present invention, Fig.13 for Figure 1 A cross-sectional view of a semiconductor device is formed along the XX direction, Fig.14 for Figure 1 A cross-sectional view of a semiconductor device is formed along the YY direction. After the lightly doped region 20 is formed, a sidewall structure 21 is formed on both sides of the gate 19. Specifically, a sidewall dielectric layer (not shown in the figure) is formed on the substrate 10 and the gate 19, and the material of the sidewall dielectric layer is, for example, silicon oxide, silicon nitride, or a stack of silicon oxide and silicon nitride. After the sidewall dielectric layer is formed, for example, an etching process such as dry etching can be used to remove the gate 19 and the sidewall dielectric layer on part of the substrate 10, and the sidewall dielectric layer on both sides of the gate 19 is retained to form a sidewall structure 21. Among them, the sidewall structure 21 is, for example, flush with the height of the gate 19, and the sidewall structure 21 is, for example, in the shape of an arc.

[0070] See also Fig.13 As shown, in one embodiment of the present invention, after forming the sidewall structure 21, a heavily doped region is formed in the substrate 10 on the side of the sidewall structure 21 away from the gate 19, and the edge of the heavily doped region is aligned with the side of the sidewall structure 21 away from the gate 19. Wherein, through the photoresist process, the area where the heavily doped region needs to be formed is exposed, for example, the heavily doped region is formed by ion implantation of doped ions, and the type of the implanted ions is opposite to the type of ions in the second semiconductor layer 103, that is, the same as the type of ions in the lightly doped region 20, and the doping concentration of the heavily doped region is greater than the doping concentration of the lightly doped region 20, and the doping depth of the heavily doped region is greater than the doping depth of the lightly doped region 20. After forming the heavily doped region, the heavily doped region and the lightly doped region 20 are activated, for example, the substrate 10 is subjected to rapid thermal annealing. Through rapid thermal annealing, the lattice defects generated during the manufacturing process can be repaired and the doped ions can be activated, thereby activating the heavily doped region and the lightly doped region 20. In this embodiment, the heavily doped region in the source region 200 is defined as the source 22, and the heavily doped region in the drain region 300 is defined as the drain 23. The source 22 and the drain 23 are located on both sides of the channel region. After the source 22 and the drain 23 are formed, subsequent metal silicide and metal wiring are fabricated, which will not be described in detail here.

[0071] See also Figures 15 to 17 As shown, in one embodiment of the present invention, the present invention also provides a pair of comparisons. In the comparison example, the channel of the MOS transistor adopts a planar channel, and the remaining features are the same as those of the present application. In this embodiment, semiconductor process simulation and device simulation tools (Technology Computer Aided Design, TCAD) are used to simulate the semiconductor device (Zig channel device) provided in the embodiment and the semiconductor device (Planar channel device) provided in the comparison example. Among them, the channel length of the semiconductor device in the embodiment is, for example, 0.7 microns, that is, the distance between the source and the drain is 0.7μm, and the channel length of the semiconductor device in the comparison example is, for example, 1.2 microns, that is, the distance between the source and the drain is 1.2μm. From Fig.16 and Fig.17 It can be seen that, in the comparative example and the embodiment, by comparing the transfer characteristic curve and the subthreshold swing of the semiconductor device, the performance of the embodiment and the comparative example is similar, but the channel length of the semiconductor device in the embodiment is smaller than the channel length of the semiconductor device in the comparative example. Therefore, under the condition of the same performance, the size of the semiconductor device is reduced by about 42%, the integration of the semiconductor device is improved, the substrate utilization rate is improved, the development trend of the semiconductor device is met, and the applicability of the semiconductor device is improved.

[0072] In summary, the present invention provides a semiconductor device and a method for manufacturing the same, which can reduce the size of the semiconductor device in the length direction, thereby reducing the area of ​​the semiconductor device, improving the utilization rate of the substrate, and reducing the cost. It can reduce the distance between the source and the drain, thereby adjusting the threshold voltage, saturation current, leakage and other electrical properties of the semiconductor device, and improving the performance of the semiconductor device. It can reduce the interface state density, improve the carrier mobility, and improve the thermal stability of the semiconductor device. It can improve the integration of semiconductor devices and meet the development trend of semiconductor devices.

[0073] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: providing a substrate, the substrate comprising a channel region, a source region and a drain region, Etching a portion of the substrate to form a plurality of recesses in the channel region; A continuous epitaxial compensation layer is formed on the substrate of the concave portion and the channel region, wherein the surface of the epitaxial compensation layer has a plurality of protrusions along the length direction of the device, and the length direction is the direction from the source region to the drain region; wherein the epitaxial compensation layer is formed by an epitaxial growth method, and the epitaxial compensation layer is a single crystal silicon, gallium nitride, gallium arsenide, silicon germanium, indium nitride, aluminum nitride or silicon carbide epitaxial layer; forming a gate on the epitaxial compensation layer; forming a source electrode in the source region on one side of the gate; as well as A drain electrode is formed in the drain region at one side of the gate.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The method for forming the concave portion comprises: forming a sacrificial oxide layer and a sacrificial nitride layer in sequence on the substrate; forming a first photoresist layer on the sacrificial nitride layer, wherein a plurality of first openings distributed equidistantly are formed on the first photoresist layer, and the opening widths of the plurality of first openings are equal; The sacrificial nitride layer, the sacrificial oxide layer and a portion of the substrate are etched using the first photoresist layer as a mask to form a plurality of recesses.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: The manufacturing method further comprises: After forming the recess, removing the sacrificial nitride layer and the sacrificial oxide layer on the channel region; The continuous epitaxial compensation layer is formed on the substrate in the recess and the channel region by an epitaxial growth method.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: In the length direction, the opening width of the concave portion is 2nm~200nm, and the spacing between adjacent concave portions is 2nm~50nm.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: In the width direction of the device, the recesses are distributed in a strip shape, and the width direction is perpendicular to the length direction.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: The substrate is a single material substrate or a stacked substrate. The stacked substrate includes a first semiconductor layer, an insulating layer, and a second semiconductor layer. The insulating layer is arranged between the first semiconductor layer and the second semiconductor layer.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: When the substrate is a stacked substrate, the recess is disposed in the second semiconductor layer, and a depth of the recess is less than or equal to a thickness of the second semiconductor layer.

8. The method for manufacturing a semiconductor device according to claim 1, wherein: When the epitaxial compensation layer is formed, a triangular gap is formed at the bottom of the recess.

9. A semiconductor device, characterized in that: Obtained by the manufacturing method according to any one of claims 1 to 8, comprising: A substrate, comprising a channel region, a source region and a drain region, wherein the source region and the drain region are arranged on both sides of the channel region, and a plurality of recesses are arranged in the channel region; An epitaxial compensation layer is continuously arranged on the channel region and the recess, and a surface of the epitaxial compensation layer has a plurality of protrusions along a length direction of the device, and the length direction is a direction from the source region to the drain region; the epitaxial compensation layer is obtained by an epitaxial growth method, and the epitaxial compensation layer is a single crystal silicon, gallium nitride, gallium arsenide, silicon germanium, indium nitride, aluminum nitride or silicon carbide epitaxial layer; A gate, disposed on the epitaxial compensation layer; a source electrode, disposed in the source region on one side of the gate; and A drain electrode is arranged in the drain region on the other side of the gate.

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