A method for raising and lowering channels based on a retimer chip

Abstract

The present invention provides a method for performing channel up-and-down based on a retimer chip, specifically including the following processes: P1. The retimer chip determines whether to support the L0p function; based on the retimer chip in the P1 successfully negotiating to support the L0p function, the method also includes the following processes: P2. The retimer chip performs a down-size operation in the L0p state; P3. The retimer chip performs an up-size operation in the L0p state; the retimer chip selects to execute the P2 and P3 processes according to the current state to realize the channel up-and-down. The method solves the problem that the retimer chip realizes the dynamic channel up-and-down functions in the L0p state; realizes the channel alignment operation under the retimer chip; in the L0p state, power consumption can be reduced under the premise of ensuring full use of bandwidth; no training operation is required for the retimer chip when dynamically changing the link; the retimer chip can diagnose abnormal behavior of the current system in the L0p state.

Description

Technical Field

[0001] The invention belongs to the technical field of high-speed interface bus power management, and in particular relates to a method for performing channel lifting and lowering based on a retimer chip. Background Art

[0002] PCIe (Peripheral Component Interconnect Express) is a high-performance, universal high-speed serial bus standard proposed by Intel in 2001. It is the I / O local bus standard of the existing computer architecture. By using high-speed serial transmission, PCIe can support external devices with higher signal transmission rates and bandwidth requirements.

[0003] Compared with previous versions, PCIe6.0 introduces L0p (Low-Power Active State) mode. Earlier versions of PCIe support shutting down unused channels, but re-enabling them requires reconfiguration. The L0p mode of PCIe6.0 supports dynamic switching of channels, allowing users to more flexibly manage system power consumption and adjust the balance between performance and power consumption in real time according to application scenarios. For example, all channels can be turned on when high throughput is required, and redundant channels can be turned off to save power when high throughput is not required. This adjustment does not require operations such as phy layer training.

[0004] In the scenario of high-speed data transmission, signal quality will decrease as the transmission distance and complexity increase. As a hybrid digital-analog signal device, retimer has the ability to sense and fully recover the data signal and resend it. Using retimer to enhance the transmission signal in PCIe link can effectively solve the signal attenuation problem while ensuring the integrity and accuracy of the signal.

[0005] Compared with traditional power management strategies, such as L0s state, L0p can provide more refined and flexible power management capabilities in FLIT mode, especially for scenarios with dynamic bandwidth requirements or intermittent communication requirements. In addition, L0p can achieve dynamic switching through an automated hardware control mechanism and supports retimer devices, so that the entire link architecture can save energy while ensuring link stability and performance.

[0006] This makes it important to solve the dynamic up / down channel of the retimer chip in the L0p state. Summary of the invention

[0007] The purpose of the present invention is to propose a method for performing channel up and down based on a retimer chip, so as to solve the technical problem of dynamically up and down channels of a retimer chip in the L0p state proposed in the above background technology.

[0008] To achieve the above object, the present invention provides the following technical solutions:

[0009] A method for performing an up / down channel based on a retimer chip specifically includes the following processes:

[0010] The P1.retimer chip determines whether it supports the L0p function, which includes the following steps:

[0011] S1. The retimer is initially in the detect state. During the link establishment process, two consecutive TS1s are received that are not padpad, and the flit bit in the bitstream is valid. At the same time, the linkup of the retimer is 0 and the flit mode register is valid, and the flit mode negotiation is completed;

[0012] S2. After the flit mode is valid based on the previous negotiation, the retimer captures whether both devices support the L0p function when TS2 in the bitstream is non-padpad. When the L0p capability bit is valid, the retimer considers that both devices support the L0p function.

[0013] S3. If any of the two conditions S1 and S2 are not satisfied, the retimer considers that the L0p function is not supported;

[0014] Based on the successful negotiation of the retimer chip in P1 to support the L0p function, the method further includes the following process:

[0015] P2. The retimer chip performs down-size operation in L0p state;

[0016] P3.retimer chip performs up-size operation in L0p state;

[0017] The retimer chip selects to execute the P2 and P3 processes according to the current state to realize the lifting and lowering channels.

[0018] Furthermore, the P2 specifically comprises the following steps:

[0019] S1. When the retimer enters the no-training state, it checks whether an EIOS is received;

[0020] S2. For the lane that receives the EIOS, the retimer first forwards the EIOS in its entirety;

[0021] S3. After waiting for the EIOS forwarding to be completed, the retimer puts the lane that received the EIOS into the electrical idle state. At the same time, the retimer pulls up the pipe_rx_standby signal and sends it to the physical layer.

[0022] Furthermore, the P3 specifically comprises the following steps:

[0023] S1. Currently in L0p state, when the lane to be activated receives EIEOS, the retimer pulls pipe_rx_standy down and passes it to the physical layer;

[0024] S2. When the retimer detects the exit from the electrical idle state, it completes the de-skew operation starting from the receipt of SKP;

[0025] S3. Status judgment after up-sizing is completed: When up-sizing is completed, if the current lane is not full, the retimer continues to be in the L0p state; when the full lane is detected, the retimer exits the L0p state.

[0026] Furthermore, the invention also includes an operation flow of a channel to be activated in the L0p state of a retimer chip, which specifically includes the following steps:

[0027] When S1.retimer detects exiting the electrical idle state, it uses different methods to record the number of lanes to be active according to different technology versions. For Gen1, it detects the number of lanes with rx_elecidle pulled low. For Gen2 and above, it detects the number of lanes with rx_data_elecidle pulled low and EIEOS received at the same time.

[0028] S2. After the retimer detects that all lanes to be activated have received SKP, the retimer chip performs FIFO write operation;

[0029] S3. When lane 0 reads out SKP, the retimer chip simultaneously reads out the data of all lanes to be activated.

[0030] The present invention has the following beneficial effects:

[0031] 1. Solved the problem of retimer chip achieving dynamic channel up and down in L0p state. Through in-depth research and technological innovation, we found an effective solution to ensure that the chip can smoothly achieve dynamic channel up and down operations in this specific state, providing strong support for system performance improvement and function expansion.

[0032] 2. Based on the above method, the channel alignment operation is effectively realized under the retimer chip. With the help of advanced technical means and precise algorithms, based on this method, under the action of the retimer chip, the channel alignment is efficiently completed, making data transmission more accurate and stable, and improving the overall performance of the system.

[0033] 3. In the L0p state, it is possible to effectively reduce power consumption while ensuring full utilization of bandwidth. In the L0p state, it ensures that bandwidth is fully utilized to meet the system's demand for data transmission speed, while also reducing power consumption and improving energy efficiency.

[0034] 4. For the retimer chip, the training process can be simplified, and no training operation is required when the link is dynamically changed. This feature makes the retimer chip more convenient and efficient in practical applications, reduces the complexity and time cost of the system, and improves the reliability and stability of the system.

[0035] 5. The retimer chip can diagnose abnormal behavior of the current system in the L0p state. With its powerful diagnostic function, the retimer chip can promptly detect abnormal conditions of the system in the L0p state, providing an important basis for system maintenance and troubleshooting, and ensuring the normal operation of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0037] Figure 1 Schematic diagram of the position of L0p in the link state machine;

[0038] Figure 2 Flowchart for determining whether the retimer supports L0p function;

[0039] Figure 3 This is the flowchart of the down-size operation of the retimer chip in the L0p state;

[0040] Figure 4 This is the flow chart of the up-size operation of the retimer chip in the L0p state;

[0041] Figure 5 This is a simplified diagram of the retimer performing lane upgrading operation in L0p state;

[0042] Figure 6 This is the operation flow chart of the retimer chip in the L0p state to activate the channel;

[0043] Figure 7 This is the state machine jump block diagram at L0p. DETAILED DESCRIPTION

[0044] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0045] In the L0p state, some lanes of the link are in a dormant state, while other lanes remain active. The position of L0p in the Link Training and Status State Machine (LTSSM) is as follows: Figure 1 As shown, it is not one of the LTSSM main states, in a sense, L0p is part of L0.

[0046] The L0 state usually represents the full-performance operating state under normal working conditions. L0p can be regarded as a special case or extension of L0. It reduces power consumption while maintaining a certain degree of activity. In a sense, L0p is an optimization and supplement to L0. When the system does not need full high-performance operation but cannot enter a completely low-power state (such as L0s), L0p can provide an intermediate choice. It reduces power consumption while maintaining certain functions and responsiveness, which helps to improve the energy efficiency of the system. This design makes power management more flexible, and can dynamically switch between different states according to different workloads and needs to achieve the best balance between performance and power consumption.

[0047] The L0p state can be negotiated dynamically, and the channel can be shut down and started without going through the Recovery state. When switching between L0 and L0p states, the link always remains active, allowing for active and efficient use of L0p mode.

[0048] At the same time, for the retimer, it is possible to shut down some lanes during operation, which makes it possible to further optimize power management. When it is necessary to turn on the remaining lanes, the remaining lanes can be turned on while other lanes are working normally. This dynamic adjustment capability enables the system to allocate resources according to actual load and performance requirements. Moreover, during the startup process, the de-skew processing between new channels and the de-skew processing between newly added channels and normal active channels can be completed, ensuring the stability of the system and the accuracy of data transmission.

[0049] Open remaining channels: When a previously closed channel needs to be opened, the retimer can operate while other channels are operating normally. This means that the system can dynamically increase the number of available channels without interrupting overall operation to meet sudden increases in bandwidth requirements or to respond to specific task requirements.

[0050] De-skew between new channels: In the process of opening the remaining channels, the retimer can complete the de-skew between the new channels. Since different channels may have differences such as signal transmission delay, de-skew is a key step to ensure that each channel can work synchronously. By de-skewing the newly opened channels, the retimer can ensure good consistency and stability of data transmission between these channels.

[0051] De-skew the newly added channels from the normally active channels: Not only do the newly opened channels need to be de-skewed, but the newly added channels also need to be de-skewed from the normally active channels. This is to ensure that the channels of the entire system can maintain a coordinated and consistent working state whenever they are adjusted. This de-skew process can effectively avoid data transmission errors and performance degradation caused by signal differences between channels.

[0052] The specific implementation of the L0p function based on the retimer chip includes the following processes:

[0053] The P1.retimer chip determines whether it supports the L0p function. The process is as follows Figure 2 As shown, the specific steps include the following steps.

[0054] S1.retimer is initially in the detect state, which is a starting state for detecting and responding to link status. During the link establishment process, if two consecutive TS1 (Training Sequence 1) are received as non-padpad, and the flit bit in the code stream is valid, and the linkup of the retimer is 0 and the flit mode register is valid, it is considered that the flit mode negotiation in this link establishment is completed. This series of conditions is judged to determine whether the specific mode of data transmission is successfully negotiated, laying the foundation for the subsequent judgment of whether the L0p function is supported.

[0055] S2. After the flit mode is valid based on the previous negotiation, the retimer captures whether both devices support the L0p function when TS2 in the bitstream is non-padpad. When the L0p capability bit is valid, the retimer assumes that both devices support the L0p function. This step is to further determine the support of the L0p function based on the completion of the flit mode negotiation. By checking specific signal bits, the retimer attempts to determine whether the entire link has the ability to support the low-power mode of L0p.

[0056] S3. If any of the above two conditions are not met, the retimer will consider that the L0p function is not supported. This is a clear judgment logic that ensures that the link where the retimer is located is considered to support the L0p function only when specific link negotiation and function bit check conditions are met. If any key condition is not met, the retimer will conclude that the L0p function is not supported, and may adopt different operation strategies or enter different working states.

[0057] The P2.retimer chip performs down-size operation in L0p state. The process is as follows: Figure 3 As shown, the specific steps include the following steps.

[0058] Based on the fact that the retimer chip in P1 has successfully negotiated to support the L0p function, it means that the system has the ability to dynamically adjust the number of channels to reduce power consumption under certain circumstances.

[0059] S1. When the retimer enters the no-training state, it detects whether it has received EIOS (Electrical Idle Ordered Set). The detection in this state is to determine which channels can enter the low-power state. EIOS is usually an indication signal used to notify the devices in the link to enter the electrical idle state.

[0060] S2. For the lane that receives the EIOS, the retimer first forwards the EIOS completely to ensure that other devices on the link can also receive the signal so that they can perform corresponding operations synchronously. By forwarding the EIOS, the retimer plays a relay and coordination role to ensure the consistency of the status of the entire link.

[0061] S3. After waiting for EIOS forwarding to be completed, the retimer puts the lanes that received EIOS into electrical idle state, which means that these lanes will stop data transmission and enter low power mode to reduce the overall power consumption of the system. By putting specific lanes into electrical idle state, the retimer implements the function of dynamically adjusting the number of channels to optimize power consumption and performance according to actual needs.

[0062] At the same time, the retimer also needs to pull up the pipe_rx_standby signal and send it to the physical layer (PHY). This signal may be used to notify the physical layer (PHY) device that some channels have entered the standby or low power state. By sending this signal to the PHY, the retimer works with the PHY to ensure the stable operation of the entire system in a low power state.

[0063] In summary, the down-size operation of the retimer in the L0p state is a delicate process, which realizes the dynamic power management and performance optimization of the system by detecting the EIOS signal, forwarding the signal, putting the specific lane into the electrical idle state, and communicating with the PHY.

[0064] The P3.retimer chip performs up-size operation in L0p state. The process is as follows: Figure 4 As shown, the specific steps include the following steps.

[0065] S1. When currently in L0p state, only some lanes are active, indicating that the system is in a low-power operation mode. When the lane to be activated receives EIEOS (Electrical Idle Exit Ordered Set), the retimer needs to pull pipe_rx_standy low and pass it to PHY. This action is to notify the physical layer (PHY) device that a lane is about to change from a low-power state to an active state so that the PHY can make corresponding preparations.

[0066] S2. When the retimer detects the exit from the electrical idle state, it completes the de-skew operation from the receipt of the SKP (Skip Ordered Set). SKP plays an important role in high-speed data transmission. It can be used to adjust the clock and data alignment to ensure synchronization between different channels. By completing the de-skew operation, the retimer can ensure that data is transmitted in a synchronous manner on each channel, improving the accuracy and reliability of data transmission.

[0067] S3. Status judgment after up-size is completed: When up-size is completed, if the current lane is not full, the retimer continues to be in the L0p state, and only some channels are sent to send data, indicating that although some lanes are activated, the system has not reached the state of full load operation, so it continues to maintain low power mode and transmit data with some active lanes; when the full lane is detected and the L0p state is exited, it means that the system has returned to normal working state, all lanes are active, and can meet high data transmission requirements. At this time, the retimer is no longer in the low-power L0p state, but runs at full power to ensure efficient data transmission.

[0068] In summary, the up-size operation of the retimer in the L0p state is a dynamic process. By detecting and responding to different signals and switching states according to the activation status of the lane, the system can flexibly switch between low power consumption and high performance.

[0069] The lane upgrading operation of the retimer in L0p state can be simplified as follows: Figure 5 When the retimer performs up-size operation in L0p state, since all lanes will send SKP at the same time during the up-size process, and since the skew between each lane in L0p state is fixed, when waiting for lane0 to start reading SKP, the lane to be activated also reads FIFO data.

[0070] The P4.retimer chip is in the L0p state to activate the channel operation. The process is as follows Figure 6 As shown, the specific steps include the following steps.

[0071] The S1.retimer chip is initially in L0p state, some channels are in low power or inactive state, and only certain lanes are sending data streams.

[0072] S2.retimer continuously monitors the link status. When it detects that the electrical idle state has been exited, it needs to record the number of lanes to be active in different ways according to different technology versions.

[0073] For Gen1, detect the number of lanes pulled low by rx_elecidle. When the rx_elecidle signal is pulled low, it indicates that the corresponding lane may be about to change from the idle state to the active state. The number of lanes to be active is determined by counting the number of these pulled low signals.

[0074] For Gen2 and above, detect the number of lanes that receive EIEOS (ElectricalIdle Exit Ordered Set) while rx_data_elecidle is pulled low. rx_data_elecidle being pulled low indicates that symbol lock may have been completed, that is, the preparation for data transmission has been preliminarily completed, and receiving EIEOS further confirms that the link has exited the electrical idle state and is about to enter the active state. In this way, the number of lanes to be activated is determined.

[0075] S3. Wait for SKP and FIFO to be written

[0076] The retimer waits to detect that all lanes to be activated have received SKP (Skip Ordered Set). SKP is used to adjust clock and data alignment in high-speed data transmission to ensure synchronization between different channels. The retimer chip needs to wait for all lanes to be activated to receive SKP to ensure that these channels have completed the necessary preparations before data transmission, such as clock synchronization and data alignment.

[0077] Once all lanes to be activated have received SKP, the retimer chip will perform a FIFO (First In First Out) write operation. The received data is written into the FIFO buffer to prepare for subsequent data transmission. FIFO is a data buffering mechanism that ensures that data is stored and read in order to avoid data loss or confusion.

[0078] S4.lane0 reads SKP and data

[0079] Lane 0 is usually used as a reference channel. When lane 0 reads SKP, it means that the clock and data alignment of the entire system has reached a stable state. At this time, the retimer chip can judge the readiness of other channels based on the status of lane 0. Once lane 0 reads SKP, the retimer chip will read the data of all lanes to be activated at the same time. This ensures the synchronous transmission of data between different channels and improves the efficiency and accuracy of data transmission.

[0080] In summary, the retimer chip achieves efficient switching from low-power state to active state through precise monitoring and control in the L0p state, ensuring the stability and reliability of data transmission.

[0081] The upgrade channel is realized by switching between different states. The state machine jump diagram at L0p is as follows: Figure 7 As shown, there are mainly the following states:

[0082] 1. Bonded state

[0083] When the link is initially established, all lanes are in an active state, which means that all data channels are working normally and are ready for data transmission. In this state, the de-skew operation is completed, that is, the signal delay between different channels is adjusted to ensure that data can be transmitted synchronously on each channel. This state is the initial state of normal system operation and provides a stable foundation for subsequent data transmission.

[0084] 2.L0p_downsize_done status

[0085] When the system enters this state, the retimer will close the lanes that receive the EIOS (Electrical Idle Ordered Set). The EIOS signal is usually used to indicate that the link has entered the electrical idle state. Closing these lanes can reduce the power consumption of the system and prepare for subsequent dynamic adjustments. In this state, the system enters a low-power mode, but still maintains monitoring of the link status so that the corresponding lane can be quickly activated when needed.

[0086] 3.L0p_upsize_wait state

[0087] During the up-sizing process, the retimer first needs to identify the number and specific channels to be activated. This state indicates that the system is preparing to switch back to normal working mode from low power mode, or that more lanes need to be activated due to increased data transmission requirements. The retimer determines which lanes need to be activated and the number of lanes to be activated by monitoring the link status and receiving specific signals. This is a critical transition state to prepare for subsequent data transmission.

[0088] 4.L0p_upsize_write state

[0089] When all lanes to be activated receive SKP (Skip Ordered Set), they start writing data to FIFO (First In First Out). SKP is usually used to adjust clock and data alignment to ensure synchronization between different channels. In this state, the lanes to be activated have completed preparations and started writing data to the FIFO buffer to prepare for subsequent data transmission. This state indicates that the system is gradually returning to normal working state and data transmission is about to begin.

[0090] 5.L0p_upsize_done status

[0091] In this state, the maximum number of active lanes has not been reached after the retimer completes the up-size. At the same time, the retimer waits until lane0 starts reading SKP, and other lanes to be activated start reading data. This state indicates that the system has completed the switch from low power mode to partially active state, but may still need to further activate more lanes to meet higher data transmission requirements. At this time, the system continues to monitor the link status so that further adjustments can be made when necessary.

[0092] 6. Unbonded state

[0093] This state is similar to the IDLE state, and the link needs to re-complete the de-skew operation. If the specific number of lanes to be activated is identified as illegal (such as X3, X5, etc.) in the L0p_upsize_wait state within a period of time, or the SKP of the lane to be activated is not received in the L0p_upsize_write state for a period of time, and SKP error or FIFO overflow occurs in the L0p_upsize_done and bonded states, the system will return to the unbonded state. This state is a fault recovery state. When the system encounters an abnormal situation, by returning to the unbonded state and re-performing the de-skew operation, it can ensure that the system can re-establish a stable data transmission link.

[0094] The preferred embodiments of the present invention disclosed above are only used to help explain the present invention. The preferred embodiments do not describe all the details in detail, nor do they limit the invention to the specific implementation methods described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well.

Claims

1. A method for performing channel lifting based on a retimer chip, characterized in that: The specific process includes the following: The P1.retimer chip determines whether it supports the L0p function, which includes the following steps: S1. The retimer is initially in the detect state. During the link establishment process, two consecutive TS1s are received that are not padpad, and the flit bit in the bitstream is valid. At the same time, the linkup of the retimer is 0 and the flit mode register is valid, and the flit mode negotiation is completed; S2. After the flit mode is valid based on the previous negotiation, the retimer captures whether both devices support the L0p function when TS2 in the bitstream is non-padpad. When the L0p capability bit is valid, the retimer considers that both devices support the L0p function. S3. If any of the two conditions S1 and S2 are not satisfied, the retimer considers that the L0p function is not supported; Based on the successful negotiation of the retimer chip in P1 to support the L0p function, the method further includes the following process: P2. The retimer chip performs down-size operation in L0p state; P3.retimer chip performs up-size operation in L0p state; The retimer chip selects to execute the P2 and P3 processes according to the current state to realize the lifting and lowering channels.

2. The method for performing channel lifting based on a retimer chip according to claim 1, characterized in that: The P2 specifically comprises the following steps: S1. When the retimer enters the no-training state, it checks whether an EIOS is received; S2. For the lane that receives the EIOS, the retimer first forwards the EIOS in its entirety; S3. After waiting for the EIOS forwarding to be completed, the retimer puts the lane that received the EIOS into the electrical idle state. At the same time, the retimer pulls up the pipe_rx_standby signal and sends it to the physical layer.

3. The method for performing channel lifting based on a retimer chip according to claim 2, characterized in that: The P3 specifically comprises the following steps: S1. Currently in L0p state, when the lane to be activated receives EIEOS, the retimer pulls pipe_rx_standy down and passes it to the physical layer; S2. When the retimer detects the exit from the electrical idle state, it completes the de-skew operation starting from the receipt of SKP; S3. Status judgment after up-sizing is completed: When up-sizing is completed, if the current lane is not full, the retimer continues to be in L0p state; when a full lane is detected, the retimer exits the L0p state.

4. A method for performing channel lifting and lowering based on a retimer chip according to any one of claims 1 to 3, characterized in that: It also includes the operation flow of the retimer chip in the L0p state to be activated channel, which specifically includes the following steps: When S1.retimer detects exiting the electrical idle state, it uses different methods to record the number of lanes to be active according to different technology versions. For Gen1, it detects the number of lanes with rx_elecidle pulled low. For Gen2 and above, it detects the number of lanes with rx_data_elecidle pulled low and EIEOS received at the same time. S2. After the retimer detects that all lanes to be activated have received SKP, the retimer chip performs FIFO write operation; S3. When lane 0 reads out SKP, the retimer chip simultaneously reads out the data of all lanes to be activated.

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