A method for sharing global configuration registers

Abstract

The present invention discloses a method for sharing global configuration registers, and belongs to the technical field of integrated circuits. A main body global configuration register is implemented at the top layer or a certain layer of a chip, and the main body global configuration register can be written or read; in each module that needs to use the main body global configuration register, a set of shadow global configuration registers is implemented, and the shadow global configuration register can only be written but not read; the main body global configuration register and the shadow global configuration register share the same address (M~N). When writing to the address M~N space, the top-level main body global configuration register and the shadow global configuration registers in each module are immediately written and effective; when reading the address M~N space, only the main body global configuration register is read. The method provided by the present invention not only solves the problems of wiring complexity and wiring difficulty, but also simplifies system application, does not waste the address space of the register, and does not cause time difference in the information seen by each module.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a method for sharing a global configuration register. Background Art

[0002] In the chip, some register settings are shared by the whole chip, such as chip mode (chip_mode), system frequency (system_clock_freq), etc. In addition to being used by the top level, the bottom level modules also use them. There are currently two ways to do this: Figure 1 As shown in the figure, all the configuration register information needed is pulled to the modules that need it. The disadvantage of this method is that there are many wires, which will cause the complexity of the connection between modules, make winding difficult, and increase the interface complexity and layout and routing difficulty of each module. If the chip has m (m may be as high as dozens or even hundreds) such global configuration registers, and there are n (n may be as high as dozens or even dozens) modules that need to use this information, then each module needs to add m more input signals, and n modules need to add a total of m×n (may be as high as thousands or even tens of thousands) more. In layout and routing, a total of m×n wires need to be added. If some modules are placed far away, these m signals need to be pulled a long distance, occupying the layout and routing resources of the chip.

[0003] Method 2 Figure 2 As shown, the same registers are implemented in the modules that need to be used. Each register has its unique address. The disadvantage of this approach is that it occupies the register address. For example, the global configuration register needs addresses M0~N0. If they are implemented in n modules respectively, it is necessary to add n additional address spaces of M~N, resulting in address waste. At the same time, it will increase the complexity of system application. The system needs to configure multiple sets of registers during configuration, and it is necessary to ensure that there are no missing modules and that the information configured in each module is exactly the same. At the same time, it is necessary to avoid the situation where the inter-module linkage behavior errors caused by the time difference between the configuration of the registers of each module occur. Each module configures the same system parameters, such as the chip mode. Because of the time relationship before and after the configuration, the values ​​of the chip mode seen by each module are different within a certain period of time. At this time, it is necessary to ensure that the chip does not work abnormally.

[0004] As the size of chips grows, the wiring complexity and routing difficulties of method one become increasingly prominent, and the register address space waste and system complexity problems caused by method two also become increasingly prominent. Summary of the invention

[0005] The object of the present invention is to provide a method for sharing a global configuration register to solve the problems in the background technology.

[0006] In order to solve the above technical problems, the present invention provides a method for sharing a global configuration register, comprising:

[0007] Implementing a global configuration register of the main body at the top layer or a certain layer of the chip, wherein the global configuration register of the main body can be written or read through a register control bus;

[0008] In each module that needs to use the main body global configuration register, a set of shadow global configuration registers is implemented, and the shadow global configuration register can only be written but not read through the register control bus; the shadow global configuration register and the main body global configuration register use the same register address M~N;

[0009] When writing to the address M~N space, the top-level global configuration register of the main body and the shadow global configuration registers in each module are immediately written and take effect;

[0010] When the address M~N space is read, what is read is the main body global configuration register, that is, the main body global configuration register responds to the read instruction of the register control bus.

[0011] In one implementation, the register addresses of the main body global configuration register and the shadow global configuration register are the same; while configuring the main body global configuration register, all shadow global configuration registers can also see the same control signal and perform the same write operation, and the newly written value and the main body global configuration register take effect at the same time, ensuring that all modules see the same configuration information at the same time point.

[0012] In one implementation, the top-level main body global configuration register and the shadow global configuration register in each module are connected via a register control bus, which reduces the wiring between modules, reduces the complexity of the module interface and the complexity of the system.

[0013] In one embodiment, a monitoring module for the shadow global configuration register is set in each module that needs to use the main body global configuration register. The shadow global configuration register cannot be directly read out through the register control bus to confirm the value. The monitoring module reads out the shadow global configuration register for observation in an indirect way, selects the shadow global configuration register that needs to be observed and puts it into the readable register, and reads the value through the register control bus; or selects the shadow global configuration register that needs to be observed and puts it into the internal observation bus, and sends it to the chip pin for observation.

[0014] In one embodiment, the monitoring module checks and confirms whether the value of the shadow global configuration register meets expectations; controls and monitors the shadow global configuration register simultaneously through an existing register control bus, or observes the chip pins through an existing internal observation bus, without causing complexity of the module interface and system complexity.

[0015] The present invention provides a method for sharing global configuration registers. It only needs to configure a set of main body global configuration registers through the register control bus to make all shadow global configuration registers used in this information module effective at the same time. The problem of many connections between modules is reduced, which not only solves the problem of winding resources, but also simplifies the interface of each module and reduces the complexity of chip integration; in addition, it also solves the problem of register address waste caused by each module having a set of global configuration registers, and effectively solves the problem of system application complexity caused by the need to configure the same information several times, and avoids the problem of behavioral errors caused by different information viewing times due to time differences in configuring registers of different modules. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 The existing method is to pull all the configuration register information that needs to be used into the schematic diagram and layout wiring diagram of the module that needs to be used.

[0017] Figure 2 It is a schematic diagram and layout diagram of the existing method 2 for implementing the same register in the modules required.

[0018] Figure 3 It is a schematic diagram and layout wiring diagram of a method for sharing a global configuration register provided by the present invention.

[0019] Figure 4 It is a schematic diagram showing that when address M is written in the present invention, the top-level main body global configuration register and the shadow global configuration registers in each module are immediately written and take effect.

[0020] Figure 5 It is a schematic diagram of reading the global configuration register of the main body when reading address M according to the present invention.

[0021] Figure 6 This is a flowchart in which the top-level main body global configuration register and the shadow global configuration registers in each module are immediately written into and take effect when the address M space is written in the present invention.

[0022] Figure 7 It is a flow chart of reading the global configuration register of the main body when reading the address M space of the present invention.

[0023] Figure 8 It is a schematic diagram of the time when the configuration of each register of the present invention takes effect. DETAILED DESCRIPTION

[0024] The following is a further detailed description of a method for sharing a global configuration register proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0025] The present invention provides a method for sharing a global configuration register, such as Figure 3 As shown in the figure, the "entity global configuration register" is implemented (that is, actually made) at the top level or a certain level (the level is not limited, the figure takes the top level as an example), and its reading and writing are the same as ordinary registers, which can be written and read. In each module that needs to use this entity global configuration register, each implements a special set of "shadow global configuration registers", which are different from ordinary configuration registers. They can only be written but not read.

[0026] The addresses of the main body global configuration register and the shadow global configuration register are exactly the same, and their meanings are the same. For example, there is an address space with addresses M~N in the main body global configuration register, and there is also an address space with addresses M~N in the shadow global configuration register. The register with address M is the same as the chip mode (chip_mode).

[0027] By implementing the main body and shadow global configuration registers between modules, there is no need to pull many additional (up to thousands or tens of thousands) signal lines for configuration registers between modules. Read and write operations can be performed through the original register control bus, thus solving the problems of wiring complexity and winding difficulties in traditional methods.

[0028] When Figure 4 When the CPU issues a write instruction and writes address M to value B, the registers with address M in the top-level "global configuration register" and the "global configuration register in shadow" in each module are immediately written and effective, and the written values ​​are the same, both B. Figure 5 The central processing unit shown in the figure issues a read instruction to read address M. Only the global configuration register of the main body responds to the read instruction, and what is read is the value B of the global configuration register of the main body.

[0029] The main body global configuration register and the shadow global configuration register share the same address, which solves the problem of register address waste caused by the independent address of the register of each module in the traditional method.

[0030] like Figure 6 As shown in FIG. 1 , it is a flowchart of the CPU issuing a write instruction to write the register with address M to value B. Figure 7As shown, it is a flowchart of the central processing unit sending a read instruction, reading a register with address M, and returning a value of B.

[0031] The CPU only needs to issue a write instruction once to configure the main body global configuration register and the shadow global configuration register at the same time, which solves the problem of system configuration complexity caused by traditional methods. The values ​​of the main body global configuration register and the shadow global configuration register will be updated at the same time, such as Figure 8 As shown, it is ensured that the configuration information seen by all modules at the same time point is the same, avoiding the risk of abnormal chip behavior caused by the time difference between the effective time of each module configuration when configuring multiple modules in the traditional method.

[0032] The present invention not only solves the problems of wiring complexity and wiring difficulty in the existing traditional method, but also solves the problems of register address space waste and high system usage complexity in the traditional method.

[0033] The present invention also provides a monitoring module for monitoring the shadow global configuration register in the module. Because the shadow global configuration register cannot be directly read out through the register control bus to confirm the value, the monitoring module reads the shadow global configuration register out for observation in an indirect manner. The shadow global configuration register that needs to be observed can be selected and placed in a readable register, and the value can be read through the register control bus. The shadow global configuration register that needs to be observed can also be selected and placed in an internal observation bus and sent to the chip pin for observation.

[0034] The chip of the present invention has a main body global configuration register and a shadow global configuration register, and the register addresses are the same, and there is no additional register address overhead; when configuring the main body global configuration register, all the shadow global configuration registers will take effect at the same time, ensuring that the configuration information seen at the same time is the same; a monitoring module is provided to check and confirm whether the value of the shadow global configuration register meets expectations; the monitoring module also provides two methods, and the shadow global configuration register that needs to be observed can be selected and read out for observation through a register control bus, or sent to an internal signal observation bus planned for the chip and sent out for observation through the chip pins; the present invention controls and monitors the shadow global configuration register at the same time through the existing register control bus, or sends it to the chip pins for observation through the existing internal observation bus, without causing the complexity of the module interface and the complexity of the system.

[0035] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for sharing a global configuration register, characterized in that: include: Implementing a global configuration register of the main body at the top layer or a certain layer of the chip, wherein the global configuration register of the main body can be written or read through a register control bus; In each module that needs to use the main body global configuration register, a set of shadow global configuration registers is implemented, and the shadow global configuration register can only be written but not read through the register control bus; the shadow global configuration register and the main body global configuration register use the same register address M~N; When writing to the address M~N space, the top-level global configuration register of the main body and the shadow global configuration registers in each module are immediately written and take effect; When reading the address space M~N, what is read is the global configuration register of the main body, that is, the global configuration register of the main body responds to the read instruction of the register control bus; A monitoring module for the shadow global configuration register is set in each module that needs to use the main body global configuration register. The shadow global configuration register cannot be directly read out through the register control bus to confirm the value. The monitoring module reads out the shadow global configuration register for observation in an indirect way, selects the shadow global configuration register that needs to be observed and puts it into the readable register, and reads the value through the register control bus; or selects the shadow global configuration register that needs to be observed and puts it into the internal observation bus, and sends it to the chip pin for observation; The monitoring module checks and confirms whether the value of the shadow global configuration register meets expectations; The shadow global configuration register is controlled and monitored simultaneously through an existing register control bus, or sent to a chip pin for observation through an existing internal observation bus, without causing the complexity of the module interface and the system complexity.

2. The method for sharing a global configuration register as claimed in claim 1, characterized in that: The register addresses of the main body global configuration register and the shadow global configuration register are the same; when configuring the main body global configuration register, all shadow global configuration registers can also see the same control signal and perform the same write operation. The newly written value and the main body global configuration register take effect at the same time, ensuring that all modules see the same configuration information at the same time point.

3. The method for sharing a global configuration register as claimed in claim 1, characterized in that: The top-level main body global configuration register and the shadow global configuration register in each module are connected via a register control bus, which reduces the connection between modules, reduces the complexity of the module interface and the complexity of the system.

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