Cache memory and corresponding cache processing method thereof

Abstract

The invention discloses a cache memory and a corresponding cache processing method thereof. A plurality of cache groups are stored through a label unit in a cache memory, each cache group comprises a plurality of cache lines, each cache line comprises a label bit and an index bit, the label bit is used for storing a label address, the index bit is used for storing an index, a data unit is used for storing data, an identifier of the data is the index, and after an access request is received, the label address is stored in the data unit. And obtaining a matched existing label address according to a target label address in the access request, and accessing corresponding data in the data unit according to a target index corresponding to the matched existing label address. Therefore, the label address and the data are associated through the index, dynamic mapping between the data and the label address is achieved, the capacity proportion between the data and the label address can be flexibly adjusted, the capacity of the label unit can be increased, and meanwhile the capacity of the data unit can be kept unchanged; to improve hit rate without increasing area and power consumption of a cache memory.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a cache memory and a corresponding cache processing method. Background Art

[0002] In the field of computer technology, in order to increase the speed of data access by the processor, a cache memory is usually set between the processor and the main memory. The cache memory stores frequently used data, so that the processor can directly exchange data with the cache memory without accessing the main memory.

[0003] Among them, set-associative mapping is a common address mapping method. In the set-associative mapping in the prior art, tags and data are statically mapped, that is, the indexing method of tags is always equal to the indexing method of data. Therefore, if you want to increase the cache memory capacity to improve the hit rate, you usually need to increase the number of tags and the number of data at the same time. However, the bit width of the data is usually large, and increasing the amount of data will bring more area and power consumption to the chip. Summary of the invention

[0004] In view of this, an embodiment of the present invention aims to provide a cache memory and a corresponding cache processing method thereof, which can increase the capacity of the tag unit while keeping the data unit capacity unchanged, so as to improve the hit rate without increasing the area and power consumption of the cache memory.

[0005] In a first aspect, an embodiment of the present invention provides a cache processing method, which is applied to a cache memory, wherein the cache memory includes a tag unit and a data unit, wherein the tag unit stores multiple cache groups, each cache group includes multiple cache lines, each cache line includes a tag bit and an index bit, the tag bit is used to store a tag address, the index bit is used to store an index, the data unit is used to store data, and an identifier of the data is the index, and the method includes:

[0006] receiving an access request, wherein the access request includes a target tag address;

[0007] Matching the target label address with an existing label address in the label unit;

[0008] In response to obtaining a matching existing label address, determining a target index corresponding to the matching existing label address; and

[0009] The corresponding data is accessed in the data unit according to the target index.

[0010] In a second aspect, an embodiment of the present invention provides a cache memory, wherein the cache memory comprises:

[0011] A tag unit, used to store a plurality of cache groups, each cache group includes a plurality of cache lines, each cache line includes a tag bit and an index bit, the tag bit is used to store a tag address, and the index bit is used to store an index;

[0012] A data unit, used for storing data, wherein an identifier of the data is the index;

[0013] An information unit, used to store the valid state and replacement state of each data and the position of the label address corresponding to the data in the label unit;

[0014] A matching unit is used to receive an access request, wherein the access request includes a target tag address, match the target tag address with an existing tag address in the tag unit, and in response to obtaining a matched existing tag address, determine a target index corresponding to the matched existing tag address and access corresponding data in the data unit according to the target index.

[0015] In a third aspect, an embodiment of the present invention provides a cache processing device, which is applied to a cache memory, wherein the cache memory includes a tag unit and a data unit, wherein the tag unit stores multiple cache groups, each cache group includes multiple cache lines, each cache line includes a tag bit and an index bit, the tag bit is used to store a tag address, the index bit is used to store an index, the data unit is used to store data, and the identifier of the data is the index, and the device includes:

[0016] A request receiving unit, configured to receive an access request, wherein the access request includes a target tag address;

[0017] A label address matching unit, used to match the target label address with an existing label address in the label unit;

[0018] a target index determining unit, configured to determine a target index corresponding to the matched existing label address in response to obtaining the matched existing label address; and

[0019] A data access unit is used to access corresponding data in the data unit according to the target index.

[0020] In a fourth aspect, an embodiment of the present invention provides an electronic device, the electronic device comprising:

[0021] processor;

[0022] Address bus;

[0023] Data bus;

[0024] Main memory;

[0025] A cache memory as described in the second aspect.

[0026] The technical solution of the embodiment of the present invention stores multiple cache groups through the tag unit in the cache memory, each cache group includes multiple cache lines, each cache line includes a tag bit and an index bit, the tag bit is used to store the tag address, the index bit is used to store the index, the data unit stores data, the identifier of the data is the index, after receiving the access request, the matching existing tag address is obtained according to the target tag address in the access request, and the corresponding data is accessed in the data unit according to the target index corresponding to the matching existing tag address. Thus, the tag address and the data are respectively associated through the index, and the dynamic mapping between the data and the tag address is realized, the capacity ratio between the data and the tag address can be flexibly adjusted, and the capacity of the tag unit can be increased while keeping the data unit capacity unchanged, so as to improve the hit rate without increasing the area and power consumption of the cache memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0028] Figure 1 is a schematic diagram of an electronic device according to an embodiment of the present invention;

[0029] Figure 2 is a schematic diagram of a prior art group-associative mapping;

[0030] Figure 3 It is a schematic diagram of the mapping relationship of the prior art;

[0031] Figure 4 is a schematic diagram of a cache memory according to an embodiment of the present invention;

[0032] Figure 5 is a flow chart of a cache processing method according to an embodiment of the present invention;

[0033] Figure 6 is a schematic diagram of a group associative mapping according to an embodiment of the present invention;

[0034] Figure 7 is a schematic diagram of a group associative mapping according to another embodiment of the present invention;

[0035] Figure 8 is a schematic diagram of a group associative mapping according to another embodiment of the present invention;

[0036] Fig. 9 is a flow chart of a cache processing method according to another embodiment of the present invention;

[0037] Fig.10 It is a schematic diagram of a cache processing device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0038] The present invention is described below based on embodiments, but the present invention is not limited to these embodiments. In the detailed description of the present invention below, some specific details are described in detail. It is possible for a person skilled in the art to fully understand the present invention without the description of these details. In order to avoid confusing the essence of the present invention, known methods, processes, flows, components and circuits are not described in detail.

[0039] In addition, persons of ordinary skill in the art will appreciate that the drawings provided herein are for illustration purposes and are not necessarily drawn to scale.

[0040] At the same time, it should be understood that in the following description, "circuit" refers to a conductive loop composed of at least one element or subcircuit through electrical connection or electromagnetic connection. When an element or circuit is said to be "connected to" another element or an element / circuit is said to be "connected between" two nodes, it can be directly coupled or connected to another element or there can be an intermediate element, and the connection between the elements can be physical, logical, or a combination thereof. On the contrary, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.

[0041] Unless the context clearly requires otherwise, the words "include", "comprising" and the like throughout this application should be interpreted as including rather than exclusive or exhaustive; that is, as meaning "including but not limited to".

[0042] In the description of the present invention, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0043] Figure 1 Schematic diagram of an electronic device according to an embodiment of the present invention. Figure 1 As shown, the electronic device according to the embodiment of the present invention includes a processor 1, a cache memory 2, a main memory 3, an address bus 4 and a data bus 5.

[0044] The processor 1 may be an independent microprocessor or a collection of one or more microprocessors.

[0045] Main memory 3 is internal memory, also known as memory, which is used to store programs and data.

[0046] The address bus 4 is used to transmit the address of data.

[0047] The data bus 5 is used to transmit data.

[0048] Since the operation speed of the processor is too fast, the data access speed of the main memory 3 cannot keep up with the speed of the processor 1, so a cache memory 2 is set between the processor 1 and the main memory 3. Cache memory is a memory with a faster access speed than the main memory. It has a relatively small capacity but a much higher speed than the main memory. The cache memory stores the data frequently used by the processor, so that the processor can directly exchange data with the cache memory without accessing the main memory. It can solve the speed mismatch problem between the processor 1 and the main memory 3, avoid frequent data access between the main memory and the auxiliary memory, and thus improve the execution efficiency of the system.

[0049] Since the capacity of cache memory 2 is smaller than that of main memory 3, cache memory 2 can only store a portion of the data in main memory 3. Therefore, not all data accessed by the processor are stored in cache memory. The hit rate is the ratio of information to be accessed by the processor that is already in the cache memory, which is used to measure the efficiency of the cache memory.

[0050] In order to facilitate the exchange of information between the cache and the main memory, both the cache and the main memory are divided into equal blocks. A cache block is also called a cache line. Each block consists of several bytes. The length of the block is called the block length. Since the capacity of the cache is much smaller than that of the main memory, the number of blocks in the cache is much smaller than the number of blocks in the main memory. The cache only stores copies of the most active blocks in the main memory.

[0051] Assuming that the main memory is addressed by bytes and the address is represented by n-bit binary code, then the main memory capacity is 2 n B; the block size is 16 bytes, so the number of blocks in main memory is: 2 n / 16=2 n-4 . Then if each block is also numbered, it actually corresponds to the first n-4 bits in the address. Therefore, the main memory address is divided into two parts: the upper n-4 bits represent the "block address" in the main memory, and the lower 4 bits represent the "intra-block address". The intra-block address is actually the "offset" of the specific storage word in the block. Similarly, the address in the cache can also be divided into two parts. Since the block length in the cache is consistent with the main memory, the lower 4 bits are also the intra-block address; the remaining high bits are the block number of the cache. The number of bits in the cache block number is less than n-4.

[0052] The information in the cache block is a copy of a block in the main memory. Address mapping refers to mapping the main memory address space to the cache address space. Since the cache and main memory blocks are the same length, and the address within the block is just the "offset" of the word in the current block, the address within the block remains unchanged after the mapping conversion. Therefore, it is only necessary to map between the cache block number and the main memory block number. Since there are far fewer cache blocks than main memory blocks, it is impossible for a cache block to always correspond to a unique main memory block. It is necessary to add a mark to each block in the cache to indicate which block in the main memory it is a copy of. The content of this mark should be able to uniquely determine the number of the corresponding main memory block. In addition, in order to indicate whether the information in the cache line is valid, each cache line also needs to have a valid bit. When this bit is 1, it means that the main memory block data of the mapping in the cache is valid; if it is 0, it is invalid.

[0053] Among them, the address mapping methods include direct mapping, fully associative mapping and set associative mapping. The embodiment of the present invention adopts the set associative mapping method. Among them, the idea of ​​set associative mapping is to divide the cache into Q cache groups of equal size, each cache group has multiple cache lines, and each main memory block can be loaded into any line of the corresponding cache group. In other words, the correspondence between the main memory block and the cache group is fixed, while the multiple cache lines in the cache group and the main memory block are not fixed.

[0054] Figure 2 Schematic diagram of the prior art group-associative mapping. Figure 2 As shown, it includes main memory blocks, cache groups and cache blocks. Among them, the main memory blocks are data blocks in the main memory, the cache blocks are data blocks in the cache, each cache group includes multiple cache lines, and each cache line is used to store a tag address, or cache tag, which is used to search for cache data and is the unique identifier of the cache data.

[0055] exist Figure 2 In the embodiment shown, there are 8 main memory blocks, namely a0-a7; there are two cache groups, namely S0 and S1. Each cache group has two cache lines, cache group S0 includes cache lines b0 and b1, and cache group S1 includes cache lines b2 and b3. The number of cache blocks is the same as the number of cache lines, and they correspond one to one. The four cache blocks are c0-c3.

[0056] Among them, main memory blocks a0, a2, a4, and a6 can only be placed in cache group S0, but can be placed in any cache line therein. Main memory blocks a1, a3, a5, and a7 can only be placed in cache group S1, but can be placed in any cache line therein.

[0057] The relationship between the group number of the cache group and the block number of the main memory block is as follows:

[0058] Group number = main memory block number mod group number

[0059] Wherein, mod is a modulo operation, and the number of groups is the total number of cache groups.

[0060] In the prior art, each tag address (Cache Tag) is associated with one data (Cache Data), and the address of the Tag in the Tag SRAM is consistent with the address of the Data in the Data SRAM.

[0061] When a cache access hits, the input tag gets a fixed Set ID through a specific algorithm (for example, a fixed piece of data is intercepted from the tag), and then reads the Tag SRAM according to the Set ID to obtain all tags, and matches the target tag with all tags in the Set. If the same tag exists in the Set, it is considered a match hit, and the physical position of the hit tag in the Set is called the Way ID. Therefore, the index of the tag in the Tag SRAM is {Set ID, Way ID}, and similarly, the index of the data in the Data SRAM is still {Set ID, Way ID}.

[0062] When the cache access misses, the input tag obtains a fixed Set ID through a specific algorithm, and then reads the Tag SRAM according to the SetID to obtain all tags, and matches the target tag with all tags in the Set. All existing tags in the Tag are different from the input tags, and the match is considered a miss. At this time, if there are idle resources in the Set, the allocated Way ID is obtained according to the allocation algorithm; if there are no idle resources in the Set, the replacement Way ID is obtained according to the replacement algorithm based on the state of each tag. Finally, {Set ID, Way ID} simultaneously completes the writing of the input tag and data to the Tag SRAM and Data SRAM.

[0063] Since each cache line can only store one main memory block, when the number of main memory blocks corresponding to the cache group is greater than the number of cache lines in the cache group, it may be insufficient. For example, when it is necessary to frequently access main memory blocks a0, a2, a4, and a6, since cache group S0 can only store the tag addresses of two cache blocks at the same time, repeated misses may occur.

[0064] In the prior art, a common solution to the above problem is to increase the number of cache lines in each cache group. Figure 3As shown, the number of cache lines in the cache group is changed from two to four. In this case, when the main memory blocks a0, a2, a4, and a6 need to be frequently accessed, since the cache group S0 can store the tag addresses of four cache blocks at the same time, repeated misses will not occur.

[0065] However, since the number of cache lines and cache blocks is the same and corresponds one to one, the number of cache blocks is also doubled. Since the bit width of cache blocks is usually large, increasing the number of cache blocks will bring more area and power consumption to the chip. At the same time, since the number of cache lines in each cache group is the same, the number of cache lines in other cache groups will increase. When the usage of cache lines in other cache groups remains unchanged, the utilization rate of cache lines will be only 50%, and the utilization rate of cache blocks will also be 50%.

[0066] Therefore, the present invention provides a cache memory and a corresponding cache processing method thereof, so as to improve the hit rate without increasing the area and power consumption of the cache memory.

[0067] Figure 4 Schematic diagram of a cache memory according to an embodiment of the present invention. Figure 4 As shown, the cache memory Cache of the embodiment of the present invention includes a tag unit 21, a data unit 22, an information unit 23, a matching unit 24, a data allocation and replacement unit 25, and a tag allocation and replacement unit 26.

[0068] The tag unit 21 is used to store multiple cache groups, each cache group includes multiple cache lines, each cache line includes a tag bit and an index bit, the tag bit is used to store a tag address, and the index bit is used to store an index.

[0069] Furthermore, the tag address stored in the tag bit is a Cache Tag, which is used to search for cache data and is a unique identifier of cache data. The Cache Tag is a part of the Cache memory address and is used to associate with the main memory address of a row of data. The Cache Tag usually contains enough information to uniquely identify a data block in the main memory so that the Cache can determine whether a given main memory access already has a corresponding copy in the Cache. Specifically, the specific content of the CacheTag can be configured according to actual conditions, and the embodiment of the present invention does not limit this. For example, the Cache Tag includes the high-order part of the block address and the valid bit (Valid Bit). For the high-order part of the block address: Since the Cache usually uses data blocks as storage units, and these blocks correspond to blocks in the main memory, the Tag usually contains the high-order part of the main memory block address. These high-order addresses are used to uniquely identify a main memory block in the Cache. The valid bit (Valid Bit) is used to indicate whether the cache line contains valid data. During the cache search process, both the valid bit and the Tag will be checked. In some embodiments, the Cache Tag may also include other status bits, such as a Dirty Bit, which is used to indicate whether the data in the Cache line has been modified and these modifications have not yet been written back to the main memory.

[0070] It should be noted that the specific implementation of the Cache Tag may refer to various existing methods, and the embodiment of the present invention does not limit this.

[0071] In some embodiments, the tag unit 21 includes a Tag SRAM (Tag Static Random-Access Memory) and a read-write control logic. The Tag SRAM is used to store the correspondence between the tag bit and the index bit. The read-write control logic is used to read the correspondence between the tag bit and the index bit from the Tag SRAM, or write the correspondence between the tag bit and the index bit into the Tag SRAM, etc.

[0072] The data unit 22 is used to store data, and the identifier of the data is the index. The data stored in the data unit 22 is the data in the main memory, that is, by storing the data frequently used by the processor in the data unit 22 of the cache memory, the processor can directly exchange data with the cache memory without accessing the main memory.

[0073] Furthermore, the data unit 22 includes a Data SRAM (Data Static Random-Access Memory) and a read / write control logic. The Data SRAM is used to store data. The read / write control logic is used to read data from the Data SRAM or write data into the Data SRAM.

[0074] The information unit 23 is used to store the validity status and replacement status of each data and the position of the label address corresponding to the data in the label unit.

[0075] The valid state refers to whether the data is available. If valid, it means the data is available. If invalid, it means the data is unavailable. The replacement state refers to whether the data is replaced.

[0076] The matching unit 24 is used to receive an access request, which includes a target tag address, match the target tag address with an existing tag address in the tag unit, and in response to obtaining a matched existing tag address, determine a target index corresponding to the matched existing tag address and access corresponding data in the data unit according to the target index.

[0077] The data allocation and replacement unit 25 is used to manage the data unit, wherein the management of the data unit allocates idle resources in the data unit, or replaces occupied resources with new data.

[0078] The label allocation and replacement unit 26 is used to manage the label unit, wherein managing the label unit means writing a new label address into the label unit or replacing an existing label address.

[0079] In some embodiments, the matching unit is used to determine a target cache group in the cache group according to the target tag address, obtain an existing tag address stored in the target cache group, and match the existing tag address with the target tag address.

[0080] In some embodiments, the matching unit is used to determine the cache group identifier corresponding to the target tag address through a predetermined algorithm to determine the target cache group.

[0081] In some embodiments, the cache memory further comprises:

[0082] A data allocation and replacement unit, used for managing the data unit;

[0083] The label allocation and replacement unit is used to manage the label unit.

[0084] In some embodiments, in response to not obtaining an existing tag address that matches the target tag address and the target cache group having no free cache lines, the tag allocation and replacement unit obtains the replacement status corresponding to each existing tag address in the target cache group, determines the tag address that needs to be replaced based on the replacement status corresponding to the existing tag address, determines a new tag address, keeps the index unchanged, and replaces the tag address that needs to be replaced with the new tag address; the data allocation and replacement unit replaces the data corresponding to the tag address that needs to be replaced in the data unit with new data.

[0085] In some embodiments, in response to not obtaining an existing tag address that matches the target tag address, the target cache group has free cache lines and the resources of the data unit are not exhausted, the tag allocation and replacement unit determines a new tag address, obtains a new index based on the valid state of the data and a predetermined allocation algorithm, and writes the new tag address and the new index to the free cache line; the data allocation and replacement unit determines new data and writes the new data to the data unit.

[0086] In some embodiments, in response to not obtaining an existing tag address that matches the target tag address, the target cache group having free cache lines and the resources of the data unit being exhausted, the data allocation and replacement unit obtains a replacement status of the data, determines the data that needs to be replaced based on the replacement status of the data and a predetermined replacement algorithm, deletes the data that needs to be replaced in the data unit, determines new data, and writes the new data into the data unit; the tag allocation and replacement unit determines an index that needs to be replaced, a new tag address and a new index, writes the new tag address and the new index into a free cache line, and deletes the cache line corresponding to the index that needs to be replaced in the tag unit.

[0087] The embodiment of the present invention stores multiple cache groups through the tag unit in the cache memory, each cache group includes multiple cache lines, each cache line includes a tag bit and an index bit, the tag bit is used to store the tag address, the index bit is used to store the index, the data unit stores data, the identifier of the data is the index, after receiving an access request, the matching existing tag address is obtained according to the target tag address in the access request, and the corresponding data is accessed in the data unit according to the target index corresponding to the matching existing tag address. Thus, the tag address and the data are respectively associated through the index, and the dynamic mapping between the data and the tag address is realized, the capacity ratio between the data and the tag address can be flexibly adjusted, and the capacity of the tag unit can be increased while keeping the data unit capacity unchanged, so as to improve the hit rate without increasing the area and power consumption of the cache memory.

[0088] Figure 5FIG. 1 is a flow chart of a cache processing method according to an embodiment of the present invention. Figure 5 As shown, the cache processing method of the embodiment of the present invention includes the following steps:

[0089] Step S101: Receive an access request.

[0090] In this embodiment, the cache memory receives the access request sent by the processor. Figure 1 When the processor needs to access data, it sends an access request to the cache memory through the address bus, and the access request includes the target tag address. Specifically, when the processor needs to issue a data access request to a certain address, this address is usually a virtual address, which needs to be converted into a physical address through the translation lookaside buffer (TLB) in the memory management unit (MMU) or the MMU itself. The converted physical address is then used to access the cache. In other words, the target tag address is actually the physical address of the data that the processor needs to access.

[0091] Step S102: Determine the target cache group.

[0092] In this embodiment, the cache memory determines a target cache group in the cache group according to the target tag address.

[0093] Specifically, Figure 6 Schematic diagram of group associative mapping according to an embodiment of the present invention. Figure 6 The data formats of the tag unit and the data unit are shown.

[0094] The tag unit stores a plurality of cache groups, Figure 6 S0 and S1 in.

[0095] Each cache group includes multiple cache lines, where Figure 6 Each cache group in includes four cache lines.

[0096] Each buffer row includes a tag bit and an index bit, wherein the tag bit is used to store a tag address, and the index bit is used to store an index. The data unit is used to store data, and an identifier of the data is the index.

[0097] exist Figure 6 In the example, it is assumed that the cache memory currently stores four data, which are stored in data units, namely D1-D4. Each data has corresponding information stored in the tag unit for easy reading. Each data has corresponding information including a tag address and an index. The tag address is the same as or at least partially the same as the physical address of the data in the main memory. The index is the identifier of the data, that is, the corresponding data is queried in the data unit through the index. Figure 6In the example, the tag addresses and indexes corresponding to data D1-D4 are (tag3, index3), (tag2, index2), (tag1, index1), and (tag4, index4). Among them, (tag1, index1) is stored in cache group S0, and (tag2, index2), (tag3, index3), and (tag4, index4) are stored in cache group S1. Figure 6 As shown, each cache group includes four dotted boxes, each dotted box represents a cache line, each cache line has a tag bit and an index bit, the left side is the tag bit, and the right side is the index bit, the tag bit is used to store the tag address, and the index bit is used to store the index.

[0098] After receiving an access request, the embodiment of the present invention obtains the target tag address and determines the target cache group in the cache group according to the target tag address. The target tag address is the physical address of the data in the main memory. At the same time, in the group associative mapping, the correspondence between the physical address in the main memory and the cache group has been divided in advance, so the cache group identifier corresponding to the target tag address can be determined by a predetermined algorithm to determine the target cache group.

[0099] In an optional implementation, the predetermined algorithm is:

[0100] Cache group ID = main memory block number mod group number

[0101] The main memory block number is obtained from the target tag address, and the group number is the number of cache groups of the cache memory.

[0102] Step S103: Obtain the existing tag address.

[0103] In this embodiment, an existing tag address already stored in the target cache group is obtained.

[0104] by Figure 6 For example, assuming that the target cache group is S0, the existing tag address is tag1; assuming that the target cache group is S1, the existing tag addresses are tag2, tag3 and tag4.

[0105] Step S104: hit or not.

[0106] In this embodiment, the existing label address and the target label address are matched to detect whether there is an existing label address matching the target label address, wherein the existing label address matching the target label address generally means that the two are the same.

[0107] If there is a matching existing label address, it indicates a hit, and the process goes to step S105.

[0108] If there is no matching existing tag address, it means no hit, and the process goes to step S106.

[0109] Step S105: access corresponding data.

[0110] In this embodiment, in response to obtaining a matching existing tag address, a target index corresponding to the matching existing tag address is determined, and corresponding data is accessed in the data unit according to the target index.

[0111] Step S106: Check whether there is any free cache line in the target cache group.

[0112] In this embodiment, in response to not obtaining an existing tag address matching the target tag address, the idle state of the target cache group is determined, that is, whether there is an idle cache line in the target cache group is detected.

[0113] In response to the target cache group having no free cache lines, the process goes to step S107 .

[0114] In response to the target cache group having a free cache line, the process proceeds to step S108 .

[0115] Step S107: Replace the tag address and data.

[0116] In this embodiment, if there is no matching existing tag address, it means a miss, and the corresponding data needs to be put into the cache memory. At this time, if the target cache group has no free cache line, a replacement operation needs to be performed.

[0117] Specifically, the replacement status corresponding to each existing tag address in the target cache group is obtained, and the tag address to be replaced is determined according to the replacement status corresponding to the existing tag address. A new tag address is determined according to the target tag address, the index is kept unchanged, the tag address to be replaced is replaced with the new tag address, and the data corresponding to the tag address to be replaced in the data unit is replaced with the new data.

[0118] It should be noted that the replacement state in the embodiment of the present invention refers to various states used when executing the replacement algorithm, for example, the access frequency and the number of accesses of the data corresponding to each existing tag address.

[0119] Among them, determining the tag address that needs to be replaced can be achieved in various ways, such as a random algorithm, a first in first out algorithm (FIFO), a least recently used algorithm (LRU) or a least frequently used algorithm (LFU). Among them, the random algorithm randomly determines the tag address to be replaced, and the implementation method is relatively simple. The first in first out algorithm selects the earliest called-in tag address for replacement. The least recently used algorithm is based on the principle of locality and selects the cache line that has not been accessed for the longest time as the cache line to be replaced. The least recently used algorithm sets a counter for each cache line to record the usage and selects to eliminate a cache line according to the count value. The least frequently used algorithm swaps out the cache line with the least number of accesses in a period of time.

[0120] The new tag address is identical or at least partially identical to the target tag address.

[0121] That is to say, when a miss occurs, if the target cache group is full, the replacement algorithm is calculated according to the replacement status of each tag address in the target cache group, and the replacement Way ID is obtained, while retaining the original mapping relationship, that is, the index of the data in the data unit still uses the old index, and finally the target tag address overwrites the old existing tag address, and the new data overwrites the old data, keeping the index unchanged.

[0122] by Figure 7 Take this as an example to illustrate. Assuming that the target cache group is S1, as shown in the figure, the target cache group is full. Through calculation, the tag address that needs to be replaced is tag3. The new tag address is tag-new, and the new data is D-new. The tag unit and data unit after replacement are as follows Figure 8 That is, keep the index unchanged and replace the label address and data.

[0123] Step S108: Allocate cache lines.

[0124] In this embodiment, if there is no matching existing tag address, it means a miss, and the corresponding data needs to be placed in the cache memory. At this time, if the target cache group has a free cache line, a cache line needs to be allocated. Among them, allocating a cache line means allocating an idle cache line. The allocation algorithm can be implemented in various ways, such as random allocation or sequential allocation.

[0125] Step S109: Whether the resources of the data unit are exhausted.

[0126] In this embodiment, after the cache line is allocated, it is detected whether the resources of the data unit are exhausted.

[0127] In response to the resource of the data unit being exhausted, the process proceeds to step S110.

[0128] In response to the resource of the data unit not being exhausted, the process proceeds to step S111.

[0129] Step S110: Execute replacement of data units.

[0130] In this embodiment, in response to the exhaustion of resources of the data unit, it is necessary to delete the old data and write new data, that is, to perform replacement of the data unit to replace the tag address and the data.

[0131] Specifically, the replacement status of the data is obtained, the index to be replaced and the data to be replaced are determined according to the replacement status of the data and a predetermined replacement algorithm, the data to be replaced is deleted in the data unit, a new tag address, new data and a new index are determined, the new tag address and the new index are written into an idle cache line, and the new data is written into the data unit.

[0132] Among them, the replacement state of the data can be obtained in the information unit, and the replacement state refers to the various states used when executing the replacement algorithm, such as the access frequency and number of accesses of each data. The index to be replaced and the data to be replaced are determined according to the replacement state of the data and the predetermined replacement algorithm, which can be implemented based on various methods, such as the above-mentioned random algorithm, the first-in-first-out algorithm (Fisrt In First Out, FIFO), the least recently used algorithm (Least Recently Used, LRU) or the least frequently used algorithm (Least Frequently Used, LFU), etc. For determining the new tag address, new data and new index, the new tag address is determined according to the target tag address, and the new data is obtained in the main memory according to the target tag address. The new index can be obtained in various ways, as long as it is different from the stored index. The new tag address and the new index are written into the free cache line, and the new data is written into the data unit.

[0133] Step S111: Execute allocation of data units.

[0134] In this embodiment, in response to the resource of the data unit not being exhausted, the data is written, that is, the data unit is allocated and the tag address and data are written.

[0135] Specifically, a new tag address and new data are determined, a new index is acquired according to the valid state of the data and a predetermined allocation algorithm, the new tag address and the new index are written into an idle cache line, and the new data is written into the data unit.

[0136] The new tag address is determined according to the target tag address, and the new data is obtained in the main memory according to the target tag address.

[0137] For obtaining a new index according to the valid state of the data and a predetermined allocation algorithm, the valid state of the data is stored in the information unit, and the predetermined allocation algorithm refers to a predetermined index allocation algorithm. The predetermined allocation algorithm can be implemented based on various methods, such as random allocation, sequential allocation, etc., as long as the new index obtained is different from the stored index. The new tag address and the new index are written into an idle cache line. The new data is written into the data unit.

[0138] In some embodiments, obtaining a new index can be achieved by presetting an index that is the same as the amount of data that can be stored in the data unit. Assuming that the maximum amount of data that can be stored in the data unit is N, N indexes are set. When a new index needs to be obtained, an unused index among the N indexes is detected and one of them is selected. The selection method can be random selection or sequential selection, that is, the index with the highest sorting among the unused indexes is selected as the new index.

[0139] The embodiment of the present invention sets an index so that the tag address is independent of the data. The identifier of the data is no longer a tag, but a separately stored index, and each index is associated with the tag address. When the input target tag address hits an existing tag address in the cache group, data access is completed according to the index corresponding to the hit existing tag address. When a miss occurs, if the cache group is full, the replacement algorithm is calculated according to the replacement status of each tag address in the cache group, and the replacement Way ID is obtained, while retaining the original mapping relationship, that is, the index of the data still uses the old index, and finally the new tag address covers the old tag address, and the new data covers the old data, keeping the index unchanged. When a miss occurs, if the cache group is not full, the information unit is read to obtain the valid status of each data. If the resources of the data unit are not exhausted, the allocation algorithm is completed to calculate the index according to the valid status in the information unit, and finally the new tag address is written into the tag unit, the index is written into the tag unit, and the data is written into the data unit; if the resources of the data unit are exhausted, the replaced index is calculated according to the replacement information in the information unit according to the replacement algorithm, and the position of the tag address associated with the current data is obtained according to the replaced index. Finally, the new tag address and index are written into the tag unit, the old tag address and index are deleted from the tag unit, and the new data is written into the data unit.

[0140] The embodiment of the present invention stores multiple cache groups through the tag unit in the cache memory, each cache group includes multiple cache lines, each cache line includes a tag bit and an index bit, the tag bit is used to store the tag address, the index bit is used to store the index, the data unit stores data, the identifier of the data is the index, after receiving an access request, the matching existing tag address is obtained according to the target tag address in the access request, and the corresponding data is accessed in the data unit according to the target index corresponding to the matching existing tag address. Thus, the tag address and the data are respectively associated through the index, and the dynamic mapping between the data and the tag address is realized, the capacity ratio between the data and the tag address can be flexibly adjusted, and the capacity of the tag unit can be increased while keeping the data unit capacity unchanged, so as to improve the hit rate without increasing the area and power consumption of the cache memory.

[0141] Fig. 9 : is a flow chart of a cache processing method according to another embodiment of the present invention. The cache processing method according to the embodiment of the present invention is applied to a cache memory, the cache memory includes a tag unit and a data unit, the tag unit stores multiple cache groups, each cache group includes multiple cache lines, each cache line includes a tag bit and an index bit, the tag bit is used to store a tag address, the index bit is used to store an index, the data unit is used to store data, the identifier of the data is the index, and the method includes the following steps:

[0142] Step S210: receiving an access request, wherein the access request includes a target tag address.

[0143] Step S220: Match the target label address with the existing label address in the label unit.

[0144] Step S230: In response to obtaining the matching existing label address, determine the target index corresponding to the matching existing label address.

[0145] Step S240: Access corresponding data in the data unit according to the target index.

[0146] In some embodiments, matching the target tag address with an existing tag address in the tag unit includes:

[0147] Determining a target cache group in the cache group according to the target tag address;

[0148] Obtaining an existing tag address stored in the target cache group;

[0149] The existing label address and the target label address are matched.

[0150] In some embodiments, determining the target cache group in the cache group according to the target tag address includes:

[0151] The cache group identifier corresponding to the target tag address is determined by a predetermined algorithm to determine the target cache group.

[0152] In some embodiments, the method further comprises:

[0153] In response to not acquiring an existing tag address matching the target tag address, determining an idle state of the target cache group;

[0154] In response to the target cache group having a free cache line, writing or replacing a tag address and data according to resource usage of the data unit;

[0155] In response to the target cache group having no free cache line, the tag address and the data are replaced.

[0156] In some embodiments, in response to the target cache group having a free cache line, writing or replacing the tag address and data according to the resource usage of the data unit includes:

[0157] Get the valid status of each data;

[0158] Determining resource usage of the data unit according to the validity status of the data;

[0159] In response to the resource of the data unit not being exhausted, writing the tag address and the data;

[0160] In response to exhaustion of resources of the data unit, the tag address and the data are replaced.

[0161] In some embodiments, in response to the target cache group having no free cache line, replacing the tag address and data comprises:

[0162] Obtaining a replacement status corresponding to each existing tag address in the target cache group; and

[0163] Determining a label address that needs to be replaced according to a replacement state corresponding to the existing label address;

[0164] Determine the new label address;

[0165] The index is kept unchanged, the label address to be replaced is replaced with the new label address, and the data in the data unit corresponding to the label address to be replaced is replaced with the new data.

[0166] In some embodiments, in response to the resource of the data unit not being exhausted, writing the tag address and the data comprises:

[0167] Determine the new tag address and new data;

[0168] Acquire a new index according to the valid state of the data and a predetermined allocation algorithm;

[0169] Writing the new tag address and the new index into an idle cache line;

[0170] The new data is written into the data unit.

[0171] In some embodiments, in response to exhaustion of resources of the data unit, replacing the tag address and data comprises:

[0172] Get the replacement status of data;

[0173] Determining the index to be replaced and the data to be replaced according to the replacement state of the data and a predetermined replacement algorithm;

[0174] Deleting data to be replaced in the data unit;

[0175] Determine the new tag address, new data, and new index;

[0176] The new tag address and the new index are written into the free cache line, and the new data are written into the data unit.

[0177] In some embodiments, in response to exhaustion of resources of the data unit, replacing the tag address and data further comprises:

[0178] The cache line corresponding to the index that needs to be replaced is deleted in the tag unit.

[0179] The embodiment of the present invention stores multiple cache groups through the tag unit in the cache memory, each cache group includes multiple cache lines, each cache line includes a tag bit and an index bit, the tag bit is used to store the tag address, the index bit is used to store the index, the data unit stores data, the identifier of the data is the index, after receiving an access request, the matching existing tag address is obtained according to the target tag address in the access request, and the corresponding data is accessed in the data unit according to the target index corresponding to the matching existing tag address. Thus, the tag address and the data are respectively associated through the index, and the dynamic mapping between the data and the tag address is realized, the capacity ratio between the data and the tag address can be flexibly adjusted, and the capacity of the tag unit can be increased while keeping the data unit capacity unchanged, so as to improve the hit rate without increasing the area and power consumption of the cache memory.

[0180] Fig.10 Schematic diagram of a cache processing device according to an embodiment of the present invention. Fig.10As shown, the cache processing device of the embodiment of the present invention includes a request receiving unit 101, a tag address matching unit 102, a target index determining unit 203 and a data access unit 104. Among them, the request receiving unit 101 is used to receive an access request, and the access request includes a target tag address. The tag address matching unit 102 is used to match the target tag address with an existing tag address in the tag unit. The target index determining unit 103 is used to determine the target index corresponding to the matching existing tag address in response to obtaining a matching existing tag address. The data access unit 104 is used to access the corresponding data in the data unit according to the target index.

[0181] In some embodiments, the tag address matching unit includes:

[0182] a cache group determination subunit, configured to determine a target cache group in the cache group according to the target tag address;

[0183] An existing tag address acquisition subunit, used to acquire an existing tag address stored in the target cache group;

[0184] The address matching subunit is used to match the existing label address with the target label address.

[0185] In some embodiments, the cache group determination subunit is used to:

[0186] The cache group identifier corresponding to the target tag address is determined by a predetermined algorithm to determine the target cache group.

[0187] In some embodiments, the apparatus further comprises:

[0188] a state determination unit, configured to determine an idle state of the target cache group in response to failure to obtain an existing tag address matching the target tag address;

[0189] a first processing unit, configured to write or replace a tag address and data according to resource usage of the data unit in response to the target cache group having a free cache line;

[0190] The second processing unit is configured to replace the tag address and the data in response to the target cache group having no free cache lines.

[0191] In some embodiments, the first processing unit includes:

[0192] A valid status acquisition subunit is used to acquire the valid status of each data;

[0193] A resource usage determination subunit, configured to determine resource usage of a data unit according to a valid state of the data;

[0194] a writing subunit, for writing a tag address and data in response to the resource of the data unit not being exhausted;

[0195] The replacement subunit is used to replace the tag address and the data in response to exhaustion of resources of the data unit.

[0196] In some embodiments, the second processing unit includes:

[0197] a replacement status acquisition subunit, configured to acquire a replacement status corresponding to each existing tag address in the target cache group; and

[0198] A first determining subunit, configured to determine a label address to be replaced according to a replacement state corresponding to the existing label address;

[0199] A second determining subunit, used to determine a new label address;

[0200] The updating subunit is used to keep the index unchanged, replace the label address that needs to be replaced with the new label address, and replace the data corresponding to the label address that needs to be replaced in the data unit with the new data.

[0201] In some embodiments, the writing subunit is used to:

[0202] Determine the new tag address and new data;

[0203] Acquire a new index according to the valid state of the data and a predetermined allocation algorithm;

[0204] Writing the new tag address and the new index into an idle cache line;

[0205] The new data is written into the data unit.

[0206] In some embodiments, the replacement subunit is used to:

[0207] Get the replacement status of data;

[0208] Determining the index to be replaced and the data to be replaced according to the replacement state of the data and a predetermined replacement algorithm;

[0209] Deleting data to be replaced in the data unit;

[0210] Determine the new tag address, new data, and new index;

[0211] The new tag address and the new index are written into the free cache line, and the new data are written into the data unit.

[0212] In some embodiments, the replacement subunit is further configured to:

[0213] The cache line corresponding to the index that needs to be replaced is deleted in the tag unit.

[0214] The embodiment of the present invention stores multiple cache groups through the tag unit in the cache memory, each cache group includes multiple cache lines, each cache line includes a tag bit and an index bit, the tag bit is used to store the tag address, the index bit is used to store the index, the data unit stores data, the identifier of the data is the index, after receiving an access request, the matching existing tag address is obtained according to the target tag address in the access request, and the corresponding data is accessed in the data unit according to the target index corresponding to the matching existing tag address. Thus, the tag address and the data are respectively associated through the index, and the dynamic mapping between the data and the tag address is realized, the capacity ratio between the data and the tag address can be flexibly adjusted, and the capacity of the tag unit can be increased while keeping the data unit capacity unchanged, so as to improve the hit rate without increasing the area and power consumption of the cache memory.

[0215] It should be understood by those skilled in the art that the embodiments of the present invention may be provided as methods, devices (equipment) or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0216] The present invention is described with reference to flowcharts of methods, apparatuses (devices) and computer program products according to embodiments of the present application. It should be understood that each process in the flowchart can be implemented by computer program instructions.

[0217] These computer program instructions may be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction device that implements the process Figure 1 A function specified in a process or multiple processes.

[0218] These computer program instructions may also be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce instructions for implementing the process Figure 1 A device that specifies functions in a process or multiple processes.

[0219] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A cache processing method, applied to a cache memory, characterized in that: The cache memory comprises a tag unit and a data unit, the tag unit stores a plurality of cache groups, each cache group comprises a plurality of cache lines, each cache line comprises a tag bit and an index bit, the tag bit is used to store a tag address, the index bit is used to store an index, the data unit is used to store data, an identifier of the data is the index, and the method comprises: receiving an access request, wherein the access request includes a target tag address; Matching the target label address with an existing label address in the label unit; In response to obtaining a matching existing label address, determining a target index corresponding to the matching existing label address; and The corresponding data is accessed in the data unit according to the target index.

2. The method according to claim 1, characterized in that The matching of the target label address with the existing label address in the label unit includes: Determining a target cache group in the cache group according to the target tag address; Obtaining an existing tag address stored in the target cache group; The existing label address and the target label address are matched.

3. The method according to claim 2, characterized in that Determining a target cache group in the cache group according to the target tag address includes: The cache group identifier corresponding to the target tag address is determined by a predetermined algorithm to determine the target cache group.

4. The method according to claim 2, characterized in that: The method further comprises: In response to not acquiring an existing tag address matching the target tag address, determining an idle state of the target cache group; In response to the target cache group having a free cache line, writing or replacing a tag address and data according to resource usage of the data unit; In response to the target cache group having no free cache line, the tag address and the data are replaced.

5. The method according to claim 4, characterized in that In response to the target cache group having a free cache line, writing or replacing the tag address and data according to the resource usage of the data unit includes: Get the valid status of each data; Determining resource usage of the data unit according to the validity status of the data; In response to the resource of the data unit not being exhausted, writing the tag address and the data; In response to exhaustion of resources of the data unit, the tag address and the data are replaced.

6. The method according to claim 4, characterized in that In response to the target cache group having no free cache line, replacing the tag address and data comprises: Obtaining a replacement status corresponding to each existing tag address in the target cache group; and Determining a label address that needs to be replaced according to a replacement state corresponding to the existing label address; Determine the new label address; The index is kept unchanged, the label address to be replaced is replaced with the new label address, and the data in the data unit corresponding to the label address to be replaced is replaced with the new data.

7. The method according to claim 5, characterized in that In response to the resource of the data unit not being exhausted, writing the tag address and data comprises: Determine the new tag address and new data; Acquire a new index according to the valid state of the data and a predetermined allocation algorithm; Writing the new tag address and the new index into an idle cache line; The new data is written into the data unit.

8. The method according to claim 5, characterized in that In response to exhaustion of resources of the data unit, replacing the tag address and data comprises: Get the replacement status of data; Determining the index to be replaced and the data to be replaced according to the replacement state of the data and a predetermined replacement algorithm; Deleting data to be replaced in the data unit; Determine the new tag address, new data, and new index; The new tag address and the new index are written into the free cache line, and the new data are written into the data unit.

9. The method according to claim 8, characterized in that In response to exhaustion of resources of the data unit, replacing the tag address and data further comprises: The cache line corresponding to the index that needs to be replaced is deleted in the tag unit.

10. A cache memory, characterized in that: The cache memory comprises: A tag unit, used to store a plurality of cache groups, each cache group includes a plurality of cache lines, each cache line includes a tag bit and an index bit, the tag bit is used to store a tag address, and the index bit is used to store an index; A data unit, used for storing data, wherein an identifier of the data is the index; An information unit, used to store the valid state and replacement state of each data and the position of the label address corresponding to the data in the label unit; A matching unit is used to receive an access request, wherein the access request includes a target tag address, match the target tag address with an existing tag address in the tag unit, and in response to obtaining a matched existing tag address, determine a target index corresponding to the matched existing tag address and access corresponding data in the data unit according to the target index.

11. The cache memory according to claim 10, wherein: The cache memory also includes: A data allocation and replacement unit, used for managing the data unit; The label allocation and replacement unit is used to manage the label unit.

12. A cache processing device, applied to a cache memory, characterized in that: The cache memory comprises a tag unit and a data unit, the tag unit stores a plurality of cache groups, each cache group comprises a plurality of cache lines, each cache line comprises a tag bit and an index bit, the tag bit is used to store a tag address, the index bit is used to store an index, the data unit is used to store data, an identifier of the data is the index, and the device comprises: A request receiving unit, configured to receive an access request, wherein the access request includes a target tag address; A label address matching unit, used to match the target label address with an existing label address in the label unit; a target index determining unit, configured to determine a target index corresponding to the matched existing label address in response to obtaining the matched existing label address; and A data access unit is used to access corresponding data in the data unit according to the target index.

13. An electronic device, characterized in that: The electronic device comprises: processor; Address bus; Data bus; Main memory; A cache memory as claimed in any one of claims 10 to 11.

Images