Display substrate and display device

Abstract

The invention provides a display substrate and a display device, relates to the technical field of display, and is used for improving the touch uniformity of a product. The display substrate comprises a substrate body, a plurality of touch electrode blocks, virtual sub-pixels and a common signal bus, wherein the touch electrode blocks, the virtual sub-pixels and the common signal bus are all arranged on the substrate body. The orthographic projection of the virtual sub-pixel on the substrate is located between the orthographic projection of the common signal bus on the substrate and the orthographic projection of the touch electrode block on the substrate; the virtual sub-pixel comprises a virtual common electrode pattern, and the virtual common electrode pattern is coupled with the common signal bus.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] In recent years, In-Cell Touch products have attracted widespread attention for their thinness, lightness and high definition. However, for large-sized In-Cell Touch products, the touch performance is greatly affected due to the large difference in the load of each touch electrode block. Therefore, how to improve the touch uniformity has become an urgent problem to be solved. Summary of the invention

[0003] An object of the present invention is to provide a display substrate and a display device for improving the touch uniformity of a product.

[0004] In order to achieve the above object, the present invention provides the following technical solutions:

[0005] A first aspect of the present invention provides a display substrate, comprising: a base substrate and a plurality of touch electrode blocks, virtual sub-pixels and a common signal bus, all of which are arranged on the base substrate;

[0006] The orthographic projection of the virtual sub-pixel on the base substrate is located between the orthographic projection of the common signal bus on the base substrate and the orthographic projection of the touch electrode block on the base substrate; the virtual sub-pixel includes a virtual common electrode pattern, and the virtual common electrode pattern is coupled to the common signal bus.

[0007] Optionally, the common signal bus includes a bus main body and a plurality of bus extension parts respectively coupled to the bus main body, and the bus extension parts are coupled to the virtual common electrode patterns in the corresponding virtual sub-pixels.

[0008] Optionally, the bus main body and the bus extension portion form an integrated structure, and the bus extension portion is directly overlapped with the virtual common electrode pattern in the corresponding virtual sub-pixel.

[0009] Optionally, the virtual sub-pixel further includes a virtual common electrode line, and the virtual common electrode line is coupled to an end of the virtual common electrode pattern;

[0010] The virtual common electrode pattern extends along a first direction; the first end of the virtual common electrode line and the first end of the bus extension portion are arranged along the first direction, the first end of the virtual common electrode line is an end of the virtual common electrode line close to the bus main body, and the first end of the bus extension portion is an end of the bus extension portion away from the bus main body.

[0011] Optionally, a distance between a first end of the virtual common electrode line and a first end of the bus extension portion is greater than or equal to one third of a length of the virtual common electrode pattern along the first direction.

[0012] Optionally, the bus main body portion and the bus extension portion are coupled via a first conductive connection portion;

[0013] The virtual sub-pixel further includes a virtual common electrode line, and the virtual common electrode line is coupled to an end of the virtual common electrode pattern; the bus extension portion is coupled to the virtual common electrode line in the corresponding virtual sub-pixel.

[0014] Optionally, the bus extension portion includes a first extension portion and a second extension portion coupled to each other; the first extension portion has the same extension direction as the adjacent bus main portion, and the orthographic projection of the first extension portion on the substrate substrate and the orthographic projection of the bus main portion on the substrate substrate are arranged along a direction intersecting the extension direction of the adjacent bus main portion; the second extension portion is coupled to the virtual common electrode line in the corresponding virtual sub-pixel; and the first conductive connection portion is coupled to the bus main portion and the first extension portion, respectively.

[0015] Optionally, the width of the first extending portion in a direction perpendicular to its own extending direction is greater than the width of the second extending portion in a direction perpendicular to its own extending direction.

[0016] Optionally, the extending direction of the second extending portion is the same as the extending direction of the virtual common electrode line; or,

[0017] The extending direction of the second extending portion is the same as the extending direction of the virtual common electrode pattern; or,

[0018] The second extending portion includes at least two sub-portions coupled in sequence, and the extending directions of two adjacent sub-portions are different.

[0019] Optionally, the display substrate further includes a gate metal layer and a source-drain metal layer, the bus main body is provided in the same layer and material as the source-drain metal layer, and the bus extension is provided in the same layer and material as the gate metal layer.

[0020] Optionally, the display substrate further includes a gate metal layer, and the bus main body portion and the bus extension portion are both provided in the same layer and with the same material as the gate metal layer.

[0021] Optionally, in the case where the bus extension portion includes a first extension portion and a second extension portion coupled to each other, the bus main body portion includes a first bus portion and a second bus portion alternately arranged, a width of the first bus portion along an extension direction perpendicular to the bus main body portion is smaller than a width of the second bus portion, and the first bus portion and the first extension portion are arranged along an extension direction perpendicular to the bus main body portion.

[0022] Optionally, the display substrate further comprises: a gate driving circuit and a plurality of scanning lines; at least a portion of the orthographic projection of the bus body portion on the base substrate is located between the orthographic projection of the gate driving circuit on the base substrate and the orthographic projection of the plurality of scanning lines on the base substrate;

[0023] A plurality of second conductive connection parts, wherein the orthographic projection of the second conductive connection part on the base substrate overlaps with the orthographic projection of the bus body part on the base substrate, and the plurality of second conductive connection parts are respectively coupled to the gate driving circuit;

[0024] A plurality of third conductive connection parts and a plurality of fourth conductive connection parts, wherein the third conductive connection parts are respectively coupled with the corresponding second conductive connection parts and fourth conductive connection parts, and the fourth conductive connection parts and the corresponding scanning lines form an integrated structure.

[0025] Optionally, the fourth conductive connection portion includes a first conductive portion and a second conductive portion coupled to each other, the first conductive portion and the adjacent bus main portion extending in the same direction, the orthographic projection of the first conductive portion on the substrate and the orthographic projection of the second conductive connection portion on the substrate are arranged along a direction intersecting the extending direction of the adjacent bus main portion, and the second conductive portion and the scanning line extending in the same direction;

[0026] The third conductive connection portion is respectively coupled to the corresponding second conductive connection portion and the first conductive portion, and the second conductive portion and the corresponding scan line form an integrated structure.

[0027] Optionally, at least a portion of the orthographic projection of the first conductive portion on the base substrate is located between the orthographic projection of the first extending portion on the base substrate and the orthographic projection of the virtual common electrode pattern on the base substrate;

[0028] The orthographic projection of the first conductive portion on the base substrate and at least a portion of the orthographic projection of the second extending portion on the base substrate are arranged along an extending direction of the bus body portion adjacent thereto;

[0029] At least a portion of an orthographic projection of the first conductive portion on the base substrate and at least a portion of an orthographic projection of the second extending portion on the base substrate are arranged along a direction intersecting an extending direction of the adjacent bus body portion.

[0030] Optionally, the display substrate further comprises: a gate driving circuit and a plurality of scanning lines; at least a portion of the orthographic projection of the bus body portion on the base substrate is located between the orthographic projection of the gate driving circuit on the base substrate and the orthographic projection of the plurality of scanning lines on the base substrate;

[0031] A plurality of second conductive connection parts, the orthographic projections of the second conductive connection parts on the base substrate overlap with the orthographic projections of the bus main body on the base substrate, the plurality of second conductive connection parts are respectively coupled to the gate drive circuit, and the second conductive connection parts and the corresponding scan lines form an integrated structure.

[0032] Optionally, the display substrate further includes a plurality of normal sub-pixels, and the normal sub-pixels include normal common electrode patterns;

[0033] The plurality of normal common electrode patterns included in the plurality of normal sub-pixels are divided into a plurality of touch electrode blocks, the touch electrode block includes at least two normal common electrode patterns, and in the same touch electrode block, the normal common electrode patterns arranged along the second direction are coupled through normal common electrode lines;

[0034] The virtual sub-pixel further includes a virtual common electrode line, and a gap exists between the virtual common electrode line and a normal common electrode line adjacent to the virtual common electrode line along the second direction.

[0035] Optionally, the display substrate further includes a plurality of data lines, and the orthographic projections of the data lines on the base substrate partially overlap with the orthographic projections of the normal common electrode lines on the base substrate.

[0036] Optionally, the virtual sub-pixel further includes a virtual common electrode line, and an end portion of the virtual common electrode pattern coupled to the virtual common electrode line includes a first notch, and the first notch is close to the normal common electrode line.

[0037] Optionally, the end portion of the virtual common electrode pattern coupled to the virtual common electrode line further includes a second notch, and the second notch is arranged opposite to the first notch along the second direction.

[0038] Based on the technical solution of the above-mentioned display substrate, a second aspect of the present invention provides a display device, comprising the above-mentioned display substrate.

[0039] In the technical solution provided by the present invention, the virtual sub-pixel includes a virtual common electrode pattern, and the virtual common electrode pattern is coupled to the common signal bus, so that the virtual common electrode pattern has the same potential as the common signal transmitted by the common signal bus. When the display substrate is in the touch period, each touch electrode block in the display substrate receives the common signal through the corresponding touch signal line, so that no matter the touch electrode block located in the center of the display substrate or the electrode block close to the edge of the display substrate, the structure around each touch electrode block has the same potential as the common signal, so that each touch electrode block in the display substrate can be in the same electrical environment, thereby effectively improving the touch uniformity of the display substrate and improving the display quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0041] Figure 1 A first schematic layout diagram of a display substrate provided by an embodiment of the present invention;

[0042] Figure 2 for Figure 1 A schematic diagram of the layout of the middle gate metal layer and the first conductive layer;

[0043] Figure 3 For Figure 2 A schematic diagram of the layout of the source and drain metal layers is added on the basis of FIG.

[0044] Figure 4 A second schematic layout diagram of a display substrate provided by an embodiment of the present invention;

[0045] Figure 5 for Figure 4 A schematic diagram of the layout of the middle gate metal layer and the first conductive layer;

[0046] Figure 6 For Figure 5 A schematic diagram of the layout of the source and drain metal layers is added on the basis of FIG.

[0047] Figure 7 A third schematic layout diagram of a display substrate provided by an embodiment of the present invention;

[0048] Figure 8 for Figure 7 A schematic diagram of the layout of the middle gate metal layer and the first conductive layer;

[0049] Fig. 9 For Figure 8 A schematic diagram of the layout of the source and drain metal layers is added on the basis of FIG.

[0050] Fig.10 A fourth schematic layout diagram of a display substrate provided by an embodiment of the present invention;

[0051] Fig.11 for Fig.10 Schematic diagram of the cross section along the A1A2 direction;

[0052] Fig.12 for Fig.10 A schematic diagram of the layout of the middle gate metal layer and the first conductive layer;

[0053] Fig.13 For Fig.12 A schematic diagram of the layout of the source and drain metal layers is added on the basis of FIG.

[0054] Fig.14 A schematic structural diagram of a display substrate provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0055] In order to further illustrate the display substrate and the display device provided by the embodiments of the present invention, a detailed description is given below in conjunction with the accompanying drawings.

[0056] See also Figure 1 , Figure 4 , Figure 7 , Fig.10 and Fig.14 , an embodiment of the present invention provides a display substrate, comprising: a base substrate 10 and a plurality of touch electrode blocks 110 all arranged on the base substrate 10, a virtual sub-pixel Dum and a common signal bus Bus-L;

[0057] The orthographic projection of the virtual sub-pixel Dum on the base substrate 10 is located between the orthographic projection of the common signal bus Bus-L on the base substrate 10 and the orthographic projection of the touch electrode block 110 on the base substrate 10; the virtual sub-pixel Dum includes a virtual common electrode pattern Dum1, and the virtual common electrode pattern Dum1 is coupled to the common signal bus Bus-L (including the bus main body Bus-L1 and the bus extension part Bus-L2).

[0058] Exemplarily, the display substrate includes a touch area 11 and a peripheral area 12 located around the touch area 11 , and the peripheral area 12 surrounds the touch area 11 .

[0059] Exemplarily, the touch electrode block 110 is located in the touch area 11, and the virtual sub-pixel Dum and the common signal bus Bus-L are located in the peripheral area 12. The common signal bus Bus-L is used to transmit common signals.

[0060] Exemplarily, the multiple touch electrode blocks 110 are distributed in an array, and the common signal bus Bus-L at least partially surrounds the multiple touch electrode blocks 110. Optionally, the common signal bus Bus-L completely surrounds the touch electrode block 110. Taking a rectangular display substrate as an example, the peripheral area 12 includes an upper frame area, a lower frame area, a left frame area and a right frame area. In at least one of the upper frame area, the lower frame area, the left frame area and the right frame area, the orthographic projection of the virtual sub-pixel Dum on the substrate substrate is located between the orthographic projection of the common signal bus Bus-L on the substrate substrate and the orthographic projection of the touch electrode block 110 on the substrate substrate. It should be noted that the technical solution provided in the embodiment of the present invention can be applied to at least one of the upper frame area, the lower frame area, the left frame area and the right frame area. Further, the technical solution provided in the embodiment of the present invention can be applied to the left frame area and the right frame area.

[0061] Exemplarily, the display substrate further includes a plurality of touch signal lines TX, and the touch signal lines TX are coupled to the corresponding touch electrode blocks 110 to provide common signals to the touch electrode blocks 110 during a touch period.

[0062] Exemplarily, the virtual sub-pixel Dum includes a virtual common electrode pattern Dum1 , and the virtual common electrode pattern Dum1 is coupled to the common signal bus Bus-L and can receive a common signal transmitted by the common signal bus Bus-L.

[0063] According to the specific structure of the display substrate described above, in the display substrate provided by the embodiment of the present invention, the virtual sub-pixel Dum includes a virtual common electrode pattern Dum1, and the virtual common electrode pattern Dum1 is coupled to the common signal bus Bus-L, so that the virtual common electrode pattern Dum1 has the same potential as the common signal transmitted by the common signal bus Bus-L. When the display substrate is in the touch period, each touch electrode block 110 in the display substrate receives the common signal through the corresponding touch signal line, so that no matter the touch electrode block 110 located in the center of the display substrate or the electrode block close to the edge of the display substrate, the structure around each touch electrode block 110 has the same potential as the common signal, so that each touch electrode block 110 in the display substrate can be in the same electrical environment, that is, the peripheral load of each touch electrode block 110 in the display substrate is consistent, thereby effectively improving the touch uniformity of the display substrate and improving the display quality.

[0064] like Figures 1 to 14As shown, in some embodiments, the common signal bus Bus-L includes a bus main portion Bus-L1 and a plurality of bus extension portions Bus-L2 respectively coupled to the bus main portion Bus-L1, and the bus extension portion Bus-L2 is coupled to the virtual common electrode pattern Dum1 in the corresponding virtual sub-pixel Dum.

[0065] It should be noted that the black dots in the drawings represent the locations of the via holes. VGL in the drawings represents the first level signal line.

[0066] Exemplarily, the bus main body Bus-L1 at least partially surrounds the touch area 11. For example, the bus main body Bus-L1 completely surrounds the touch area 11.

[0067] Exemplarily, the bus main body Bus-L1 and the bus extension part Bus-L2 are arranged at the same layer, or the bus main body Bus-L1 and the bus extension part Bus-L2 are arranged at different layers.

[0068] Exemplarily, the bus main body portion Bus-L1 and the bus extension portion Bus-L2 form an integrated structure.

[0069] Exemplarily, the bus main portion Bus-L1 is directly coupled to the bus extension portion Bus-L2, or the bus main portion Bus-L1 is indirectly coupled to the bus extension portion Bus-L2.

[0070] The above-mentioned setting of the bus extension portion Bus-L2 is respectively coupled with the bus main portion Bus-L1 and the virtual common electrode pattern Dum1 in the corresponding virtual sub-pixel Dum. By changing the shape of the bus extension portion Bus-L2, it is easier to achieve electrical connection between the bus main portion Bus-L1 and the virtual common electrode pattern Dum1, which effectively reduces the layout difficulty of the common signal bus.

[0071] like Figures 1 to 3 In some embodiments, the bus main body Bus-L1 and the bus extension portion Bus-L2 form an integrated structure, and the bus extension portion Bus-L2 is directly overlapped with the virtual common electrode pattern Dum1 in the corresponding virtual sub-pixel Dum.

[0072] like Fig.11 As shown, exemplarily, the display substrate includes a first conductive layer, a gate metal layer, a gate insulating layer GI, an active layer ACT, a source-drain metal layer, a passivation layer PVX and a second conductive layer formed in sequence in a direction away from the base substrate 10. The gate insulating layer does not require a mask and is designed to be tiled on the entire surface. Fig.11401 in the figure represents a first electrode of the transistor, and 402 represents a second electrode of the transistor.

[0073] Exemplarily, the bus main portion Bus-L1 and the bus extension portion Bus-L2 are both provided in the same layer and with the same material as the gate metal layer.

[0074] Exemplarily, both the first conductive layer and the second conductive layer are made of indium tin oxide material, but not limited thereto.

[0075] Exemplarily, the first conductive layer includes the virtual common electrode pattern Dum1 and the normal common electrode pattern Nor1. The second conductive layer includes the virtual pixel electrode pattern Dum3 in the virtual sub-pixel Dum and the normal pixel electrode pattern Nor3 in the normal sub-pixel Nor. The second conductive layer may further include a conductive connection portion.

[0076] The above-mentioned setting forms the bus main body Bus-L1 and the bus extension part Bus-L2 as an integrated structure, so that the bus main body Bus-L1 and the bus extension part Bus-L2 can be formed simultaneously in the same composition process, which effectively simplifies the manufacturing process flow of the display substrate and reduces the manufacturing cost of the display substrate.

[0077] The above-mentioned setting of directly overlapping the bus extension portion Bus-L2 with the corresponding virtual common electrode pattern Dum1 in the virtual sub-pixel Dum not only ensures the connection performance between the bus extension portion Bus-L2 and the virtual common electrode pattern Dum1 in the virtual sub-pixel Dum, but also further simplifies the manufacturing process of the display substrate and reduces the manufacturing cost of the display substrate.

[0078] like Figures 1 to 3 In some embodiments, the virtual sub-pixel Dum further includes a virtual common electrode line Dum2, and the virtual common electrode line Dum2 is coupled to an end of the virtual common electrode pattern Dum1;

[0079] The virtual common electrode pattern Dum1 extends along a first direction; the first end of the virtual common electrode line Dum2 and the first end of the bus extension portion Bus-L2 are arranged along the first direction, the first end of the virtual common electrode line Dum2 is an end of the virtual common electrode line Dum2 close to the bus main portion Bus-L1, and the first end of the bus extension portion Bus-L2 is an end of the bus extension portion Bus-L2 away from the bus main portion Bus-L1.

[0080] Exemplarily, the virtual common electrode line Dum2 is provided in the same layer and material as the gate metal layer, and the virtual common electrode line Dum2 is directly overlapped with the end of the virtual common electrode pattern Dum1.

[0081] Exemplarily, the distance between the first end of the virtual common electrode line Dum2 and the first end of the bus extension portion Bus-L2 is greater than or equal to one third of the length of the virtual common electrode pattern Dum1 along the first direction. For example: the distance between the first end of the virtual common electrode line Dum2 and the first end of the bus extension portion Bus-L2 is equal to one half of the length of the virtual common electrode pattern Dum1 along the first direction.

[0082] The above-mentioned setting arranges the first end of the virtual common electrode line Dum2 and the first end of the bus extension portion Bus-L2 along the first direction, so that the first end of the virtual common electrode line Dum2 and the first end of the bus extension portion Bus-L2 are staggered, avoiding tip discharge between the first end of the virtual common electrode line Dum2 and the first end of the bus extension portion Bus-L2, thereby ensuring the working stability of the display substrate.

[0083] like Figures 4 to 13 As shown, in some embodiments, the bus main body portion Bus-L1 and the bus extension portion Bus-L2 are coupled via a first conductive connection portion 21;

[0084] The virtual sub-pixel Dum further includes a virtual common electrode line Dum2, and the virtual common electrode line Dum2 is coupled to the end of the virtual common electrode pattern Dum1; the bus extension portion Bus-L2 is coupled to the virtual common electrode line Dum2 in the corresponding virtual sub-pixel Dum.

[0085] Exemplarily, the bus main body Bus-L1 and the bus extension Bus-L2 are arranged in the same layer or in different layers, and the first conductive connection part 21 is arranged in different layers from the bus main body Bus-L1 and the bus extension Bus-L2. For example: the bus main body Bus-L1 and the bus extension Bus-L2 are arranged in the same layer and the same material as the gate metal layer, and the first conductive connection part 21 is arranged in the same layer and the same material as the first conductive layer. For example: the bus main body Bus-L1 is arranged in the same layer and the same material as the source and drain metal layer, the bus extension Bus-L2 is arranged in the same layer and the same material as the gate metal layer, and the first conductive connection part 21 is arranged in the same layer and the same material as the first conductive layer.

[0086] Exemplarily, the orthographic projection of the first conductive connection portion 21 on the substrate has an overlapping area with the orthographic projection of the bus main portion Bus-L1 on the substrate, and in the overlapping area, the first conductive connection portion 21 is coupled to the bus main portion Bus-L1 through a via. The orthographic projection of the first conductive connection portion 21 on the substrate has an overlapping area with the orthographic projection of the bus extension portion Bus-L2 on the substrate, and in the overlapping area, the first conductive connection portion 21 is coupled to the bus extension portion Bus-L2 through a via.

[0087] Exemplarily, the bus extension portion Bus-L2 is coupled to the virtual common electrode line Dum2 in the corresponding virtual sub-pixel Dum, and the electrical connection between the bus extension portion Bus-L2 and the corresponding virtual common electrode pattern Dum1 is achieved through the virtual common electrode line Dum2.

[0088] The above arrangement couples the bus main body Bus-L1 and the bus extension Bus-L2 via the first conductive connection portion 21, thereby avoiding the risk of tip discharge caused by direct tip connection between the bus main body Bus-L1 and the thinner bus extension Bus-L2.

[0089] like Figures 4 to 13 As shown, in some embodiments, the bus extension portion Bus-L2 includes a first extension portion Bus-L21 and a second extension portion Bus-L22 coupled to each other; the first extension portion Bus-L21 has the same extension direction as its adjacent bus main portion Bus-L1, and the orthographic projection of the first extension portion Bus-L21 on the substrate substrate and the orthographic projection of the bus main portion Bus-L1 on the substrate substrate are arranged along a direction intersecting with the extension direction of the adjacent bus main portion Bus-L1; the second extension portion Bus-L22 is coupled to the virtual common electrode line Dum2 in the corresponding virtual sub-pixel Dum; the first conductive connection portion 21 is coupled to the bus main portion Bus-L1 and the first extension portion Bus-L21, respectively.

[0090] Exemplarily, the first extension portion Bus-L21 and the second extension portion Bus-L22 form an integral structure.

[0091] Exemplarily, the second extending portion Bus-L22 is coupled to an end portion of the first extending portion Bus-L21, or the second extending portion Bus-L22 is coupled to a middle portion of the first extending portion Bus-L21.

[0092] Exemplarily, the first direction intersects the second direction, the first direction includes a longitudinal direction, and the second direction includes a transverse direction, but is not limited thereto.

[0093] Exemplarily, the orthographic projection of the first conductive connection portion 21 on the substrate has an overlapping area with the orthographic projection of the first extension portion Bus-L21 on the substrate, and in the overlapping area, the first conductive connection portion 21 is coupled to the first extension portion Bus-L21 through a via.

[0094] like Fig.12 As shown, exemplarily, a width d4 of the first extension portion Bus-L21 perpendicular to its own extension direction is greater than a width d5 ​​of the second extension portion Bus-L22 perpendicular to its own extension direction.

[0095] The above-mentioned setting method not only ensures the connection stability between the bus main part Bus-L1 and the bus extension part Bus-L2, but also increases the relative area between the bus main part Bus-L1 and the bus extension part Bus-L2, and effectively eliminates the risk of tip discharge between the bus main part Bus-L1 and the bus extension part Bus-L2.

[0096] like Figures 7 to 9 As shown, in some embodiments, the extending direction of the second extending portion Bus-L22 is the same as the extending direction of the virtual common electrode line Dum2.

[0097] Exemplarily, the second extending portion Bus-L22 and the virtual common electrode line Dum2 both extend in a direction intersecting with an extending direction of the bus main body portion Bus-L1 adjacent thereto.

[0098] The above configuration makes the first extension portion Bus-L21 and the second extension portion Bus-L22 closer to the virtual common electrode line Dum2, effectively reducing the layout difficulty while ensuring that the bus extension portion Bus-L2 is coupled to the corresponding virtual common electrode line Dum2.

[0099] In some embodiments, the extending direction of the second extending portion Bus-L22 is the same as the extending direction of the virtual common electrode pattern Dum1. For example: the second extending portion located in the upper frame area and the lower frame area of ​​the display substrate.

[0100] like Figures 4 to 6 As shown, in some embodiments, the second extension portion Bus-L22 includes at least two sub-portions coupled in sequence, and the extension directions of two adjacent sub-portions are different.

[0101] Exemplarily, the second extension portion Bus-L22 includes a first sub-portion, a second sub-portion and a third sub-portion coupled in sequence, the first sub-portion and the third sub-portion both extend in a direction intersecting with an extension direction of the adjacent bus main portion Bus-L1, and the extension direction of the second sub-portion is the same as the extension direction of the adjacent bus main portion Bus-L1.

[0102] The above configuration allows the specific shape of the bus extension portion Bus-L2 to be flexibly arranged according to the surrounding structure, while ensuring that the bus extension portion Bus-L2 is coupled to the corresponding virtual common electrode line Dum2, and effectively reduces the difficulty of layout.

[0103] like Figures 4 to 9 As shown, in some embodiments, the display substrate further includes a gate metal layer and a source-drain metal layer, the bus main body Bus-L1 is arranged in the same layer and material as the source-drain metal layer, and the bus extension portion Bus-L2 is arranged in the same layer and material as the gate metal layer.

[0104] The above-mentioned configuration enables the bus main body Bus-L1 to be formed in the same patterning process as the source-drain metal layer, and the bus extension Bus-L2 to be formed in the same patterning process as the gate metal layer, which effectively simplifies the manufacturing process of the display substrate and reduces the manufacturing cost.

[0105] like Figures 1 to 3 , Figures 10 to 12 As shown, in some embodiments, the display substrate further includes a gate metal layer, and the bus main body portion Bus-L1 and the bus extension portion Bus-L2 are both provided in the same layer and with the same material as the gate metal layer.

[0106] The above configuration enables the bus main body Bus-L1 and the bus extension Bus-L2 to be formed in the same patterning process as the gate metal layer, which effectively simplifies the manufacturing process of the display substrate and reduces the manufacturing cost.

[0107] like Figures 10 to 13 As shown, in some embodiments, when the bus extension portion Bus-L2 includes a first extension portion Bus-L21 and a second extension portion Bus-L22 coupled to each other, the bus main body portion Bus-L1 includes a first bus portion Bus-L11 and a second bus portion Bus-L12 alternately arranged, and along the extension direction perpendicular to the bus main body portion, a width d2 of the first bus portion Bus-L11 is smaller than a width d3 of the second bus portion Bus-L12, and the first bus portion Bus-L11 and the first extension portion Bus-L21 are arranged along the extension direction perpendicular to the bus main body portion.

[0108] Exemplarily, the orthographic projection of the second bus portion Bus-L12 on the base substrate and the orthographic projection of the first extension portion Bus-L21 on the base substrate are arranged in a direction parallel to the adjacent bus main body portion Bus-L1.

[0109] Exemplarily, the orthographic projection of the second bus portion Bus-L12 toward the boundary of the touch area 11 on the substrate is flush with the orthographic projection of the first extension portion Bus-L21 toward the boundary of the touch area 11 on the substrate, but is not limited thereto.

[0110] For example, when the first extension portion Bus-L21 and the bus body portion Bus-L1 are provided in the same layer and with the same material, the minimum distance between the two can be set to be greater than or equal to 5 micrometers. For example, it can be set to be equal to 8 micrometers, but it is not limited thereto.

[0111] The above arrangement is conducive to realizing a narrow-frame display substrate, and is also conducive to reducing the difficulty of layout of the display substrate in a limited layout space.

[0112] like Figures 10 to 13 As shown, in some embodiments, the display substrate further includes: a gate driving circuit GOA and a plurality of scanning lines 30; at least a portion of the orthographic projection of the bus main body Bus-L1 on the base substrate is located between the orthographic projection of the gate driving circuit GOA on the base substrate and the orthographic projection of the plurality of scanning lines 30 on the base substrate;

[0113] A plurality of second conductive connection parts 22, wherein the orthographic projection of the second conductive connection part 22 on the substrate overlaps with the orthographic projection of the bus main part Bus-L1 on the substrate, and the plurality of second conductive connection parts 22 are respectively coupled to the gate drive circuit GOA;

[0114] A plurality of third conductive connection parts 23 and a plurality of fourth conductive connection parts 24 , wherein the third conductive connection parts 23 are respectively coupled with the corresponding second conductive connection parts 22 and fourth conductive connection parts 24 , and the fourth conductive connection parts 24 and the corresponding scanning lines 30 form an integrated structure.

[0115] Exemplarily, the gate driving circuit GOA is located at the left frame and / or the right frame of the display substrate, but is not limited thereto.

[0116] Exemplarily, the display product adopts a dual gate line control structure, that is, normal sub-pixels Nor in the same row are controlled by two scan lines 30 , for example: odd-numbered normal sub-pixels Nor in the same row are controlled by one scan line 30 , and even-numbered normal sub-pixels Nor are controlled by another scan line 30 .

[0117] Exemplarily, the normal sub-pixel Nor includes a normal common electrode pattern Nor1 and a normal pixel electrode pattern Nor3 which are relatively arranged in a direction perpendicular to the substrate, and also includes a normal control circuit 40, wherein the normal control circuit 40 is respectively coupled to the corresponding scan line 30, the data line DA and the normal pixel electrode pattern Nor3, and the normal control circuit 40 controls the conduction or disconnection of the electrical connection between the coupled data line DA and the normal pixel electrode pattern Nor3 under the control of the coupled scan line 30.

[0118] Exemplarily, the normal control circuit 40 includes a control transistor, a gate of the control transistor is coupled to the corresponding scan line 30, a first electrode of the control transistor is coupled to the corresponding data line DA, and a second electrode of the control transistor is coupled to the corresponding normal pixel electrode.

[0119] Exemplarily, the virtual sub-pixel Dum includes a virtual common electrode pattern Dum1 and a virtual pixel electrode pattern Dum3 which are arranged opposite to each other in a direction perpendicular to the base substrate, and also includes a virtual control circuit, which is coupled to the corresponding scan line 30 and data line DA respectively.

[0120] Exemplarily, the virtual control circuit includes a control transistor, a gate of the control transistor is coupled to the corresponding scan line 30, a first electrode of the control transistor is coupled to the corresponding data line DA, a second electrode of some of the control transistors is coupled to the corresponding virtual pixel electrode, and a second electrode of some of the control transistors is in a floating state.

[0121] Exemplarily, the display substrate further includes a liquid crystal layer, and the liquid crystal layer can be deflected under the joint action of the normal common electrode pattern Nor1 and the normal pixel electrode pattern Nor3 in the normal sub-pixel Nor, thereby realizing a display function.

[0122] Exemplarily, the second conductive connection portion 22 is arranged in a different layer from the bus main body Bus-L1. The bus main body Bus-L1 includes a hollow area, and at least part of the second conductive connection portion 22 is located in the hollow area. This arrangement can reduce the parasitic capacitance between the second conductive connection portion 22 and the bus main body Bus-L1.

[0123] Exemplarily, the second conductive connection portion 22 is provided in the same layer and material as the source / drain metal layer, the third conductive connection portion 23 is provided in the same layer and material as the first conductive layer, and the fourth conductive connection portion 24 is provided in the same layer and material as the gate metal layer.

[0124] Exemplarily, the orthographic projection of the third conductive connection portion 23 on the substrate substrate and the orthographic projection of the second conductive connection portion 22 on the substrate substrate have an overlapping area, and the third conductive connection portion 23 is coupled to the second conductive connection portion 22 through a via hole in the overlapping area. The orthographic projection of the third conductive connection portion 23 on the substrate substrate and the orthographic projection of the fourth conductive connection portion 24 on the substrate substrate have an overlapping area, and the third conductive connection portion 23 is coupled to the fourth conductive connection portion 24 through a via hole in the overlapping area.

[0125] like Figures 10 to 13 As shown, illustratively, the fourth conductive connection portion 24 includes a first conductive portion 241 and a second conductive portion 242 coupled to each other, the first conductive portion 241 and its adjacent bus main body portion Bus-L1 have the same extension direction, the orthographic projection of the first conductive portion 241 on the substrate substrate and the orthographic projection of the second conductive connection portion 22 on the substrate substrate are arranged along a direction intersecting with the extension direction of the adjacent bus main body portion Bus-L1, and the second conductive portion 242 extends along the direction intersecting with the extension direction of the adjacent bus main body portion Bus-L1;

[0126] The third conductive connection portion 23 is coupled to the corresponding second conductive connection portion 22 and the first conductive portion 241 , respectively. The second conductive portion 242 and the corresponding scan line 30 form an integrated structure.

[0127] Exemplarily, the second conductive portion 242 extends in the same direction as the scanning line 30.

[0128] Exemplarily, the first conductive portion 241 and the second conductive portion 242 are formed as an integral structure.

[0129] The above arrangement ensures the connection reliability between the second conductive connection part 22 and the fourth conductive connection part 24 , and at the same time increases the facing area between the second conductive connection part 22 and the fourth conductive connection part 24 , thereby avoiding the problem of tip discharge.

[0130] like Figures 10 to 13As shown, in some embodiments, at least part of the orthographic projection of the first conductive portion 241 on the substrate is located between the orthographic projection of the first extension portion Bus-L21 on the substrate and the orthographic projection of the virtual common electrode pattern Dum1 on the substrate;

[0131] The orthographic projection of the first conductive portion 241 on the base substrate and at least part of the orthographic projection of the second extension portion Bus-L22 on the base substrate are arranged along the extension direction of the bus main body portion adjacent thereto;

[0132] At least part of the orthographic projection of the first conductive portion 241 on the base substrate and at least part of the orthographic projection of the second extending portion Bus-L22 on the base substrate are arranged along a direction intersecting the extending direction of the adjacent bus main portion Bus-L1.

[0133] like Fig.10 As shown, exemplarily, the second extension portion Bus-L22 includes a first sub-portion, a second sub-portion and a third sub-portion coupled in sequence, and the orthographic projection of the first conductive portion 241 on the substrate substrate and at least a portion of the orthographic projection of the first sub-portion on the substrate substrate are arranged along the extension direction of the adjacent bus main body portion; at least a portion of the orthographic projection of the first conductive portion 241 on the substrate substrate and at least a portion of the orthographic projection of the second sub-portion on the substrate substrate are arranged in a direction intersecting with the extension direction of the adjacent bus main body portion Bus-L1.

[0134] The above-mentioned setting method enables the bus extension portion Bus-L2 to bypass the third conductive connection portion 23 and the fourth conductive connection portion 24, thereby reducing the layout difficulty of the display substrate while ensuring that the bus extension portion Bus-L2, the third conductive connection portion 23 and the fourth conductive connection portion 24 all have sufficient layout space.

[0135] like Figures 4 to 9 As shown, in some embodiments, the display substrate further includes: a gate driving circuit GOA and a plurality of scanning lines 30; at least a portion of the orthographic projection of the bus main body Bus-L1 on the base substrate is located between the orthographic projection of the gate driving circuit GOA on the base substrate and the orthographic projection of the plurality of scanning lines 30 on the base substrate;

[0136] A plurality of second conductive connection parts 22, the orthographic projection of the second conductive connection part 22 on the substrate overlaps with the orthographic projection of the bus main part Bus-L1 on the substrate, the plurality of second conductive connection parts 22 are respectively coupled to the gate drive circuit GOA, and the second conductive connection part 22 and the corresponding scanning line 30 form an integrated structure.

[0137] Exemplarily, the second conductive connection portion 22 and the corresponding scan line 30 are both provided in the same layer and with the same material as the gate metal layer.

[0138] The above arrangement is conducive to achieving a narrow frame of the display substrate and reducing the difficulty of the frame layout of the display substrate.

[0139] like Figures 1 to 3 As shown, in some embodiments, the display substrate further includes a plurality of normal sub-pixels Nor, and the normal sub-pixels Nor include a normal common electrode pattern Nor1;

[0140] The plurality of normal common electrode patterns Nor1 included in the plurality of normal sub-pixels Nor are divided into a plurality of touch electrode blocks 110, wherein the touch electrode block 110 includes at least two normal common electrode patterns Nor1, and in the same touch electrode block 110, the normal common electrode patterns Nor1 arranged along the second direction are coupled via a normal common electrode line Nor2;

[0141] The virtual sub-pixel Dum further includes a virtual common electrode line Dum2, and a gap (eg, Figure 2 As shown, it has a width d1).

[0142] Exemplarily, the touch electrode block 110 includes a plurality of normal common electrode patterns Nor1 distributed in an array. In the same touch electrode block 110, the normal common electrode patterns Nor1 located in the same row along a direction intersecting an extension direction of an adjacent bus main body Bus-L1 are coupled through a corresponding normal common electrode line Nor2, and two adjacent rows of normal common electrode patterns Nor1 along the first direction are coupled through a fifth conductive connection portion 25.

[0143] Exemplarily, the normal common electrode pattern Nor1 is multiplexed as the touch electrode block 110 . The virtual common electrode pattern Dum1 is not multiplexed as the touch electrode block 110 .

[0144] A gap width d1 between the virtual common electrode line Dum2 and the normal common electrode line Nor2 adjacent to the virtual common electrode line Dum2 in a direction intersecting the extending direction of the bus body portion Bus-L1 adjacent to the virtual common electrode line Dum2 is greater than or equal to 10 micrometers.

[0145] The above-mentioned setting of a gap between the virtual common electrode line Dum2 and the normal common electrode line Nor2 adjacent to the direction intersecting with the extension direction of the adjacent bus main body Bus-L1 can effectively avoid tip discharge between the virtual common electrode line Dum2 and the normal common electrode line Nor2 adjacent to the direction intersecting with the extension direction of the adjacent bus main body Bus-L1, and avoid short circuit between the virtual common electrode line Dum2 and the normal common electrode line Nor2 adjacent to the direction intersecting with the extension direction of the adjacent bus main body Bus-L1.

[0146] There is a gap between the adjacent normal common electrode lines Nor2 along the second direction, and the width of the gap is greater than or equal to 10 microns. This arrangement can avoid tip discharge between the adjacent normal common electrode lines Nor2 along the second direction and avoid short circuit between the adjacent normal common electrode lines Nor2 along the second direction.

[0147] like Figures 1 to 13 As shown, in some embodiments, the display substrate further includes a plurality of data lines DA, the orthographic projections of the data lines DA on the base substrate partially overlap with the orthographic projections of the normal common electrode lines Nor2 on the base substrate (eg, Figure 3 position W1).

[0148] Exemplarily, the data line DA and the source / drain metal layer are provided in the same layer and with the same material.

[0149] Exemplarily, each of the data lines DA overlaps the same number of the normal common electrode lines Nor2.

[0150] Exemplarily, an orthographic projection of the data line DA on the base substrate does not overlap with an orthographic projection of the virtual common electrode line Dum2 on the base substrate.

[0151] Exemplarily, the orthographic projection of the data line DA closest to the virtual sub-pixel Dum on the substrate at least partially overlaps with the orthographic projection of the normal common electrode line Nor2 coupled to the normal common electrode pattern Nor1 in the adjacent touch electrode block 110 on the substrate. The orthographic projection of the first part of the normal common electrode line Nor2 on the substrate is located between the orthographic projection of the data line DA on the substrate and the orthographic projection of the bus main body Bus-L1 on the substrate, and the length of the first part along the second direction is greater than or equal to 4 microns.

[0152] Exemplarily, the virtual control circuit included in the virtual sub-pixel Dum has the same structure as the normal control circuit 40 included in the normal sub-pixel Nor.

[0153] The above configuration makes the load formed by each data line DA and the gate metal layer around it consistent, which can effectively maintain the uniformity of the image quality of the display substrate.

[0154] like Figure 1 middle Figure 3 As shown, in some embodiments, the virtual sub-pixel Dum further includes a virtual common electrode line Dum2, and the end of the virtual common electrode pattern Dum1 coupled to the virtual common electrode line Dum2 includes a first notch Q1, and the first notch Q1 is close to the normal common electrode line Nor2.

[0155] Since there is no dielectric between the virtual common electrode line Dum2 and the normal common electrode line Nor2, the virtual common electrode line Dum2 and the normal common electrode line Nor2 can maintain a short circuit prevention distance equal to or greater than 6 micrometers. The above distance can be achieved by providing the first gap Q1.

[0156] like Figure 1 middle Figure 3 As shown, in some embodiments, the end portion where the virtual common electrode pattern Dum1 is coupled to the virtual common electrode line Dum2 further includes a second notch Q2, and the second notch Q2 is arranged opposite to the first notch Q1 along the second direction.

[0157] The above configuration achieves the symmetry of the virtual common electrode pattern Dum1 along the second direction. At the same time, the normal common electrode pattern Nor1 is configured to have the first notch Q1 and the second notch Q2, thereby improving the uniformity of the display substrate.

[0158] The end of the virtual common electrode pattern Dum1 away from the virtual common electrode line Dum2 is set to have no notch, and the end of the normal common electrode pattern Nor1 away from the normal common electrode line Nor2 is set to have no notch, which effectively increases the area of ​​the common electrode pattern and improves the aperture ratio of the display substrate.

[0159] In order to ensure that the charging capacity and load of all sub-pixels are consistent, the common electrode pattern structure and the pixel electrode pattern structure are the same in the virtual sub-pixel and the normal sub-pixel. The common electrode pattern and the common electrode line are both used to transmit common signals, and the two layers are directly overlapped. At the junction of two adjacent touch electrode blocks, and at the junction of the virtual sub-pixel and the touch electrode block, the common electrode line made of the gate metal layer is disconnected, and the pixel electrode pattern covers the disconnection, ensuring that the pixel storage capacitors of each sub-pixel around the junction are the same, thereby ensuring consistent pixel charging rate and uniform image quality.

[0160] An embodiment of the present invention further provides a display device, comprising the display substrate provided by the above embodiment.

[0161] Exemplarily, the display device includes a liquid crystal display device, but is not limited thereto.

[0162] It should be noted that the display device can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane, etc.

[0163] In the display substrate provided in the above embodiment, the virtual sub-pixel includes a virtual common electrode pattern, and the virtual common electrode pattern is coupled to the common signal bus, so that the virtual common electrode pattern has the same potential as the common signal transmitted by the common signal bus. When the display substrate is in the touch period, each touch electrode block in the display substrate receives the common signal through the corresponding touch signal line, so that no matter the touch electrode block located in the center of the display substrate or the electrode block close to the edge of the display substrate, the structure around each touch electrode block has the same potential as the common signal, so that each touch electrode block in the display substrate can be in the same electrical environment, thereby effectively improving the touch uniformity of the display substrate and improving the display quality.

[0164] Therefore, when the display device provided by the embodiment of the present invention includes the above-mentioned display substrate, it also has the above-mentioned beneficial effects, which will not be described in detail here.

[0165] It should be noted that the signal line extends along the X direction means that the signal line includes a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along the X direction, and the length of the main part extending along the X direction is greater than the length of the secondary part extending along other directions.

[0166] It should be noted that the "same layer" in the embodiment of the present invention may refer to a film layer on the same structural layer. Or, for example, a film layer on the same layer may be a film layer for forming a specific pattern formed by the same film forming process, and then the film layer is patterned by the same mask through a single composition process to form a layer structure. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0167] In the various method embodiments of the present invention, the serial numbers of the steps cannot be used to limit the sequence of the steps. For ordinary technicians in this field, without paying creative work, changes to the sequence of the steps are also within the protection scope of the present invention.

[0168] It should be noted that each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiment, since it is basically similar to the product embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the product embodiment.

[0169] Unless otherwise defined, the technical terms or scientific terms used in this disclosure should be understood by people with ordinary skills in the field to which the present invention belongs. "First", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect", "couple" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0170] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0171] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0172] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A display substrate, It is characterized in that include: A base substrate and a plurality of touch electrode blocks, virtual sub-pixels and a common signal bus all arranged on the base substrate; The orthographic projection of the virtual sub-pixel on the base substrate is located between the orthographic projection of the common signal bus on the base substrate and the orthographic projection of the touch electrode block on the base substrate; the virtual sub-pixel includes a virtual common electrode pattern, and the virtual common electrode pattern is coupled to the common signal bus.

2. The display substrate according to claim 1, It is characterized in that The common signal bus includes a bus main body and a plurality of bus extensions respectively coupled to the bus main body, and the bus extensions are coupled to the virtual common electrode patterns in the corresponding virtual sub-pixels.

3. The display substrate according to claim 2, It is characterized in that The bus main body and the bus extension portion form an integrated structure, and the bus extension portion is directly overlapped with the virtual common electrode pattern in the corresponding virtual sub-pixel.

4. The display substrate according to claim 3, It is characterized in that The virtual sub-pixel further includes a virtual common electrode line, and the virtual common electrode line is coupled to an end of the virtual common electrode pattern; The virtual common electrode pattern extends along a first direction; the first end of the virtual common electrode line and the first end of the bus extension portion are arranged along the first direction, the first end of the virtual common electrode line is an end of the virtual common electrode line close to the bus main body, and the first end of the bus extension portion is an end of the bus extension portion away from the bus main body.

5. The display substrate according to claim 4, It is characterized in that A distance between a first end of the virtual common electrode line and a first end of the bus extension portion is greater than or equal to one third of a length of the virtual common electrode pattern along the first direction.

6. The display substrate according to claim 2, It is characterized in that The bus main body portion and the bus extension portion are coupled via a first conductive connection portion; The virtual sub-pixel further includes a virtual common electrode line, and the virtual common electrode line is coupled to an end of the virtual common electrode pattern; the bus extension portion is coupled to the virtual common electrode line in the corresponding virtual sub-pixel.

7. The display substrate according to claim 6, It is characterized in that The bus extension includes a first extension portion and a second extension portion coupled to each other; The first extension portion and the adjacent bus body portion extend in the same direction, and the orthographic projection of the first extension portion on the base substrate and the orthographic projection of the bus body portion on the base substrate are arranged along a direction intersecting the extending direction of the adjacent bus body portion; The second extending portion is coupled to the virtual common electrode line in the corresponding virtual sub-pixel; and the first conductive connecting portion is coupled to the bus main body and the first extending portion, respectively.

8. The display substrate according to claim 7, It is characterized in that The width of the first extending portion in a direction perpendicular to its own extending direction is greater than the width of the second extending portion in a direction perpendicular to its own extending direction.

9. The display substrate according to claim 7, It is characterized in that The extending direction of the second extending portion is the same as the extending direction of the virtual common electrode line; or, The extending direction of the second extending portion is the same as the extending direction of the virtual common electrode pattern; or, The second extending portion includes at least two sub-portions coupled in sequence, and the extending directions of two adjacent sub-portions are different.

10. The display substrate according to claim 7, It is characterized in that The display substrate further comprises a gate metal layer and a source-drain metal layer, the bus main body is provided in the same layer and material as the source-drain metal layer, and the bus extension is provided in the same layer and material as the gate metal layer.

11. The display substrate according to claim 3 or 7, It is characterized in that The display substrate further comprises a gate metal layer, and the bus main body portion and the bus extension portion are both provided in the same layer and with the same material as the gate metal layer.

12. The display substrate according to claim 11, It is characterized in that In the case where the bus extension portion includes a first extension portion and a second extension portion coupled to each other, the bus main body portion includes a first bus portion and a second bus portion alternately arranged, a width of the first bus portion along an extension direction perpendicular to the bus main body portion is smaller than a width of the second bus portion, and the first bus portion and the first extension portion are arranged along an extension direction perpendicular to the bus main body portion.

13. The display substrate according to claim 12, It is characterized in that The display substrate further comprises: a gate driving circuit and a plurality of scanning lines; at least a portion of the orthographic projection of the bus main body portion on the base substrate is located between the orthographic projection of the gate driving circuit on the base substrate and the orthographic projection of the plurality of scanning lines on the base substrate; A plurality of second conductive connection parts, wherein the orthographic projection of the second conductive connection part on the base substrate overlaps with the orthographic projection of the bus body part on the base substrate, and the plurality of second conductive connection parts are respectively coupled to the gate driving circuit; A plurality of third conductive connection parts and a plurality of fourth conductive connection parts, wherein the third conductive connection parts are respectively coupled with the corresponding second conductive connection parts and fourth conductive connection parts, and the fourth conductive connection parts and the corresponding scanning lines form an integrated structure.

14. The display substrate according to claim 13, It is characterized in that The fourth conductive connection portion includes a first conductive portion and a second conductive portion coupled to each other, the first conductive portion and the adjacent bus main portion extending in the same direction, the orthographic projection of the first conductive portion on the substrate and the orthographic projection of the second conductive connection portion on the substrate are arranged along a direction intersecting the extending direction of the adjacent bus main portion, and the second conductive portion and the scanning line extending in the same direction; The third conductive connection portion is respectively coupled to the corresponding second conductive connection portion and the first conductive portion, and the second conductive portion and the corresponding scan line form an integrated structure.

15. The display substrate according to claim 14, It is characterized in that At least a portion of the orthographic projection of the first conductive portion on the base substrate is located between the orthographic projection of the first extending portion on the base substrate and the orthographic projection of the virtual common electrode pattern on the base substrate; The orthographic projection of the first conductive portion on the base substrate and at least a portion of the orthographic projection of the second extending portion on the base substrate are arranged along an extending direction of the bus body portion adjacent thereto; At least a portion of an orthographic projection of the first conductive portion on the base substrate and at least a portion of an orthographic projection of the second extending portion on the base substrate are arranged along a direction intersecting an extending direction of the adjacent bus body portion.

16. The display substrate according to claim 2, It is characterized in that The display substrate further comprises: a gate driving circuit and a plurality of scanning lines; at least a portion of the orthographic projection of the bus main body portion on the base substrate is located between the orthographic projection of the gate driving circuit on the base substrate and the orthographic projection of the plurality of scanning lines on the base substrate; A plurality of second conductive connection parts, the orthographic projections of the second conductive connection parts on the base substrate overlap with the orthographic projections of the bus main body on the base substrate, the plurality of second conductive connection parts are respectively coupled to the gate drive circuit, and the second conductive connection parts and the corresponding scan lines form an integrated structure.

17. The display substrate according to claim 1, It is characterized in that The display substrate further comprises a plurality of normal sub-pixels, wherein the normal sub-pixels comprise normal common electrode patterns; The plurality of normal common electrode patterns included in the plurality of normal sub-pixels are divided into a plurality of touch electrode blocks, the touch electrode block includes at least two normal common electrode patterns, and in the same touch electrode block, the normal common electrode patterns arranged along the second direction are coupled through normal common electrode lines; The virtual sub-pixel further includes a virtual common electrode line, and a gap exists between the virtual common electrode line and a normal common electrode line adjacent to the virtual common electrode line along the second direction.

18. The display substrate according to claim 17, It is characterized in that The display substrate further includes a plurality of data lines, and the orthographic projections of the data lines on the base substrate partially overlap with the orthographic projections of the normal common electrode lines on the base substrate.

19. The display substrate according to claim 17, It is characterized in that The virtual sub-pixel further includes a virtual common electrode line, and the end of the virtual common electrode pattern coupled to the virtual common electrode line includes a first notch, and the first notch is close to the normal common electrode line.

20. The display substrate according to claim 19, It is characterized in that The end portion of the virtual common electrode pattern coupled to the virtual common electrode line further includes a second notch, and the second notch is arranged opposite to the first notch along the second direction.

21. A display device, It is characterized in that The invention comprises the display substrate according to any one of claims 1 to 20.

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