Method for manufacturing semiconductor device

Abstract

A manufacturing method of a semiconductor device includes the following steps. A well implant process is performed on a region of a substrate. A source / drain implantation process is performed in the region of the substrate. An active region is defined on the region of the substrate. A plurality of shallow trench isolation structures are formed in the active region. An annealing process is performed on the region of the substrate. According to the manufacturing method, a dopant implantation process is performed on a wide area of a substrate before defining an active area or forming a shallow trench isolation structure, so that random dopant fluctuation can be reduced.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device manufacturing method for reducing random dopant fluctuations. Background Art

[0002] Integrated circuit (IC) devices (also called semiconductor chips) can contain millions of transistors and other circuit components fabricated on a single silicon crystal substrate (wafer). In recent years, the size of IC components has been rapidly reduced in order to reduce costs and mass produce. Some problems have arisen in nanoscale components, such as random dopant fluctuations. Summary of the invention

[0003] The present disclosure provides an innovative semiconductor device manufacturing method to solve the problems of the prior art.

[0004] In some embodiments disclosed herein, a method for manufacturing a semiconductor device includes the following steps: performing a well implantation process on a region of a substrate; performing a source / drain implantation process on the region of the substrate; defining an active region on the region of the substrate; forming a plurality of shallow trench isolation structures in the active region; and performing an annealing process on the region of the substrate.

[0005] In some embodiments of the present disclosure, the source / drain implantation process is performed after the well implantation process is performed.

[0006] In some embodiments of the present disclosure, the active region is defined after the source / drain implantation process is performed.

[0007] In some embodiments of the present disclosure, the annealing process is performed after the plurality of shallow trench isolation structures are formed.

[0008] In some embodiments of the present disclosure, the annealing process includes a first annealing step using a first annealing temperature and a second annealing step using a second annealing temperature, wherein the first annealing temperature is lower than the second annealing temperature.

[0009] In some embodiments of the present disclosure, the first annealing step is a shallow trench isolation annealing.

[0010] In some embodiments of the present disclosure, the second annealing step is a dopant activation annealing.

[0011] In some embodiments of the present disclosure, the dopant activation anneal is performed by a rapid thermal annealing system.

[0012] In some embodiments of the present disclosure, forming the plurality of shallow trench isolation structures includes etching the region to form a plurality of trenches and forming an insulating material in the plurality of trenches.

[0013] In some embodiments of the present disclosure, the insulating material includes oxide and nitride materials.

[0014] In some embodiments disclosed herein, a method for manufacturing a semiconductor memory device includes: performing a dopant implantation process on a region of a substrate; after performing the dopant implantation process, forming an active region and a plurality of shallow trench isolation structures on the region of the substrate; and performing an annealing process on the region of the substrate.

[0015] In some embodiments of the present disclosure, performing the dopant implantation process includes performing a well implantation process and performing a source / drain implantation process.

[0016] In some embodiments of the present disclosure, the annealing process is performed after forming the plurality of shallow trench isolation structures.

[0017] In some embodiments of the present disclosure, the annealing process includes a first annealing step using a first annealing temperature and a second annealing step using a second annealing temperature, wherein the first annealing temperature is lower than the second annealing temperature.

[0018] In some embodiments of the present disclosure, the first annealing step is a shallow trench isolation annealing.

[0019] In some embodiments of the present disclosure, the second annealing step is a dopant activation annealing.

[0020] In summary, the semiconductor device manufacturing method disclosed herein performs a dopant implantation process on a wide area of ​​a substrate before defining an active region or forming a shallow trench isolation structure, which helps to reduce random dopant fluctuation.

[0021] The above description will be described in detail below with reference to implementation examples, and further explanations will be provided for the technical solutions disclosed herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to make the above and other objects, features, advantages and embodiments of the present disclosure more clearly understood, the accompanying drawings are described as follows:

[0023] Figure 1 depicts a portion of an active region of a semiconductor substrate according to some embodiments of the present disclosure;

[0024] Figure 2 A semiconductor substrate having a device region and a shallow trench isolation region according to some embodiments of the present disclosure is shown;

[0025] Figure 3 illustrates a cross-sectional view of a first transistor device at an early stage according to some embodiments of the present disclosure;

[0026] Figure 4 illustrates a cross-sectional view of a second transistor device at an early stage according to some embodiments of the present disclosure;

[0027] Figure 5 illustrates another cross-sectional view of a first transistor device according to some embodiments of the present disclosure;

[0028] Figure 6 illustrates another cross-sectional view of a second transistor device according to some embodiments of the present disclosure;

[0029] Figure 7 A schematic diagram showing voltage variation between a first transistor device and a second transistor device according to some embodiments of the present disclosure is shown;

[0030] Figure 8 A schematic diagram showing current variation between a first transistor device and a second transistor device according to some embodiments of the present disclosure is shown;

[0031] Fig. 9 Another schematic diagram showing a current variation between a first transistor device and a second transistor device according to some embodiments of the present disclosure is shown;

[0032] Fig.10 illustrates some steps of a method for manufacturing a first transistor device according to some embodiments of the present disclosure; and

[0033] Fig.11 Part of the steps of a method for manufacturing a second transistor device according to some embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0034] In order to make the description of the present disclosure more detailed and complete, reference may be made to the attached drawings and various embodiments described below, in which the same numbers represent the same or similar components. On the other hand, well-known components and steps are not described in the embodiments to avoid unnecessary limitations on the present disclosure.

[0035] Please refer to Figure 1 , Figure 2 , Figure 1 illustrates a portion of an active region of a semiconductor substrate according to some embodiments of the present disclosure, Figure 2 A semiconductor substrate having a device region and a shallow trench isolation region according to some embodiments of the present disclosure is shown.

[0036] The term "active region" refers to the region of a semiconductor component where current flows and the component's primary function occurs. It is a portion of the semiconductor material that is intentionally doped or modified to produce desired electronic behavior. The active region 102 is defined in a semiconductor substrate, and shallow trench isolation structures 106 are formed between adjacent component regions 104 on the substrate. The term "shallow trench isolation" also refers to a technique used in semiconductor manufacturing to electrically isolate adjacent active regions or components on a silicon substrate. It helps prevent unwanted electrical interactions and leakage currents between different components, ensuring proper operation and reliability of the integrated circuit (IC).

[0037] The process of manufacturing the shallow trench isolation structure 106 generally includes the following steps.

[0038] Substrate preparation: Semiconductor wafers, usually made of silicon, are cleaned and prepared for further processing.

[0039] Trench formation: A pattern is created on the wafer surface using lithography. The pattern defines the location and size of the isolation trench. A masking material such as photoresist is applied and exposed to ultraviolet (UV) light through a mask, followed by development to form the photoresist pattern.

[0040] Etching: Dry or wet etching is used to etch away exposed silicon dioxide (SiO2) areas to form shallow trenches. The depth of the trenches is usually in the range of a few hundred nanometers to a few microns.

[0041] Liner Deposition: A thin layer of oxide, called a liner, is deposited on the sidewalls and bottom of the trench. The liner material is typically silicon dioxide (SiO2) or other suitable dielectric material. The liner helps improve electrical isolation and prevents contaminants from diffusing into the active area.

[0042] Trench filling: The trenches are filled with dielectric materials, such as chemical vapor deposited oxides, or a combination of oxides (such as oxide 106b) and other materials such as silicon nitride (such as nitride 106a). Excess filling materials are usually removed using a chemical mechanical planarization (CMP) process to flatten the wafer surface.

[0043] Planarization: Planarize the wafer surface to ensure that the entire wafer surface is uniform and flat, eliminating any irregularities or topographical variations caused by the trench filling process.

[0044] Please refer to Figure 3 , Figure 4 , Figure 3 FIG. 1 is a cross-sectional view of a first transistor device 100 a at an early stage according to some embodiments of the present disclosure. Figure 4A cross-sectional view of a second transistor device 100b at an early stage according to some embodiments of the present disclosure is shown. In some embodiments of the present disclosure, the first transistor device 100a is generally manufactured by a first manufacturing method (eg Fig.10 200a), while the second transistor device 100b is typically manufactured by a second manufacturing method (eg, Fig.11 The second transistor device 100b manufactured by the manufacturing method 200b has a better distribution of dopant atoms in the semiconductor material than the first transistor device 100a manufactured by the manufacturing method 200a. In other words, the manufacturing method 200b is proposed to reduce random dopant fluctuations in the semiconductor device. As the transistor size decreases and approaches nanometer-scale size, random dopant fluctuations become particularly important. As the transistor size decreases, the number of dopant atoms in the active region of the device also decreases. Therefore, the influence of dopant atoms becomes more obvious, resulting in increased variability in device characteristics. The first transistor device 100a has a well implanted region 112, a source / drain region 114, and a junction 116 therebetween. The second transistor device 100b has a well implanted region 112', a source / drain region 114', and a junction 116' therebetween.

[0045] Please refer to Fig.10 , Fig.11 , Fig.10 FIG. 1 shows some steps of a method for manufacturing a first transistor device according to some embodiments of the present disclosure. Fig.11 Part of the steps of a method for manufacturing a second transistor device according to some embodiments of the present disclosure is shown. The method 200a includes steps 202, 204, 206, 208, 210 and 212. In step 202 of the method 200a, a region or portion of the substrate is defined as an "active region", for example, Figure 1 An active region 102 of a semiconductor substrate is formed in the active region 102 of the semiconductor substrate.

[0046] In step 204 of the manufacturing method 200 a , shallow trench isolation is formed between adjacent device regions 104 , for example Figure 2 A shallow trench isolation structure 106 is formed in the semiconductor substrate to electrically isolate adjacent active regions or devices.

[0047] In step 206 of the manufacturing method 200a, an annealing process is performed on the shallow trench isolation structure 106 between adjacent component areas 104. The annealing process after forming the shallow trench isolation structure is used to relieve stress, enhance the properties of the insulating material, achieve a flat surface, and improve electrical isolation. With respect to stress relief, the shallow trench isolation process involves etching trenches in a silicon substrate and filling them with an insulating material (usually an oxide). Due to the difference in thermal expansion coefficients between silicon and the insulator, the process may introduce mechanical stress in the surrounding silicon region. Annealing can help relieve such stress by allowing the silicon lattice to relax and adjust its structure, thereby reducing the possibility of strain-induced defects. With respect to enhancing the properties of the insulating material, the filling material used in the shallow trench isolation process, such as silicon dioxide (SiO2), may not have a completely dense structure after deposition. Annealing the wafer at high temperature helps promote the densification of the oxide material, thereby improving its electrical and mechanical properties. Densification reduces the occurrence of defects, such as voids or weak interfaces, and enhances the insulation performance of the shallow trench isolation structure. Regarding planarization, the shallow trench isolation structure formation process typically causes oxide material to protrude above the silicon surface, resulting in a non-flat topography. Annealing can facilitate the planarization of the shallow trench isolation structure by flowing the oxide material and smoothing the surface. This planarization step is critical for subsequent processing steps (such as depositing metal or dielectric layers) to ensure uniformity and proper adhesion. Regarding electrical isolation enhancement, the main purpose of the shallow trench isolation structure is to provide electrical isolation between adjacent active regions in a semiconductor device (such as a transistor device). Annealing can improve the quality of the oxide-silicon interface, reduce leakage current and enhance isolation characteristics. The annealing process helps to remove any contaminants or impurities that may be introduced during the formation of the shallow trench isolation structure, thereby improving electrical performance and device reliability.

[0048] In step 208 of the manufacturing method 200a, the component area (eg Figure 1 A well implantation process is performed in a device region 104 in the semiconductor device 100a, wherein the shallow trench isolation structure 106 is shielded or masked. The well implantation process is used to form a well implantation region 112 of the first transistor device 100a. P-type dopants, such as boron, are used to create p-wells in CMOS technology. It introduces acceptor states in the semiconductor lattice, resulting in an excess of holes, which leads to p-type behavior. N-type dopants, such as phosphorus, arsenic, or antimony, are used to create n-wells in CMOS technology. It introduces donor states in the semiconductor lattice, resulting in an excess of electrons, which leads to n-type behavior. The choice of dopant for well implantation is based on the desired doping concentration, electrical characteristics, and overall device requirements. The type and concentration of the dopant determines the conductivity and threshold voltage of the resulting well region, which are key parameters that control the behavior of transistors and other semiconductor components.

[0049] In step 210 of the manufacturing method 200a, a component region (eg Figure 2 The source / drain implantation process is performed in the device region 104 in the first transistor device 100a, wherein the shallow trench isolation structure 106 is shielded or masked. The term "source / drain implantation process" refers to the step of intentionally implanting dopant atoms into the source and drain regions of the transistor. The source / drain implantation process is used to form the source / drain region 114 of the first transistor device 100a. A p-type dopant, such as boron, is implanted into the source and drain regions of the p-channel transistor. It introduces acceptor states in the semiconductor lattice, which are conducive to the formation of a pn junction (e.g. Figure 3 n-type dopants (e.g., phosphorus, arsenic, or antimony) are used to implant into the source and drain regions of n-channel transistors. They introduce donor states into the semiconductor lattice, creating a structure that promotes the np junction (e.g., Figure 3 An n-type region is formed by the junction 116 in the middle.

[0050] In step 212 of the manufacturing method 200a, another annealing process is performed on the first transistor device 100a. This annealing process has a different purpose from the annealing process in step 206, and is used to activate and redistribute the dopant in the lattice of the semiconductor material. The implantation of dopants involves introducing impurity atoms into the semiconductor substrate to change its electrical properties. During the implantation process, high-energy ions are accelerated and directed to the surface of the semiconductor material. These ions penetrate the material and embed into the lattice, destroying its regular arrangement. This implantation process introduces electrically active dopant atoms into specific areas of the semiconductor, forming areas with changed conductive properties. However, the dopant implanted by ions is usually in an electrically inactive state and may not make a significant contribution to the desired electrical behavior of the semiconductor device. Therefore, an annealing process is performed to activate the dopant and restore the lattice structure.

[0051] The manufacturing method 200b includes steps 201, 203, 205, 207 and 209. In step 201 of the manufacturing method 200b, Figure 1 The substrate in the well implantation process is performed before the active region or shallow trench isolation is defined. This well implantation process is used to form the well implantation region 112' of the second transistor device 100b. Similar to step 208 of the manufacturing method 200a, p-type dopants or n-type dopants can be used to achieve the same purpose. Since step 201 is performed on a wide area of ​​the semiconductor substrate, before the active region or shallow trench isolation is defined, the dopant can be implanted into the well and the dopant atoms have a better distribution in the semiconductor material.

[0052] In step 203 of the manufacturing method 200b, Figure 1The source / drain implantation process is performed on the substrate in the semiconductor substrate before the active region or shallow trench isolation is defined. The source / drain implantation process is used to form the source / drain region 114' of the second transistor device 100b. Similar to step 210 of the manufacturing method 200a, p-type dopants or n-type dopants can be used to achieve the same purpose. Since step 203 is performed on a wide area of ​​the semiconductor substrate before the active region or shallow trench isolation is defined, the dopant can be implanted into the well and the dopant atoms have a better distribution in the semiconductor material.

[0053] In step 205 of the manufacturing method 200b, a region or a portion of the substrate is defined as an "active region", e.g. Figure 1 The active region 102 in the semiconductor substrate is formed. This step 205 is similar to the step 202 of the manufacturing method 200a, but is performed after the well implantation process and the source / drain implantation process.

[0054] In step 207 of the manufacturing method 200 b , shallow trench isolation is formed between adjacent device regions 104 , for example Figure 2 A shallow trench isolation structure 106 is formed in the semiconductor substrate to electrically isolate adjacent active region components. This step 207 is similar to step 204 of the manufacturing method 200a, but is performed after the well implantation process and the source / drain implantation process. In step 207, the shallow trench can be etched with a higher power (e.g., in dry etching) or a longer etching time than step 204 because the substrate has been implanted with dopants and is less susceptible to etching.

[0055] In step 209 of the manufacturing method 200b, an annealing process is performed on the second transistor device 100b. The annealing process may include a shallow trench isolation anneal using a first annealing temperature as a first annealing step and a dopant activation anneal using a second annealing temperature as a second annealing step, wherein the first annealing temperature is lower than the second annealing temperature. The shallow trench isolation annealing is performed to relieve stress, improve the quality of the isolation oxide, and ensure the integrity of the surrounding transistor structure. The purpose of the shallow trench isolation annealing process is mainly to optimize the performance of the isolation oxide material rather than to activate the dopant. Compared with the dopant activation annealing, the shallow trench isolation annealing is usually performed at a lower temperature, usually in the range of several hundred degrees Celsius. The equipment used for the shallow trench isolation annealing may include a furnace system, a rapid thermal processing tool, or a dedicated annealing chamber customized for oxide annealing. The dopant activation annealing is performed directly and continuously after the shallow trench isolation annealing to activate the dopant and restore the lattice structure, as described in step 212. The temperature required for this annealing process is usually very high, ranging from several hundred to more than one thousand degrees Celsius, depending on the specific dopant and the requirements of the target device. This high temperature annealing is usually performed using dedicated equipment, such as a rapid thermal annealing (RTA) system or a furnace annealing chamber. Compared with the manufacturing method 200a, the annealing process in step 209 includes a shallow trench isolation annealing and a dopant activation annealing that are performed consecutively after the shallow trench isolation is formed. Although the shallow trench isolation annealing is performed at a lower temperature than the dopant activation annealing, it still has a thermal effect that causes dopant activation.

[0056] Please refer to Figure 5 , Figure 6 , Figure 5 Another cross-sectional view of a first transistor device according to some embodiments of the present disclosure is shown, Figure 6 Another cross-sectional view of a second transistor device according to some embodiments of the present disclosure is shown. The first transistor device 100a is manufactured based on the manufacturing method 200a. Figure 5 The first transistor device 100a has two junctions 126 and junction 128. Junction 126 is between the bit line contact 122 and the underlying well implant region 112. Junction 128 is between the capacitor cell contact 124 and the underlying well implant region 112. The second transistor device 100b is manufactured based on the manufacturing method 200b. Figure 6 There are also two junctions 126' and junction 128' in the second transistor device 100b. Junction 126' exists between the bit line contact 122' and the underlying well implant region 112'. Junction 128' exists between the capacitor cell contact 124' and the underlying well implant region 112'. Junction 126' is aligned with junction 126 at approximately the same depth, and junction 128' is aligned with junction 128 at approximately the same depth. Figure 3 , Figure 4 In the embodiment, junctions 116' are aligned with junctions 116 at substantially the same depth. To achieve aligned junctions (116, 116'), aligned junctions (126, 126'), and aligned junctions (128, 128'), steps 201 and 203 of manufacturing method 200b should be performed with less power and lower power relative to the dopant density of steps 208 and 210 of manufacturing method 200a to mitigate the thermal effects of sequentially performing shallow trench isolation annealing and dopant activation annealing.

[0057] Please refer to Figure 7 , which shows a voltage variation diagram between a first transistor device and a second transistor device according to some embodiments of the present disclosure. Due to the adjusted junction profile, the operating voltage SVt of the second transistor device 100b is about 5.5% lower than the operating voltage SVt of the first transistor device 100a.

[0058] Please refer to Figure 8 , which is a schematic diagram showing current variation between a first transistor device and a second transistor device according to some embodiments of the present disclosure. Due to the adjusted junction profile, the saturation current Idsat of the second transistor device 100b is about 1.1% greater than the saturation current Idsat of the first transistor device 100a.

[0059] Please refer to Fig. 9 , which illustrates another current variation diagram between the first transistor device and the second transistor device according to some embodiments of the present disclosure. Due to the adjusted junction profile, the idle current Igidl of the second transistor device 100b is about 30.4% lower than the idle current Igidl of the first transistor device 100a.

[0060] In summary, the semiconductor device manufacturing method disclosed herein performs a dopant implantation process on a wide area of ​​a substrate before defining an active region or forming a shallow trench isolation structure, which helps to reduce random dopant fluctuation.

[0061] Although the present disclosure has been disclosed in the above embodiments, it is not intended to limit the present disclosure. Those skilled in the art may make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be determined by the definition of the attached claims.

[0062]

Explanation of symbols

[0063] In order to make the above and other objects, features, advantages and embodiments of the present disclosure more clearly understood, the attached symbols are explained as follows:

[0064] 100a: first transistor device

[0065] 100b: Second transistor device

[0066] 102: Active area

[0067] 104: Component Area

[0068] 106: Shallow Trench Isolation Structure

[0069] 106b: Oxide

[0070] 106a: Nitride

[0071] 112: Well implantation region

[0072] 114: Source / drain region

[0073] 116: Meet

[0074] 112': Well implantation region

[0075] 114': Source / drain region

[0076] 116': Meet

[0077] 122: Bit line contact

[0078] 122': bit line contact

[0079] 124: Capacitive Cell Contact

[0080] 124': Capacitive cell contact

[0081] 126: Meet

[0082] 128: Meet

[0083] 126': Meet

[0084] 128': Meet

[0085] 200a: Manufacturing method

[0086] 202, 204, 206, 208, 210, 212: Steps

[0087] 200b: Manufacturing method

[0088] 201, 203, 205, 207, 209: Steps

[0089] SVt: Operation voltage

[0090] Idsat: saturation current

[0091] Igidl: Idle current.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: Include: performing a well implantation process on a region of the substrate; Performing a source / drain implantation process in the region of the substrate; defining an active region on said region of said substrate; forming a plurality of shallow trench isolation structures in the active region; as well as An annealing process is performed on the region of the substrate. 2 . The manufacturing method according to claim 1 , wherein the source / drain implantation process is performed after the well implantation process is performed. 3 . The manufacturing method according to claim 1 , wherein the active region is defined after the source / drain implantation process is performed. 4 . The manufacturing method according to claim 1 , wherein the annealing process is performed after the plurality of shallow trench isolation structures are formed. 5 . The manufacturing method according to claim 1 , wherein the annealing process includes a first annealing step using a first annealing temperature and a second annealing step using a second annealing temperature, the first annealing temperature being lower than the second annealing temperature. The manufacturing method according to claim 5 , wherein the first annealing step is a shallow trench isolation annealing.

7. The manufacturing method according to claim 5, wherein the second annealing step is a dopant activation annealing. 8 . The manufacturing method according to claim 7 , wherein the dopant activation annealing is performed by a rapid thermal annealing system. 9 . The manufacturing method according to claim 1 , wherein forming the plurality of shallow trench isolation structures comprises etching the region to form a plurality of trenches and forming an insulating material in the plurality of trenches.

10. The manufacturing method according to claim 9, wherein the insulating material comprises oxide and nitride materials.

11. A method for manufacturing a semiconductor device, characterized in that: Include: performing a dopant implantation process on a region of a substrate; After performing the dopant implantation process, forming an active region and a plurality of shallow trench isolation structures on the region of the substrate; as well as An annealing process is performed on the region of the substrate. 12 . The manufacturing method according to claim 11 , wherein performing the dopant implantation process comprises performing a well implantation process and performing a source / drain implantation process. 13 . The manufacturing method according to claim 11 , wherein the annealing process is performed after forming the plurality of shallow trench isolation structures. 14 . The manufacturing method according to claim 11 , wherein the annealing process includes a first annealing step using a first annealing temperature and a second annealing step using a second annealing temperature, the first annealing temperature being lower than the second annealing temperature.

15. The manufacturing method according to claim 14, wherein the first annealing step is a shallow trench isolation annealing.

16. The manufacturing method according to claim 14, wherein the second annealing step is a dopant activation annealing.

Images