Three-dimensional chip
By setting a temperature sensor and silicon perforation structure in the three-dimensional chip, sensing temperature changes and adjusting the refresh cycle of the memory array, the data loss problem of the three-dimensional chip under temperature changes is solved, and effective data protection is achieved.
Patent Information
- Application Number
- CN202311026783.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-06-07
- Filing Date
- 2023-08-15
- Publication Date
- 2024-12-10
AI Technical Summary
Due to the sensitivity of temperature changes in the memory, the prior art is difficult to effectively predict and adjust the refresh frequency of the memory, resulting in the possible loss of data.
A three-dimensional chip is designed to prevent data loss by setting a temperature sensor and a silicon perforation structure in the chip. The temperature sensor is adjacent to the silicon perforation structure to sense temperature changes and to pre-adjust the refresh cycle of the memory array according to the sensing results.
By adjusting the refresh frequency of the memory array in advance, it can effectively prevent data loss in the memory array and ensure the correctness of stored data.
Smart Images
Figure CN119108358A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a chip, in particular to a three-dimensional chip. Background Art
[0002] As three-dimensional chips are widely used in memory applications, the heat flow of the chip has gradually become one of the important considerations in designing memory. Because the operations within the memory are very sensitive to temperature changes, it is even more necessary to adjust the memory operations specifically according to temperature changes. Summary of the invention
[0003] The present invention provides a three-dimensional chip, which can predict the temperature rise of the memory when the memory is heated by other chips, and then adjust the refresh frequency cycle of the memory in advance.
[0004] A three-dimensional chip of the present invention comprises a multi-layer chip, a silicon via structure and a temperature sensor. The chips are stacked and arranged one on another. The silicon via structure is arranged through the chips. The temperature sensor is arranged on a first chip in the chip. The temperature sensor is arranged adjacent to the silicon via structure and is used to sense a first temperature sensing result corresponding to the temperature of the silicon via structure.
[0005] Based on the above, the three-dimensional chip in the above embodiment can obtain the temperature sensing result corresponding to the TSV structure through the temperature sensor, so as to pre-adjust the refresh cycle of the memory array to avoid data loss. BRIEF DESCRIPTION OF THE DRAWINGS
[0006] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.
[0007] Figure 1 is a cross-sectional schematic diagram of a three-dimensional chip according to an embodiment of the present invention;
[0008] Figure 2 for Figure 1 A schematic diagram showing the relationship between refresh cycle and temperature in a memory array;
[0009] Figure 3 FIG. 4 is a schematic top view of a chip according to an embodiment of the present invention.
[0010] Description of Figure Numbers
[0011] 1: Three-dimensional chip;
[0012] 10: Temperature sensor;
[0013] 11: memory array;
[0014] B1, B2: micro solder joints;
[0015] D1~D3: chip;
[0016] L1: broken line;
[0017] P1~P4: conductor;
[0018] VIN: input signal;
[0019] V1~V3: silicon vias;
[0020] V21~V24, VS: silicon through-hole structure;
[0021] VSS: Reference ground voltage. DETAILED DESCRIPTION
[0022] Reference Figure 1 , the three-dimensional chip 1 includes chips D1 to D3, a silicon through-hole structure VS, a temperature sensor 10 and a memory array 11. In the three-dimensional chip 1, the chips D1 to D3 are stacked in sequence in the vertical direction to form a three-dimensional structure. The chip D2 between the chips D1 and D3 is provided with a temperature sensor 10 and a memory array 11. The temperature sensor 10 is arranged adjacent to the silicon through-hole structure VS. The silicon through-hole structure VS is arranged through the chips D1 to D3 and connected in the vertical direction. Specifically, the three-dimensional chip 1 can increase the density of transistor elements per unit area by stacking a plurality of chips D1 to D3 in the vertical direction, thereby having the advantage of, for example, reducing the area of the three-dimensional chip 1 after packaging. In addition, the memory array 11 arranged in the chip D2 may, for example, include a plurality of dynamic random-access memory (DRAM) units and is more susceptible to temperature, so the temperature can be sensed by the temperature sensor 10 arranged on the same chip substrate to adjust the operation of the memory array 11 (for example, the refresh cycle of the memory array 11). The temperature sensor 10 may be, for example, a thermal diode, a thermistor, or other temperature sensors implemented by field effect transistors or bipolar transistors.
[0023] In detail, although not explicitly shown, semiconductor elements and patterned wires that provide electrical connections to these semiconductor elements may be selectively provided on each chip D1-D3, so that the pre-planned and designed circuit logic can be implemented with semiconductor elements by circuit layout on the chips D1-D3. Furthermore, these semiconductor elements will consume power during operation, thus forming various heat sources on each chip D1-D3. For chip D2 in the three-dimensional chip 1, due to the three-dimensional structure of the stacked arrangement of the three-dimensional chip 1, the heat of the chip D2 in the middle layer is easier to accumulate and difficult to dissipate, so the temperature of chip D2 is more easily affected by chips in other layers. Therefore, in order to more accurately grasp the temperature on chip D2, or to more accurately grasp the influence of chips in other layers on chip D2, the temperature sensor 10 is arranged adjacent to the silicon via structure VS to produce a temperature result corresponding to the silicon via structure VS.
[0024] The through silicon via structure VS is set through the chips D1~D3. Chip D1, for example, includes a substrate D1S and a metal structure D1M set on the substrate D1S; chip D2, for example, includes a substrate D2S and a metal structure D2M set on the substrate D2S; chip D3, for example, includes a substrate D3S and a metal structure D3M set on the substrate D3S. Specifically, each chip includes a substrate and a metal structure above the substrate, and the metal structure may include a plurality of metal layers of different heights for setting patterned metal wires. The through silicon via structure VS is set through these substrates and metal structures. The through silicon via structure VS includes a plurality of through silicon vias V1~V3, which are respectively set in the substrates of chips D1~D3. The through silicon via V1 penetrates the substrate D1S and the metal structure D1M of the chip D1; the through silicon via V2 penetrates the substrate D2S and the metal structure D2M of the chip D2; the through silicon via V3 penetrates the substrate D3S and the metal structure D3M of the chip D3. The silicon vias V1 to V3 are connected by micro-bumps B1 and B2 (or solder balls). In detail, the silicon vias V1 to V3 and the micro-bumps B1 and B2 are formed by conductive materials, and the thermal conductivity of the silicon via structure VS as a whole is greater than the thermal conductivity of the substrate, so in some implementations, redundant silicon vias and micro-bumps can be used to help the chip dissipate heat. In some embodiments, the silicon via used to transfer heat flow can be a redundant silicon via, which is not connected to the wire of any metal layer in the metal structure, thereby avoiding the additional heat energy generated when transmitting electrical signals, which is continuously accumulated in the silicon via, thereby causing inaccurate temperature sensing results.
[0025] Furthermore, the silicon through vias V1-V3 provided in each chip D1-D3 are in contact with the substrate of each chip D1-D3, respectively, and metal contacts can be provided in the metal structure of each chip D1-D3 as required to electrically connect with each silicon through via V1-V3, thereby realizing heat flow transfer across chip layers in the three-dimensional chip 1. On the other hand, since the silicon through vias V1-V3 and the micro solder joints B1 and B2 are formed by conductive materials, the silicon through via structure VS as a whole has better thermal conductivity than the substrate of the chips D1-D3 and the filler between the chips. In other words, the thermal conductivity of the silicon through via structure VS is greater than the thermal conductivity of the substrate of each chip D1-D3. In this way, through the silicon through via structure VS directly contacting the substrate of each chip D1-D3, the silicon through via structure VS can also provide an additional heat flow path in the vertical direction in the three-dimensional chip 1. Compared with the temperature change of chip D2 which may be caused by heat flow transmitted through air or other supporting structures, the temperature of the silicon via structure VS can be heated by chip D1 or D3 earlier. Therefore, by monitoring the temperature of the silicon via structure VS, the temperature change trend caused by other chips D1 and D3 to chip D2 can be known in advance.
[0026] Since the memory array 11 in the chip D2 is relatively sensitive to temperature during operation, in addition to considering the heat energy generated by the memory array 11 itself during operation, it is also necessary to monitor the heat energy from other chip layers (such as adjacent chips D1 and D3). In this case, the temperature sensor 10 is disposed in the chip 10 in a manner adjacent to the silicon via structure VS, and the heat energy of other chip layers is monitored through the thermal conductivity of the silicon via structure VS. Therefore, the temperature sensor 10 can be used to generate a temperature sensing result corresponding to the temperature of the silicon via structure VS, thereby serving as a reference for the operation of the memory array 11.
[0027] In detail, in order to accurately determine the temperature impact on chip D2 caused by the heat energy on chips D1 and D3, the silicon via structure VS used to transfer heat flow is redundant in the three-dimensional chip 1, that is, the silicon via structure VS is designed to be electrically floating or coupled to a fixed level reference voltage, thereby eliminating the additional impact of signal transmission on heat energy. In this case, the silicon via structure VS is of course kept open or disconnected from the temperature sensor 10.
[0028] In one embodiment, a controller (not shown) is also provided on the chip D2. Figure 1), coupled to the temperature sensor 10 and the memory array 11. The controller can receive the temperature sensing result generated by the memory array 11, and increase the refresh frequency of the memory array 11 when the temperature of the silicon through-via structure VS is greater than the temperature threshold. In other words, when the controller determines that the temperature on the silicon through-via structure VS is greater than the temperature threshold, it may represent that one of the chips D1 and D3 above or below the chip D2 has a temperature greater than the temperature threshold, and the chip D2 is being heated. Since the silicon through-via temperature rises faster than the substrate, in this case, the controller can pre-adjust the refresh frequency of the memory array 11 when it is determined that the temperature of the silicon through-via structure VS is greater than the temperature threshold, thereby avoiding the loss of stored data in the memory array 11 due to the upcoming temperature rise.
[0029] Figure 2 for Figure 1 Schematic diagram of the relationship between the refresh cycle and temperature in the memory array 11. As shown by the broken line L1, the relationship between the refresh cycle and temperature in the memory array 11 may have multiple turning points. Every time the temperature of the memory array 11 changes and crosses these turning points, its refresh cycle also needs to be adjusted accordingly. The temperature values corresponding to these turning points can be stored in the controller as one or more temperature thresholds, thereby operating the refresh cycle or refresh frequency of the memory array 11 in the corresponding range to maintain the storage data of the memory array 11 correct.
[0030] In one embodiment, when the controller determines that the temperature of the TSV structure VS crosses a certain threshold during the heating process, Figure 2 When one of the temperature thresholds is exceeded, the controller can accordingly reduce the refresh cycle of the memory array 11 (i.e., increase the refresh frequency of the memory array 11). In other words, the controller can monitor the temperature sensing result provided by the temperature sensor 10 in real time, and when the temperature sensing result shows that the temperature of the TSV structure VS crosses one of the temperature thresholds during the rising process, the refresh cycle of the memory array 11 is correspondingly reduced.
[0031] In one embodiment, in addition to the temperature sensor 10 (e.g., the first temperature sensor) disposed adjacent to the TSV structure VS in the chip D2, another temperature sensor (e.g., the second temperature sensor) may be disposed inside the memory array 11. The first temperature sensor and the second temperature sensor may respectively generate a first temperature sensing result and a second temperature sensing result, which correspond to the temperature of the TSV structure VS and the temperature of the memory array 11, respectively. In this way, the controller may adjust the operation of the memory array 11 according to the temperature of the memory array 11 displayed by the second temperature sensing result in addition to the temperature of the TSV structure VS displayed by the first temperature sensing result.
[0032] In one embodiment, the controller may increase the refresh frequency of the memory array 11 when the first temperature sensing result shows that the temperature of the TSV structure VS is greater than the temperature threshold, and the second temperature sensing result shows that the temperature of the memory array 11 is less than the temperature threshold. In this case, when the temperature of the TSV structure VS is greater than the temperature of the memory array 11, it means that heat energy is flowing to the chip D2 and causing the temperature of the chip D2 and the memory array 11 to rise. In this case, the controller will increase the refresh frequency of the memory array 11 in advance when it is determined that the temperature of the TSV structure VS rises to greater than the temperature threshold, even if the temperature of the chip D2 or the memory array 11 has not yet exceeded the temperature threshold, to prevent data loss.
[0033] In one embodiment, the operation of pre-adjusting the refresh frequency of the memory array 11 in the above embodiment is not only limited to the case where the temperature of the memory array 11 is less than the temperature threshold, but also limited to the case where the difference between the temperature of the memory array 11 and the temperature threshold is less than a preset temperature range. For example, the controller can be set to pre-adjust the memory array 11 only when it is determined that the temperature of the memory array 11 is less than 10°C of the temperature threshold. In this way, when the temperature of the memory array 11 is less than the temperature threshold and is less than 10°C, even if the controller determines that the temperature of the silicon through-via structure VS is greater than the temperature threshold, the controller will not increase the refresh frequency of the memory array 11, because the memory array 11 is still in a relatively low temperature state at this time, and the heat energy transmitted from other chips will not cause the data of the memory array to be lost in a short time.
[0034] On the other hand, during the cooling process, the controller must control the refresh cycle of the memory array 11 according to the temperature of the memory array 11. Therefore, the controller must increase the refresh cycle of the memory array 11 only when the first temperature sensing result and the second temperature sensing result both show that the temperature of the silicon via structure VS and the memory array 11 are both lower than the temperature threshold. If only the temperature of the memory array 11 or the temperature of the silicon via structure VS drops below the temperature threshold, the controller will still maintain the refresh cycle setting of the memory array 11 to ensure that the stored data is correct.
[0035] Figure 3 FIG. 1 is a top view of a chip D2 according to an embodiment of the present invention. The chip D2 is provided with through-silicon via structures V21 to V24 and a temperature sensor 10. Specifically, Figure 3 This is to clearly explain the positional relationship between the TSV structures V21-V24 and the temperature sensor 10, and how the temperature sensor 10 accurately senses the temperature of the TSV structures V21-V24. Figure 3 Part of the circuit structure (such as the controller and the memory array, etc.) disposed on the chip D2 is omitted.
[0036] In detail, a total of TSV structures V21-V24 are provided in the chip D2. The TSV structures V21-V24 are not only adjacent to the temperature sensor 10, but also arranged around the temperature sensor 10 as the center. In this way, the temperature changes caused by the TSV structures V21-V24 can be uniformly transmitted to the temperature sensor 10. On the other hand, in addition to enhancing the sensing of the temperature sensor 10 through the positional relationship between the TSV structures V21-V24 and the temperature sensor 10, wires P1-P4 can also be provided above the chip D2 to be arranged around the temperature sensor 10 as the center, further enhancing the heat conduction effect between the TSV structures V21-V24 and the temperature sensor 10.
[0037] In detail, the wires P1-P4 are arranged on the chip D2 in a staggered manner around the temperature sensor 10, and the wires P1-P4 are arranged on the metal layer of the same height in the metal structure D2M of the chip D2. For example, there is an open circuit between the wires P1 and the wire P2. Among the wires P1-P4, the wires P1 and P3 are coupled to the temperature sensor 10, and can be used to provide the temperature sensor 10 with a reference ground voltage VSS and an input signal VIN for transmission. In addition, the wire P2 is coupled to the silicon via structures V21 and V22, and the wire P4 is coupled to the silicon via structures V23 and V24. In this case, by arranging the wires P1-P4 around the temperature sensor 10, the heat exchange rate between the silicon via structures V21-V24 and the temperature sensor 10 can be accelerated. The temperature sensing result generated by the temperature sensor 10 can more quickly reflect the temperature changes of the silicon via structures V21-V24, so that the controller can adjust the refresh frequency of the memory array 11 accordingly.
[0038] In one embodiment, the shape, position, structure and number of the silicon through-via structures V21-V24 and the wires P1-P4 disposed on the chip D2 can be adaptively adjusted to meet different design requirements. For example, the wires P1-P4 can be disposed on metal layers at different heights in the metal structure D2M of the chip D2, but the wires P1-P4 can still be disposed around the temperature sensor 10, thereby increasing the contact area of the wires P1-P4 and the heat exchange rate between the silicon through-via structures V21-V24 and the temperature sensor 10. Alternatively, the wires connected to the silicon through-via structures V21-V24 are not limited to two, and are not limited to the surrounding method. For example, the wires connected to the silicon through-via structures V21-V24 can have a zigzag or grid structure, which can also achieve the effect of increasing the contact area.
[0039] In summary, the three-dimensional chip of the above embodiment can generate a temperature sensing result corresponding to the temperature of the TSV structure through the temperature sensor disposed adjacent to the TSV structure. Accordingly, the temperature rise of the memory array can be predicted based on the sensing result of the temperature sensor, and the refresh cycle of the memory array can be adjusted in advance, thereby effectively preventing the loss of data in the memory array and maintaining the correctness of the data stored in the memory array.
Claims
1. A three-dimensional chip, comprising: Multi-layer chips, wherein the multiple chips are stacked on top of each other; At least one through silicon via structure is disposed through the plurality of chips; as well as The temperature sensor is disposed on a first chip among the plurality of chips. The temperature sensor is disposed adjacent to the at least one TSV structure and is used to sense a first temperature sensing result corresponding to the temperature of the at least one TSV structure.
2. The three-dimensional chip according to claim 1, further comprising: A memory array, disposed on the first chip; as well as The controller is coupled to the temperature sensor and increases the refresh frequency of the memory array when the first temperature sensing result shows that the temperature of the at least one TSV structure is greater than a temperature threshold.
3. The three-dimensional chip according to claim 2, wherein the temperature sensor is a first temperature sensor, and the three-dimensional chip further comprises: The second temperature sensor is disposed adjacent to the memory array and is used to sense a second temperature sensing result corresponding to the temperature of the memory array. 4 . The three-dimensional chip according to claim 1 , wherein a circuit is open between the temperature sensor and the at least one TSV structure. 5 . The three-dimensional chip according to claim 1 , wherein a thermal conductivity of the at least one TSV structure is greater than a thermal conductivity of substrates of the plurality of chips.
6. The three-dimensional chip according to claim 1, further comprising: A first conductive line coupled to the at least one TSV structure and disposed on the first chip; as well as a second wire, coupled to the temperature sensor and disposed on the first chip, The first conductive wire and the second conductive wire are both disposed around the temperature sensor as the center. 7 . The three-dimensional chip according to claim 6 , wherein the first conductive wires and the second conductive wires are disposed on the first chip in a staggered manner surrounding the temperature sensor. 8 . The three-dimensional chip according to claim 6 , wherein the first conductive line and the second conductive line are disposed on a same metal layer on the first chip. 9 . The three-dimensional chip according to claim 6 , wherein the second wire is used to provide the temperature sensor with an input signal or a reference voltage. 10 . The three-dimensional chip according to claim 6 , wherein the first conductive line and the second conductive line are disposed in different metal layers on different first chips. The three-dimensional chip according to claim 1 , wherein the at least one TSV structure is redundant.