Semiconductor device

Abstract

A semiconductor device is provided with: a chip-shaped semiconductor element (10); and anisotropic graphite (30) having one surface (31) on which the semiconductor element is disposed, and having one direction along the one surface as a c-axis direction. A semiconductor element is bonded to one surface of anisotropic graphite via a first bonding layer (20). In addition, a ceramic substrate (70) is disposed on the opposite side of the semiconductor element with anisotropic graphite interposed therebetween. A metal plate (50) comprising a metal plate-like member is disposed between the anisotropic graphite and the ceramic substrate.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device that dissipates heat by mounting a semiconductor element on anisotropic graphite. Background Art

[0002] Patent document 1 proposes a semiconductor package in which a semiconductor element is mounted on an anisotropic graphite composite. The anisotropic graphite composite is formed by compounding a quadrilateral plate-shaped anisotropic graphite, a metal layer for bonding, and an insulating inorganic material layer. The semiconductor element is bonded to the plate-shaped anisotropic graphite, and an inorganic material layer is arranged on the opposite side of the semiconductor element relative to the anisotropic graphite, so that while ensuring insulation, a semiconductor package is formed by bonding a cooler to the inorganic material layer. The anisotropic graphite and the inorganic material layer are bonded by a thinner metal layer of about 8μm to 50μm composed of plating or metal solder.

[0003] In such a structure, the directions along one side and the other side orthogonal to the surface of the anisotropic graphite are set as the X-axis and the Y-axis, and the thickness direction of the anisotropic graphite orthogonal to the X-axis and the Y-axis is set as the Z-axis. In addition, the crystal orientation of the anisotropic graphite is set as the Z-axis direction. In addition, the semiconductor element is arranged on the anisotropic graphite surface by aligning one side of the quadrilateral chip-shaped semiconductor element toward the X-axis direction and the other side orthogonal to the Y-axis direction, thereby improving the heat dissipation.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2021-100006 Summary of the invention

[0007] However, in the semiconductor package of Patent Document 1, the crystal orientation of the anisotropic graphite is oriented toward the Z-axis direction. Although the heat conduction in the X-axis direction and the Z-axis direction is good, the heat conduction in the Y-axis direction is not good. In addition, in the structure in which the anisotropic graphite and the inorganic material layer are connected only by a thin metal layer, the heat conduction effect in the Y-axis direction in the anisotropic graphite is low, and the heat generated by the semiconductor element cannot be dissipated. Therefore, the thermal resistance of the semiconductor package cannot be reduced.

[0008] An object of the present disclosure is to reduce thermal resistance in a semiconductor device that dissipates heat by mounting a semiconductor element on graphite.

[0009] A semiconductor device of one technical solution disclosed in the present invention comprises: a chip-shaped semiconductor element; anisotropic graphite having a side on which the semiconductor element is arranged, with a direction along the side being a c-axis direction; a first bonding layer for bonding the semiconductor element to the side of the anisotropic graphite; a plate-shaped insulating component for insulating the anisotropic graphite and arranged on the opposite side of the semiconductor element via the anisotropic graphite; a metal plate composed of a metal plate-shaped component arranged between the anisotropic graphite and the insulating component; a second bonding layer for bonding the anisotropic graphite to the metal plate; and a third bonding layer for bonding the metal plate to the insulating component.

[0010] In this way, the metal plate is provided between the anisotropic graphite and the insulating member. Thus, heat can be conducted to the outer edge of the anisotropic graphite via the metal plate. Therefore, the thermal resistance of the semiconductor device can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a cross-sectional view of the semiconductor device according to the first embodiment.

[0012] Figure 2 yes Figure 1 A perspective view of a semiconductor device shown.

[0013] Figure 3 is a cross-sectional view of a semiconductor device shown as a reference structure.

[0014] Figure 4 Yes means Figure 3 FIG. 4 is a diagram showing simulation results of heat conduction in a semiconductor device having a reference structure.

[0015] Figure 5 Yes means Figure 1 FIG. 2 is a diagram showing simulation results of the heat conduction behavior in the semiconductor device according to the first embodiment.

[0016] Figure 6 This is a graph showing the relationship between the thickness of the metal plate and the thermal resistance [°C / W] of the semiconductor device.

[0017] Figure 7 It is a cross-sectional view of a semiconductor device according to a second embodiment.

[0018] Figure 8 It is a cross-sectional view of a semiconductor device according to a third embodiment. DETAILED DESCRIPTION

[0019] Hereinafter, embodiments of the present disclosure will be described based on the drawings. In addition, in each embodiment including other embodiments described below, the same or equivalent parts are given the same reference numerals and described.

[0020] (First embodiment)

[0021] Reference Figure 1 to Figure 6 A first embodiment of the present disclosure will be described.

[0022] In the drawings attached to this specification, an X-axis, a Y-axis, and a Z-axis are shown. The description is given with an arbitrary direction being the X-axis, a direction perpendicular to the X-axis being the Y-axis, and a direction perpendicular to the X-axis and the Y-axis being the Z-axis.

[0023] like Figure 1 and Figure 2 As shown, the semiconductor device of this embodiment includes a semiconductor element 10, a first bonding layer 20, anisotropic graphite 30, a second bonding layer 40, a metal plate 50, a third bonding layer 60, and a ceramic substrate 70. The semiconductor element 10 is cooled by bonding the ceramic substrate 70 to a cooler 80.

[0024] The semiconductor element 10 is a semiconductor chip in which a power element is implanted. Examples of power elements include IGBT (Insulated Gate Bipolar Transistor) and MOSFET (metal-oxide-semiconductor field-effect transistor). Here, the semiconductor element 10 is a semiconductor chip in which a vertical IGBT is implanted. Figure 2 As shown, the semiconductor element 10 is provided with an upper surface electrode 11. The upper surface electrode 11 is an electrode connected to the emitter of the vertical IGBT, etc., and is arranged on the side of one side 12 of the semiconductor element 10. In addition, although not shown in the figure, a control electrode not shown in the figure is arranged on the one side 12 at a position different from the upper surface electrode 11. These upper surface electrodes 11 and control electrodes can be electrically connected to the outside by connecting to bonding wires or conductor components. In addition, although not shown in the figure, a lower surface electrode not shown in the figure is arranged on the other side of the opposite side of the one side 12. The lower surface electrode is an electrode connected to the collector of the vertical IGBT, etc., and is connected to the anisotropic graphite 30 via the first bonding layer 20. The first bonding layer 20 is made of a conductive material as described later, and the anisotropic graphite 30 is a conductor, so by connecting the conductor component to the anisotropic graphite 30 for external extraction, the lower surface electrode can also be electrically connected to the outside.

[0025] The semiconductor element 10 has a quadrilateral plate shape on its upper surface, and is arranged in such a manner that two opposite sides 12a of one side 12 are along the X-axis, two opposite sides 12b of the other side are along the Y-axis, and the thickness direction is along the Z-axis. In addition, in this specification, the "along" X-axis, Y-axis, etc. is preferably parallel, but is not necessarily limited to the case of parallel, and also includes the case of being inclined relative to the axis.

[0026] The first bonding layer 20 is made of a conductive bonding material such as solder, silver paste, or silver flakes. The thickness of the first bonding layer 20 is arbitrary, and is, for example, 0.02 to 0.05 mm. The semiconductor element 10 is electrically and physically bonded to the anisotropic graphite 30 through the first bonding layer 20 .

[0027] The anisotropic graphite 30 is graphite having thermal anisotropy and functions as a heat spreader. The thickness of the anisotropic graphite 30 is arbitrary, and is, for example, 2 mm.

[0028] like Figure 2 As shown, the anisotropic graphite 30 has a crystal structure of a graphite structure formed by overlapping graphite layers of hexagonal plate crystals, the direction of the overlapping graphite layers is the c-axis, and the plane direction of the graphite layers with the c-axis as the normal direction is the a-axis. The upper surface shape of the anisotropic graphite 30 is a quadrilateral plate, and is configured in a manner that the two opposite sides 31a of one side 31 of the anisotropic graphite 30 are along the X-axis, the two opposite sides 31b of the other side are along the Y-axis, and the thickness direction is along the Z-axis. That is, in the anisotropic graphite 30, the a-axis is configured along the X-axis and the Z-axis, and the c-axis is configured along the Y-axis. In addition, the size of the anisotropic graphite 30 is such that in the X-axis direction, the two sides 31a are larger than the two sides 12a of the semiconductor element 10, and in the Y-axis direction, the two sides 31b are larger than the two sides 12b of the semiconductor element 10. Furthermore, the semiconductor element 10 is bonded to a substantially central position of one surface 31 of the anisotropic graphite 30 via the first bonding layer 20 .

[0029] The anisotropic graphite 30 has a high thermal conductivity of about 1700 [W / mK] in the a-axis direction, i.e., the X-axis direction and the Z-axis direction, and a low thermal conductivity of about 7 [W / mK] in the c-axis direction, i.e., the Y-axis direction. Therefore, when the semiconductor element 10 generates heat, heat easily moves in the anisotropic graphite 30 along the a-axis due to high thermal conductivity, but heat is difficult to move in the c-axis direction compared to the direction along the a-axis due to low thermal conductivity.

[0030] The second bonding layer 40 and the third bonding layer 60 are provided for bonding the metal plate 50 to the anisotropic graphite 30 and the ceramic substrate 70. The second bonding layer 40 and the third bonding layer 60 may be made of different materials, but are made of the same material here, for example, bonding materials with high thermal conductivity such as silver paste and silver solder, which are made of conductive materials here. The thickness of the second bonding layer 40 and the third bonding layer 60 is arbitrary, for example, both are set to 0.02 to 0.05 mm. The anisotropic graphite 30 is physically bonded to the metal plate 50 by the second bonding layer 40, and the metal plate 50 is physically connected to the ceramic substrate 70 by the third bonding layer 60. In addition, in the case of the present embodiment, since the second bonding layer 40 is made of conductive material, the second bonding layer 40 also electrically bonds the anisotropic graphite 30 to the metal plate 50.

[0031] The metal plate 50 is equivalent to the first metal plate, and is a metal plate-shaped member having a higher thermal conductivity than the ceramic substrate 70 and the anisotropic graphite 30 in at least the c-axis direction. The metal plate 50 is sandwiched between the anisotropic graphite 30 and the ceramic substrate 70, and is bonded between them via the second bonding layer 40 and the third bonding layer 60. The upper surface shape of the metal plate 50 is a quadrilateral shape, and is configured in a manner that the two opposite sides 51a of one side of the surface 51 of the metal plate 50 are along the X-axis, the two opposite sides 51b of the other side are along the Y-axis, and the thickness direction is along the Z-axis. The size of the metal plate 50 is the same as or greater than the anisotropic graphite 30, that is, the two sides 51a are the same size or greater than the two sides 31a of the anisotropic graphite 30, and the two sides 51b of the other side are also the same size or greater than the two sides 31b of the anisotropic graphite 30. In addition, from the Z-axis direction, the anisotropic graphite 30 is configured so that it does not extend from the metal plate 50. However, due to manufacturing errors or the like, it is acceptable that the two sides 51 a of the metal plate 50 are slightly smaller than the two sides 31 a of the anisotropic graphite 30 , or the two sides 51 b of the metal plate 50 are slightly smaller than the two sides 31 b of the anisotropic graphite 30 .

[0032] The metal plate 50 is made of a metal material such as gold, silver, copper, aluminum, molybdenum, or tungsten. The thickness of the metal plate 50 is 0.2 mm to 3.0 mm, preferably 1 mm to 2 mm, and more preferably 1.5±0.1 mm.

[0033] The ceramic substrate 70 is an insulating component arranged on the opposite side of the semiconductor element 10 via the anisotropic graphite 30. The ceramic substrate 70 is composed of an insulating plate-shaped component with high thermal conductivity, for example, aluminum nitride or aluminum oxide. While realizing insulation between the metal plate 50, the anisotropic graphite 30 and the semiconductor element 10 and the cooler 80, the ceramic substrate 70 transfers the heat generated by the semiconductor element 10 to the cooler 80 via the anisotropic graphite 30 and the metal plate 50 for cooling. The ceramic substrate 70 also has a quadrilateral shape on the upper surface, and is arranged in a manner that the two opposite sides 71a of one side of the surface 71 of the ceramic substrate 70 are along the X-axis, the two opposite sides 71b of the other side are along the Y-axis, and the thickness direction is along the Z-axis. The size of the ceramic substrate 70 is the same as or larger than that of the metal plate 50, that is, the two sides 71a are the same size or larger than the two sides 51a of the metal plate 50, and the two sides 71b of the other side are also the same size or larger than the two sides 51b of the metal plate 50. The thickness of the ceramic substrate 70 is arbitrary, but is set to a thickness capable of suppressing creeping discharge, and is set to 0.32 mm, for example.

[0034] The cooler 80 radiates heat by exchanging heat with cooling water, air, etc., and is, for example, a metal member. The shape of the cooler 80 is arbitrary, and it can be composed of heat dissipation fins, etc. The ceramic substrate 70 is attached to the surface of the cooler 80 .

[0035] The semiconductor device of this embodiment is configured by such a structure. Next, the operation and effect of the semiconductor device of this embodiment will be described.

[0036] As described above, in the semiconductor device of the present embodiment, the metal plate 50 composed of a metal plate-like member is arranged between the anisotropic graphite 30 and the ceramic substrate 70. By providing the metal plate 50 composed of such a plate-like member, it is easy to conduct heat in the Y-axis direction of the anisotropic graphite 30, and it is possible to easily dissipate the heat generated by the semiconductor element 10. As a result, the thermal resistance of the semiconductor device can be reduced. The reason for obtaining such an effect is described below based on simulation.

[0037] As a reference construction, Figure 3 As shown in FIG. 1 , a heat conduction method is simulated for a structure in which the metal plate 50 is not provided and the anisotropic graphite 30 and the ceramic substrate 70 are bonded by a thin second bonding layer 40. This structure is equivalent to the structure of the semiconductor package described in Patent Document 1. Figure 1 The semiconductor device having the structure of the present embodiment shown was also subjected to a simulation of the heat conduction method. Figure 4 and Figure 5 Respectively Figure 3 The reference construction shown and Figure 1The simulation results of the semiconductor device of this embodiment are shown. Figure 4 and Figure 5 The figure shows the heat conduction analysis results obtained by CAE (Computer Aided Engineering) in the cross section along the Y-axis direction. The wider the interval between hatching lines, the lower the temperature.

[0038] like Figure 4 As shown, in the reference structure, the temperature is low at both ends of the anisotropic graphite 30 in the Y-axis direction. This means that the heat generated by the semiconductor element 10 is not sufficiently transferred in the Y-axis direction. Thus, in the reference structure, the effect of conducting heat in the Y-axis direction in the anisotropic graphite 30 is low, and the heat generated by the semiconductor element 10 cannot be dissipated, so the thermal resistance of the semiconductor device cannot be reduced.

[0039] In contrast, in the semiconductor device of the present embodiment, it can be seen that the temperature at both ends of the anisotropic graphite 30 in the Y-axis direction is higher than that of the reference structure. This means that the heat generated by the semiconductor element 10 is sufficiently conducted in the Y-axis direction. Thus, in the semiconductor device of the present embodiment, the effect of conducting heat in the Y-axis direction in the anisotropic graphite 30 is high, and the heat generated by the semiconductor element 10 can be dissipated. Therefore, the thermal resistance of the semiconductor device can be reduced.

[0040] Such a difference is considered to be caused by whether the metal plate 50 is present between the anisotropic graphite 30 and the ceramic substrate 70. In the reference structure, since only the thin second bonding layer 40 is present, it is not easy to diffuse heat through the second bonding layer 40, and the heat is not fully conducted in the direction of the arrow A1 in the figure, that is, the Y-axis direction of the anisotropic graphite 30. As a result, the heat is not conducted to a large range in the anisotropic graphite 30, and the range of heat conduction in the ceramic substrate 70 is also reduced. Therefore, the thermal resistance of the semiconductor device cannot be reduced.

[0041] On the other hand, when the metal plate 50 is present as in the semiconductor device of the present embodiment, as indicated by arrow A2 in the figure, the heat conducted from the semiconductor element 10 to the anisotropic graphite 30 is diffused through the metal plate 50 and is also conducted in the Y-axis direction in the anisotropic graphite 30. Therefore, the same state as the heat conduction from the semiconductor element 10 to a wide range in the anisotropic graphite 30 is achieved. As a result, the heat is conducted to a wider range of the ceramic substrate 70, and cooling can be performed with a larger area, so that the thermal resistance of the semiconductor device can be reduced.

[0042] In addition, the thermal resistance can be reduced by including the metal plate 50 as in the semiconductor device of this embodiment, and the thickness of the metal plate 50 is also studied. As a result, it is found that the thickness of the metal plate 50 and the thermal resistance [°C / W] of the semiconductor device are Figure 6 The relationship shown.

[0043] Specifically, if Figure 6 As shown, relative to the case where the thickness of the metal plate 50 is 0, that is, the metal plate 50 is not provided, if the metal plate 50 is provided, the thermal resistance gradually decreases. In particular, the decrease in thermal resistance is significantly shown in the range of the thickness of the metal plate 50 being 0.2 mm or more and 3.0 mm, and the thermal resistance further decreases if it is 1.0 mm or more and 2.0 mm or more. The thermal resistance is lowest when the thickness of the metal plate 50 is 1.5 mm. In addition, although the thermal resistance is lowest when the thickness of the metal plate 50 is 1.5 mm, it becomes the same thermal resistance as when it is 1.5 mm in the range of ±0.1 mm from here. In addition, if the metal plate 50 is too thick, the distance from the anisotropic graphite 30 to the cooler 80 becomes larger, and there is a situation where the cooling effect is suppressed. Regarding the thickness of the metal plate 50, it is preferably set to be less than 3.0 mm.

[0044] The relationship between the thickness of the metal plate 50 and the thermal resistance slightly changes depending on the material of the metal plate 50 and the structure of the semiconductor device, but has basically the same tendency.

[0045] Therefore, in the semiconductor device of the present embodiment, the thickness of the metal plate 50 is set to be greater than or equal to 0.2 mm and less than or equal to 3.0 mm, preferably greater than or equal to 1 mm and less than or equal to 2 mm, and more preferably 1.5±0.1 mm.

[0046] As described above, in the semiconductor device of the present embodiment, the metal plate 50 is provided between the anisotropic graphite 30 and the ceramic substrate 70. Thus, heat can be conducted to the outer edge side of the anisotropic graphite 30 via the metal plate 50. Specifically, the effect of conducting heat in the Y-axis direction in the anisotropic graphite 30 can be improved. Therefore, the thermal resistance of the semiconductor device can be reduced.

[0047] Specifically, the thermal resistance of the semiconductor device can be reduced by setting the thickness of the metal plate 50 to 0.2 mm to 3.0 mm, preferably to 1.0 mm to 2.0 mm. In particular, setting the thickness of the metal plate 50 to 1.5±0.1 mm is preferred because the thermal resistance of the semiconductor device can be further reduced.

[0048] (Second embodiment)

[0049] The second embodiment is described below. This embodiment is different from the first embodiment in that the structure between the semiconductor element 10 and the anisotropic graphite 30 is changed. The other parts are the same as the first embodiment, so only the parts different from the first embodiment will be described.

[0050] like Figure 7 As shown, the semiconductor device of this embodiment includes a metal plate 90 corresponding to the second metal plate between the semiconductor element 10 and the anisotropic graphite 30. The material that can constitute the metal plate 90 is the same as that of the metal plate 50. The metal plate 90 can be made of the same material, the same thickness, and the same size as the metal plate 50, but can also be made of a different material, a different thickness, and a different size. Here, the metal plate 90 is made of the same material, the same thickness, and the same size as the metal plate 50.

[0051] Specifically, the metal plate 90 is bonded to one side 31 of the anisotropic graphite 30 via the fourth bonding layer 100. The upper surface of the metal plate 90 is in the shape of a quadrilateral, and is arranged in such a manner that the two opposite sides 91a of one side of the surface 91 of the metal plate 90 are along the X-axis, the two opposite sides 91b of the other side are along the Y-axis, and the thickness direction is along the Z-axis. In addition, a semiconductor element 10 is bonded to the surface of the metal plate 90 via the first bonding layer 20. The semiconductor element 10 is set to a substantially central position in the surface 91 of the metal plate 90. In addition, the material that can constitute the fourth bonding layer 100 is the same as that of the second bonding layer 40 and the third bonding layer 60.

[0052] Thus, if the metal plate 90 is also disposed between the semiconductor element 10 and the anisotropic graphite 30, the heat can be diffused and conducted in the Y-axis direction through the metal plate 90. Therefore, the heat transfer in the Y-axis direction can be promoted by the metal plate 90 in addition to the metal plate 50, and the thermal resistance of the semiconductor device can be further reduced.

[0053] (Third embodiment)

[0054] The third embodiment is described. This embodiment changes the structure around the anisotropic graphite 30 compared to the first and second embodiments, and the rest is the same as the first and second embodiments, so only the parts different from the first and second embodiments are described. Here, the case where the structure of this embodiment is applied to the structure of the first embodiment is described, but it can also be applied to the structure of the second embodiment.

[0055] like Figure 8As shown, the semiconductor device of the present embodiment includes a metal plate 110 in a manner that covers the periphery of the anisotropic graphite 30, specifically, the plane along the Z axis which is the normal direction of one face 31, that is, the side face 32 of the anisotropic graphite 30. The metal plate 110 is equivalent to a covering metal plate. The metal plate 110 is arranged in a manner that covers at least the side face 32 parallel to the Z axis and the Y axis in the anisotropic graphite 30. In the present embodiment, the metal plate 110 is arranged in a manner that covers the entire surface of the four side faces 32 of the anisotropic graphite 30.

[0056] The material that can constitute the metal plate 90 is the same as that of the metal plate 50. The metal plate 110 can be made of the same material, the same thickness, and the same size as the metal plate 50, or can be made of a different material, a different thickness, and a different size. Here, the metal plate 90 is made of the same material, the same thickness, and the same size as the metal plate 50. In addition, in the case of this embodiment, the thickness direction of the metal plate 110 is the normal direction of each side surface 32 covered.

[0057] Specifically, the metal plate 110 is bonded to the side surface 32 of the anisotropic graphite 30 via a bonding layer 120 corresponding to the side bonding layer. The metal plate 110 has a quadrilateral shape as viewed from the direction along the thickness direction, and each side is made into a size corresponding to each side of the side surface 32 of the anisotropic graphite 30. In addition, the material that can constitute the bonding layer 120 is the same as that of the second bonding layer 40 and the third bonding layer 60.

[0058] In this way, if the metal plate 110 is arranged so as to cover the side surface 32 of the anisotropic graphite 30, heat is easily diffused in the Y-axis direction by heat conduction through the metal plate 110. Therefore, heat conduction in the Y-axis direction can be promoted by the metal plate 110 in addition to the metal plate 50, and the thermal resistance of the semiconductor device can be further reduced.

[0059] (Other embodiments)

[0060] The present disclosure is described based on the above-mentioned embodiments, but is not limited to the embodiments, and also includes various modifications or modifications within the equivalent range. In addition, various combinations and forms, and other combinations and forms including only one element, the above or the below thereof, also fall within the scope and concept of the present disclosure.

[0061] For example, in each of the above-described embodiments, the ceramic substrate 70 is used as the insulating member. However, the insulating member is not limited to the ceramic substrate 70 and may be formed of other insulating materials.

[0062] In addition, in each of the above-mentioned embodiments, an example is given in which one semiconductor element 10, one anisotropic graphite 30, one metal plate 50, and one ceramic substrate 70 are used as one set of semiconductor devices, and one set of semiconductor devices is bonded to one cooler 80. However, this is just an example, and a structure in which two or more sets of semiconductor devices are bonded to the same cooler 80 is also possible.

[0063] In addition, an example of a structure in which one semiconductor element 10 is arranged for each of the anisotropic graphite 30, the metal plate 50, and the ceramic substrate 70 is given. However, in this regard, a structure in which two semiconductor elements 10 are arranged for each of the anisotropic graphite 30, the metal plate 50, and the ceramic substrate 70 may be made. For example, in the case where the semiconductor switching elements of the upper arm and the lower arm in the inverter circuit are constituted by the semiconductor elements 10, the semiconductor elements 10 of the upper arm and the lower arm are connected in series. In such a case, if the semiconductor element 10 of one side is mounted on the surface of the anisotropic graphite 30 in the reverse direction relative to the semiconductor element 10 of the other side, they can be connected in series.

[0064] Furthermore, the upper surface shapes of the semiconductor element 10 , the anisotropic graphite 30 , the metal plate 50 , and the ceramic substrate 70 do not necessarily need to be a quadrilateral, and may be, for example, shapes in which each corner or a part of the corner is cut off.

Claims

1. A semiconductor device, It is characterized in that have: A semiconductor component in the form of a chip; Anisotropic graphite has a surface on which the semiconductor element is arranged, and one direction along the surface is defined as a c-axis direction; A first bonding layer, bonding the semiconductor element to the one side of the anisotropic graphite; A plate-shaped insulating member is disposed on the opposite side of the semiconductor element via the anisotropic graphite to insulate the anisotropic graphite; A metal plate, which is composed of a metal plate-shaped member disposed between the anisotropic graphite and the insulating member; A second bonding layer bonding the anisotropic graphite to the metal plate; as well as The third bonding layer bonds the metal plate and the insulating member.

2. The semiconductor device according to claim 1, It is characterized in that The metal plate has a thickness of 0.2 mm or more and 3.0 mm or less.

3. The semiconductor device according to claim 1, It is characterized in that The metal plate has a thickness of 1.0 mm or more and 2.0 mm or less.

4. The semiconductor device according to claim 1, It is characterized in that The thickness of the above metal plate is 1.5±0.1 mm.

5. The semiconductor device according to claim 1, It is characterized in that The metal plate is made of a metal material having a higher thermal conductivity than the insulating member.

6. The semiconductor device according to claim 1, It is characterized in that The above metal plate is used as the first metal plate; have: a second metal plate disposed on the one surface of the anisotropic graphite; and A fourth bonding layer bonding the second metal plate to the anisotropic graphite; The semiconductor element is bonded to the second metal plate via the first bonding layer.

7. The semiconductor device according to any one of claims 1 to 6, It is characterized in that have: a covering metal plate covering at least a surface along the c-axis of the anisotropic graphite among the side surfaces along the normal direction of the one surface in the anisotropic graphite; and The side bonding layer bonds the cover metal plate to the anisotropic graphite.

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