Chip packaging structure and preparation method thereof

Abstract

The invention provides a chip packaging structure and a preparation method thereof. The chip packaging structure comprises a substrate; the chip is arranged on one side of the substrate; the at least one wiring layer is arranged on one side, deviating from the substrate, of the chip; the at least one dielectric layer is arranged between the chip and the wiring layer, and / or is arranged between the adjacent wiring layers; the interconnection structure is located in the dielectric layer, and the interconnection structure is connected with the chip and the wiring layer adjacent to the chip and / or is connected with the two adjacent wiring layers; wherein at least one interconnection structure comprises a step structure. According to the technical scheme of the invention, the thermal stress of the interconnection structure can be offset, the interconnection structure is prevented from being thinned or broken, and the yield of the chip packaging structure is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor packaging technology, and in particular to a chip packaging structure and a preparation method thereof. Background Art

[0002] With the development of semiconductor technology, advanced packaging technology plays an increasingly important role in chips. The packaging structure involves a variety of materials, such as plastic layer, dielectric layer, metal wire layer, etc. Due to the mismatch of the coefficient of thermal expansion (CTE) of various materials, it will cause uneven force at various locations and generate stress, which can easily cause the connection between multiple metal wire layers to break. Summary of the invention

[0003] In order to solve the above problems, the embodiments of the present application provide a chip packaging structure and a method for preparing the same.

[0004] In a first aspect, an embodiment of the present application provides a chip packaging structure, comprising: a substrate; a chip, arranged on one side of the substrate; at least one wiring layer, arranged on the side of the chip facing away from the substrate; at least one dielectric layer, arranged between the chip and the wiring layer, and / or arranged between adjacent wiring layers; an interconnection structure, located in the dielectric layer, the interconnection structure connecting the chip and the wiring layer adjacent to the chip, and / or connecting two adjacent wiring layers; wherein at least one interconnection structure comprises a step structure.

[0005] In combination with the first aspect, the interconnection structure includes at least one step structure; preferably, the step structure includes at least one of a plane or a curved surface; preferably, along a cross section perpendicular to the substrate, the interconnection structure is step-shaped; preferably, along multiple cross sections perpendicular to the substrate, the interconnection structure has the same shape; preferably, along a cross section perpendicular to the substrate, the interconnection structure includes at least one of a straight line segment or a curved segment; preferably, along a cross section perpendicular to the substrate, the interconnection structure is an S-shaped curve.

[0006] In combination with the first aspect, the chip packaging structure includes at least two wiring layers and at least two dielectric layers; preferably, the wiring layer includes a first wiring layer and a second wiring layer arranged in sequence along a direction away from the substrate, and the dielectric layer includes a first dielectric layer and a second dielectric layer, the first dielectric layer is located between the first wiring layer and the chip, and the second dielectric layer is located between the first wiring layer and the second wiring layer; the interconnection structure includes a first interconnection structure and a second interconnection structure, the first interconnection structure is located in the first dielectric layer, connecting the first wiring layer and the chip; the second interconnection structure is located in the second dielectric layer, connecting the first wiring layer and the second wiring layer; the second interconnection structure includes a step structure; preferably, the first interconnection structure and the second interconnection structure both include a step structure.

[0007] In combination with the first aspect, the interconnection structure includes a first part, the first part includes a first end and a second end that are relatively arranged, the first end is located on a side of the dielectric layer close to the substrate, and the second end is located on a side of the dielectric layer away from the substrate; the chip includes a pin, the first end is connected to the pin, and the second end is connected to a wiring layer adjacent to the chip; or, the first end is connected to one wiring layer, and the second end is connected to another wiring layer adjacent to the wiring layer; preferably, the interconnection structure also includes a second part, the second part includes a third end and a fourth end that are relatively arranged, the third end is located on a side of the dielectric layer close to the substrate, and the fourth end is located on a side of the dielectric layer away from the substrate; the third end and the first end are connected to the same pin of the chip, or, the third end and the first end are connected to the same wiring layer; the fourth end is suspended; preferably, the first part and the second part are mirror-symmetrical.

[0008] In combination with the first aspect, the material of the interconnect structure includes at least one of copper, aluminum, titanium, nickel, gold, and silver; preferably, the material of the wiring layer includes at least one of copper, aluminum, titanium, nickel, gold, and silver; preferably, the material of the interconnect structure is the same as the material of the wiring layer, and the interconnect structure and the wiring layer are prepared in the same layer; preferably, along the direction perpendicular to the substrate, the thickness of the wiring layer is greater than or equal to 1um and less than or equal to 50um, preferably greater than or equal to 5um and less than or equal to 20um; preferably, the thickness of the interconnect structure is greater than or equal to 1um and less than or equal to 50um, preferably greater than or equal to 5um and less than or equal to 20um; preferably, the chip packaging structure includes at least two wiring layers, and the orthographic projections of the wiring layers of different layers on the substrate are staggered; preferably, the material of the dielectric layer includes at least one of Ajinomoto laminated dielectric film, photosensitive polyimide, polyimide, and epoxy resin; preferably, along the direction perpendicular to the substrate, the thickness of the dielectric layer is greater than or equal to 2um and less than or equal to 100um, preferably greater than or equal to 8um and less than or equal to 20um.

[0009] In combination with the first aspect, the chip packaging structure also includes a first film layer, which is arranged around the chip, and a dielectric layer is filled between the first film layer and the chip; preferably, the material of the first film layer includes an epoxy molding compound; or, the chip packaging structure also includes a second film layer, which wraps the chip, and the material of the second film layer is the same as that of the dielectric layer; preferably, the chip includes a plurality of pins, and each pin is connected to an interconnection structure.

[0010] In combination with the first aspect, the chip packaging structure also includes a protective layer, which is arranged on the side of the wiring layer farthest from the substrate away from the substrate; the protective layer covers the interconnect structure farthest from the substrate and at least part of the wiring layer farthest from the substrate; preferably, the protective layer has a through hole, and the wiring layer farthest from the substrate exposes part of the connecting solder balls through the through hole; preferably, the material of the protective layer includes at least one of ink, polyimide, photosensitive polyimide, and Ajinomoto laminated dielectric film; preferably, along the direction perpendicular to the substrate, the thickness of the protective layer is greater than or equal to 5um and less than or equal to 100um, preferably greater than or equal to 20um and less than or equal to 50um.

[0011] In a second aspect, an embodiment of the present application provides a method for preparing a chip packaging structure, comprising: fixing a chip on a substrate; alternately forming at least one dielectric layer, an interconnection structure and at least one wiring layer on a side of the chip facing away from the substrate; the interconnection structure is located in the dielectric layer, the interconnection structure connects the chip and the wiring layer adjacent to the chip, and / or connects two adjacent wiring layers, and at least one interconnection structure includes a step structure.

[0012] In combination with the second aspect, in the step of alternately forming at least one dielectric layer, an interconnection structure and at least one wiring layer on the side of the chip facing away from the substrate, the step of forming a dielectric layer, an interconnection structure and a wiring layer includes: forming a dielectric layer on the side of the chip or the upper wiring layer facing away from the substrate, preparing a via in the dielectric layer, and the side wall of the via includes a step structure; using photoresist, forming an interconnection structure in the via and forming a wiring layer on the side of the dielectric layer facing away from the substrate through electroplating, evaporation or magnetron sputtering process; preferably, forming a dielectric layer on the side of the chip or the upper wiring layer facing away from the substrate, and the step of preparing the via in the dielectric layer includes: depositing a dielectric material on the side of the chip or the upper wiring layer facing away from the substrate to obtain a dielectric layer, wherein when the dielectric material is deposited on the side of the upper wiring layer facing away from the substrate, the dielectric material covers the upper interconnection structure and fills the via in the upper dielectric layer; forming a via on the dielectric layer by an etching process; preferably, the etching process includes at least one of half-tone masking, multi-step photolithography, laser etching or chemical dry etching.

[0013] In combination with the second aspect, the method also includes: forming a protective layer on the side of the last wiring layer facing away from the substrate; preferably, forming a protective layer on the side of the last wiring layer facing away from the substrate, including: forming an insulating material layer on the side of the last wiring layer facing away from the substrate, the insulating material layer covering the last layer of interconnection structure and filling the vias in the last layer of dielectric layer; patterning the insulating material layer to obtain a protective layer, the protective layer exposing a portion of the last wiring layer.

[0014] Through the above scheme, at least one interconnection structure is set as a step structure. Under the action of thermal stress, the shape of the interconnection structure changes, which can offset the thermal stress, thereby preventing the interconnection structure from being stretched or broken, and improving the yield of the chip packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic diagram of the deformation of the interconnect structure under thermal stress.

[0016] Figure 2 Schematic cross-sectional views of various interconnect structures are shown.

[0017] Figure 3 It is a schematic diagram of a chip packaging structure provided by an exemplary embodiment of the present application.

[0018] Figure 4 is a schematic diagram of a chip packaging structure provided by yet another exemplary embodiment of the present application.

[0019] Figure 5 is a schematic diagram of a chip packaging structure provided by yet another exemplary embodiment of the present application.

[0020] Figure 6 is a schematic diagram of a chip packaging structure provided by yet another exemplary embodiment of the present application.

[0021] Figure 7 is a schematic diagram of a chip packaging structure provided by yet another exemplary embodiment of the present application.

[0022] Figure 8 is a schematic diagram of a chip packaging structure provided by yet another exemplary embodiment of the present application.

[0023] Fig. 9 is a schematic diagram of a chip packaging structure provided by yet another exemplary embodiment of the present application.

[0024] Fig.10a is a schematic diagram of a chip packaging structure provided by yet another exemplary embodiment of the present application.

[0025] Fig.10b yes Fig.10a A top view of the chip packaging structure is shown.

[0026] Fig.11 It is a schematic flow chart of a method for preparing a chip packaging structure provided by an exemplary embodiment of the present application.

[0027] Figures 12a to 12d It is a structural schematic diagram of a method for preparing a chip packaging structure provided in one embodiment of the present application. DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0029] Generally, in a chip packaging structure, due to the small size of the chip, the chip pins are led out through multiple wiring layers to be connected to corresponding electronic devices through solder balls. A dielectric layer is provided between the multiple wiring layers, and an interconnection structure is provided on the dielectric layer. Adjacent wiring layers or wiring layers and chips are electrically connected through the interconnection structure. The interconnection structure is provided as a straight line segment between adjacent wiring layers. Optionally, the interconnection structure is perpendicular to the wiring layer.

[0030] Due to the large difference in the coefficient of thermal expansion (CTE) between the dielectric layer material and the chip (as well as the plastic layer and protective layer in the chip packaging structure), the stress generated during thermal expansion can cause the interconnect structure to deform (for example, be stretched and thinned). If the stress is too large, the interconnect structure may be fractured or damaged, resulting in poor signal connection. Figure 1 is a schematic diagram of the deformation of the interconnect structure under thermal stress. Figure 1 As shown in FIG. 1 , the structure includes a wiring layer 40, a dielectric layer 50, an interconnection structure 60 and a protective layer 70. The interconnection structure 60 connects adjacent wiring layers 40. When there is no thermal stress, the interconnection structure 60 is in a vertical shape with a length of H. Under the action of thermal stress, the interconnection structure 60 is stretched into an inclined shape with a length of L. According to Hooke's law, the deformation of the interconnection structure 60 is Among them, F 0is the tensile force applied to the wiring layer 40, which is caused by the different CTE of different materials, and the tensile force will cause stress in the interconnection structure 60; E is the Young's modulus of the interconnection structure 60, t is the thickness of the interconnection structure 60, and W is the width of the interconnection structure 60. It can be seen from the above deformation formula that the relevant parameters of the interconnection structure 60 (for example, the material and size of the interconnection structure 60, etc.) will affect the deformation of the interconnection structure 60. However, in the packaging process, the size of the interconnection structure 60 will be limited by other packaging structures (for example, the thickness of the dielectric layer, the size of the packaging structure, etc.). In addition, in order to ensure the electrical connection between the multi-layer metal wires, the material of the interconnection structure 60 needs to be metal. Therefore, it is not easy to reduce the deformation of the interconnection structure 60 by changing the relevant parameters of the interconnection structure 60. In the prior art, the solution to reduce the deformation of the interconnection structure 60 is mainly to reduce the stress (or tensile force) caused by thermal expansion. In order to reduce the stress caused by thermal expansion, a dielectric layer material with a low CTE is usually selected to reduce the thermal expansion difference between the dielectric layer and the chip (for example, silicon-based chip), the plastic layer and other materials, thereby reducing the stress on the interconnection structure 60. However, low CTE dielectric layer materials are relatively expensive; in addition, low CTE dielectric layer materials only reduce the stress caused by thermal expansion to a certain extent, and cannot completely eliminate it. As the number of dielectric layers increases, the stress caused by thermal expansion will increase. Therefore, for packaging structures with multiple wiring layers and multiple dielectric layers, there is still a risk of deformation or breakage of the interconnect structure 60.

[0031] In view of the above problems, an embodiment of the present application provides a chip packaging structure.

[0032] The chip packaging structure includes a substrate; a chip, which is arranged on one side of the substrate; at least one wiring layer, which is arranged on the side of the chip away from the substrate; at least one dielectric layer, which is arranged between the chip and the wiring layer, and / or between adjacent wiring layers; an interconnection structure, which is located in the dielectric layer, and the interconnection structure connects the chip and the wiring layer adjacent to the chip, and / or connects two adjacent wiring layers; wherein at least one interconnection structure includes a step structure. The interconnection structure is set as a step structure, and under the action of thermal stress, the shape of the interconnection structure can change (for example, from a curve to a straight line, or the curvature of the curve is changed) to offset the thermal stress, avoid the interconnection structure from being stretched or broken, and improve the yield of the chip packaging structure, especially the yield of the chip packaging structure with multiple wiring layers.

[0033] In an embodiment of the present application, the interconnection structure includes at least one step structure. Optionally, the step structure includes at least one of a plane or a curved surface. Along a cross section perpendicular to the substrate, the interconnection structure is step-shaped. Optionally, along multiple cross sections perpendicular to the substrate, the shape of the interconnection structure is the same. Optionally, along a cross section perpendicular to the substrate, the interconnection structure includes at least one of a straight line segment or a curved line segment. Preferably, along a cross section perpendicular to the substrate, the interconnection structure is an S-shaped curve. Figure 2 Schematic cross-sectional views of various interconnect structures are shown. Figure 2 As shown, along the cross section perpendicular to the substrate, the interconnection structure 60 is stepped. Along the cross section perpendicular to the substrate, the interconnection structure 60 includes a plurality of straight segments (e.g., two straight segments, three straight segments, five straight segments, etc.), or a plurality of curved segments (e.g., one curved segment, two curved segments, four curved segments, etc.). Optionally, the interconnection structure is an S-shaped curve. It can be understood that Figure 2 The shape of the interconnection structure in the figure is only an example, and the interconnection structure may also be other shapes.

[0034] Figure 3 Schematic diagram of a chip packaging structure provided by an embodiment of the present application. Figure 3 As shown, the chip packaging structure includes a substrate 10, a chip 20, a wiring layer 40, a dielectric layer 50 and an interconnection structure 60. In this embodiment, a wiring layer 40 and a dielectric layer 50 are provided as an example for description.

[0035] like Figure 3 As shown, the chip 20 is disposed on one side of the substrate 10. The chip 20 includes a plurality of pins 210, each of which is connected to an interconnection structure 60. Figure 3 In the embodiment, the pin 210 includes a first pin 211 and a second pin 212. The first pin 211 is connected to an interconnection structure 60, and the second pin 212 is connected to an interconnection structure 60. It can be understood that the first pin 211 and the second pin 212 are only examples, and the chip 20 may also include other pins 210.

[0036] like Figure 3 As shown, the wiring layer 40 is arranged on the side of the chip 20 away from the substrate 10, the dielectric layer 50 is arranged between the chip 20 and the wiring layer 40, and the interconnection structure 60 is located in the dielectric layer 50. The interconnection structure 60 connects the chip 20 (for example, connects the first pin 211 or the second pin 212 of the chip 20) and the wiring layer 40.

[0037] In the embodiment of the present application, the interconnection structure 60 includes a step structure. Optionally, the interconnection structure 60 includes a first portion 611 and a second portion 612 that are mirror-symmetrical. The first portion 611 includes a first end 6111 and a second end 6112 that are oppositely disposed, the first end 6111 being located on a side of the dielectric layer 50 close to the substrate 10, and the second end 6112 being located on a side of the dielectric layer 50 away from the substrate 10. The first end 6111 is connected to a pin 210 (e.g., a first pin 211 or a second pin 212) of the chip 20, and the second end 6112 is connected to the wiring layer 40. The second part 612 includes a third end 6121 and a fourth end 6122 that are arranged opposite to each other. The third end 6121 is located on the side of the dielectric layer 50 close to the substrate 10, and the fourth end 6122 is located on the side of the dielectric layer 50 away from the substrate 10. The third end 6121 and the first end 6111 are connected to the same pin 210 (for example, the first pin 211 or the second pin 212) of the chip 20, and the fourth end 6122 is suspended, that is, the fourth end 6122 does not need to transmit electrical signals. In the embodiment of the present application, only one end of the interconnection structure 60 (for example, the second end 6112) needs to be connected to the wiring layer 40 to achieve electrical connection. If both ends of the interconnection structure 60 (for example, the second end 6112 and the fourth end 6122) are connected to the wiring layer 40, it is difficult to achieve in terms of process. It can be understood that here only the second end 6112 is connected to the wiring layer 40 and the fourth end 6122 is suspended as an example for explanation. In other embodiments, the fourth end 6122 may be connected to the wiring layer and the second end 6112 may be suspended, and this application does not limit this. The interconnect structure 60 is set to a first part 611 and a second part 612 that are mirror-symmetrical, which can simplify the preparation process. Optionally, the first part 611 and the second part 612 may also be asymmetric, which is not limited in this application. Optionally, the interconnect structure 60 may include only the first part 611 or only the second part 612.

[0038] In an embodiment of the present application, the material of the interconnect structure 60 includes at least one of copper (Cu), aluminum (Al), titanium (Ti), nickel (Ni), gold (Au), and silver (Ag). The material of the wiring layer 40 includes at least one of Cu, Al, Ti, Ni, Au, and Ag. Optionally, the material of the interconnect structure 60 is the same as the material of the wiring layer 40. In this case, the interconnect structure 60 and the wiring layer 40 can be prepared in the same layer. Optionally, in a direction perpendicular to the substrate 10, the thickness of the wiring layer 40 is greater than or equal to 1um and less than or equal to 50um, preferably greater than or equal to 5um and less than or equal to 20um. Exemplarily, the thickness of the wiring layer 40 is 1um, 5um, 10um, 15um, 20um, 30um, 40um, and 50um. Optionally, the thickness of the interconnect structure 60 is greater than or equal to 1um and less than or equal to 50um, preferably greater than or equal to 5um and less than or equal to 20um. Exemplarily, the thickness of the interconnect structure 60 is 1um, 5um, 10um, 15um, 20um, 30um, 40um, 50um. When the interconnect structure 60 and the wiring layer 40 are prepared in the same layer, the thickness of the interconnect structure 60 is the same as the thickness of the wiring layer 40. Optionally, the material of the dielectric layer 50 includes at least one of Ajinomoto Build-up Film (ABF), photosensitive polyimide (PSPI), polyimide (PI), and epoxy resin. Optionally, along the direction perpendicular to the substrate 10, the thickness of the dielectric layer 50 is greater than or equal to 2um and less than or equal to 100um, preferably greater than or equal to 8um and less than or equal to 20um. Exemplarily, the thickness of the dielectric layer 50 is 2um, 5um, 8um, 10um, 15um, 20um, 30um, 40um, 45um, 50um, 55um, 60um, 70um, 80um, 90um, or 100um.

[0039] Continue to refer Figure 3 The chip packaging structure also includes a first film layer 30, which is arranged around the peripheral side of the chip 20, and a dielectric layer 50 is filled between the first film layer 30 and the chip 20. Optionally, the material of the first film layer 30 includes an epoxy molding compound (EMC). EMC has good electrical insulation performance, thermal stability, mechanical strength, etc., and can meet the packaging requirements of the chip 20. In this case, the chip packaging structure is an embedded chip packaging structure. Optionally, other packaging structures can also be used, for example, the chip 20 is directly wrapped by the material of the dielectric layer. Figure 4 It is a schematic diagram of a chip packaging structure provided in yet another embodiment of the present application. Figure 4 The chip packaging structure shown is similar to Figure 3The difference between the chip packaging structure shown is that the chip packaging structure includes a second film layer 31, and the second film layer 31 wraps the chip 20. Optionally, the material of the second film layer 31 is the same as the material of the dielectric layer 50.

[0040] Continue to refer Figure 3 , the chip packaging structure further includes a protective layer 70, which is arranged on the side of the wiring layer 40 away from the substrate 10. The protective layer 70 covers the interconnect structure 60 and at least part of the wiring layer 40. The protective layer 70 has a through hole, and the wiring layer farthest from the substrate 10 covers the part of the through hole exposed by the connection solder ball, that is, the part of the wiring layer 40 not covered by the protective layer 70 is connected to the solder ball (not shown in the figure), so as to realize the electrical connection between the chip 20 and other structures. Optionally, the protective layer 70 is a material with insulation and water and oxygen isolation capabilities. Exemplarily, the material of the protective layer 70 includes at least one of ink, polyimide, photosensitive polyimide, and ajinomoto laminated dielectric film. Optionally, the material of the protective layer 70 is the same as the material of the dielectric layer 50. Optionally, along the direction perpendicular to the substrate 10, the thickness of the protective layer 70 is greater than or equal to 5um and less than or equal to 100um, preferably greater than or equal to 20um and less than or equal to 50um. Exemplarily, the thickness of the protective layer 70 is 5um, 10um, 15um, 20um, 30um, 40um, 50um, 60um, 70um, 80um, 90um, 100um. Optionally, when the chip packaging structure includes a multi-layer wiring layer 40, the protective layer 70 is arranged on the side of the wiring layer 40 farthest from the substrate 10 away from the substrate 10. At this time, the protective layer 70 covers the interconnection structure 60 farthest from the substrate 10 and at least part of the wiring layer 40 farthest from the substrate 10, wherein the part of the wiring layer 40 farthest from the substrate that is not covered by the protective layer 70 is connected to the solder ball.

[0041] In an embodiment of the present application, the interconnection structure 60 includes a step structure. Under the action of thermal stress, the step structure is deformed (for example, stretched from a curve to a straight line, or stretched from a broken line to a straight line, or the curvature of the curve changes) to offset the thermal stress, thereby preventing the interconnection structure from being stretched or broken, thereby improving the yield of the chip packaging structure.

[0042] Typically, the chip packaging structure includes a multi-layer wiring layer 40 and a multi-layer dielectric layer 50. For the dielectric layer 50 in direct contact with the first film layer 30 and the chip 20, due to the friction limitation between the dielectric layer 50 and the first film layer 30, the thermal expansion deformation of the dielectric layer 50 is small and close to the first film layer 30. For the dielectric layer 50 far away from the first film layer 30, since it is not limited by the first film layer 30, the thermal expansion deformation of the dielectric layer 50 is large, thereby generating stress on the interconnection structure 60. Therefore, the embodiment of the present application is also applicable to the case of a multi-layer wiring layer 40 and a multi-layer dielectric layer 50. In addition, if the dielectric layer 50 is thicker, the thermal expansion deformation will also be more obvious, so the embodiment of the present application is also applicable to the case where the dielectric layer 50 is thicker. The present application is described below in conjunction with specific embodiments.

[0043] Figure 5 FIG. 1 is a schematic diagram of a chip packaging structure provided by another exemplary embodiment of the present application. Figure 5 As shown, Figure 5 The chip packaging structure shown is similar to Figure 4 The difference between the chip packaging structure shown is that the wiring layer 40 includes a first wiring layer 410 and a second wiring layer 420 arranged in sequence in a direction away from the substrate 10, and the dielectric layer 50 includes a first dielectric layer 510 and a second dielectric layer 520. The first dielectric layer 510 is located between the first wiring layer 410 and the chip 20, and the second dielectric layer 520 is located between the first wiring layer 410 and the second wiring layer 420. The interconnection structure 60 includes a first interconnection structure 610 and a second interconnection structure 620. The first interconnection structure 610 is located in the first dielectric layer 510 and connects the first wiring layer 410 and the chip 20; the second interconnection structure 620 is located in the second dielectric layer 520 and connects the first wiring layer 410 and the second wiring layer 420. The first interconnection structure 610 and the second interconnection structure 620 include a step structure.

[0044] Optionally, the orthographic projections of the first wiring layer 410 and the second wiring layer 420 on the substrate 10 are staggered. That is, the orthographic projections of the first wiring layer 410 and the second wiring layer 420 on the substrate 10 do not overlap to avoid generating parasitic capacitance.

[0045] Optionally, the thickness of the first dielectric layer 510 and / or the second dielectric layer 520 is greater than or equal to 2um and less than or equal to 100um, preferably greater than or equal to 8um and less than or equal to 20um. Exemplarily, the thickness of the first dielectric layer 510 and / or the second dielectric layer 520 is 2um, 5um, 8um, 10um, 15um, 20um, 30um, 40um, 45um, 50um, 55um, 60um, 70um, 80um, 90um, 100um. When the dielectric layer 50 (for example, the first dielectric layer 510 and / or the second dielectric layer 520) is thicker, the thermal expansion deformation of the dielectric layer 50 will be relatively obvious. In the present application, the interconnection structure 60 (for example, the first interconnection structure 610 and the second interconnection structure 620) is set as a step structure, which can alleviate or eliminate the stress caused by the thermal expansion of the dielectric layer 50 and prevent the interconnection structure 60 from being stretched or broken.

[0046] like Figure 5 As shown, the first interconnect structure 610 and the second interconnect structure 620 both include a step structure. Under the action of thermal stress, the shape of the interconnect structure (for example, the first interconnect structure 610 and / or the second interconnect structure 620) changes, which can offset the thermal stress, avoid the interconnect structure from being stretched or broken, and improve the yield of the chip packaging structure.

[0047] Optionally, the shapes of the first interconnect structure 610 and the second interconnect structure 620 may be the same or different. For example, the first interconnect structure 610 is a curve with a step structure, and the second interconnect structure 620 is a broken line with a step structure. In order to simplify the preparation process, it is preferred that the first interconnect structure 610 and the second interconnect structure 620 have the same shape.

[0048] Optionally, Figure 6 is a schematic diagram of a chip packaging structure provided by yet another exemplary embodiment of the present application. Figure 6 and Figure 5 The difference is that the first interconnection structure 610 is a straight line, and the second interconnection structure 620 includes a step structure. The first interconnection structure 610 connects the chip 20 and the first wiring layer 410. Since the first dielectric layer 510 is in direct contact with the first film layer 30, the first dielectric layer 510 is affected by the friction between the first film layer 30 and the thermal expansion deformation of the first dielectric layer 510 is small. Therefore, the first interconnection structure 610 can be set as a straight line, which can simplify the preparation process of the first interconnection structure 610, save manufacturing time, and improve efficiency.

[0049] In the embodiment of the present application, the first interconnect structure 610 and the second interconnect structure 620 both include a first portion 611 and a second portion 612 that are mirror-symmetrical. For details on the structures of the first portion 611 and the second portion 612, please refer to the present application. Figure 3In the embodiment of the present application, the first interconnect structure 610 and the second interconnect structure 620 are set to be mirror-symmetrical first part 611 and second part 612, which can simplify the preparation process. Optionally, the first interconnect structure 610 and / or the second interconnect structure 620 may include an asymmetric first part and second part. Alternatively, the first interconnect structure 610 and the second interconnect structure 620 include only the first part or only the second part.

[0050] Figure 7 and Figure 8 is a schematic diagram of a chip packaging structure provided by yet another exemplary embodiment of the present application. Figure 7 and Figure 5 The difference is that the first interconnect structure 610 and the second interconnect structure 620 include only the first portion or only the second portion. Figure 8 and Figure 6 The difference is that the second interconnect structure 620 includes only the first portion or only the second portion.

[0051] Fig. 9 is a schematic diagram of a chip packaging structure provided by yet another exemplary embodiment of the present application. Fig. 9 and Figure 6 The difference is that Fig. 9 The wiring layer 40 in the figure also includes a third wiring layer 430. The third wiring layer 430 is located on the side of the second wiring layer 420 away from the substrate 10, and a third dielectric layer 530 is arranged between the third wiring layer 430 and the second wiring layer 420. A third interconnection structure 630 is arranged in the third dielectric layer 530, and the third interconnection structure 630 connects the second wiring layer 420 and the third wiring layer 430. In the embodiment of the present application, the first interconnection structure 610 is a straight line, and the second interconnection structure 620 and the third interconnection structure 630 include a step structure. As the number of layers of the dielectric layer 50 increases, the thermal expansion and deformation of the dielectric layer 50 away from the substrate 10 becomes more and more obvious. Therefore, setting the interconnection structure 60 (especially the second interconnection structure 620 and the third interconnection structure 630) with a step structure can alleviate or eliminate the stress caused by the thermal expansion of the dielectric layer 50 and prevent the interconnection structure 60 from being stretched or broken.

[0052] The embodiments of the present application only list chip packaging structures with two or three wiring layers. It can be understood that, according to actual needs, the chip packaging structure can be provided with multiple wiring layers, for example, four or five layers, etc., as long as at least one interconnect structure includes a step structure. Optionally, the number of wiring layers is related to the size of the chip, for example, the smaller the size of the chip, the more wiring layers there are.

[0053] Fig.10a FIG10 is a schematic diagram of a chip packaging structure provided by another exemplary embodiment of the present application. Figure 6The difference is that the chip packaging structure in FIG. 10 includes two chips 20 , namely a first chip 21 and a second chip 22 , that is, the embodiment of the present application can be applicable to a packaging structure having multiple chips. Fig.10b yes Fig.10a The top view of the chip packaging structure shown in FIG. Fig.10b As shown, the protection layer 70 exposes at least a portion of the wiring layer 40 , and the exposed wiring layer 40 is connected to a solder ball (not shown).

[0054] In a second aspect, an embodiment of the present application provides a method for preparing a chip packaging structure, which is used to prepare the above-mentioned chip packaging structure.

[0055] Fig.11 It is a schematic flow chart of a method for preparing a chip packaging structure provided by an exemplary embodiment of the present application. Figures 12a to 12d Schematic diagram of a method for preparing a chip packaging structure according to an embodiment of the present application. Figure 6 Taking the chip packaging structure shown in the figure as an example, it can be understood that the chip packaging structures in other figures can also be prepared according to this method. Fig.11 As shown, the method includes the following steps.

[0056] S110, fixing the chip on the substrate.

[0057] In the embodiment of the present application, the substrate may be a silicon substrate, a glass plate, a steel plate, a plastic plate, etc. Optionally, a first film layer is formed on the substrate, and the first film layer has a space for accommodating the chip, and the chip is placed in the space and fixed (for example, glued to the substrate). Fig.12a As shown, the first film layer 30 is disposed around the chip 20. In the embodiment of the present application, the thickness of the first film layer 30 is the same as that of the chip 20 to completely accommodate the chip 20. In the embodiment of the present application, the material of the first film layer 30 includes EMC. EMC has good electrical insulation performance, thermal stability, mechanical strength, etc., and can meet the packaging requirements of the chip 20.

[0058] Optionally, the first film layer is omitted, the chip is directly fixed to the substrate, and the chip is wrapped with a dielectric layer in a subsequent step.

[0059] S120, alternately forming at least one dielectric layer, an interconnect structure, and at least one wiring layer on a side of the chip facing away from the substrate.

[0060] In an embodiment of the present application, the interconnection structure is located in the dielectric layer, the interconnection structure connects the chip and the wiring layer adjacent to the chip, and / or connects two adjacent wiring layers, and at least one interconnection structure includes a step structure.

[0061] Optionally, the steps of forming a dielectric layer, an interconnection structure and a wiring layer include: forming a dielectric layer on the side of the chip or the upper wiring layer facing away from the substrate, preparing a via in the dielectric layer, and the side wall of the via includes a step structure; using photoresist, forming an interconnection structure in the via and forming a wiring layer on the side of the dielectric layer facing away from the substrate through electroplating, evaporation or magnetron sputtering process.

[0062] Optionally, a dielectric layer is formed on the side of the chip or the upper wiring layer away from the substrate, and the step of preparing vias in the dielectric layer includes: depositing dielectric material on the side of the chip or the upper wiring layer away from the substrate to obtain a dielectric layer; and forming vias on the dielectric layer by an etching process. Wherein, when the dielectric material is deposited on the side of the upper wiring layer away from the substrate, the dielectric material covers the upper interconnect structure and fills the upper via. Optionally, the etching process includes at least one of half tone mask, multi-step photolithography, laser etching or chemical dry etching.

[0063] The following is an explanation of the preparation of two wiring layers and two dielectric layers as an example. Specifically, a dielectric material is deposited on the side of the chip 20 facing away from the substrate 10 to obtain a first dielectric layer 510. Optionally, the dielectric material fills the gap between the chip 20 and the first film layer 30. In an embodiment of the present application, the material of the first dielectric layer 510 is a material capable of photolithographic patterning, such as ABF, PSPI; or a material not capable of photolithographic patterning, such as PI, epoxy resin, etc. The first dielectric layer 510 is etched to form a first via 511. In an embodiment of the present application, the first via 511 is a straight hole, and the etching process includes at least one of photolithography, laser etching or chemical dry etching.

[0064] In the embodiment of the present application, the first wiring layer 410 and the first interconnection structure 610 are prepared by the same step. The first interconnection structure 610 is formed in the first via hole 511 by electroplating using photoresist, and the first wiring layer 410 is formed on the side of the first dielectric layer 510 away from the substrate 10. Specifically, first, a seed layer is prepared on the side of the first dielectric layer 510 away from the substrate 10 and in the first via hole 511. Methods for preparing the seed layer include but are not limited to physical vapor deposition (PVD), evaporation, etc. The material of the seed layer includes but is not limited to a titanium / copper (Ti / Cu) composite layer, a titanium / gold (Ti / Au) composite layer, etc. Among them, the titanium layer directly contacts the first dielectric layer 510. Since titanium has good adhesion, the first wiring layer 410 and / or the first interconnection structure 610 generated subsequently have good adhesion to the first dielectric layer 510, avoiding the occurrence of falling off, separation, etc. Optionally, the thickness of the seed layer is 0.1 to 0.8 um, preferably 0.3 to 0.5 um, and illustratively, the thickness of the seed layer is 0.1 um, 0.3 um, 0.5 um, 0.6 um, 0.7 um, and 0.8 um. The thickness of the titanium layer is 0.08 to 0.5 um, preferably 0.2 to 0.3 um, and illustratively, the thickness of the titanium layer is 0.08 um, 0.1 um, 0.2 um, 0.3 um, 0.4 um, and 0.5 um. After forming the seed layer, a photoresist is coated on the seed layer, and a patterned photoresist is generated by exposure and development. Then, a metal layer is formed on the seed layer not covered with the photoresist by an electroplating process, and a first wiring layer 410 and a first interconnect structure 610 are generated by removing the photoresist and etching (for example, wet etching, dry etching) processes to obtain the following. Figure 12b The structure shown. In the embodiment of the present application, the first wiring layer 410 and the first interconnect structure 610 are preferably made of the same material. Optionally, the materials of the first wiring layer 410 and the first interconnect structure 610 include, but are not limited to, one or more of Cu, Al, Ti, Ni, Au, and Ag. Since copper has good electrical conductivity and heat transfer properties and is low in cost, the material of the first wiring layer 410 and the first interconnect structure 610 is preferably copper. Optionally, the thickness of the first wiring layer 410 and / or the first interconnect structure 610 is 1 to 50 um, preferably 5 to 20 um. Exemplarily, the thickness of the first wiring layer 410 and / or the first interconnect structure 610 is 1 um, 5 um, 10 um, 15 um, 20 um, 30 um, 40 um, and 50 um.

[0065] Optionally, when preparing the first wiring layer 410 and the first interconnect structure 610, evaporation or magnetron sputtering can also be used. Specifically, a photoresist is coated on the first dielectric layer 510 and in the first via hole 511, and a patterned photoresist is generated by exposure and development. Then, a metal layer is formed on the surface of the first dielectric layer 510 not covered with the photoresist and in the via hole by evaporation or magnetron sputtering, and the photoresist is removed to obtain the first wiring layer 410 and the first interconnect structure 610.

[0066] Optionally, the first wiring layer 410 and the first interconnect structure 610 may be prepared in steps, for example, the first wiring layer 410 is prepared first and then the first interconnect structure 610 is prepared; or the first interconnect structure 610 is prepared first and then the first wiring layer 410 is prepared. In this case, the first wiring layer 410 and the first interconnect structure 610 may be made of different materials. For example, the first wiring layer 410 is copper, and the first interconnect structure 610 is aluminum.

[0067] It can be understood that the number and routing method of the first wiring layer 410 can be set as needed, and the embodiment of the present disclosure does not limit the specific configuration of the first wiring layer 410.

[0068] Then, a second dielectric layer 520 is prepared on the side of the first wiring layer 410 facing away from the substrate 10. Specifically, a dielectric material is deposited on the side of the first wiring layer 410 facing away from the substrate 10 to obtain the second dielectric layer 520, and the dielectric material covers the first interconnect structure 610 and fills the first via hole 511 in the first dielectric layer 510. A second via hole 521 is formed on the second dielectric layer 520 by an etching process, and the second via hole includes a step structure.

[0069] In the embodiment of the present application, the etching process includes at least one of half tone mask, multi-step photolithography, laser etching or chemical dry etching. Optionally, the material of the second dielectric layer 520 includes but is not limited to ABF, PSPI, PI, epoxy resin and other materials. Preferably, the material of the second dielectric layer 520 is the same as the material of the first dielectric layer 510. Optionally, the thickness of the second dielectric layer 520 is the same as the thickness of the first dielectric layer 510.

[0070] If the material of the second dielectric layer 520 is a material capable of photolithographic patterning, such as ABF or PSPI, the etching process may be a half-tone mask or a multi-step photolithography process. According to the shape of the via hole to be formed, the mask of the half-tone mask or the steps of the multi-step photolithography are adjusted to obtain the desired second via hole shape. Both the half-tone mask and the multi-step photolithography are conventional processes in the art and will not be described in detail here.

[0071] If the material of the second dielectric layer 520 is a material that is not capable of photolithographic patterning, such as PI, epoxy resin, etc., the etching process may be laser etching or chemical dry etching. According to the shape of the via hole to be formed, the etching depth of the laser etching or chemical dry etching is adjusted to obtain the desired second via hole shape. Both laser etching and chemical dry etching are conventional processes in the art and will not be described in detail here.

[0072] After forming the second dielectric layer 520 and the second via hole 521, the second interconnect structure 620 located in the second via hole 521 and the second wiring layer 420 located on the side of the second dielectric layer away from the substrate 10 are simultaneously prepared. The method for preparing the second wiring layer 420 and the second interconnect structure 620 is the same as the method for preparing the first wiring layer 410 and the first interconnect structure 610, and will not be repeated here. For example, the second wiring layer 420 and the second interconnect structure 620 can be formed by electroplating, evaporation, magnetron sputtering, etc., to obtain Fig.12c The structure shown.

[0073] In the embodiment of the present application, the second wiring layer 420 and the second interconnect structure 620 are preferably made of the same material. Optionally, the material of the second wiring layer 420 and the second interconnect structure 620 includes, but is not limited to, one or more of Cu, Al, Ti, Ni, Au, and Ag. The material of the second wiring layer 420 and the second interconnect structure 620 is preferably copper. Optionally, the thickness of the second wiring layer 420 and / or the second interconnect structure 620 is the same as the thickness of the first wiring layer 410 and / or the first interconnect structure 610.

[0074] Optionally, the second wiring layer 420 and the second interconnect structure 620 may be prepared in steps, for example, first preparing the second wiring layer 420 and then preparing the second interconnect structure 620; or first preparing the second interconnect structure 620 and then preparing the second wiring layer 420. In this case, the second wiring layer 420 and the second interconnect structure 620 may be made of different materials.

[0075] It can be understood that the number and routing method of the second wiring layers 420 can be set as needed, and the embodiment of the present disclosure does not limit the specific configuration of the second wiring layers 420.

[0076] S130, forming a protection layer on a side of the last wiring layer facing away from the substrate.

[0077] Optionally, an insulating material layer is formed on the side of the last wiring layer facing away from the substrate, the insulating material layer covers the last interconnect structure and fills the vias in the last dielectric layer; the insulating material layer is patterned to obtain a protective layer, and the protective layer exposes part of the last wiring layer.

[0078] like Fig.12dAs shown, an insulating material layer is formed on the side of the second wiring layer 420 facing away from the substrate 10, and the insulating material layer covers the second interconnect structure 620 and fills the second via 521 in the second dielectric layer 520. The insulating material layer is patterned to obtain a protective layer 70, and the protective layer 70 exposes a portion of the second wiring layer 420. The exposed second wiring layer 420 can be electrically connected to the solder ball, thereby realizing electrical connection between the chip 20 and other structures.

[0079] In the embodiment of the present application, the protective layer 70 is a material having the ability to insulate and isolate water and oxygen. For example, the protective layer 70 is ink, PI, PSPI, ABF, etc. Optionally, the material of the protective layer 70 can be the same as the material of the first dielectric layer 510 and / or the second dielectric layer 520.

[0080] Understandably, Figures 12a to 12d Only the method of preparing two wiring layers is shown, and those skilled in the art can prepare one or more wiring layers according to actual needs, for example, three layers, four layers, five layers, etc.

[0081] The basic principles of the present application are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present application are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present application. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, not for limitation, and the above details do not limit the present application to being implemented by adopting the above specific details.

[0082] The block diagrams of the devices, apparatuses, equipment, and systems involved in this application are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagram. As will be appreciated by those skilled in the art, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including", "comprising", "having", etc. are open words, referring to "including but not limited to", and can be used interchangeably with them. The words "or" and "and" used here refer to the words "and / or" and can be used interchangeably with them, unless the context clearly indicates otherwise. The words "such as" used here refer to the phrase "such as but not limited to", and can be used interchangeably with them.

[0083] It should also be noted that in the apparatus, device and method of the present application, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as equivalent solutions of the present application.

[0084] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present application. Therefore, the present application is not intended to be limited to the aspects shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0085] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present application to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. A chip packaging structure, characterized in that: include: substrate; A chip is arranged on one side of the substrate; At least one wiring layer is arranged on a side of the chip away from the substrate; At least one dielectric layer is arranged between the chip and the wiring layer, and / or between adjacent wiring layers; An interconnect structure, located in the dielectric layer, the interconnect structure connecting the chip and the wiring layer adjacent to the chip, and / or connecting two adjacent wiring layers; Wherein, at least one of the interconnect structures comprises a step structure.

2. The chip packaging structure according to claim 1, characterized in that: The interconnect structure includes at least one step structure; Preferably, the step structure includes at least one of a flat surface or a curved surface; Preferably, along a cross section perpendicular to the substrate, the interconnect structure is step-shaped; Preferably, along a plurality of cross sections perpendicular to the substrate, the interconnection structure has the same shape; Preferably, along a cross section perpendicular to the substrate, the interconnect structure comprises at least one of a straight line segment or a curved line segment; Preferably, along a cross section perpendicular to the substrate, the interconnection structure is an S-shaped curve.

3. The chip packaging structure according to claim 1, characterized in that: comprising at least two wiring layers and at least two dielectric layers; Preferably, the wiring layer includes a first wiring layer and a second wiring layer sequentially arranged in a direction away from the substrate, the dielectric layer includes a first dielectric layer and a second dielectric layer, the first dielectric layer is located between the first wiring layer and the chip, and the second dielectric layer is located between the first wiring layer and the second wiring layer; The interconnect structure comprises a first interconnect structure and a second interconnect structure, wherein the first interconnect structure is located in the first dielectric layer and connects the first wiring layer and the chip; the second interconnect structure is located in the second dielectric layer and connects the first wiring layer and the second wiring layer; The second interconnect structure comprises a step structure; Preferably, the first interconnect structure and the second interconnect structure both include a step structure.

4. The chip packaging structure according to any one of claims 1 to 3, characterized in that: The interconnect structure comprises a first part, the first part comprises a first end and a second end which are arranged opposite to each other, the first end is located at a side of the dielectric layer close to the substrate, and the second end is located at a side of the dielectric layer away from the substrate; The chip includes a pin, the first end is connected to the pin, and the second end is connected to the wiring layer adjacent to the chip; or, the first end is connected to one wiring layer, and the second end is connected to another wiring layer adjacent to the wiring layer; Preferably, the interconnection structure further comprises a second part, the second part comprises a third end and a fourth end which are arranged opposite to each other, the third end is located at a side of the dielectric layer close to the substrate, and the fourth end is located at a side of the dielectric layer away from the substrate; The third end and the first end are connected to the same pin of the chip, or the third end and the first end are connected to the same wiring layer; the fourth end is suspended; Preferably, the first portion and the second portion are mirror-symmetrical.

5. The chip packaging structure according to any one of claims 1 to 3, characterized in that: The material of the interconnect structure includes at least one of copper, aluminum, titanium, nickel, gold, and silver; Preferably, the material of the wiring layer includes at least one of copper, aluminum, titanium, nickel, gold, and silver; Preferably, the material of the interconnect structure is the same as that of the wiring layer, and the interconnect structure and the wiring layer are prepared in the same layer; Preferably, along a direction perpendicular to the substrate, the thickness of the wiring layer is greater than or equal to 1 um and less than or equal to 50 um, preferably greater than or equal to 5 um and less than or equal to 20 um; Preferably, the thickness of the interconnect structure is greater than or equal to 1 um and less than or equal to 50 um, preferably greater than or equal to 5 um and less than or equal to 20 um; Preferably, the chip packaging structure comprises at least two wiring layers, and the orthographic projections of the wiring layers of different layers on the substrate are staggered; Preferably, the material of the dielectric layer includes at least one of Ajinomoto laminated dielectric film, photosensitive polyimide, polyimide, and epoxy resin; Preferably, along a direction perpendicular to the substrate, the thickness of the dielectric layer is greater than or equal to 2 um and less than or equal to 100 um, preferably greater than or equal to 8 um and less than or equal to 20 um.

6. The chip packaging structure according to any one of claims 1 to 3, characterized in that: The chip packaging structure further includes a first film layer, the first film layer is arranged around the periphery of the chip, and the dielectric layer is filled between the first film layer and the chip; Preferably, the material of the first film layer comprises epoxy molding compound; Alternatively, the chip packaging structure further includes a second film layer, the second film layer wraps the chip, and the material of the second film layer is the same as that of the dielectric layer; Preferably, the chip comprises a plurality of pins, each of which is connected to one of the interconnect structures.

7. The chip packaging structure according to any one of claims 1 to 3, characterized in that: The chip packaging structure further includes a protective layer, which is arranged on a side of the wiring layer farthest from the substrate and away from the substrate; The protective layer covers the interconnect structure farthest from the substrate and at least a portion of the wiring layer farthest from the substrate; Preferably, the protection layer has a through hole, and a portion of the wiring layer farthest from the substrate that is exposed through the through hole is connected to a solder ball; Preferably, the material of the protective layer includes at least one of ink, polyimide, photosensitive polyimide, and Ajinomoto laminated dielectric film; Preferably, along a direction perpendicular to the substrate, the thickness of the protective layer is greater than or equal to 5 um and less than or equal to 100 um, preferably greater than or equal to 20 um and less than or equal to 50 um.

8. A method for preparing a chip packaging structure, characterized in that: include: Fixing the chip on the substrate; At least one dielectric layer, an interconnect structure and at least one wiring layer are alternately formed in sequence on a side of the chip facing away from the substrate; The interconnect structure is located in the dielectric layer, and the interconnect structure connects the chip and the wiring layer adjacent to the chip, and / or connects two adjacent wiring layers, and at least one of the interconnect structures includes a step structure.

9. The method for preparing a chip packaging structure according to claim 8, characterized in that: In the step of alternately forming at least one dielectric layer, an interconnection structure, and at least one wiring layer on the side of the chip facing away from the substrate, the step of forming a dielectric layer, an interconnection structure, and a wiring layer comprises: Forming the dielectric layer on the side of the chip or the upper wiring layer away from the substrate, preparing a via hole in the dielectric layer, wherein the side wall of the via hole includes the step structure; Using photoresist, forming the interconnection structure in the via hole and forming the wiring layer on the side of the dielectric layer away from the substrate by electroplating, evaporation or magnetron sputtering process; Preferably, a dielectric layer is formed on the side of the chip or the upper wiring layer facing away from the substrate, and the step of preparing vias in the dielectric layer includes: Depositing a dielectric material on the side of the chip or the upper wiring layer away from the substrate to obtain the dielectric layer, wherein when the dielectric material is deposited on the side of the upper wiring layer away from the substrate, the dielectric material covers the upper interconnect structure and fills the vias in the upper dielectric layer; forming the via hole on the dielectric layer by an etching process; Preferably, the etching process includes at least one of half-tone mask, multi-step photolithography, laser etching or chemical dry etching.

10. The method for preparing a chip packaging structure according to claim 9, characterized in that: Also includes: Forming a protective layer on the side of the last wiring layer away from the substrate; Preferably, forming a protective layer on the side of the last wiring layer away from the substrate comprises: forming an insulating material layer on the side of the last wiring layer away from the substrate, wherein the insulating material layer covers the last interconnect structure and fills the vias in the last dielectric layer; The insulating material layer is patterned to obtain the protective layer, and the protective layer exposes a portion of the last wiring layer.

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