Preparation method of light-emitting chip

Abstract

The invention relates to a light-emitting chip preparation method, which comprises the following steps that a first electrode layer and an epitaxial layer are prepared on a driving backboard, and the first electrode layer is electrically connected between the driving backboard and the epitaxial layer; etching the epitaxial layer to form a plurality of epitaxial structures arranged at intervals; preparing a mask layer on the surface, deviating from the driving backboard, of each epitaxial structure; wherein the mask layer comprises a protective layer and photoresist; patterning the first electrode layer by adopting a dry etching technology so as to expose the driving back plate between the epitaxial structures; wherein the photoresist is used for protecting the epitaxial structure, and the protective layer is melted during dry etching and flows along the side wall of the epitaxial structure to cover the side wall; and removing the mask layer and preparing a second electrode layer on each epitaxial structure. According to the preparation method of the light-emitting chip, the light-emitting efficiency and the light-emitting effect of the light-emitting chip can be improved, and the yield of the prepared light-emitting chip can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a method for preparing a light-emitting chip. Background Art

[0002] The metals of the two electrodes of the light-emitting chip are usually made of metals with good conductivity, such as platinum (Pt), gold (Au), titanium (Ti), etc. Since these metals have strong passivation and high etching difficulty, and the light-emitting chip is usually micron-sized, dry etching technology is generally used to etch the electrode layer to prepare the electrodes of the light-emitting chip.

[0003] In the process of etching the electrode layer using dry etching technology, high-energy ions physically bombard the electrode layer, causing metal particles in the electrode layer to sputter onto the side walls of the epitaxial structure. The metal sputtered onto the side walls may cause the current to be unable to pass through the quantum well layer in the epitaxial structure or cause the light-emitting chip to short-circuit, thereby reducing the luminous efficiency and luminous effect of the light-emitting chip and reducing the yield rate of the light-emitting chip. Summary of the invention

[0004] In view of the above-mentioned deficiencies in the prior art, the purpose of the present application is to provide a method for preparing a light-emitting chip that can improve the yield rate of light-emitting chip preparation.

[0005] The present application provides a method for preparing a light-emitting chip, comprising the following steps:

[0006] A first electrode layer and an epitaxial layer are prepared on the driving backplane, wherein the first electrode layer is electrically connected between the driving backplane and the epitaxial layer;

[0007] Etching the epitaxial layer to form a plurality of epitaxial structures arranged at intervals;

[0008] A mask layer is prepared on the surface of each epitaxial structure away from the driving backplane; wherein the mask layer includes a protective layer and a photoresist;

[0009] The first electrode layer is patterned by dry etching technology to expose the driving backplane between the epitaxial structures; wherein the photoresist is used to protect the epitaxial structure, and the protective layer melts during dry etching and flows along the sidewalls of the epitaxial structure to cover the sidewalls;

[0010] The mask layer is removed and a second electrode layer is formed on each epitaxial structure.

[0011] The light-emitting chip preparation method of the present application can bond the epitaxial layer to the driving backplane by setting a first electrode layer between the driving backplane and the epitaxial layer to realize the electrical connection between the driving backplane and the epitaxial layer, thereby realizing the light-emitting function of the light-emitting chip prepared by the light-emitting chip preparation method. At the same time, by bonding the epitaxial layer to the driving backplane, it is possible to transmit signals to each light-emitting chip to control the light emission of each light-emitting chip, thereby ensuring that the light-emitting effect of each light-emitting chip meets the display requirements. By preparing the first electrode layer and the second electrode layer on opposite sides of the epitaxial structure in a direction perpendicular to the plane of the driving backplane, the first electrode layer and the second electrode layer can work together to pass current into the epitaxial structure to turn on the epitaxial structure and emit light outward. The light-emitting chip with a vertical structure has good antistatic ability and good heat dissipation ability. By preparing the first electrode layer and the second electrode layer on opposite sides of the epitaxial structure in a direction perpendicular to the plane of the driving backplane, the light-emitting chip prepared by the light-emitting chip preparation method of the present application is a vertical structure to improve the working performance of the manufactured light-emitting chip.

[0012] The light-emitting chip preparation method of the present application prepares a mask layer on the surface of each epitaxial structure away from the driving backplane, and uses a dry etching technique to pattern the first electrode layer to remove the first electrode layer between the epitaxial structures and expose the driving backplane between the epitaxial structures, thereby forming a plurality of independent light-emitting chips bonded to the driving backplane. At the same time, by etching the first electrode layer between the epitaxial structures to form a plurality of independent light-emitting chips, each light-emitting chip forms an effect of being directly bonded to the driving backplane, thereby simplifying the preparation process of the vertical structure light-emitting chip and improving the preparation efficiency of the vertical structure light-emitting chip. By preparing a photoresist on the side of each epitaxial structure away from the driving backplane, the epitaxial structure can be protected in the subsequent preparation process to avoid damage to the epitaxial structure in the subsequent etching process and affect the working performance and working efficiency of the epitaxial structure.

[0013] In the process of patterning the first electrode layer using dry etching technology, the dissociated high-energy ions physically bombard the mask layer, causing the temperature of the mask layer to rise, thereby causing the protective layer to melt and flow to cover the side walls of the epitaxial structure, so as to protect the side walls of the epitaxial structure, and avoid metal particles from sputtering onto the epitaxial structure during the etching of the first electrode layer, causing the current to be unable to pass through the quantum well layer in the epitaxial structure or the light-emitting chip to short-circuit, so as to improve the yield rate of the light-emitting chip made by the light-emitting chip preparation method of the present application, and ensure the light-emitting efficiency and light-emitting effect of the light-emitting chip. At the same time, by using the energy generated in the dry etching process to heat the protective layer synchronously while etching the first electrode layer and causing the protective layer to melt and cover the side walls of the epitaxial structure, the preparation process of the light-emitting chip preparation method of the present application can be further simplified, and the preparation efficiency of the light-emitting chip preparation method of the present application can be further simplified.

[0014] In one embodiment, the protection layer is located between the epitaxial structure and the photoresist.

[0015] In this embodiment, a protective layer is arranged between the epitaxial structure and the photoresist, that is, the photoresist is covered on the side of the protective layer facing away from the driving backplane, so that the photoresist is located in the outermost layer to ensure that the photoresist can protect the epitaxial structure while also protecting the protective layer, and can improve the etching accuracy and etching effect in the subsequent dry etching process of the first electrode layer.

[0016] In one embodiment, the melting point of the protective layer is between 70°C and 120°C.

[0017] In this embodiment, by setting the melting point temperature of the protective layer between 70°C and 120°C, the energy generated during the dry etching process can reach the melting point temperature of the protective layer, thereby ensuring the melting effect and efficiency of the protective layer, and avoiding the phenomenon that the protective layer cannot be melted due to the melting point temperature being too high. At the same time, by controlling the melting point temperature of the protective layer between 70°C and 120°C, the shaping effect of the protective layer can be ensured, and the phenomenon that the protective layer may melt prematurely due to the excessively high ambient temperature before etching the first electrode layer can be avoided.

[0018] In one embodiment, the material of the protection layer is polyimide (PI) or polymethyl methacrylate (PMMA).

[0019] In this embodiment, the film layer made of polyimide or polymethyl methacrylate has good thermal sensitivity and fluidity. By setting the material of the protective layer to polyimide or polymethyl methacrylate, the thermal sensitivity of the protective layer can be improved, thereby improving the flow effect and flow efficiency of the protective layer on the side wall of the epitaxial structure.

[0020] In one embodiment, the epitaxial structure has a top surface and a bottom surface facing each other, the top surface is located on a side of the epitaxial structure facing away from the driving backplane, and a projection of the top surface on the driving backplane is contained within the bottom surface.

[0021] In this embodiment, the projection of the top surface on the driving backplane is arranged to be accommodated in the bottom surface, so that the side walls of the epitaxial structure are perpendicular to the plane of the driving backplane or inclined relative to the plane of the driving backplane, that is, the cross-section of the epitaxial structure forms a "regular trapezoid" or "rectangular" shape, which can further improve the flow effect of the protective layer on the side walls of the epitaxial structure, and further improve the covering effect and covering efficiency of the protective layer.

[0022] In one embodiment, the protective layer melts and flows along the sidewall of the epitaxial structure during dry etching, comprising:

[0023] The protection layer continuously covers the sidewall along the circumference of the epitaxial structure.

[0024] In this embodiment, a protective layer is provided to continuously cover the side walls along the circumference of the epitaxial structure, so that the protective layer can continuously cover and protect the side walls along the circumference of the epitaxial structure, thereby ensuring and improving the coverage rate and coverage effect of the protective layer on the epitaxial structure, so as to further improve the yield rate of the light-emitting chip prepared by the light-emitting chip preparation method of the present application.

[0025] In one embodiment, the protective layer melts and flows along the sidewall of the epitaxial structure during dry etching, comprising:

[0026] The protection layer at least completely covers the sidewalls of the epitaxial structure.

[0027] In this embodiment, by setting a protective layer to at least completely cover the side walls of the epitaxial structure, the coverage effect and coverage rate of the protective layer on the epitaxial structure can be guaranteed, so as to further improve the protective effect of the protective layer on the epitaxial structure, thereby improving the yield rate of the light-emitting chip prepared by the light-emitting chip preparation method of the present application.

[0028] In one embodiment, a mask layer is prepared on a surface of each epitaxial structure facing away from the driving backplane, including:

[0029] A pre-mask layer is prepared on the surface of each epitaxial structure away from the driving backplane by a spin coating method;

[0030] The pre-mask layer is patterned by using exposure and development technology to expose the first electrode layer between the epitaxial structures. The pre-mask layer forms a mask layer on the surface of each epitaxial structure away from the driving backplane.

[0031] In this embodiment, a mask layer is prepared on the surface of each epitaxial structure away from the driving backplane by adopting a rotary coating method. This can improve the uniformity of each protective layer in the planar direction of the driving backplane, thereby improving the uniformity of the protective layer flowing from various positions on the side wall of the epitaxial structure in the circumferential direction, thereby improving the coverage effect and coverage uniformity of the protective layer, and avoiding the occurrence of uneven coverage that affects the protective effect of the protective layer on the side wall of the epitaxial structure.

[0032] In one embodiment, the mask layer is removed and a second electrode layer is prepared on each epitaxial structure, including:

[0033] Using an organic degumming solution to remove the mask layer;

[0034] A second electrode layer is prepared on each epitaxial structure.

[0035] In this embodiment, by using an organic degumming solution to remove the mask layer, the mask layer can be removed to facilitate subsequent process preparation, and at the same time, the metal particles sputtered onto the protective layer can be removed to obtain an epitaxial structure with good performance, thereby improving the working performance and work efficiency of the epitaxial structure.

[0036] In one embodiment, before preparing the second electrode layer on each epitaxial structure, the method comprises:

[0037] A passivation layer is prepared on each epitaxial structure, wherein the passivation layer covers the epitaxial structure and the first electrode layer;

[0038] A through hole is formed on the surface of the passivation layer away from the driving back plate, and the through hole penetrates to the epitaxial structure;

[0039] Then, a second electrode layer is prepared on each epitaxial structure, including:

[0040] A second electrode layer is prepared on the surface of the passivation layer facing away from the driving back plate. The second electrode layer extends into the through hole and is electrically connected to the epitaxial structure.

[0041] In this embodiment, by preparing a passivation layer on each epitaxial structure, it is possible to protect each epitaxial structure, the first electrode layer and other layer structures, thereby preventing harmful impurities from contaminating or oxidizing each layer structure in the light-emitting chip, thereby ensuring the normal working performance and working effect of the light-emitting chip. By opening a through hole in the passivation layer, it is convenient to prepare the second electrode layer later, and the second electrode layer can be electrically connected to the epitaxial structure, thereby achieving the effect of conducting the epitaxial structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A schematic diagram of a working scenario of a light-emitting chip prepared by the light-emitting chip preparation method of the present application;

[0043] Figure 2 for Figure 1 A schematic diagram of the cross-sectional structure of the light emitting chip at the AA position in the illustrated embodiment;

[0044] Figure 3 A schematic diagram of the workflow of the light-emitting chip preparation method of the present application;

[0045] Figure 4 A schematic diagram of the structure when bonding the epitaxial layer on the driving backplane from a side perspective;

[0046] Figure 5 for Figure 4 A schematic structural diagram from a side perspective when preparing multiple epitaxial structures in the embodiment shown;

[0047] Figure 6 A schematic diagram of a workflow for preparing a mask layer on the surface of each epitaxial structure facing away from the driving backplane;

[0048] Figure 7 A schematic diagram of the structure from one side when a pre-mask layer is prepared on the surface of each epitaxial structure facing away from the substrate;

[0049] Figure 8 A schematic diagram of a structure from a side perspective when a mask layer is formed on a surface of each epitaxial structure facing away from the substrate;

[0050] Fig. 9 A schematic diagram of the structure from one side when the first electrode layer is patterned using dry etching technology;

[0051] Fig.10 for Fig. 9 A schematic structural diagram from a side perspective when the protective layer flows to the second side wall of the first electrode layer in the illustrated embodiment;

[0052] Fig.11 A schematic diagram of the structure from one side when the first electrode layer to the driving layer is etched by dry etching method;

[0053] Fig.12 A schematic diagram of the workflow for removing the mask layer and preparing a second electrode layer on each epitaxial structure;

[0054] Fig.13 for Fig.12 A schematic structural diagram of a side viewing angle when the mask layer is removed in the embodiment shown;

[0055] Fig.14 A schematic diagram of a workflow for preparing a second electrode layer on each epitaxial structure;

[0056] Fig.15 A schematic diagram of the structure from one side when preparing a passivation layer on each epitaxial structure;

[0057] Fig.16 This is a schematic structural diagram from a side perspective when preparing a through hole on the surface of the passivation layer facing away from the substrate.

[0058] Reference numerals:

[0059] 10-light-emitting chip; 101-substrate; 102-driving layer; 103-driving backplane; 11-first electrode layer; 111-second side wall; 112-etching surface; 12-second electrode layer; 13-epitaxial structure; 131-top surface; 132-side wall; 133-bottom surface; 13a-epitaxial layer; 14-passivation layer; 141-through hole; 20-mask layer; 20a-pre-mask layer; 21a-pre-protective layer; 21-protective layer; 22a-pre-photoresist; 22-photoresist; S-gap. DETAILED DESCRIPTION

[0060] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thoroughly and comprehensively understood.

[0061] The following descriptions of the embodiments are with reference to the attached diagrams to illustrate specific embodiments that the present application can be used to implement. The serial numbers for the components herein, such as "first", "second", etc., are only used to distinguish the objects described and do not have any order or technical meaning. The "connection" and "coupling" mentioned in the present application, unless otherwise specified, include direct and indirect connections (couplings). The directional terms mentioned in the present application, such as "upper", "lower", "front", "back", "left", "right", "inside", "outside", "side", etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for better and clearer explanation and understanding of the present application, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present application.

[0062] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be fixedly connected, detachably connected, or integrally connected; it can be mechanically connected; it can be directly connected, or indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances. It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including", "may include", "include", or "may include" used in this application indicate the existence of the corresponding functions, operations, elements, etc. disclosed, and do not limit one or more other functions, operations, elements, etc. In addition, the terms "including" or "include" indicate the existence of the corresponding features, numbers, steps, operations, elements, components, or combinations thereof disclosed in the specification, and do not exclude the existence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, and are intended to cover non-exclusive inclusions.

[0063] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0064] Please also read Figure 1 and Figure 2 , Figure 1 Schematic diagram of the working scene of the light-emitting chip 10 prepared by the light-emitting chip preparation method of the present application, Figure 2 for Figure 1 The cross-sectional structure diagram of the light emitting chip 10 at the AA position in the embodiment shown. Figure 1 and Figure 2 As shown, multiple light-emitting chips 10 are mounted on a driving backplane 103. The driving backplane 103 includes a substrate 101 and a driving layer 102. The driving layer 102 is stacked on one side of the substrate 101. The driving layer 102 is located between the light-emitting chip 10 and the substrate 101, and is electrically connected to each light-emitting chip 10, so as to control the light emission of the multiple light-emitting chips 10.

[0065] The plurality of light emitting chips 10 are arranged at intervals on a surface of the driving layer 102 facing away from the substrate 101 .

[0066] The light emitting chip 10 is used to emit light outward, and the color of the light emitted by each light emitting chip 10 may be different. The color of the light emitted by each light emitting chip 10 may be, but is not limited to, any one of red, green, blue, and yellow.

[0067] The driving layer 102 is used to drive and control the light emission of each light emitting chip 10, that is, the driving layer 102 can transmit signals to each light emitting chip 10 to control the light emission of each light emitting chip 10, so as to ensure that the light emitting effect of each light emitting chip 10 meets the display requirements. For example, the driving layer 102 can be, but is not limited to, a structure such as a transmission wire arranged on the substrate 101.

[0068] It should be noted that other structures or components for driving and controlling the light emitting chip 10 to emit light may be further provided on the driving backplane 103 , so as to meet different design requirements of the light emitting chip 10 .

[0069] For example, in a possible embodiment, the driving backplane 103 may also be provided with a driving chip (not shown in the figure) and multiple driving circuits (not shown in the figure) and other structures. The driving chip is connected to each light-emitting chip 10 through each driving circuit, and the driving chip can also provide a driving signal to each light-emitting chip 10 to achieve the effect of controlling the light emission of each light-emitting chip 10, thereby meeting different light-emitting requirements.

[0070] It should be noted that in Figure 1In the illustrated embodiment, only one possible arrangement and quantity of the light emitting chips 10 is exemplified, but the quantity and arrangement of the plurality of light emitting chips 10 are not limited to this. In other embodiments of the present application, the arrangement and quantity of the plurality of light emitting chips 10 can be adjusted according to actual design requirements, and the embodiments of the present application do not specifically limit this.

[0071] At the same time, it should be noted that Figure 1 In the illustrated embodiment, only one possible structural size and structural shape of the driving layer 102 and the light emitting chip 10 is exemplarily introduced, but the actual structural shape and actual structural size of the driving layer 102 and the light emitting chip 10 are not limited thereto.

[0072] like Figure 2 As shown, the substrate 101 is used to provide support and bearing for the functional structures or components such as the light emitting chip 10 and the driving layer 102. That is, various electronic devices or structures for realizing the functions of the light emitting chip 10 can be arranged on the substrate 101, so that the substrate 101 has the effect of bearing and fixing the various electronic devices or structures of the light emitting chip 10.

[0073] The substrate 101 may be made of, but is not limited to, silicon (Si), germanium (Ge), or copper (Cu).

[0074] In the embodiment, the material of the substrate 101 may include, but is not limited to, any one of silicon (Si), germanium (Ge), and copper (Cu). Since silicon, germanium, and copper have the characteristics of high thermal conductivity, by setting the material of the substrate 101 to include at least one of silicon, germanium, and copper, the heat dissipation efficiency and heat dissipation effect of the substrate 101 can be improved, thereby improving the working performance and working life of the light-emitting chip 10.

[0075] and, Figure 2 Only one structural shape and size of the substrate 101, such as area, thickness, etc., is used for exemplary description, and the specific structural shape or size of the substrate 101 is not limited to this. That is, the structural shape and size of the substrate 101 can be adjusted according to actual needs.

[0076] Furthermore, the light emitting chip 10 may be, but not limited to, a light emitting chip such as LED, mini-LED, or Micro-LED. Meanwhile, the structure of the light emitting chip 10 may be, but not limited to, a vertical structure, a flip-chip structure, a face-up structure, or the like.

[0077] The embodiment of the present application is described by taking the example that each light-emitting chip 10 is a vertical structure chip.

[0078] exist Figure 2In the illustrated embodiment, each light emitting chip 10 is a vertical structure chip, that is, the two electrode layers of each light emitting chip 10 are respectively located on two opposite sides of the epitaxial structure.

[0079] Specifically, the light emitting chip 10 includes a first electrode layer 11, an epitaxial structure 13 and a second electrode layer 12. The epitaxial structure 13 is stacked between the first electrode layer 11 and the second electrode layer 12 in a direction perpendicular to the plane of the substrate 101, and the first electrode layer 11 and the second electrode layer 12 are both electrically connected to the epitaxial structure 13.

[0080] The epitaxial structure 13 is electrically connected between the first electrode layer 11 and the second electrode layer 12 so that the first electrode layer 11 and the second electrode layer 12 can work together to pass current into the epitaxial structure 13 to turn on the epitaxial structure 13 and emit light outward.

[0081] At the same time, the epitaxial structure 13 is stacked between the first electrode layer 11 and the second electrode layer 12, so that the light-emitting chip 10 forms a vertical structure chip, thereby improving the antistatic ability and heat dissipation ability of the light-emitting chip 10, thereby ensuring the working performance and working efficiency of the light-emitting chip 10.

[0082] The polarities of the first electrode layer 11 and the second electrode layer 12 are opposite. That is, when the first electrode layer 11 in the epitaxial structure 13 is an N-type electrode layer, the second electrode layer 12 is a P-type electrode layer. At this time, the first electrode layer 11 can transmit electrons to the multi-quantum well layer in the epitaxial structure 13, and the second electrode layer 12 can transmit holes to the multi-quantum well layer in the epitaxial structure 13. The electrons and holes are recombined in the multi-quantum well layer to form photons and emit light, so as to form the effect that the epitaxial structure 13 emits light outward.

[0083] Alternatively, when the first electrode layer 11 in the epitaxial structure 13 is a P-type electrode layer, the second electrode layer 12 is an N-type electrode layer. At this time, the first electrode layer 11 transmits holes to the multi-quantum well layer, and the second electrode layer 12 transmits electrons to the multi-quantum well layer. The electrons and holes are recombined in the multi-quantum well layer to form photons and emit light, so as to form the effect that the epitaxial structure 13 emits light outward.

[0084] It should be noted that in Figure 2 In the illustrated embodiment, the light emitting chip 10 is exemplarily described by taking the first electrode layer 11 of the epitaxial structure 13 as an N-type electrode layer and the second electrode layer 12 as a P-type electrode layer as an example, but it is not limited to the first electrode layer 11 being only an N-type electrode layer and the second electrode layer 12 being only a P-type electrode layer.

[0085] At the same time, Figure 2In the illustrated embodiment, only a possible structural layout position and connection position between the epitaxial structure 13, the first electrode layer 11 and the second electrode layer 12 in the light-emitting chip 10 are taken as an example to illustrate the position of each functional layer structure in the light-emitting chip 10, and the position of each functional layer structure in the light-emitting chip 10 is not limited to this, and it can be adjusted according to actual needs.

[0086] For an embodiment, please refer to Figure 2 .exist Figure 2 In the illustrated embodiment, the light emitting chip 10 further includes a passivation layer 14, which covers the epitaxial structure 13 and the first electrode layer 11. A through hole 141 is provided on the surface of the passivation layer 14 facing away from the driving backplane 103, that is, a through hole 141 is provided on the surface of the passivation layer 14 facing away from the substrate 101. The through hole 141 penetrates the epitaxial structure 13.

[0087] Specifically, Figure 2 As shown, the passivation layer 14 covers the top surface 131, side wall 132 of the epitaxial structure 13, and the second side wall 111 of the first electrode layer 11, and is connected to the surface of the driving layer 102 away from the substrate 101. Among them, at least part of the top surface 131 of the epitaxial structure 13 is exposed to the outside from the through hole 141.

[0088] The second electrode layer 12 is disposed on a surface of the passivation layer 14 facing away from the substrate 101 , and the second electrode layer 12 extends into the through hole 141 and is electrically connected to the epitaxial structure 13 .

[0089] It can be understood that by providing the passivation layer 14, the various epitaxial structures 13, the first electrode layer 11 and other layer structures can be protected to prevent harmful impurities from contaminating or oxidizing the various layer structures in the light-emitting chip 10, thereby ensuring the normal working performance and working effect of the light-emitting chip 10. By opening the through hole 141 on the passivation layer 14, it is convenient to prepare the second electrode layer 12 later, and the second electrode layer 12 can be electrically connected to the epitaxial structure 13, so as to achieve the effect of conducting the epitaxial structure 13.

[0090] See also Figure 3 , Figure 3 Schematic diagram of the process of preparing a light-emitting chip of the present application. The light-emitting chip preparation method of the present application is used to prepare the light-emitting chip 10 described in any of the above embodiments. Figure 3 In the embodiment shown, the method for preparing the light-emitting chip of the present application includes the following steps:

[0091] S100, preparing a first electrode layer 11 and an epitaxial layer 13a on the driving backplane 103, wherein the first electrode layer 11 is electrically connected between the driving backplane 103 and the epitaxial layer 13a;

[0092] For details, please refer to Figure 4 , Figure 4 It is a structural schematic diagram from a side perspective when the epitaxial layer 13a is bonded on the driving backplane 103. In step S100 "preparing the first electrode layer 11 and the epitaxial layer 13a on the driving backplane 103", the epitaxial layer 13a can be first grown on the growth substrate, and the driving layer 102 and the first electrode layer 11 can be prepared on the substrate 101 by metal evaporation or other process technologies, but not limited to, and then the epitaxial layer 13a is transferred from the growth substrate, and the epitaxial layer 13a is bonded to the first electrode layer 11, and the growth substrate is removed.

[0093] It can be understood that transferring the epitaxial layer 13 a and bonding it to the first electrode layer 11 can form an effect of bonding the epitaxial layer 13 a to the driving backplane 103 , so as to facilitate the subsequent process of preparing the light-emitting chip 10 .

[0094] like Figure 4 As shown, a driving layer 102, a first electrode layer 11 and an epitaxial layer 13a are prepared on a surface of one side of a substrate 101, and the driving layer 102, the first electrode layer 11 and the epitaxial layer 13a are stacked in sequence. That is, the driving layer 102 is stacked between the substrate 101 and the first electrode layer 11, and the epitaxial layer 13a is stacked on the side of the first electrode layer 11 away from the substrate 101.

[0095] S200, etching the epitaxial layer 13a to form a plurality of epitaxial structures 13 arranged at intervals;

[0096] See also Figure 5 , Figure 5 for Figure 4 The schematic diagram of the structure when preparing multiple epitaxial structures 13 in the embodiment shown is a side view. Figure 5 As shown, the epitaxial layer 13 a may be etched by, but is not limited to, dry etching or wet etching to form a plurality of epitaxial structures 13 arranged at intervals on a side of the first electrode layer 11 away from the substrate 101 .

[0097] In other words, the plurality of epitaxial structures 13 are arranged at intervals on a side of the first electrode layer 11 facing away from the substrate 101 , and each of the epitaxial structures 13 is electrically connected to the first electrode layer 11 .

[0098] It should be noted that in Figure 5 In the illustrated embodiment, only two epitaxial structures 13 are formed on the surface of the first electrode layer 11 away from the substrate 101 as an example for illustrative description, but the embodiment of the present application is not limited to only being able to form two epitaxial structures 13 after etching the epitaxial layer 13a. The number, size, shape and other features of the epitaxial structures 13 formed after etching the epitaxial layer 13a can be changed according to actual design requirements, and the present application does not make specific limitations on this.

[0099] S300, preparing a mask layer 20 on the surface of each epitaxial structure 13 away from the driving backplane 103; wherein the mask layer 20 includes a protective layer 21 and a photoresist 22;

[0100] See also Figure 6 , Figure 6 A schematic diagram of the process of preparing a mask layer 20 on the surface of each epitaxial structure 13 away from the driving back plate 103. Figure 6 In the illustrated embodiment, step S300 of “preparing a mask layer 20 on a surface of each epitaxial structure 13 facing away from the driving back plate 103 ” includes:

[0101] S301, using a spin coating method to prepare a pre-mask layer 20a on the surface of each epitaxial structure 13 away from the driving backplane 103;

[0102] See also Figure 7 , Figure 7 1 is a schematic structural diagram of a side view when a pre-mask layer 20a is prepared on the surface of each epitaxial structure 13 facing away from the substrate 101. Figure 7 As shown, the pre-mask layer 20 a may be prepared on the surface of the epitaxial structure 13 facing away from the substrate 101 by a spin coating method.

[0103] The pre-mask layer 20a includes a pre-protection layer 21a and a pre-photoresist 22a.

[0104] exist Figure 7 In the embodiment shown, the pre-protection layer 21a is stacked between the epitaxial structure 13 and the pre-photoresist 22a. Specifically, the pre-protection layer 21a and the pre-photoresist 22a can be sequentially coated on the surface of each epitaxial structure 13 away from the substrate 101 by a spin coating method.

[0105] In other words, a pre-protective layer 21a can be first coated on the surface of each epitaxial structure 13 facing away from the substrate 101, and then a pre-photoresist 22a can be coated on the surface of the pre-protective layer 21a facing away from the substrate 101, so as to form the effect of the pre-protective layer 21a and the pre-photoresist 22a on the surface of each epitaxial structure 13 facing away from the substrate 101 in sequence.

[0106] It can be understood that by adopting a spin coating method to prepare a pre-mask layer 20a on the surface of each epitaxial structure 13 away from the substrate 101, a plurality of mask layers 20 can be formed eventually, so as to improve the uniformity of each protective layer 21 along the planar direction of the substrate 101, thereby improving the uniformity of the protective layer 21 flowing from various positions around the epitaxial structure 13 on the side wall 132, thereby improving the coverage effect and coverage uniformity of the protective layer 21, and avoiding the occurrence of uneven coverage that affects the protective effect of the protective layer 21 on the side wall of the epitaxial structure 13.

[0107] It should be noted that in Figure 7 In the embodiment shown, only the spin coating method is used to prepare the pre-mask layer 20a as an example for illustrative description, but it is not limited to the present application that only the spin coating method can be used to prepare the pre-mask layer 20a. In other embodiments of the present application, other possible methods or process means can also be used to prepare the pre-mask layer 20a, and the present application does not make specific limitations on this.

[0108] S302 , patterning the pre-mask layer 20 a by using exposure and development technology to expose the first electrode layer 11 between the epitaxial structures 13 . The pre-mask layer 20 a forms a mask layer 20 on the surface of each epitaxial structure 13 away from the driving backplane 103 .

[0109] See also Figure 8 , Figure 8 It is a structural schematic diagram from a side perspective when a mask layer 20 is formed on the surface of each epitaxial structure 13 facing away from the substrate 101. Figure 8 In the illustrated embodiment, the pre-mask layer 20 a may be patterned by using an exposure and development technique to expose the first electrode layer 11 between the epitaxial structures 13 . The pre-mask layer 20 a forms a mask layer 20 on the surface of each epitaxial structure 13 facing away from the substrate 101 .

[0110] Specifically, Figure 8 As shown, each epitaxial structure 13 has a top surface 131 and a bottom surface 133 facing each other, and the top surface 131 is located on the side of the epitaxial structure 13 facing away from the driving backplane 103. The pre-mask layer 20a can be exposed and developed to form a mask layer 20 on the top surface 131 of each epitaxial structure 13, that is, each mask layer 20 covers the top surface 131 of one epitaxial structure 13.

[0111] It is understandable that by preparing photoresist 22 on the side of each epitaxial structure 13 facing away from the substrate 101, the epitaxial structure 13 can be protected in the subsequent preparation process to avoid damage to the epitaxial structure 13 in the subsequent etching process and affect the working performance and working efficiency of the epitaxial structure 13.

[0112] For an embodiment, please refer to Figure 8 .like Figure 8 As shown, the protection layer 21 is located between the epitaxial structure 13 and the photoresist 22 .

[0113] By setting the protective layer 21 between the epitaxial structure 13 and the photoresist 22, that is, covering the side of the protective layer 21 away from the substrate 101, the photoresist 22 is located in the outermost layer to ensure that the photoresist 22 can protect the epitaxial structure 13 while at the same time protecting the protective layer 21, and can improve the etching accuracy and etching effect in the subsequent dry etching process of the first electrode layer 11.

[0114] In one embodiment, the melting point of the protective layer 21 is between 70° C. and 120° C.

[0115] In this embodiment, the melting point temperature of the protective layer 21 is set between 70°C and 120°C, so that the energy generated in the subsequent dry etching process can reach the melting point temperature of the protective layer 21, thereby ensuring the melting effect and efficiency of the protective layer 21 and avoiding the phenomenon that the melting point temperature of the protective layer 21 is too high and cannot be melted.

[0116] At the same time, by controlling the melting point of the protective layer 21 to be between 70° C. and 120° C., the shaping effect of the protective layer 21 can be ensured, thereby preventing the protective layer 21 from melting prematurely due to excessively high ambient temperature before etching the first electrode layer 11 .

[0117] In one embodiment, the material of the protection layer 21 is polyimide (PI) or polymethyl methacrylate (PMMA).

[0118] The film layer made of polyimide or polymethyl methacrylate has good thermal sensitivity and fluidity. By setting the material of the protective layer 21 to polyimide or polymethyl methacrylate, the thermal sensitivity of the protective layer 21 can be guaranteed, thereby ensuring the flow effect and flow efficiency of the protective layer 21 on the side wall 132 of the epitaxial structure 13.

[0119] S400, patterning the first electrode layer 11 by dry etching technology to expose the driving backplane 103 between the epitaxial structures 13; wherein the photoresist 22 is used to protect the epitaxial structure 13, and the protective layer 21 melts during dry etching and flows along the sidewalls 132 of the epitaxial structure 13 to cover the sidewalls 132;

[0120] See also Fig. 9 , Fig. 9 The schematic diagram of the structure from a side perspective when the first electrode layer 11 is patterned by dry etching technology. In step S400 "patterning the first electrode layer 11 by dry etching technology to expose the driving backplane 103 between the epitaxial structures 13", the first electrode layer 11 is etched by dry etching technology, so that the preparation of the light-emitting chip 10 of micron size can be achieved.

[0121] A mask layer 20 is prepared on the surface of each epitaxial structure 13 facing away from the substrate 101, and the first electrode layer 11 is patterned using a dry etching technique to remove the first electrode layer 11 between the epitaxial structures 13 and expose the driving backplane 103 between the epitaxial structures 13, thereby forming a plurality of independent light-emitting chips 10 bonded to the driving backplane 103.

[0122] At the same time, by etching the first electrode layer 11 between the epitaxial structures 13 to form a plurality of independent light-emitting chips 10, each light-emitting chip 10 is directly bonded to the driving backplane 103, thereby simplifying the preparation process of the vertical structure light-emitting chip 10 and improving the preparation efficiency of the vertical structure light-emitting chip 10.

[0123] Furthermore, in the process of patterning the first electrode layer 11 by dry etching technology, the dissociated high-energy ions physically bombard the mask layer 20 to increase the temperature of the mask layer 20 , thereby causing the protective layer 21 to melt and flow to cover the sidewalls 132 of the epitaxial structure 13 .

[0124] During the dry etching process of the first electrode layer 11 , the energy generated by the physical bombardment of the mask layer 20 by the dissociated high-energy ions is relatively large, so the temperature of the protective layer 21 rises rapidly, that is, the temperature of the protective layer 21 reaches its own melting point at a relatively fast speed to melt.

[0125] However, the dry etching technology has a slow etching speed when etching the first electrode layer 11. Therefore, in a possible embodiment, Fig. 9 As shown, the protective layer 21 melts and flows along the side wall 132 of the epitaxial structure 13 to the side of the bottom surface 133 of the epitaxial structure 13, so as to protect the side wall of the epitaxial structure and avoid metal particles from being sputtered onto the epitaxial structure 13 during the etching process of the first electrode layer 11, resulting in the undesirable phenomenon that the current cannot pass through the quantum well layer in the epitaxial structure 13 or the light-emitting chip 10 is short-circuited, so as to improve the yield rate of the light-emitting chip 10 manufactured by the light-emitting chip preparation method of the present application and ensure the light-emitting efficiency and light-emitting effect of the light-emitting chip 10.

[0126] For an embodiment, please refer to Fig. 9 .like Fig. 9 As shown, step S400 “the protective layer 21 melts during dry etching and flows along the sidewall 132 of the epitaxial structure 13 ” includes:

[0127] The protection layer 21 continuously covers the sidewall 132 along the circumference of the epitaxial structure 13 .

[0128] In the present embodiment, the protective layer 21 is provided to continuously cover the side wall 132 along the circumference of the epitaxial structure 13, so that the protective layer 21 can continuously cover and protect the side wall 132 along the circumference of the epitaxial structure 13, thereby ensuring and improving the coverage rate and coverage effect of the protective layer 21 on the epitaxial structure 13, so as to further improve the yield rate of the light-emitting chip 10 prepared by the light-emitting chip preparation method of the present application.

[0129] For an embodiment, please refer to Fig. 9 .like Fig. 9As shown, step S400 “the protective layer 21 melts during dry etching and flows along the sidewall 132 of the epitaxial structure 13 ” includes:

[0130] The protection layer 21 at least completely covers the sidewalls 132 of the epitaxial structure 13 .

[0131] In this embodiment, by setting the protective layer 21 to at least completely cover the side wall 132 of the epitaxial structure 13, the coverage effect and coverage rate of the protective layer 21 on the epitaxial structure 13 can be guaranteed, so as to further improve the protective effect of the protective layer 21 on the epitaxial structure 13, thereby improving the yield rate of the light-emitting chip 10 prepared by the light-emitting chip preparation method of the present application.

[0132] For an embodiment, please refer to Fig. 9 .like Fig. 9 As shown, the projection of the top surface 131 of the epitaxial structure 13 on the driving back plate 103 is contained within the bottom surface 133 , that is, the projection of the top surface 131 on the driving layer 102 is contained within the bottom surface 133 .

[0133] Specifically, in Fig. 9 In the illustrated embodiment, along the planar direction of the substrate 101, the area of ​​the top surface 131 is smaller than the area of ​​the bottom surface 133, thereby forming an effect in which the projection of the top surface 131 on the driving layer 102 is contained within the bottom surface 133, so that the side wall 132 of the epitaxial structure 13 is formed perpendicular to the plane of the substrate 101 or inclined relative to the plane of the substrate 101.

[0134] That is, the cross section of the epitaxial structure 13 is formed into a “regular trapezoid” shape, which can further improve the flow effect of the protective layer 21 on the sidewall 132 of the epitaxial structure 13 and further improve the coverage effect and coverage efficiency of the protective layer 21 .

[0135] It should be noted that in Fig. 9 In the illustrated embodiment, only a possible embodiment in which the projection of the top surface 131 on the driving layer 102 is contained within the bottom surface 133 is taken as an example for illustrative introduction, but the relative sizes of the top surface 131 and the bottom surface 133 are not limited to this. In other embodiments of the present application, the relative sizes of the top surface 131 and the bottom surface 133 can be adjusted according to actual design requirements, and the present application does not make specific limitations on this.

[0136] For example, in one possible embodiment, along the planar direction of the substrate 101, the area of ​​the top surface 131 may also be equal to the area of ​​the bottom surface 133, so as to form an effect in which the side wall 132 of the epitaxial structure 13 is perpendicular to the substrate 101, that is, the cross-section of the epitaxial structure 13 forms a "rectangular" shape, so as to further improve the flow effect and flow rate of the protective layer 21 on the side wall 132.

[0137] For an example, see Fig.10 , Fig.10 for Fig. 9 The structure diagram of the protective layer 21 flowing to the second side wall 111 of the first electrode layer 11 in the embodiment shown is a side view. Fig.10 As shown, step S400 “the protective layer 21 melts during dry etching and flows along the sidewall 132 of the epitaxial structure 13 ” includes:

[0138] After the protective layer 21 completely covers the side wall 132 of the epitaxial structure 13 , the protective layer 21 continues to flow along the second side wall 111 of the first electrode layer 11 toward the substrate 101 , and a gap S is left between the side of the protective layer 21 close to the substrate 101 and the etched surface 112 of the first electrode layer 11 .

[0139] It can be understood that in this embodiment, after the protective layer 21 completely covers the side wall 132 of the epitaxial structure 13, the protective layer 21 continues to flow along the second side wall 111. At this time, a gap S is left between the side of the protective layer 21 close to the substrate 101 and the etched surface 112 of the first electrode layer 11, and the value of S is greater than 0, so as to prevent the protective layer 21 from flowing too fast and affecting the etching effect and etching efficiency of the first electrode layer 11.

[0140] For further information, see Fig.11 , Fig.11 1 is a schematic diagram of the structure from one side when the first electrode layer 11 to the driving layer 102 is etched by dry etching. Fig.11 As shown, when the first electrode layer 11 to the driving layer 102 are etched by dry etching, the driving layer 102 between the epitaxial structures 13 is exposed, so that a plurality of independent light-emitting chips 10 bonded to the driving layer 102 can be formed.

[0141] During the dry etching of the first electrode layer 11 , the protective layer 21 completely covers the sidewalls 132 of the epitaxial structure 13 , thereby avoiding the undesirable phenomenon of metal particles sputtering onto the epitaxial structure 13 during the etching of the first electrode layer 11 , thereby obtaining an epitaxial structure 13 with good performance.

[0142] S500 , removing the mask layer 20 and forming a second electrode layer 12 on each epitaxial structure 13 .

[0143] See also Fig.12 , Fig.12 A schematic diagram of a process for removing the mask layer 20 and preparing a second electrode layer 12 on each epitaxial structure 13. Fig.12 As shown, step S500 of “removing the mask layer 20 and preparing a second electrode layer 12 on each epitaxial structure 13” includes:

[0144] S501, removing the mask layer 20 using an organic degumming solution;

[0145] See also Fig.13 , Fig.13 for Fig.12 The structure diagram of the embodiment shown is a side view of removing the mask layer 20. Fig.13 In the illustrated embodiment, an organic stripping solution may be used to remove the protective layer 21 and the photoresist 22 , and while cleaning and removing the mask layer 20 , metal particles sputtered onto the protective layer 21 may be removed.

[0146] In other words, the protective layer 21 and the photoresist 22 in the mask layer 20 are both adhesive layers, and the mask layer 20 can be removed by an organic degumming solution. While removing the mask layer 20 to facilitate subsequent process preparation, the metal particles sputtered onto the protective layer 21 can be simultaneously removed to obtain an epitaxial structure 13 with good performance, thereby improving the working performance and working efficiency of the epitaxial structure 13.

[0147] S502 , preparing a second electrode layer 12 on each epitaxial structure 13 .

[0148] See also Fig.14 , Fig.14 FIG. 1 is a schematic diagram of a process for preparing a second electrode layer 12 on each epitaxial structure 13. Fig.14 As shown, step S502 of "preparing a second electrode layer 12 on each epitaxial structure 13" includes:

[0149] S5021, preparing a passivation layer 14 on each epitaxial structure 13, wherein the passivation layer 14 covers the epitaxial structure 13 and the first electrode layer 11;

[0150] See also Fig.15 , Fig.15 This is a schematic diagram of the structure when the passivation layer 14 is prepared on each epitaxial structure 13 from a side perspective. Fig.15 As shown, the passivation layer 14 covers the surface of each epitaxial structure 13 facing away from the substrate 101 and covers the second side wall 111 of the first electrode layer 11 to form a plurality of independent light-emitting chips 10 .

[0151] in, Fig.15 The passivation layer 14 in the illustrated embodiment may be Figure 2 The technical effects and structural features of the passivation layer 14 in the illustrated embodiment are the same and will not be described in detail here. Fig.15 The structural features and technical effects of the passivation layer 14 in the illustrated embodiment.

[0152] S5022, preparing a through hole 141 on the surface of the passivation layer 14 away from the driving back plate 103, wherein the through hole 141 penetrates to the epitaxial structure 13;

[0153] See also Fig.16 , Fig.16 This is a schematic diagram of the structure when preparing the through hole 141 on the surface of the passivation layer 14 facing away from the substrate 101 from a side perspective. Fig.16 In the illustrated embodiment, the through hole 141 may be formed on the surface of the passivation layer 14 facing away from the substrate 101 by etching or the like.

[0154] Specifically, each through hole 141 penetrates the passivation layer 14 in a direction perpendicular to the plane of the substrate 101, so that at least a portion of the top surface 131 of the epitaxial structure 13 corresponding to each through hole 141 is exposed, which facilitates the subsequent preparation of the second electrode layer 12 and enables the second electrode layer 12 to be electrically connected to the epitaxial structure 13.

[0155] in, Fig.16 The through hole 141 in the illustrated embodiment can be connected to Figure 2 The technical effects and structural features of the through hole 141 in the illustrated embodiment are the same and will not be described in detail here. Fig.16 The structural features and technical effects of the through hole 141 in the illustrated embodiment.

[0156] S5023 , preparing a second electrode layer 12 on the surface of the passivation layer 14 facing away from the driving backplane 103 , wherein the second electrode layer 12 extends into the through hole 141 and is electrically connected to the epitaxial structure 13 .

[0157] For details, please refer to Figure 2 .like Figure 2 As shown, a second electrode layer 12 is prepared on the surface of the passivation layer 14 facing away from the substrate 101 , and the second electrode layer 12 extends into the through hole 141 and is electrically connected to the epitaxial structure 13 , thereby completing the preparation of the light-emitting chip 10 .

[0158] Typically, in the process of etching the electrode layer using dry etching technology, high-energy ions physically bombard the electrode layer, causing metal particles in the electrode layer to sputter onto the side walls of the epitaxial structure. The metal sputtered onto the side walls may cause the current to be unable to pass through the quantum well layer in the epitaxial structure or cause the light-emitting chip to short-circuit.

[0159] The method for preparing the light-emitting chip of the present application prepares a mask layer 20 on the surface of each epitaxial structure 13 away from the driving backplane 103, and uses a dry etching technique to pattern the first electrode layer 11 to remove the first electrode layer 11 between the epitaxial structures 13 and expose the driving backplane 103 between the epitaxial structures 13, thereby being able to form a plurality of independent light-emitting chips 10 bonded to the driving backplane 103.

[0160] At the same time, by etching the first electrode layer 11 between the epitaxial structures 13 to form a plurality of independent light-emitting chips 10, each light-emitting chip 10 is directly bonded to the driving backplane 103, thereby simplifying the preparation process of the vertical structure light-emitting chip 10 and improving the preparation efficiency of the vertical structure light-emitting chip 10.

[0161] By preparing photoresist 22 on the side of each epitaxial structure 13 facing away from the substrate 101 , the epitaxial structure 13 can be protected in subsequent preparation steps to avoid damage to the epitaxial structure 13 in subsequent etching processes, thereby preventing the working performance and working efficiency of the epitaxial structure 13 from being affected.

[0162] In the process of patterning the first electrode layer 11 by dry etching technology, the dissociated high-energy ions physically bombard the mask layer 20, causing the temperature of the mask layer 20 to increase, thereby causing the protective layer 21 to melt and flow to cover the side walls 132 of the epitaxial structure 13, so as to protect the side walls 132 of the epitaxial structure 13, and avoid metal particles from sputtering onto the epitaxial structure 13 during the etching of the first electrode layer 11, resulting in the undesirable phenomenon that the current cannot pass through the quantum well layer in the epitaxial structure 13 or the light-emitting chip 10 is short-circuited, so as to improve the yield rate of the light-emitting chip 10 manufactured by the light-emitting chip preparation method of the present application, and ensure the light-emitting efficiency and light-emitting effect of the light-emitting chip 10.

[0163] At the same time, by using the energy generated in the dry etching process to synchronously heat the protective layer 21 and melt the protective layer 21 to cover the side wall 132 of the epitaxial structure 13 while etching the first electrode layer 11, the preparation process of the light-emitting chip preparation method of the present application can be further simplified, and the preparation efficiency of the light-emitting chip preparation method of the present application can be further simplified.

[0164] It should be understood that the terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0165] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples" or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0166] It should be understood that the application of this application is not limited to the above examples. For ordinary technicians in this field, they can make improvements or changes based on the above description, and all these improvements and changes should fall within the scope of protection of the claims attached to this application. Ordinary technicians in this field can understand that all or part of the processes of the above embodiments are implemented, and equivalent changes made according to the claims of this application still fall within the scope covered by this application.

Claims

1. A method for preparing a light-emitting chip, characterized in that: The steps include: Preparing a first electrode layer and an epitaxial layer on the driving backplane, wherein the first electrode layer is electrically connected between the driving backplane and the epitaxial layer; Etching the epitaxial layer to form a plurality of epitaxial structures arranged at intervals; A mask layer is prepared on the surface of each epitaxial structure away from the driving backplane; wherein the mask layer comprises a protective layer and a photoresist; The first electrode layer is patterned by dry etching technology to expose the driving backplane between the epitaxial structures; wherein the photoresist is used to protect the epitaxial structure, and the protective layer melts during dry etching and flows along the sidewalls of the epitaxial structure to cover the sidewalls; The mask layer is removed and a second electrode layer is prepared on each of the epitaxial structures.

2. The method for preparing a light-emitting chip according to claim 1, characterized in that: The protection layer is located between the epitaxial structure and the photoresist.

3. The method for preparing a light-emitting chip according to claim 1, characterized in that: The melting point of the protective layer is between 70°C and 120°C.

4. The method for preparing a light-emitting chip according to claim 3, characterized in that: The material of the protective layer is polyimide or polymethyl methacrylate.

5. The method for preparing a light-emitting chip according to claim 1, characterized in that: The epitaxial structure has a top surface and a bottom surface facing each other. The top surface is located on a side of the epitaxial structure facing away from the driving backplane, and a projection of the top surface on the driving backplane is contained within the bottom surface.

6. The method for preparing a light-emitting chip according to any one of claims 1 to 5, characterized in that: The protective layer melts during dry etching and flows along the sidewall of the epitaxial structure, comprising: The protection layer continuously covers the side wall along the circumference of the epitaxial structure.

7. The method for preparing a light-emitting chip according to claim 6, characterized in that: The protective layer melts during dry etching and flows along the sidewall of the epitaxial structure, comprising: The protection layer at least completely covers the sidewalls of the epitaxial structure.

8. The method for preparing a light-emitting chip according to any one of claims 1 to 5, characterized in that: The step of preparing a mask layer on a surface of each epitaxial structure away from the driving backplane comprises: Using a spin coating method to prepare a pre-mask layer on the surface of each epitaxial structure away from the driving backplane; The pre-mask layer is patterned by using an exposure and development technology to expose the first electrode layer between the epitaxial structures. The pre-mask layer forms the mask layer on the surface of each epitaxial structure away from the driving backplane.

9. The method for preparing a light-emitting chip according to any one of claims 1 to 5, characterized in that: The step of removing the mask layer and preparing a second electrode layer on each of the epitaxial structures comprises: Using an organic degumming solution to remove the mask layer; The second electrode layer is prepared on each of the epitaxial structures respectively.

10. The method for preparing a light-emitting chip according to claim 9, characterized in that: Before the second electrode layer is prepared on each of the epitaxial structures, the method includes: Preparing a passivation layer on each of the epitaxial structures, wherein the passivation layer covers the epitaxial structure and the first electrode layer; A through hole is formed on a surface of the passivation layer away from the driving backplane, wherein the through hole penetrates the epitaxial structure; Then, the second electrode layer is prepared on each of the epitaxial structures, including: The second electrode layer is prepared on the surface of the passivation layer facing away from the driving backplane, and the second electrode layer extends into the through hole and is electrically connected to the epitaxial structure.

Images