Semiconductor structure, forming method thereof and memory system

Abstract

The invention provides a semiconductor structure, a forming method thereof and a memory system, and the forming method comprises the steps: providing a substrate, and forming a plurality of sacrificial structures in the substrate; the bottom surface of the sacrificial structure is higher than the bottom surface of the substrate; forming a stack structure on the substrate, and forming a plurality of channel holes which penetrate through the stack structure along a first direction and extend into the sacrificial structure; at least two channel holes are formed in each sacrificial structure; the first direction is the stacking direction of the stacking structure; the extension direction of the sacrificial structure intersects with the first direction; removing the plurality of sacrificial structures so as to form a plurality of cavities in the substrate; and forming a channel structure in the channel hole, and forming an initial connection structure connected with the channel structure in the cavity.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same, and a memory system. Background Art

[0002] In order to meet the demand for memory integration, a three-dimensional semiconductor structure including a stacked structure and a channel structure penetrating the stacked structure has been proposed. In the process of forming the three-dimensional semiconductor structure, it is necessary to first form a channel hole (CH) penetrating the stacked structure, and then form a channel structure in the channel hole.

[0003] However, as the integration of memory is further improved, the aspect ratio of the channel hole increases, resulting in the increasing difficulty of the etching process. The depths of the multiple channel holes extending through the stacked structure into the substrate are different, resulting in poor uniformity of the channel structure and increasing the difficulty of the back-side lead-out process of the channel structure. In addition, when a channel structure is formed in a channel hole with a large aspect ratio, the step coverage of the film layer in the channel structure is low, which will have a negative impact on the performance of the memory cell. Summary of the invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor structure and a method for forming the same, and a memory system to solve at least one problem existing in the prior art.

[0005] To achieve the above objectives, the technical solution of the embodiment of the present disclosure is implemented as follows:

[0006] In a first aspect, an embodiment of the present disclosure provides a method for forming a semiconductor structure, comprising:

[0007] Providing a substrate, and forming a plurality of sacrificial structures in the substrate; the bottom surface of the sacrificial structures is higher than the bottom surface of the substrate;

[0008] A stacking structure is formed on the substrate, and a plurality of channel holes are formed along a first direction that penetrate the stacking structure and extend into the sacrificial structure; at least two channel holes are formed on each of the sacrificial structures; the first direction is the stacking direction of the stacking structure; the extending direction of the sacrificial structure intersects with the first direction;

[0009] removing the plurality of sacrificial structures to form a plurality of cavities in the substrate;

[0010] A channel structure is formed in the channel hole, and an initial connection structure connected to the channel structure is formed in the cavity.

[0011] In an optional embodiment, the forming of a channel structure in the channel hole and the forming of an initial connection structure connected to the channel structure in the cavity include:

[0012] A functional layer and a channel layer are sequentially formed along the sidewalls of the channel hole and the inner wall of the cavity to form the channel structure and the initial connection structure.

[0013] In an optional embodiment, a semiconductor layer is formed between the stacked structure and the substrate, and the semiconductor layer includes a semiconductor material; the initial connection structure includes a first portion in contact with the semiconductor layer and a second portion away from the semiconductor layer, and the first portion and the second portion both include the functional layer and the channel layer; and the formation method further includes:

[0014] removing the substrate and the second portion from a side of the substrate away from the stacked structure, and exposing the semiconductor layer and the channel layer of the first portion, with the remaining initial connection structure constituting a connection structure;

[0015] An active layer covering the semiconductor layer and the connection structure is formed, wherein the channel layer in the channel structure is connected to the active layer through the connection structure; the active layer comprises a doped semiconductor material.

[0016] In an optional embodiment, the forming of a plurality of channel holes penetrating the stacked structure along the first direction and extending into the sacrificial structure includes:

[0017] Under preset etching process conditions, the stacked structure and the sacrificial structure are etched along the first direction and stopped at the sacrificial structure to form the channel hole; under the preset etching process conditions, the etching rate of the sacrificial structure is less than the etching rate of the substrate.

[0018] In an optional embodiment, the material of the sacrificial structure includes carbon.

[0019] In an optional embodiment, each of the sacrificial structures extends along the second direction, and the multiple sacrificial structures are arranged along a third direction, and the second direction intersects with the third direction and is perpendicular to the first direction.

[0020] In an optional implementation, a size of the sacrificial structure in a fourth direction perpendicular to the second direction ranges from 80 nm to 120 nm.

[0021] In an optional implementation, the sizes of the multiple sacrificial structures in the first direction are the same and are all smaller than 500 nm.

[0022] In an optional embodiment, the forming method further comprises:

[0023] forming a first bonding layer on the stacked structure;

[0024] Providing a peripheral circuit wafer, the peripheral circuit wafer comprising a peripheral circuit and a second bonding layer located on the peripheral circuit;

[0025] The first bonding layer and the second bonding layer are bonded.

[0026] In a second aspect, an embodiment of the present disclosure provides a semiconductor structure, including:

[0027] A stacked structure and an active layer located on one side of the stacked structure;

[0028] A plurality of channel structures penetrating the stack structure along a first direction; the first direction is a stacking direction of the stack structure;

[0029] A plurality of connection structures are located between the active layer and the stacked structure; each of the connection structures is connected to at least two of the channel structures; and an extension direction of the connection structure intersects with the first direction.

[0030] In an optional embodiment, the channel structure and the connection structure both include a channel layer; the channel layer of the channel structure is connected to the channel layer of the connection structure; and the channel layer in the channel structure is connected to the active layer through the connection structure.

[0031] In an optional embodiment, the channel structure and the connection structure both include a functional layer located between the channel layer and the stacking structure; and the functional layer of the channel structure is connected to the functional layer of the connection structure.

[0032] In an optional implementation, the semiconductor structure further includes:

[0033] A semiconductor layer is located between the connection structure and the stack structure; the semiconductor layer is in contact with a side of the connection structure away from the active layer.

[0034] In an optional embodiment, the semiconductor layer includes a semiconductor material, and the active layer includes a doped semiconductor material.

[0035] In an optional embodiment, each of the connection structures extends along the second direction, and the multiple connection structures are arranged along a third direction; the second direction intersects with the third direction and is perpendicular to the first direction.

[0036] In an optional embodiment, a size of the connection structure in a fourth direction perpendicular to the second direction ranges from 30 nm to 70 nm.

[0037] In an optional implementation, the semiconductor structure further includes:

[0038] a first bonding layer located on the other side of the two opposite sides of the stacked structure in the first direction;

[0039] a second bonding layer located on a side of the first bonding layer away from the stacking structure;

[0040] The peripheral circuit is located on a side of the second bonding layer away from the first bonding layer.

[0041] In a third aspect, an embodiment of the present disclosure provides a memory system, including:

[0042] At least one semiconductor structure according to any one of the above embodiments;

[0043] The controller is coupled to the semiconductor structure and configured to control the semiconductor structure.

[0044] In the technical solution provided by the present disclosure, a plurality of sacrificial structures are formed in the substrate and at least two channel holes are formed on each sacrificial structure, and then the sacrificial structure is removed to form a cavity connected to the channel hole, and a channel structure and an initial connection structure are formed in the channel hole and the cavity, respectively. On the one hand, the bottom of the channel hole stops inside the sacrificial structure, and after the sacrificial structure is removed to form the cavity, an initial connection structure will be formed in the cavity, and a channel structure will be formed in the channel hole located on the cavity, so that the bottom of each channel structure is flush, which is conducive to improving the uniformity of the channel structure; on the other hand, since at least two channel holes are formed on each sacrificial structure, in the process of forming the channel structure, the reaction gas can diffuse to the bottom of the channel hole along the plurality of channel holes connected to the same cavity, so that the concentration of the reaction gas at the bottom of the channel hole can be increased, and then the step coverage of each film layer in the channel structure can be increased; on the other hand, a connection structure that connects the channel structure to the active layer is further formed by the initial connection structure, and there is a large contact surface between the connection structure and the active layer, which can reduce the contact resistance and improve the reliability of the channel structure lead-out. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 A schematic diagram of a process for forming a semiconductor structure provided by an embodiment of the present disclosure;

[0046] Figures 2 to 25 A schematic diagram of a semiconductor structure forming process provided by an embodiment of the present disclosure;

[0047] Fig.26A schematic diagram of a memory provided by an embodiment of the present disclosure;

[0048] Fig. 27 A schematic diagram of a memory system provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0049] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0050] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0051] In the drawings, like reference numerals refer to like elements throughout.

[0052] It should be understood that spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial description terms used herein are interpreted accordingly.

[0053] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0054] In the related art, multiple channel holes penetrating the stacked structure are formed by an etching process, and multiple channel holes are filled to form a channel structure. However, as the integration of the memory increases, the aspect ratio of the channel hole increases accordingly, and the difficulty of controlling the etching process continues to increase. The depths of the multiple channel holes extending into the substrate that penetrate the stacked structure are different, and the critical dimensions (Critical Dimension, CD) at the bottom of the multiple channel holes are also difficult to maintain uniformity, which leads to poor uniformity of the channel structure formed in the channel hole and increases the difficulty of the process of back-leading the channel structure. Here, the critical dimension at the bottom of the channel hole refers to the radial dimension at the bottom of the channel hole.

[0055] In addition, when a channel structure is formed in a channel hole with a large depth-to-width ratio through a deposition process, the concentration of the reaction gas is lower in the channel hole closer to the substrate, resulting in a lower step coverage of the film layer in the channel structure, that is, the film layer thickness is smaller at a position closer to the substrate, which in turn has a negative impact on the performance of the memory cell. For example, when the thickness of the tunnel oxide layer in the channel structure cannot meet the design requirements of the memory cell, it will affect the data retention capability of the memory cell and may cause the threshold voltage of the memory cell to drift, thereby causing data reading and writing errors and reducing the reliability of the memory cell.

[0056] Therefore, how to improve the uniformity of the channel structure and the step coverage of each film layer in the channel structure has become a problem that needs to be solved urgently. In this regard, the present disclosure proposes the following implementation methods.

[0057] The present invention provides a method for forming a semiconductor structure. Figure 1 Schematic diagram of a process for forming a semiconductor structure provided by an embodiment of the present disclosure. Figure 1 As shown, the method for forming a semiconductor structure includes the following steps:

[0058] Step S10: providing a substrate, and forming a plurality of sacrificial structures in the substrate; the bottom surface of the sacrificial structures is higher than the bottom surface of the substrate;

[0059] Step S20: forming a stacked structure on the substrate, and forming a plurality of channel holes penetrating the stacked structure along a first direction and extending into the sacrificial structure; at least two channel holes are formed on each of the sacrificial structures; the first direction is the stacking direction of the stacked structure; the extending direction of the sacrificial structure intersects with the first direction;

[0060] Step S30: removing the plurality of sacrificial structures to form a plurality of cavities in the substrate;

[0061] Step S40: forming a channel structure in the channel hole, and forming an initial connection structure connected to the channel structure in the cavity.

[0062] Figures 2 to 25 The structure diagram of the semiconductor structure forming process provided by the embodiment of the present disclosure is as follows. Figures 1 to 25 The method for forming the semiconductor structure provided by the embodiment of the present disclosure is described in detail.

[0063] Combined with reference Figures 2 to 4 , perform step S10 to provide a substrate 100 and form a plurality of sacrificial structures 106 in the substrate 100 ; the bottom surface of the sacrificial structures 106 is higher than the bottom surface of the substrate 100 .

[0064] In some embodiments, Figure 2 As shown, the substrate 100 includes a semiconductor substrate 101 and an initial oxide layer 102 formed on the surface of the semiconductor substrate 101 .

[0065] In some specific examples, the semiconductor substrate 101 can be a single semiconductor material substrate (for example, a silicon substrate, a germanium substrate, etc.), a compound semiconductor material substrate (for example, a germanium silicon substrate, etc.), or a silicon on insulator (SOI) substrate, a germanium on insulator (GeOI) substrate, etc.

[0066] In some specific examples, the initial oxide layer 102 may be formed on the surface of the semiconductor substrate 101 by a wet oxidation process.

[0067] In some embodiments, the specific process of forming a plurality of sacrificial structures 106 in the substrate 100 may be: Figure 2 , a mask layer 103 and a patterned photoresist layer 104 are formed on the substrate 100; Figure 3 , etching the mask layer 103 using the patterned photoresist layer 104 as a mask to form a patterned mask layer, and etching the substrate 100 using the patterned mask layer as a mask to form a trench 105 in the substrate 100; Figure 4 , a sacrificial material is filled in the trench 105 to form a sacrificial structure 106 .

[0068] In some embodiments, when the sacrificial material is filled in the groove 105, the formed sacrificial material layer will also cover the remaining mask layer 103. The first planarization treatment can be performed on the side of the sacrificial material layer away from the substrate 100, and the layer stops on the remaining mask layer 103 so that the top surface of the remaining sacrificial material layer is flush with the top surface of the remaining mask layer 103. Then, the remaining mask layer 103 is removed, and the second planarization treatment is performed on the side of the sacrificial material layer away from the substrate 100, and the layer stops on the initial oxide layer 102 to form a sacrificial structure 106, and the top surface of the sacrificial structure 106 is flush with the top surface of the initial oxide layer 102.

[0069] In the embodiment of the present disclosure, the mask layer 103 may be a composite mask layer composed of multiple mask layers, and the material of the mask layer 103 includes but is not limited to silicon oxynitride, amorphous carbon and silicon nitride.

[0070] In some specific examples, the material of the sacrificial structure 106 includes, but is not limited to, carbon.

[0071] In the embodiment of the present disclosure, the extending direction of the sacrificial structure 106 intersects with the first direction. Here, the first direction is the thickness direction of the substrate 100.

[0072] In some specific examples, a plurality of sacrificial structures 106 are formed in the substrate 100 , each sacrificial structure 106 extends along the second direction, and the plurality of sacrificial structures 106 are arranged along a third direction, the second direction intersects the third direction, and are both perpendicular to the first direction.

[0073] In a specific example, Figure 5 FIG. 1 is a top view of a semiconductor structure after a sacrificial structure 106 is formed in the substrate 100. Figure 5 As shown, each sacrificial structure 106 extends along the X direction, and a plurality of sacrificial structures 106 are arranged along the Y direction. Here, the second direction is the X direction, and the third direction is the Y direction.

[0074] In another specific example, Figure 6 FIG. 1 is a top view of a semiconductor structure after a sacrificial structure 106 is formed in the substrate 100. Figure 6 As shown, each sacrificial structure 106 extends along the Y direction, and a plurality of sacrificial structures 106 are arranged along the X direction. Here, the second direction is the Y direction, and the third direction is the X direction.

[0075] In yet another specific example, Figure 7 FIG. 1 is a top view of a semiconductor structure after a sacrificial structure 106 is formed in the substrate 100. Figure 7 As shown, a plurality of sacrificial structures 106 are arranged along the X direction, and the extending direction of the sacrificial structures 106 is not perpendicular to the X direction. Here, the third direction is the X direction, and the second direction intersects the third direction.

[0076] It should be noted that the embodiment of the present disclosure only imposes specific restrictions on the first direction, that is, the first direction is the thickness direction of the substrate, which is also the Z direction in the figure, and does not impose restrictions on the second direction and the third direction, that is, does not impose specific restrictions on the extension direction and arrangement direction of the sacrificial structure 106. In addition, Figures 5 to 7 The number of sacrificial structures 106 is only an example, and the embodiment of the present disclosure does not limit the specific number of sacrificial structures 106.

[0077] The above embodiment takes the example that the extension directions of the plurality of sacrificial structures 106 are the same. In other embodiments, the extension directions of the plurality of sacrificial structures 106 may also be different.

[0078] In the embodiment of the present disclosure, the dimensions of the plurality of sacrificial structures 106 in the first direction are the same, that is, the bottom surfaces of the plurality of sacrificial structures 106 are flush.

[0079] In some specific examples, the dimension of the sacrificial structure 106 in the first direction is less than 500 nm.

[0080] Combined with reference Figure 8 and Fig. 9 , perform step S20 to form a stacked structure 200 on the substrate 100 , and form a plurality of channel holes 203 that penetrate the stacked structure 200 along a first direction and extend into the sacrificial structure 106 ; at least two channel holes 203 are formed on each sacrificial structure 106 .

[0081] In some embodiments, reference Figure 8 , a stacked structure 200 is formed on a substrate 100 , and the stacked structure 200 includes isolation layers 201 and sacrificial layers 202 alternately arranged along a first direction.

[0082] It should be noted that the number of isolation layers 201 and sacrificial layers 202 in the figure is only an example, and the present disclosure does not impose any specific limitation on the number of stacking layers of the stacking structure.

[0083] In some specific examples, the stacked structure 200 is formed on the substrate 100 by a deposition process; the material of the isolation layer 201 includes but is not limited to silicon oxide, and the material of the sacrificial layer 202 includes but is not limited to silicon nitride.

[0084] In the embodiments of the present disclosure, the deposition process includes but is not limited to chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD) and atomic layer deposition (ALD).

[0085] In the embodiment of the present disclosure, the thickness direction of the substrate 100 is the same as the stacking direction of the stacking structure, and both are in the Z direction.

[0086] In some embodiments, before forming the stacked structure 200 on the substrate 100 , the method for forming a semiconductor structure further includes: forming a semiconductor layer 107 on the substrate 100 .

[0087] In some specific examples, the semiconductor layer 107 includes a semiconductor material, and the semiconductor material may include at least one of the following: polysilicon, polycrystalline germanium, and polycrystalline silicon germanium.

[0088] In some embodiments, reference Fig. 9 , forming a plurality of channel holes 203 penetrating the stacked structure 200 along the first direction and extending into the sacrificial structure 106; at least two channel holes 203 are formed on each sacrificial structure 106. Here, forming four channel holes 203 on one sacrificial structure 106 is taken as an example.

[0089] In the embodiment of the present disclosure, under preset etching process conditions, the stacked structure 200 and the sacrificial structure 106 are etched along a first direction and stopped in the sacrificial structure 106 to form a channel hole 203; and under the preset etching process conditions, the etching rate of the sacrificial structure 106 is lower than the etching rate of the stacked structure 200, and lower than the etching rate of the substrate 100, that is, compared with the method of etching the stacked structure and stopping in the substrate to form a channel hole in the related art, the bottom of the channel hole 203 in the formation method provided in the embodiment of the present disclosure stops inside the sacrificial structure 106, and the etching depth of the channel hole and the critical dimension of the bottom of the channel hole are easier to control, which is beneficial to improve the uniformity of the channel hole.

[0090] In some specific examples, the preset etching process may be a dry etching process, which includes but is not limited to plasma etching (PE), sputtering etching (SE), ion beam etching (IBE), and reactive ion etching (RIE).

[0091] In some embodiments, when the sacrificial structure 106 is formed in the substrate 100, an alignment mark of the sacrificial structure 106 is simultaneously formed in the substrate 100, and is aligned with the alignment mark of the sacrificial structure 106 when the channel hole 203 is formed, so as to ensure that the channel hole 203 can be formed above the sacrificial structure 106, and the bottom of the channel hole 203 can extend to the inside of the sacrificial structure 106. In addition, the dimension of the sacrificial structure 106 in the direction perpendicular to its extension direction should be larger than the critical dimension of the bottom of the channel hole 203, so as to ensure that the bottom of the channel hole 203 is completely located in the sacrificial structure 106.

[0092] In some specific examples, the sacrificial structure 106 extends along the second direction, and has a size ranging from 80 nm to 120 nm in a fourth direction perpendicular to the second direction; and a spacing between two adjacent sacrificial structures 106 in the fourth direction ranges from 20 nm to 40 nm.

[0093] Reference Fig.10 , step S30 is performed to remove the sacrificial structure 106 to form a plurality of cavities 204 in the substrate 100 that are connected to the channel holes 203 .

[0094] In some specific examples, the material of the sacrificial structure 106 is an organic sacrificial material containing carbon, and the method of removing the sacrificial structure 106 includes but is not limited to ashing.

[0095] In the embodiment of the present disclosure, after removing the sacrificial structure 106, the bottoms of the plurality of channel holes 203 are flush with the bottom surface of the semiconductor layer 107, so that a plurality of channel holes 203 having substantially the same size in the first direction can be formed. Here, the substantially same size of the channel holes 203 in the first direction means that the sizes of the channel holes 203 in the first direction can be equal, but a certain difference is allowed within a certain error range, and the error range may include the error difference caused by the manufacturing process.

[0096] In some embodiments, the method for forming a semiconductor structure further includes: Fig.11As shown, a sacrificial material is filled in the cavity 204 and the channel hole 203 to form a sacrificial structure 106 in the cavity 204 again, and a sacrificial filling structure 205 is formed in the channel hole 203; a stacked structure 300 is formed on the stacked structure 200, and the stacked structure 300 includes an isolation layer 301 and a sacrificial layer 302 alternately arranged along a first direction; as shown Fig.12 As shown, the stack structure 300 is etched along the first direction to form a plurality of channel holes 303 that penetrate the stack structure 300 along the first direction and extend to the sacrificial filling structure 205; Fig.13 As shown, the sacrificial filling structure 205 and the sacrificial structure 106 are removed to form the channel hole 203 and the cavity 204 again, and the channel hole 203 and the channel hole 303 corresponding to each other in the first direction are connected.

[0097] In some embodiments, only the stacking structure 200 and the channel hole 203 may be formed, and then step S40 is performed; in other embodiments, the stacking structure 300 and the channel hole 303 may be formed after the stacking structure 200 and the channel hole 203 are formed to increase the number of stacking in the first direction; in another embodiment, another stacking structure and a channel hole running through the stacking structure may be formed on the stacking structure 300 to further increase the number of stacking in the first direction. It is understandable that by sequentially forming a plurality of stacking structures and channel holes arranged in the first direction, the number of stacking can be increased while reducing the difficulty of etching the channel hole, which is conducive to forming a more integrated three-dimensional storage array. The present disclosure does not specifically limit the number of stacking structures and channel holes arranged in the first direction.

[0098] In some specific examples, after executing step S30, the arrangement of the channel hole 203 and the cavity 204 is as follows: Figures 14 to 16 As shown, the arrangement of the channel holes 203 is the same in the three examples, that is, they are aligned in the X direction and arranged in a Z shape in the Y direction, or aligned in the Y direction and arranged in a Z shape in the X direction.

[0099] In a specific example, when the arrangement of the sacrificial structure 106 is as follows Figure 5 As shown, after executing step S30, the arrangement of the channel hole 203 and the cavity 204 is as follows Fig.14 As shown, a plurality of channel holes 203 aligned in the X direction are connected to the same cavity 204 .

[0100] In another specific example, when the arrangement of the sacrificial structure 106 is as follows Figure 6 As shown, after executing step S30, the arrangement of the channel hole 203 and the cavity 204 is as follows Fig.15 As shown, a plurality of channel holes 203 aligned in the Y direction are connected to the same cavity 204 .

[0101] In another specific example, when the arrangement of the sacrificial structure 106 is as follows Figure 7 As shown, after executing step S30, the arrangement of the channel hole 203 and the cavity 204 is as follows Fig.16 As shown, the extension direction of the cavity 204 intersects with the X direction, and a plurality of channel holes 203 arranged in the extension direction of the cavity 204 are connected to the same cavity 204 .

[0102] It should be noted that the arrangement of the cavities 204, the arrangement of the channel holes 203, the number of cavities 204, the number of channel holes 203, and the number of channel holes 203 connected to the same cavity 204 in the above specific examples are merely examples. As long as one cavity 204 is connected to at least two channel holes 203, the present disclosure does not impose any restrictions on the specific arrangement and number of cavities 204 and channel holes 203.

[0103] Reference Fig.17 , performing step S40, forming a channel structure 401 in the channel hole, and forming an initial connection structure 402 connected to the channel structure 401 in the cavity 204. Here, the channel hole is a channel hole composed of the channel holes 203 and the channel holes 303 arranged in the first direction.

[0104] In some embodiments, the specific process of performing step S40 may include: sequentially forming a functional layer 403 and a channel layer 404 along the sidewalls of the channel hole and the inner wall of the cavity 204 to form a channel structure 401 and an initial connection structure 402 .

[0105] In the embodiments of the present disclosure, refer to Fig.17 In the enlarged view of the channel structure 401, the formation of the functional layer 403 may include sequentially forming a barrier layer 4031, a capture layer 4032 and a tunneling layer 4033 through a deposition process, that is, the functional layer 403 in the present disclosure may be composed of the barrier layer 4031, the capture layer 4032 and the tunneling layer 4033. In addition, after the channel layer 404 is formed, the remaining space of the channel hole and the cavity may be filled with an insulating material to form an insulating layer 405.

[0106] In some specific examples, the material of the blocking layer 4031 may include but is not limited to silicon oxide; the material of the capture layer 4032 may include but is not limited to silicon nitride; the material of the tunneling layer 4033 may include but is not limited to silicon oxide; the material of the channel layer 404 may include but is not limited to polysilicon; and the material of the insulating layer 405 may include but is not limited to silicon oxide.

[0107] In the embodiment of the present disclosure, a sacrificial structure 106 is formed in the substrate in advance, and a channel hole 203 is formed on the sacrificial structure 106. A cavity 204 connected to the channel hole 203 is further formed by removing the sacrificial material in the sacrificial structure 106, and each cavity 204 is connected to at least two channel holes 203. Then, a functional layer 403 and a channel layer 404 are sequentially formed along the side walls of the channel hole 203 and the inner walls of the cavity 204 through a deposition process. During this process, the reaction gas can diffuse along the multiple channel holes 203 connected to the same cavity 204 to the bottom of the channel hole 203 and the inside of the cavity 204, thereby increasing the reaction gas concentration at the bottom of the channel hole 203, thereby increasing the step coverage of each film layer. Meanwhile, an initial connection structure 402 may be formed in the cavity 204 , and each film layer in the initial connection structure 402 is continuous with each film layer in the channel structure 401 , that is, the initial connection structure 402 also includes a functional layer 403 , a channel layer 404 and an insulating layer 405 .

[0108] In the embodiment of the present disclosure, the bottom of the channel structure 401 formed by the above method is flush with the bottom surface of the semiconductor layer 107, the top surface of the initial lead-out connection 402 is in contact with the bottom surface of the semiconductor layer 107, and the sizes of the multiple channel structures 401 in the first direction are basically the same, which can effectively improve the uniformity of the channel structure 401.

[0109] In some embodiments, the method for forming a semiconductor structure also includes: replacing a sacrificial layer in the stacked structure with a gate layer through a gate replacement process; forming a first bonding layer on the stacked structure; providing a peripheral circuit wafer, the peripheral circuit wafer including a peripheral circuit and a second bonding layer located on the peripheral circuit; bonding the first bonding layer and the second bonding layer; and facing the substrate 100 away from the stacked structure 200 with its side facing upward.

[0110] In other embodiments, the semiconductor structure is only a memory array wafer including a stacked structure, that is, there is no need to bond the memory array wafer to the peripheral circuit wafer. In this case, the memory array wafer can be temporarily bonded to the support wafer, and the side of the substrate 100 away from the stacked structure 200 is facing upward, and the support wafer can provide support for the memory array wafer to facilitate the execution of subsequent process steps.

[0111] In some embodiments, Fig.18 FIG. 1 is a partial schematic diagram of a semiconductor structure after the side of the substrate 100 away from the stacked structure 200 faces upward. Fig.19 for Fig.18 The cross-section along line AA'. Fig.18 As shown, the sacrificial layer 202 in the stacked structure 200 is replaced by a gate layer 206 , and a plurality of gate layers 206 arranged along the Z direction surround a channel structure 401 to form a plurality of memory cells arranged along the Z direction.

[0112] Reference Fig.19 The four sidewalls of the initial connection structure 402 all include a functional layer 403 and a channel layer 404 , and the sum of the thicknesses of the functional layer 403 and the channel layer 404 in the Y direction on a single sidewall is greater than 25 nm.

[0113] In the embodiment of the present disclosure, even in the cavity 204 below the bottom of the channel hole 203, a thick functional layer 403 and a channel layer 404 can be formed, which further illustrates that the formation method provided by the embodiment of the present disclosure can improve the step coverage of each film layer in the channel structure. In addition, the step coverage of each film layer in the channel structure is improved, which can reduce the risk of data retention capability reduction and threshold voltage drift of the storage unit at the bottom of the channel structure due to the thickness of the film layer failing to meet the design requirements, and the uniformity of multiple storage units arranged along the Z direction is also improved.

[0114] In some embodiments, in conjunction with reference Figure 20 to Figure 23 The initial connection structure 402 includes a first portion in contact with the semiconductor layer 107 and a second portion away from the semiconductor layer 107, and both the first portion and the second portion include a functional layer 403 and a channel layer 404; the method for forming a semiconductor structure also includes: removing the substrate 100 and the second portion of the initial connection structure 402 from a side of the substrate 100 away from the stacking structure 200, and exposing the semiconductor layer 107 and the channel layer 404 in the first portion of the initial connection structure 402, and the remaining initial connection structure constitutes a connection structure 406.

[0115] In some embodiments, reference Fig. 20 , the semiconductor substrate 101 may be removed first to expose the functional layer 403 and the initial oxide layer 102 of the initial connection structure 402 .

[0116] In some specific examples, the semiconductor substrate 101 may be thinned from a side of the semiconductor substrate 101 away from the stack structure 200 by a grinding process, and then the semiconductor substrate 101 may be removed by a wet etching process.

[0117] In the embodiments of the present disclosure, Fig. 20 As shown, the plane passing through the BB' line and perpendicular to the Z direction is the interface between the first part and the second part of the initial connection structure 402, and the interface is also the interface between the channel layer 404 and the insulating layer 405. The first part of the initial connection structure 402 in contact with the semiconductor layer 107 is located on the side of the interface close to the stacking structure 200, and the second part of the initial connection structure 402 is located on the side of the interface away from the stacking structure 200.

[0118] In some embodiments, in conjunction with reference Fig. 20 and Fig.21 The exposed first portion of the functional layer 403 , the initial oxide layer 102 , and a portion of the functional layer 403 in contact with the initial oxide layer 102 are removed by an etching process to expose the second portion of the channel layer 404 and the semiconductor layer 107 of the initial connection structure 402 .

[0119] In some specific examples, the materials of the semiconductor layer 107 and the channel layer 404 include semiconductor materials such as polysilicon or polycrystalline germanium, and the materials of the initial oxide layer 102 and the functional layer 403 include dielectric materials such as silicon oxide or silicon nitride. An etching process with a relatively large etching selectivity between the dielectric material and the semiconductor material can be used to simultaneously remove the exposed functional layer 403, the initial oxide layer 102, and the functional layer 403 in contact with the initial oxide layer 102, thereby, the etching of the functional layer 403 can stop on the channel layer 404, and the etching of the initial oxide layer 102 can stop on the semiconductor layer 107 to expose the second portion of the channel layer 404 and the semiconductor layer 107. Here, the etching process can be a chemical gas etching process, such as a Certas etching process.

[0120] In some embodiments, in conjunction with reference Fig.21 and Fig. 22 The exposed second portion of the channel layer 404 is removed by an etching process to expose the second portion of the insulating layer 405. During this process, since the material of the semiconductor layer 107 is similar to that of the channel layer 404 in properties, part of the semiconductor layer 107 may also be removed when the channel layer 404 is removed.

[0121] In some embodiments, in conjunction with reference Fig. 22 and Fig.23 , the second portion of the insulating layer 405 is removed to expose the first portion of the channel layer 404 , and the remaining initial connection structure constitutes a connection structure 406 .

[0122] In the related art, the method of etching the stacked structure and stopping in the substrate to form a channel hole not only causes the depth of the portion of the channel hole extending into the substrate to be different, but the maximum depth may reach 550nm, resulting in greater process difficulty in the subsequent back-side lead-out of the channel structure. In particular, when it is necessary to remove the functional layer at the bottom of the channel structure through an etching process to expose the channel layer, it is difficult to uniformly etch multiple channel structures at the same time due to the size difference of the bottom of the channel structure in its extension direction.

[0123] In the embodiment of the present disclosure, the sizes of the multiple sacrificial structures 106 in the first direction are the same and are all less than 500nm. The sizes of the initial connection structure 402 formed in the cavity 204 formed by removing the sacrificial structure 106 in the first direction are also the same and are all less than 500nm. Therefore, when part of the film layer in the initial connection structure 402 is removed by an etching process, the multiple initial connection structures 402 can be uniformly etched, that is, the formation method provided by the embodiment of the present disclosure can reduce the difficulty of the back-side lead-out process, and can also improve the uniformity of the connection structure 406 finally formed.

[0124] In some embodiments, Fig.24 for Fig.23 The top view of the connecting structure 406 is shown in FIG. Fig.23 and Fig.24 The extending direction of the finally formed connection structure 406 is the same as the extending direction of the sacrificial structure 106 formed in the substrate 100 , that is, when the sacrificial structure 106 extends along the X direction, the extending direction of the finally formed connection structure 406 is also the X direction.

[0125] In some specific examples, the dimension of the connection structure 406 in the direction perpendicular to the extending direction ranges from 30 nm to 70 nm.

[0126] In some embodiments, reference Fig.25 The method for forming a semiconductor structure further includes: forming an active layer 501 covering the semiconductor layer 107 and the connection structure 406, wherein the channel layer 404 in the channel structure 401 is connected to the active layer 501 through the connection structure 406; and the active layer 501 includes a doped semiconductor material.

[0127] In some specific examples, the specific process of forming the active layer 501 may be: forming an initial active layer covering the semiconductor layer 107 and the connection structure 406 through a deposition process, the material of the initial active layer including but not limited to polysilicon; doping the initial active layer through an ion implantation process to form the active layer 501.

[0128] In the embodiment of the present disclosure, a connection structure 406 connected to the channel structure 401 is formed on one side of the stack structure 200, and the connection structure 406 connects the channel structure 401 to the active layer 501, thereby realizing the extraction of the channel structure. Fig.24 The channel layer 404 exposed by the connection structure 406 has a larger area in a plane perpendicular to the Z direction. Therefore, when the active layer 501 covering the connection structure 406 is formed, the channel layer 404 of the connection structure 406 has a larger contact surface with the active layer 501, thereby reducing the contact resistance between the channel layer 404 and the active layer 501 and improving the reliability of the channel structure lead-out.

[0129] Based on a concept similar to the above-mentioned method for forming a semiconductor structure, the present disclosure also provides a semiconductor structure. Fig.25 , the semiconductor structure includes: a stacked structure 200 and an active layer 501 located on one side of the stacked structure 200; a plurality of channel structures 401 penetrating the stacked structure 200 along a first direction; the first direction is the stacking direction of the stacked structure 200; a plurality of connection structures 406 located between the active layer 501 and the stacked structure 200; each connection structure 406 is connected to at least two channel structures 401; and the extension direction of the connection structure 406 intersects with the first direction. Here, the first direction is the X direction.

[0130] In some embodiments, the channel structure 401 and the connection structure 406 both include a channel layer 404 , and the channel layer 404 of the channel structure 401 is connected to the channel layer 404 of the connection structure 406 ; the channel layer 404 in the channel structure 401 is connected to the active layer 501 through the connection structure 406 .

[0131] In some embodiments, the channel structure 401 and the connection structure 406 both include a functional layer 403 located between the channel layer 404 and the stacked structure 200 , and the functional layer 403 of the channel structure 401 is connected to the functional layer 403 of the connection structure 406 .

[0132] In some embodiments, the semiconductor structure further includes: a semiconductor layer 107 located between the connection structure 406 and the stacked structure 200 ; the semiconductor layer 107 is in contact with a side of the connection structure 406 away from the active layer 501 .

[0133] In some embodiments, the semiconductor layer 107 includes a semiconductor material, and the active layer 501 includes a doped semiconductor material.

[0134] In some embodiments, each connection structure 406 extends along the second direction, and a plurality of connection structures 406 are arranged along a third direction; the second direction intersects with the third direction and are both perpendicular to the first direction.

[0135] In some embodiments, a dimension of the connection structure 406 in a fourth direction perpendicular to the second direction ranges from 30 nm to 70 nm.

[0136] In the embodiment of the present disclosure, the semiconductor structure can be obtained by the method for forming the semiconductor structure in any of the above embodiments, the step coverage of each film layer in the channel structure 401 is high, and the reliability of the multiple memory cells arranged along the Z direction is high. In addition, the bottom of the channel structure 401 is flush with the side of the semiconductor layer 107 away from the stacked structure 200, and the uniformity of the channel structure 401 is high.

[0137] In the embodiment of the present disclosure, the channel structure 401 in the semiconductor structure is connected to the active layer 501 through the connecting structure 406 to realize the lead-out of the channel structure 401. The extension direction of the connecting structure 406 intersects with the extension direction of the channel structure 401, and there is a large contact surface between the channel layer 404 of the connecting structure 406 and the active layer 501, so that the contact resistance between the channel layer 404 and the active layer 501 is small, and the reliability of the lead-out of the channel structure is high.

[0138] In some embodiments, the semiconductor structure may be a memory. Fig.26 Schematic diagram of a memory provided by an embodiment of the present disclosure. Fig.26 As shown, the memory 600 includes a storage array 601, the storage array 601 includes a plurality of storage blocks 603, each storage block 603 includes a plurality of storage strings 604, and a plurality of storage cells in a storage string 604 may correspond to Fig.25 Each memory block 603 includes a plurality of word lines 605, which may correspond to a plurality of memory cells corresponding to a channel structure 401. Fig.25 The gate layer 206 in FIG.

[0139] In some embodiments, the semiconductor structure may be only a part of the memory 600 , that is, the semiconductor structure may be only the memory array 601 .

[0140] In some other embodiments, the semiconductor structure may also be a memory including a peripheral circuit, such as Fig.26 As shown, the memory 600 may further include a peripheral circuit 602 coupled to the memory array 601. In some specific examples, the peripheral circuit 602 may include circuit elements such as a page buffer sense amplifier, a column decoder / bit line driver, a row decoder / word line driver, a voltage generator, a control logic unit, a register, an interface, and a data bus.

[0141] In the embodiment of the present disclosure, the memory 600 includes but is not limited to a 3D NAND memory.

[0142] Reference Fig. 27 The present disclosure also provides a memory system 700, comprising: at least one semiconductor structure in any of the above embodiments and a controller 702; the controller 702 is coupled to the at least one semiconductor structure and configured to control the semiconductor structure. Here, the semiconductor structure may be a memory 701.

[0143] In some embodiments, the controller 702 and the one or more memories 701 may be integrated into various types of storage devices, that is, the memory system 700 may be implemented and packaged into different types of terminal electronic products.

[0144] In some specific examples, the memory system 700 can be a compact flash card (CFC), a smart media card (SMC), a memory stick (MS), a multimedia card (MMC), such as RS-MMC, MMCmicro, eMMC, etc., a secure digital card (SD card), such as Mini SD card, Micro SD card, SDHC card, etc., a universal flash storage (UFS) card and a solid state drive (SSD).

[0145] In other specific examples, the memory system 700 may be placed in a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having memory therein.

[0146] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0147] The features disclosed in several device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new device embodiments.

[0148] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A method for forming a semiconductor structure, It is characterized in that include: providing a substrate, and forming a plurality of sacrificial structures in the substrate; The bottom surface of the sacrificial structure is higher than the bottom surface of the substrate; A stacking structure is formed on the substrate, and a plurality of channel holes are formed along a first direction through the stacking structure and extending into the sacrificial structure; at least two channel holes are formed on each of the sacrificial structures; The first direction is the stacking direction of the stacking structure; the extending direction of the sacrificial structure intersects with the first direction; removing the plurality of sacrificial structures to form a plurality of cavities in the substrate; A channel structure is formed in the channel hole, and an initial connection structure connected to the channel structure is formed in the cavity.

2. The method for forming a semiconductor structure according to claim 1, It is characterized in that The step of forming a channel structure in the channel hole and forming an initial connection structure connected to the channel structure in the cavity comprises: A functional layer and a channel layer are sequentially formed along the sidewalls of the channel hole and the inner wall of the cavity to form the channel structure and the initial connection structure.

3. The method for forming a semiconductor structure according to claim 2, It is characterized in that A semiconductor layer is formed between the stacked structure and the substrate, and the semiconductor layer includes a semiconductor material; the initial connection structure includes a first portion in contact with the semiconductor layer and a second portion away from the semiconductor layer, and the first portion and the second portion both include the functional layer and the channel layer; The forming method further comprises: removing the substrate and the second portion from a side of the substrate away from the stacked structure, and exposing the semiconductor layer and the channel layer of the first portion, with the remaining initial connection structure constituting a connection structure; An active layer covering the semiconductor layer and the connection structure is formed, wherein the channel layer in the channel structure is connected to the active layer through the connection structure; the active layer comprises a doped semiconductor material.

4. The method for forming a semiconductor structure according to claim 1, It is characterized in that The forming of a plurality of channel holes penetrating the stacked structure along a first direction and extending into the sacrificial structure comprises: Under preset etching process conditions, the stacked structure and the sacrificial structure are etched along the first direction and stopped at the sacrificial structure to form the channel hole; under the preset etching process conditions, the etching rate of the sacrificial structure is less than the etching rate of the substrate.

5. The method for forming a semiconductor structure according to claim 1, It is characterized in that The material of the sacrificial structure includes carbon.

6. The method for forming a semiconductor structure according to claim 1, It is characterized in that Each of the sacrificial structures extends along a second direction, and the plurality of sacrificial structures are arranged along a third direction, the second direction intersects the third direction and is perpendicular to the first direction.

7. The method for forming a semiconductor structure according to claim 6, It is characterized in that A dimension of the sacrificial structure in a fourth direction perpendicular to the second direction ranges from 80 nm to 120 nm.

8. The method for forming a semiconductor structure according to claim 1, It is characterized in that The sizes of the multiple sacrificial structures in the first direction are the same and are all smaller than 500 nm.

9. The method for forming a semiconductor structure according to claim 1, It is characterized in that The forming method further comprises: forming a first bonding layer on the stacked structure; Providing a peripheral circuit wafer, the peripheral circuit wafer comprising a peripheral circuit and a second bonding layer located on the peripheral circuit; The first bonding layer and the second bonding layer are bonded.

10. A semiconductor structure, It is characterized in that include: A stacked structure and an active layer located on one side of the stacked structure; A plurality of channel structures penetrating the stack structure along a first direction; The first direction is the stacking direction of the stacking structure; a plurality of connection structures between the active layer and the stacked structure; Each of the connection structures is connected to at least two of the channel structures; and an extending direction of the connection structure intersects with the first direction.

11. The semiconductor structure according to claim 10, It is characterized in that The channel structure and the connection structure both include a channel layer; the channel layer of the channel structure is connected to the channel layer of the connection structure; and the channel layer in the channel structure is connected to the active layer through the connection structure.

12. The semiconductor structure according to claim 11, It is characterized in that The channel structure and the connection structure both include a functional layer located between the channel layer and the stacked structure; the functional layer of the channel structure is connected to the functional layer of the connection structure.

13. The semiconductor structure according to claim 10, It is characterized in that The semiconductor structure further comprises: A semiconductor layer is located between the connection structure and the stack structure; the semiconductor layer is in contact with a side of the connection structure away from the active layer.

14. The semiconductor structure according to claim 13, It is characterized in that The semiconductor layer includes a semiconductor material, and the active layer includes a doped semiconductor material.

15. The semiconductor structure according to claim 10, It is characterized in that Each of the connection structures extends along the second direction, and the plurality of connection structures are arranged along a third direction; the second direction intersects with the third direction and are both perpendicular to the first direction.

16. The semiconductor structure according to claim 15, It is characterized in that A dimension of the connection structure in a fourth direction perpendicular to the second direction ranges from 30 nm to 70 nm.

17. The semiconductor structure according to claim 10, It is characterized in that The semiconductor structure further comprises: a first bonding layer located on the other side of the two opposite sides of the stacked structure in the first direction; a second bonding layer located on a side of the first bonding layer away from the stacking structure; The peripheral circuit is located on a side of the second bonding layer away from the first bonding layer.

18. A memory system, It is characterized in that include: At least one semiconductor structure according to any one of claims 10 to 17; The controller is coupled to the semiconductor structure and configured to control the semiconductor structure.

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