Memory element and manufacturing method thereof

Abstract

The invention provides a memory element. The memory element comprises a substrate, a composite stacked structure, a plurality of first insulating structures and a plurality of through holes, the substrate comprises a storage surface area and a peripheral area. The composite stacked structure is located on the substrate in the storage surface area and the peripheral area. The composite stack structure includes a first stack structure. The first stacked structure comprises a plurality of first insulating layers and a plurality of middle layers which are alternately stacked on each other and located on the substrate of the peripheral area. The plurality of first insulating structures are separated from each other, extend through the first stacked structure in the peripheral region, and are respectively surrounded by the plurality of first insulating layers and the plurality of intermediate layers. The plurality of perforations extend through one of the plurality of first insulating structures.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a memory device and a manufacturing method thereof. Background Art

[0002] Non-volatile memory elements (eg, flash memory) have become a type of memory element widely used in personal computers and other electronic devices because they have the advantage that stored data will not disappear even after power is turned off.

[0003] The flash memory arrays commonly used in the industry include NOR flash memory and NAND flash memory. Since the structure of NAND flash memory is to connect each storage unit in series, its integration and area utilization are better than NOR flash memory, and it has been widely used in a variety of electronic products. In addition, in order to further improve the integration of memory elements, a three-dimensional NAND flash memory has been developed. However, there are still many challenges associated with three-dimensional NAND flash memory. Summary of the invention

[0004] The invention provides a memory element which can reduce the amount of insulating material deposited in the peripheral area.

[0005] A memory element according to an embodiment of the present invention comprises a substrate, a composite stacking structure, a plurality of first insulating structures and a plurality of through-holes. The substrate comprises a storage surface area and a peripheral area. The composite stacking structure is located on the substrate in the storage surface area and the peripheral area. The composite stacking structure comprises a first stacking structure. The first stacking structure comprises a plurality of first insulating layers and a plurality of intermediate layers alternately stacked with each other and located on the substrate in the peripheral area. The plurality of first insulating structures are separated from each other, extend through the first stacking structure in the peripheral area, and are respectively surrounded by the plurality of first insulating layers and the plurality of intermediate layers. The plurality of through-holes extend through one of the plurality of first insulating structures.

[0006] Based on the above, the stacking structure of the memory element of the embodiment of the present invention is retained in the peripheral area. The perforations in the peripheral area are isolated from each other by multiple insulating structures. The multiple insulating structures are separated from each other. The multiple insulating structures are formed by removing a small part of the stacking structure in the peripheral area and then backfilling a small amount of insulating material. Therefore, the deposition amount of insulating material can be reduced, and the time for polishing excess insulating material can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a top view of a memory element according to an embodiment of the present invention;

[0008] FIG. 2A to FIG. 2D is in accordance with Figure 1A schematic cross-sectional view of a method for manufacturing a peripheral region of a memory element as illustrated by a tangent line II';

[0009] FIG. 3A to FIG. 3J is a cross-sectional schematic diagram of a method for manufacturing a memory element according to an embodiment of the present invention;

[0010] FIG. 4A to FIG. 4N is a top view of various perforations and insulation structures according to an embodiment of the present invention;

[0011] Figure 4O to Figure 4P is a top view of various sealing rings and insulating structures according to an embodiment of the present invention;

[0012] Figure 5A and Figure 5B is a top view of various perforations and insulation structures according to an embodiment of the present invention;

[0013] Figure 6 is a cross-sectional schematic diagram of a memory element according to an embodiment of the present invention.

[0014] Description of Reference Numerals

[0015] 10, 100: Base

[0016] 20: Component layer

[0017] 30, 40: Interconnection structure

[0018] 30a, 32a: Part I

[0019] 30b, 32b: Part 2

[0020] 31a: Topmost wire

[0021] 31b: The topmost wire

[0022] 32: Joint structure

[0023] 34a, 34b: Bonding layer

[0024] 36a, 36b: Joint plug

[0025] 38a, 38b: Bonding pads

[0026] 43: Contact window opening

[0027] 44: Lining

[0028] 46. ​​COA: Contact Window

[0029] 48: Wire

[0030] 50, 60, 128, 130: Dielectric layer

[0031] 92, 101, 102: Insulation layer

[0032] 94, 126: Conductive layer

[0033] 103: Stop Structure

[0034] 104: Middle layer

[0035] 105A, 105E, 105P, 105P1, 105P2, 106: Open

[0036] 107: Insulation material

[0037] 107A, 107E, 107G, 107P, 107P1, 107P2: Insulation structure

[0038] 108: Charge storage structure

[0039] 110: Channel layer

[0040] 112: Insulation column

[0041] 114: Channel plug

[0042] 116: Separation channel

[0043] 129: Stop layer

[0044] AR: Array Area

[0045] CP: Vertical Channel Column

[0046] CSK: Composite stacking structure

[0047] D1, D2, D3: Direction

[0048] d1: diameter

[0049] DVC: Virtual Column

[0050] GR, GR1, GR2: Sealing ring

[0051] H1, H1': Height

[0052] HM: Hard Mask Layer

[0053] LBL: Local Bit Line

[0054] LP: Lower

[0055] LSL: Local Source Line

[0056] MC: Storage Unit

[0057] m1: Part 1

[0058] m2: Part 2

[0059] m3: Part 3

[0060] R1: Storage area

[0061] R2: Peripheral area

[0062] R3: Sealing ring area

[0063] RSC: Anti-step structure

[0064] SC: Ladder structure

[0065] SCR: Step Area

[0066] SK1: First stacking structure / stacked structure

[0067] SK2: Second stacking structure / stacked structure

[0068] SLIT: Separation Wall

[0069] SM1, SM2: memory elements

[0070] SW1: Inner wall

[0071] SW, SW2: outer wall

[0072] TV, TV1, TV1a, TV1b, TV2: Perforated

[0073] UP: upper part

[0074] W1, W1', W2, W2': Width

[0075] L, L': length

[0076] I-I': tangent DETAILED DESCRIPTION

[0077] Figure 1 is a top view of a memory element according to an embodiment of the present invention. Figure 2D FIG. 4 is a cross-sectional diagram of a peripheral region of a memory device according to an embodiment of the present invention. Figure 3J is a cross-sectional schematic diagram of a memory element according to an embodiment of the present invention. FIG. 4A to FIG. 4N 1 is a top view of various through-hole and insulation structures according to an embodiment of the present invention. Figure 4O to Figure 4P 1 is a top view of various sealing rings and insulating structures according to an embodiment of the present invention. Figure 5A and Figure 5B 1 is a top view of various through-hole and insulation structures according to an embodiment of the present invention.

[0078] Reference Figure 1A memory element SM1 according to an embodiment of the present invention comprises a substrate 10, a composite stack structure CSK, a plurality of insulating structures 107P, 107A, 107E, 107G, a plurality of contact windows COA, and a plurality of through holes TV. The substrate 10 comprises a storage surface area R1, a peripheral area R2, and a sealing ring area R3. The storage surface area R1 may comprise a step area SCR and a plurality of array areas AR on both sides of the step area SCR. The peripheral area R2 surrounds the storage surface area R1. The sealing ring area R3 surrounds the peripheral area R2.

[0079] Reference Figure 1 The composite stacking structure CSK is located on the substrate 10 of the storage surface area R1, the peripheral area R2 and the sealing ring area R3. The composite stacking structure CSK includes a first stacking structure SK1 and a second stacking structure SK2. The first stacking structure SK1 is located on the substrate 10 of the peripheral area R2. The second stacking structure SK2 is located on the substrate 10 of the storage surface area R1. The second stacking structure SK2 is surrounded by the first stacking structure SK1. Figure 3J The first stacked structure SK1 includes a plurality of insulating layers 102 and a plurality of intermediate layers 104 stacked alternately. The second stacked structure SK2 includes a plurality of insulating layers 102 and a plurality of conductive layers 126 stacked alternately. The memory element SM1 may include a plurality of memory cells MC located in the array region AR of the memory plane region R1.

[0080] Reference Figure 1 and Figure 3J , a plurality of contact windows COA are disposed in the step region SCR of the storage surface region R1 and are electrically connected to the plurality of conductive layers 126 (eg Figure 3J shown).

[0081] The memory element SM1 includes a plurality of insulating structures 107A. Each insulating structure 107A surrounds a plurality of contact windows COA so as to isolate the contact windows COA from the surrounding second stacked structures SK2. The plurality of insulating structures 107A are separated from each other, extend through the second stacked structures SK2 in the step region SCR of the storage plane region R1, and are respectively surrounded by a plurality of insulating layers 102 and a plurality of conductive layers 126.

[0082] Reference Figure 1 The memory element SM1 further includes a plurality of insulating structures 107E. At the ends of the plurality of array regions AR of the memory plane region R1, the first stack structure SK1 and the second stack structure SK2 are separated.

[0083] Reference Figure 1 The memory element SM1 further includes a sealing ring GR and an insulating structure 107G. The sealing ring GR is located in the sealing ring region R3. The sealing ring GR continuously surrounds the first stacked structure SK1. The sealing ring GR may be a single ring (eg, Fig.4OAs shown), the sealing ring GR can also be a double ring, including sealing rings GR1 and GR2 (as shown Figure 4P The insulating structure 107G is separated from the plurality of insulating structures 107E by the first stacking structure SK1. Figure 1 The insulating structure 107G surrounds the first stacked structure SK1 and the sealing ring GR. In other words, the sealing ring GR extends through the insulating structure 107G.

[0084] Reference Figure 1 , multiple through-holes TV and multiple insulating structures 107P′ are arranged in the peripheral region R2. Multiple through-holes TV and multiple insulating structures 107P extend through the first stacked structure SK1. In an embodiment of the present invention, multiple insulating structures 107P surround multiple through-holes TV. In other words, multiple through-holes TV′ extend through multiple insulating structures 107P, such as Figure 3J As shown. The plurality of insulating structures 107P are surrounded by the first stacked structure SK1 retained in the peripheral region R2. The plurality of insulating structures 107P are not connected to each other and are separated from each other by the first stacked structure SK1. The plurality of insulating structures 107P are also separated from the insulating structures 107A, 107E, and 107G by the first stacked structure SK1.

[0085] Reference Figure 2D , a plurality of insulating structures 107P extend through the first stacked structure SK1 in the peripheral region R2. The plurality of insulating structures 107P are respectively surrounded by a plurality of insulating layers 102 and a plurality of intermediate layers 104. The plurality of insulating structures 107P are separated from each other by the plurality of first insulating layers 102 and the plurality of intermediate layers 104 of the first stacked structure SK1.

[0086] Reference Figure 1 The shape of the insulating structure 107P can be a ring, a rectangle, a polygon or a combination thereof. For example, the insulating structure 107P1 in the insulating structure 107P is a ring, and the insulating structure 107P2 is a rectangle.

[0087] Reference Figure 1 , the insulating structure 107P1 is annular. The insulating structure 107P1 surrounds a portion of the first stacked structure SK1. Another portion of the first stacked structure SK1 surrounds the insulating structure 107P1. The annular shape may be a square ring, a rectangular ring, a circular ring, an elliptical ring, or a combination thereof. Figure 2D The inner sidewalls SW1 and the outer sidewalls SW2 of the plurality of insulating structures 107P1 are in contact with the plurality of insulating layers 102 and the plurality of intermediate layers 104 of the first stacked structure SK1 , respectively.

[0088] Reference Figure 1 , the insulating structure 107P2 is a rectangle. The rectangle can be a square, a rectangle, such as FIG. 4A to FIG. 4N as well as Figure 5Aand Figure 5B See Figure 2D , outer sidewalls SW of the plurality of insulating structures 107P2 are in contact with the plurality of insulating layers 102 and the plurality of intermediate layers 104 .

[0089] Reference Figure 2C In some embodiments, a ratio of a width (ring width) W1 to a height H1 of the insulating structure 107P1 is less than 2, or a ratio of a width W2 to a height H1 of the insulating structure 107P2 is less than 2.

[0090] Reference Figure 1 In the annular insulating structure 107P1, multiple perforations TV1 can be arranged in order. For example, multiple perforations TV1a are arranged in a single ring, multiple perforations TV1b are arranged in a double ring, and multiple perforations TV1 are arranged in more rings. In the annular insulating structure 107P1, multiple perforations TV1 can also be arranged in disorder.

[0091] Reference FIG. 4A to FIG. 4N In each rectangular insulating structure 107P2, only a single through hole TV2 may pass through (eg Figure 4A As shown) or multiple perforations TV2 pass through (as shown FIG. 4B to FIG. 4N A plurality of perforations TV2 may be arranged in an orderly manner, for example, in an array (as shown). FIG. 4B to FIG. 4N A plurality of perforations TV2 may also be arranged in a disorderly manner (not shown).

[0092] Reference Figure 5A , a plurality of through holes TV may be distributed over the entire area of ​​the insulating structure 107P. Figure 5B , the plurality of through-holes TV may be distributed in a local area of ​​the insulating structure 107P, but not in another area. Figure 5A The number of perforated TVs and Figure 5B The same number of perforated TVs. Figure 5A The length L of the insulating structure 107P in the first direction D1 is Figure 5B The lengths L of the insulating structures 107P in the first direction D1 are different. Figure 5A The width W2 of the insulating structure 107P in the second direction D2 is Figure 5B The widths W2 of the insulating structures 107P in the second direction D2 are the same. That is, the same number of the plurality of through holes TV may be disposed in different insulating structures 107P of different areas.

[0093] The plurality of through holes TV may be uniformly distributed throughout the entire area of ​​the insulating structure 107P (eg, Figure 5A ), or evenly distributed in a local area of ​​the insulating structure 107P (such as Figure 5BIn some embodiments (not shown), the plurality of through holes TV may be unevenly distributed in the entire region of the insulating structure 107P, or unevenly distributed in a local region of the insulating structure 107P.

[0094] Reference Figure 1 , each insulating structure 107P in the peripheral region R2 is located around a plurality of through-holes TV and does not occupy too much volume. Figure 2D In some embodiments, the ratio of the width W1 to the height H1 of the plurality of insulating structures 107P is less than 2. Figure 5A and Figure 5B , a ratio of a sum of a plurality of diameters d1 of a plurality of through holes TV2 along the second direction D2 to a width W2 of the insulation structure 107P along the second direction D2 is 0.006-0.15.

[0095] Reference Figure 1 In the embodiment of the present invention, the plurality of through holes TV in the first stacked structure SK1 in the peripheral region R2 are formed in the plurality of insulating structures 107P, rather than in a single block insulating structure. The method for forming the plurality of insulating structures 107P is as follows: FIG. 2A to FIG. 2D shown.

[0096] FIG. 2A to FIG. 2D is in accordance with Figure 1 FIG. 1 is a schematic cross-sectional view of a method for manufacturing a peripheral region of a memory element as illustrated by a cutting line II′.

[0097] Reference Figure 2A , a plurality of insulating layers 102 and a plurality of intermediate layers 104 are alternately stacked on the substrate 100 along a direction D3 to form a first stacked structure SK1. Other layers (not shown) may be included between the first stacked structure SK1 and the substrate 100, such as a conductive layer, an insulating layer, a component layer, etc. The insulating layer 102 and the intermediate layer 104 are, for example, silicon oxide and silicon nitride, respectively.

[0098] A plurality of openings 105P1 and 105P2 are formed in the first stacked structure SK1. The opening 105P1 is, for example, a circular opening, and the opening 105P2 is, for example, a rectangular opening. The volumes of the openings 105P1 and 105P2 are controlled within a certain range to reduce the amount of insulating material subsequently filled in the openings 105P1 and 105P2. In an embodiment of the present invention, the width W1' of the opening 105P1 in the second direction D2 and the width W2' of the opening 105P2 in the second direction D2 are controlled within a certain range. In some embodiments, the ratio of the width W1' of the opening 105P1 to the height H1' of the first stacked structure SK1 is, for example, less than 2. The ratio of the width W2' of the opening 105P2 to the height H1' of the first stacked structure SK1 is, for example, less than 2. If the ratio is greater than 2, the amount of insulating material subsequently filled in the openings 105P1 and 105P2 will increase.

[0099] On the other hand, the lengths of the openings 105P1 and 105P2 in the first direction D1 can be relatively flexible and are not strictly limited. Figure 5A and Figure 5B For example, the length L' of the opening 105P2 in the first direction D1 may be shorter (eg Figure 5A ), or longer (as shown in Figure 5B This is because the insulating material 107 (as shown in FIG. Figure 2B The thickness of the insulating material 107 is related to the width W2' of the opening 105P2 in the second direction D2, but is less related to the length L' of the opening 105P2 in the first direction D1. In other words, regardless of the length L' of the opening 105P2, as long as the thickness of the insulating material 107 is greater than 1 / 2 of the width W2', the opening 105P2 can be filled.

[0100] Reference Figure 2B Then, an insulating material 107 is formed on the first stacked structure SK1. The insulating material 107 continuously extends on the first stacked structure SK1 and fills the openings 105P1 and 105P2. The insulating material 107 is, for example, silicon oxide. Since the first portion m1 of the first stacked structure SK1 is still left in the annular opening 105P1, the two rectangular openings 105P2 are separated by the second portion m2 of the first stacked structure SK1, and the third portion m3 of the first stacked structure SK1 is still left between the rectangular opening 105P2 and the annular opening 105P1, the amount of the insulating material 107 required can be reduced.

[0101] Reference Figure 2C, a chemical mechanical polishing process or an etch back process is performed to remove the excess insulating material 107 on the first stacked structure SK1 to form insulating structures 107P1 and 107P2 in the openings 105P1 and 105P2. In some embodiments, the ratio of the width (ring width) W1 of the insulating structure 107P1 to the height H1 is less than 2. The ratio of the width W2 of the insulating structure 107P2 to the height H1 is less than 2.

[0102] Reference Figure 2D , a dielectric layer 128, a stop layer 129, and a dielectric layer 130 are formed on the first stacked structure SK1. The dielectric layer 128, the stop layer 129, and the dielectric layer 130 are, for example, silicon oxide, silicon nitride, or silicon nitride. Afterwards, through holes TV1b and TV2 are formed in the insulating structures 107P1 and 107P2. The method for forming the through holes TV1b and TV2 is, for example, to form a plurality of through hole openings in the dielectric layer 128, the stop layer 129, the dielectric layer 130, and the insulating structures 107P1 and 107P2, and then fill the plurality of through hole openings with metal materials, and then perform a chemical mechanical polishing process or an etching back process. The metal material is, for example, tungsten.

[0103] Reference Figure 1 In the embodiment of the present invention, the first stacked structure SK1 is retained in the peripheral region R2. The through holes TV in the peripheral region R2 are isolated from each other by the plurality of insulating structures 107P. The plurality of insulating structures 107P are separated from each other and from the plurality of insulating structures 107A, 107E, and 107G. The plurality of insulating structures 107P can be formed simultaneously when the plurality of insulating structures 107A, 107E, and 107G are formed.

[0104] FIG. 3A to FIG. 3J It is a cross-sectional schematic diagram of a method for manufacturing a memory element according to an embodiment of the present invention.

[0105] Reference Figure 3A , providing a substrate 10. The substrate 10 may be a semiconductor substrate, such as a silicon-containing substrate. The device layer 20 is formed on the substrate 10. The device layer 20 may include active devices or passive devices. Active devices are, for example, transistors, diodes, etc. Passive devices are, for example, capacitors, inductors, etc. The transistor may be an N-type metal oxide semiconductor field effect (NMOS) transistor, a P-type metal oxide semiconductor field effect (PMOS) transistor, or a complementary metal oxide semiconductor device (CMOS).

[0106] Reference Figure 3A, a first portion 30a of the interconnect structure 30 is formed on the component layer 20. The first portion 30a of the interconnect structure 30 may include a multi-layer dielectric layer (not shown) and an interconnect line (not shown) formed in the multi-layer dielectric layer. The interconnect line includes a plurality of plugs (not shown) and a plurality of wires (not shown). The dielectric layer separates adjacent wires. The wires may be connected by plugs, and the wires may be connected to the component layer 20 by plugs. The first portion 30a of the interconnect structure 30 may be formed by a single metal damascene process, a dual metal damascene process, or any known method.

[0107] Reference Figure 3A , forming a bonding structure 32 (shown in FIG. 1 ) on the first portion 30a of the interconnect structure 30 Figure 3J ). The first part 32a of the bonding structure 32 includes a bonding layer 34a, a bonding plug 36a and a bonding pad 38a. The bonding layer 34a is, for example, silicon oxide, silicon nitride or a combination thereof. The bonding plug 36a and the bonding pad 38a are, for example, copper. The bonding pad 38a is connected to the topmost wire 31a of the first part 30a of the interconnect structure 30 via the bonding plug 36a. The bonding pad 38a and the bonding plug 36a can be formed in a single or dual inlay manner. The bonding pad 38a, the bonding plug 36a and the bonding layer 34a can be polished to be coplanar via a chemical mechanical polishing process.

[0108] Reference Figure 3A , another substrate 100 is provided. The substrate 100 may be a semiconductor substrate, such as a silicon-containing substrate. An insulating layer 101 and a stop structure 103 are formed on the substrate 100. The insulating layer 101 is, for example, silicon oxide. The stop structure 103 is formed on the insulating layer 101. The stop structure 103 may include a plurality of insulating layers 92 and a plurality of conductive layers 94 alternately stacked with each other. The insulating layer 92 is, for example, silicon oxide, and the conductive layer 94 is, for example, polysilicon.

[0109] Reference Figure 3A , a lower portion LP of a stacked structure (or first stacked structure) SK1 is formed on the surface of the stop structure 103. The lower portion LP of the stacked structure SK1 includes a plurality of insulating layers 102 and a plurality of intermediate layers 104 that are alternately stacked. In some embodiments, the material of the insulating layer 102 includes silicon oxide, and the material of the intermediate layer 104 includes silicon nitride. The intermediate layer 104 can be used as a sacrificial layer, which will be partially removed in a subsequent process.

[0110] Reference Figure 3AThen, a plurality of dummy columns DVC are formed, extending through the lower LP of the stacked structure SK1. The plurality of dummy columns DVC can be formed into openings (not shown) by a single-stage photolithography and etching process or a multi-stage photolithography and etching process. The opening extends through the lower LP of the stacked structure SK1 to the stop structure 103, and even to the insulating layer 101. Then, a filling material (or self-aligned material) is filled in the opening to form. The profile of the sidewall of the opening formed by the multi-stage photolithography and etching process is, for example, bamboo-shaped.

[0111] Reference Figure 3B , an upper portion UP of the stacked structure SK1 is formed above the substrate 100. The upper portion UP of the stacked structure SK1 includes a plurality of insulating layers 102 and a plurality of intermediate layers 104 stacked on each other. The materials of the insulating layers 102 and the intermediate layers 104 of the upper portion UP of the stacked structure SK1 are the same as the materials of the insulating layers 102 and the intermediate layers 104 of the lower portion LP of the stacked structure SK1. Afterwards, a hard mask layer HM is formed on the upper portion UP of the stacked structure SK1. The hard mask layer HM is, for example, polysilicon.

[0112] Reference Figure 3C , then, the hard mask layer HM is patterned. Using the hard mask layer HM as a mask, the middle layer 104 and the insulating layer 102 of the stacked structure SK1 are patterned to form an opening 105A and a step structure SC in the storage surface area R1, and an opening 105P is formed in the peripheral area R2, and an opening 105E is formed at the end of the storage surface area R1. In some embodiments, the opening 105A and the step structure SC can be formed through a multi-stage patterning process, but the present invention is not limited thereto. The openings 105P and 105E are separated by a portion of the stacked structure SK1. The patterning process may include processes such as photolithography, etching, and trimming.

[0113] Reference Figure 3D and 3E , an insulating material 107 is formed on the stacked structure SK1 and fills the openings 105A, 105P, and 105E. The insulating material 107 is, for example, silicon oxide. A polishing process is then performed, such as a chemical mechanical polishing process, using the hard mask layer HM as a polishing stop layer to remove excess insulating material 107, so as to form insulating structures 107A, 107P, and 107E in the openings 105A, 105P, and 105E, respectively.

[0114] Reference Figure 3F, remove the hard mask layer HM. Afterwards, a patterning process is performed to remove a portion of the stacked structure SK1 to form an opening (not shown) and expose the virtual column DVC. Next, the virtual column DVC exposed by the opening is removed to form one or more openings 106 extending through the stacked structure SK1. In one embodiment, the opening 106 may have a slightly inclined sidewall. In another embodiment, the opening 106 may have a substantially vertical sidewall (not shown). In one embodiment, the opening 106 is also referred to as a vertical channel (VC) hole. In one embodiment, the opening 106 can be formed via a single-stage photolithography and etching process. In another embodiment, the opening 106 is formed by multiple stages of photolithography and etching processes. The profile of the sidewall of the opening 106 formed by multiple stages of photolithography and etching processes is, for example, bamboo-shaped.

[0115] Reference Figure 3F Then, a charge storage structure 108 is formed in the opening 106. The charge storage structure 108 is in contact with the insulating layer 102 and the intermediate layer 104. In one embodiment, the charge storage structure 108 is an oxide / nitride / oxide (ONO) composite layer. The charge storage structure 108 is, for example, a conformal layer, which is formed on the sidewalls and bottom surface of the opening 106. Then, a vertical channel column CP is formed in the remaining space of the opening 106. The vertical channel column CP can be formed by the following method.

[0116] Continue to refer to Figure 3F , a channel layer 110 is formed on the inner sidewall and bottom surface of the charge storage structure 108. In one embodiment, the material of the channel layer 110 includes undoped polysilicon. Next, an insulating column (or core insulating column) 112 is formed on the inner surface of the channel layer 110. In one embodiment, the material of the insulating column 112 includes silicon oxide. After that, a channel plug 114 is formed in the opening 106, and the channel plug 114 contacts the channel layer 110. The channel plug 114 extends from the top surface of the uppermost insulating layer 102 to a certain depth of the opening 106. In one embodiment, the material of the channel plug 114 includes a semiconductor material with doping, such as doped polysilicon. The channel layer 110, the insulating column 112 and the channel plug 114 can be collectively referred to as a vertical channel column CP. The vertical channel column CP passes through the stacked structure SK1 and extends to the stop structure 103, and even extends to the insulating layer 101. The charge storage structure 108 surrounds the vertical outer surface of the vertical channel column CP.

[0117] Reference Figure 3G, a dielectric layer 128 is formed on the stacked structure SK1. The dielectric layer 128 is, for example, silicon oxide. Thereafter, a patterning process is performed to form one or more separation trenches 116. The separation trenches 116 extend through the dielectric layer 128 and the stacked structure SK1 to divide the stacked structure SK1 into a plurality of blocks (not shown). The separation trenches 116 may have wavy sidewalls, vertical sidewalls (not shown) or slightly inclined sidewalls (not shown).

[0118] Continue to refer to Figure 3G , a replacement process is performed to replace part of the intermediate layer 104 with a conductive layer 126. First, a selective etching process is performed so that the etchant contacts the intermediate layer 104 of the stacked structure SK1 on both sides through the separation channel 116. Thereby, part of the intermediate layer 104 is removed to form a plurality of horizontal openings (not shown), leaving the intermediate layer 104 in the peripheral region R2. The selective etching process can be an isotropic etching process, such as a wet etching process. The etchant used in the wet etching process is, for example, hot phosphoric acid. Then, a conductive layer 126 is formed in the horizontal opening. The conductive layer 126 can be used as a gate layer. The conductive layer 126, for example, includes a barrier layer and a metal layer. In one embodiment, the material of the barrier layer includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof. The material of the metal layer includes tungsten (W). Part of the intermediate layer 104 is replaced by the conductive layer 126, thereby forming a stacked structure (also referred to as a second stacked structure) SK2.

[0119] The stack structure SK2 and the stack structure SK1 together form a composite stack structure CSK. The stack structure SK1 includes a plurality of alternately stacked insulating layers 102 and a plurality of intermediate layers 104. The stack structure SK2 includes a plurality of alternately stacked insulating layers 102 and a plurality of conductive layers 126. A plurality of vertical channel pillars CP extend through the stack structure SK2.

[0120] Reference Figure 3G , then, a separation wall SLIT is formed in the separation trench 116. The separation wall SLIT may include a dielectric material and a conductor material. The dielectric material is, for example, silicon nitride or a silicon oxide / silicon nitride / silicon oxide composite material. The conductor material is, for example, doped polysilicon. The conductor material of the separation wall SLIT is isolated by the dielectric material to avoid contact with the conductive layer 126. Thereafter, a stop layer 129 is formed on the dielectric layer 128 to cover the top surface of the separation wall SLIT. The stop layer 129 is, for example, silicon nitride. A dielectric layer 130 is formed on the stop layer 129. The dielectric layer 130 is, for example, silicon oxide.

[0121] Reference Figure 3G and Figure 3HThen, a plurality of contact windows COA are formed in the dielectric layer 130 to the insulating structure 107A to electrically connect the conductive layer 126 and the vertical channel pillars CP respectively. In addition, a plurality of through holes TV are formed in the dielectric layer 130 to the insulating structure 107P. The method for forming the contact windows COA and the through holes TV can first form contact window holes and through hole openings, and then form a conductor material on the dielectric layer 130, and the conductor material is also filled in the contact window holes and through hole openings. Afterwards, an etch-back or chemical mechanical polishing process is performed to remove the conductor material on the dielectric layer 130.

[0122] Reference Fig. 3I , forming a second portion 32b of the interconnect structure 30 above the substrate 100. The second portion 32b of the interconnect structure 30 may include a multi-layer dielectric layer (not shown) and an interconnect line (not shown) formed in the multi-layer dielectric layer. The interconnect line includes a plurality of plugs (not shown) and a plurality of wires (not shown), etc. The dielectric layer separates adjacent wires. The wires may be connected by plugs, and the wires may be connected to the contact window COA by the plugs. The second portion 30b of the interconnect structure 30 may be formed by a single metal inlay, a dual metal inlay process, or any known method. The second portion 32b of the interconnect structure 30 may include a local bit line LBL and a local source line LSL. The local bit line LBL and the local source line LSL may be electrically connected to the vertical channel column CP via the contact window COA.

[0123] Reference Fig. 3I , forming a bonding structure 32 (shown in FIG. 1 ) on the second portion 30b of the interconnect structure 30. Figure 3J ). The second part 32b of the bonding structure 32 includes a bonding layer 34b, a bonding plug 36b and a bonding pad 38b. The bonding pad 38b is connected to the topmost wire 31b of the second part 30b of the interconnect structure 30 via the bonding plug 36b. The materials and forming methods of the bonding layer 34b, the bonding plug 36b and the bonding pad 38b may be the same or similar to those of the bonding layer 34a, the bonding plug 36a and the bonding pad 38a.

[0124] Reference Figure 3J , the substrate 100 is turned over. The step structure SC on the turned substrate 100 is changed into an anti-step structure RSC. The contact window COA is below the anti-step structure RSC. Fig. 3I and Figure 3J, the second portion 32b of the bonding structure 32 is bonded to the first portion 32a of the bonding structure 32 to form the bonding structure 32. In the bonding structure 32, the bonding layer 34b is bonded to the bonding layer 34a, and the bonding pad 38b is bonded to the bonding pad 38a. The bonding layer 34b and the bonding layer 34a may be bonded dielectric-to-dielectric. The bonding pad 38b and the bonding pad 38a may be bonded metal-to-metal. The bonding structure 32 is located in the interconnect structure 30, between the first portion 32a and the second portion 32b of the interconnect structure 30. The bonding structure 32, the first portion 32a and the second portion 32b form the interconnect structure 30. Since the component layer 20 is, for example, a complementary metal oxide semiconductor component (CMOS), the component layer 20 is bonded to the memory array via a bonding method (for example, located at Figure 3J Therefore, this structure can also be called a CMOS-Bonded-Array (CbA) structure.

[0125] Reference Figure 3J Then, the substrate 100 is removed to expose the insulating layer 101. The substrate 100 can be removed by polishing, polishing or etching.

[0126] Reference Figure 3J, a liner 44, a contact window 46, a wire 48 and a dielectric layer 50 of the interconnection structure 40 are formed on the insulating layer 101. The contact window 46 electrically connects the through hole TV and the wire 48. The contact window 46 is electrically isolated from the conductive layer 94 of the stop structure 103 by the liner 44. The method for forming the interconnection structure 40 is described as follows. First, a photolithography and etching process is performed to form a contact window opening 43 in the insulating layer 101 and the stop structure 103. Then, a liner 44 and a contact window 46 are formed in the contact window opening 43. The method for forming the liner 44 is, for example, to form a dielectric material on the insulating layer 101 and in the contact window opening 43, and then perform anisotropic etching. The method for forming the contact window 46 is, for example, to form a conductor material on the insulating layer 101 and in the contact window opening 43, and then perform a chemical mechanical polishing process or back etching. The dielectric material is, for example, silicon nitride or a silicon oxide / silicon nitride / silicon oxide composite layer. The conductor material is, for example, doped polysilicon. Afterwards, a wire 48 and a dielectric layer 50 are formed on the insulating layer 101. The material of the wire 48 is, for example, copper or tungsten. The dielectric layer 50 can be a single layer or a multilayer. The material of the dielectric layer 50 can be silicon oxide, silicon oxynitride, silicon nitride or a combination thereof. The interconnection structure 40 can be electrically connected to the interconnection structure 30 via the through hole TV. In addition to the connection through hole, the interconnection structure 30 can also be electrically connected to the vertical channel column CP or the conductive layer 126 via the contact window COA. At this point, the fabrication of the memory element SM2 is completed.

[0127] Reference Figure 3J The memory element SM2 is a CMOS-Bonded-Array (CbA) structure. However, the present invention is not limited thereto.

[0128] Reference Figure 6 In some other embodiments, the embodiments of the present invention may also be used in a structure where the device layer 20 is formed below the memory array. This structure may also be called a complementary metal oxide semiconductor device below the memory array (CMOS-Under-Array, CUA) structure.

[0129] Reference Figure 6 The stacked structure SK1 is formed above the interconnection structure 30 on the substrate 10. The device layer 20 is formed between the interconnection structure 30 below the stacked structure SK1 and the substrate 10. The step structure SC, the insulating structures 107A, 107E, 107P, the vertical channel pillars CP, the stacked structure SK2, the contact window COA and the through hole TV are formed by a method similar to the above embodiment.

[0130] Next, a dielectric layer 60 , a contact window 46 connected to the through-hole TV, a bit line (not shown), a source line (not shown), and an interconnection structure 40 are formed.

[0131] In summary, the stacked structure of the embodiment of the present invention is retained in the peripheral area. The through holes in the peripheral area are isolated from each other by multiple insulating structures. The multiple insulating structures are separated from each other. The multiple insulating structures are formed by removing a small portion of the stacked structure in the peripheral area and then backfilling a small amount of insulating material. Therefore, the deposition amount of insulating material can be reduced, and the time for polishing to remove excess insulating material can be reduced.

Claims

1. A memory element, comprising: A substrate, including a storage surface area and a peripheral area; as well as A composite stacking structure is located on the substrate in the storage surface area and the peripheral area, wherein the composite stacking structure includes: A first stacking structure, comprising a plurality of first insulating layers and a plurality of intermediate layers alternately stacked with each other, and located on the substrate in the peripheral area; a plurality of first insulating structures, separated from each other, extending through the first stacked structure in the peripheral region, and respectively surrounded by the plurality of first insulating layers and the plurality of intermediate layers; and A plurality of through holes extend through one of the plurality of first insulating structures. 2 . The memory element according to claim 1 , wherein the plurality of first insulating structures are separated from one another by the plurality of first insulating layers and the plurality of intermediate layers of the first stacked structure. 3 . The memory element according to claim 1 , wherein a shape of the plurality of first insulating structures comprises a rectangle, and outer sidewalls of the plurality of first insulating structures are in contact with the plurality of first insulating layers and the plurality of intermediate layers. The memory element according to claim 1 , wherein a ratio of a width to a height of the plurality of first insulating structures is less than 2. 5 . 5 . The memory element according to claim 1 , wherein a ratio of a sum of a plurality of diameters of the plurality of through holes along the first direction to a width of the corresponding first insulating structure along the first direction is 0.006-0.

15. 6 . The memory device according to claim 1 , wherein the shapes of the plurality of first insulating structures include ring shapes, and inner sidewalls and outer sidewalls of the plurality of first insulating structures are in contact with the plurality of first insulating layers and the plurality of intermediate layers, respectively. 7 . The memory element according to claim 1 , wherein the plurality of first insulating structures are separated from each other by the first stacked structure.

8. The memory device according to claim 1, wherein the composite stack structure further comprises: The second stacking structure includes the plurality of first insulating layers and the plurality of conductive layers alternately stacked with each other and is located on the substrate of the storage area. 9 . The memory element of claim 8 , wherein the second stack structure is surrounded by the first stack structure.

10. The memory element according to claim 8, further comprising: A plurality of second insulating structures, separated from each other, extending through the second stacked structure in the step region of the storage surface region, and respectively surrounded by the plurality of second insulating layers and the plurality of conductive layers; as well as A plurality of contact windows extend through one of the plurality of first insulating structures and are electrically connected to the plurality of conductive layers. 11 . The memory device according to claim 8 , further comprising a plurality of third insulating structures separating the first stack structure from the second stack structure in ends of the plurality of array regions of the memory plane region.

12. The memory element according to claim 11, further comprising: a fourth insulating structure surrounding the first stacking structure; as well as A sealing ring extends through the fourth insulating structure. 13 . The memory element according to claim 12 , wherein the fourth insulating structure is separated from the plurality of third insulating structures by the first stacked structure. 14 . The memory element according to claim 12 , wherein the fourth insulating structure is separated from the plurality of first insulating structures by the first stacked structure.

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