Probe delay time determination method and device, equipment, medium and product

Abstract

The invention discloses a probe delay time determination method and device, equipment, a medium and a product, and relates to the technical field of power electronics. The probe delay time determination method comprises the following steps: acquiring a collector current of a to-be-tested power semiconductor device in a double-pulse test circuit detected by a current probe and a first voltage between a collector and an emitter detected by a voltage probe; drawing a collector current waveform corresponding to the collector current and a first voltage waveform corresponding to the first voltage; determining a first moment and a second moment according to the collector current waveform; determining a third moment corresponding to the voltage peak according to the first voltage waveform; determining a fourth moment corresponding to the maximum change rate of the collector current according to the collector current waveform; and determining the delay time of the current probe relative to the voltage probe according to the fourth moment and the third moment. According to the scheme disclosed by the invention, the calibration efficiency of the time delay between the voltage probe and the current probe can be improved.

Description

Technical Field

[0001] The present application belongs to the field of power electronics technology, and in particular, relates to a method, device, equipment, medium and product for determining a probe delay time. Background Art

[0002] Power semiconductor devices are power electronic devices used in power conversion and control circuits of power equipment, such as insulated gate bipolar transistors (IGBT). Power semiconductor devices can be used in almost all electronic manufacturing industries, such as personal computers (PCs), servers, displays and various peripherals in the computer field, mobile phones, telephones and other various terminals and local equipment in the network communication field, home appliances and various digital products in the consumer electronics field, industrial computers, various instruments and various control equipment in the industrial control category, etc.

[0003] Before using power semiconductor devices, it is necessary to test the transient characteristics of power semiconductor devices to ensure the safety and stability of electronic equipment installed with power semiconductor devices. In the related art, voltage probes and current probes are usually used to detect the voltage waveform and current waveform during the switching transient process of power semiconductor devices to test the transient characteristics of power semiconductor devices. However, there is a time delay between the voltage probe and the current probe, and the transient characteristics of the tested power semiconductor devices are inaccurate. In order to improve the accuracy of the transient characteristics of power semiconductor devices, in the related art, the time delay between the voltage probe and the current probe is mainly calibrated by an offline calibration method. The efficiency of calibrating the time delay between the voltage probe and the current probe by an offline calibration method is low. Summary of the invention

[0004] The embodiments of the present application provide a probe delay time determination method, device, equipment, medium and product, which can solve the problem of low efficiency in calibrating the time delay between a voltage probe and a current probe.

[0005] In a first aspect, an embodiment of the present application provides a method for determining a probe delay time, comprising:

[0006] Acquire a collector current of a power semiconductor device to be tested in a double pulse test circuit detected by a current probe and a first voltage between a collector and an emitter of the power semiconductor device to be tested detected by a voltage probe, wherein the collector current and the first voltage are respectively a current and a voltage during a period in which a double pulse signal is sent to a gate of the power semiconductor device to be tested;

[0007] Draw a waveform corresponding to the collector current and a waveform corresponding to the first voltage respectively to obtain a collector current waveform and a first voltage waveform;

[0008] Determine a first moment and a second moment according to the collector current waveform, wherein the first moment is the moment when the collector current starts to decrease, and the second moment is the moment when the collector current decreases to a preset current;

[0009] Determining a third time corresponding to a voltage peak according to the first voltage waveform;

[0010] Determine, according to the collector current waveform, a fourth moment corresponding to a maximum rate of change of the collector current between the first moment and the second moment;

[0011] A delay time of the current probe relative to the voltage probe is determined according to the fourth moment and the third moment.

[0012] In a second aspect, an embodiment of the present application provides a probe delay time determination device, comprising:

[0013] An acquisition module, used for acquiring a collector current of a power semiconductor device to be tested in a double pulse test circuit detected by a current probe and a first voltage between a collector and an emitter of the power semiconductor device to be tested detected by a voltage probe, wherein the collector current and the first voltage are respectively a current and a voltage during a period in which a double pulse signal is sent to a gate of the power semiconductor device to be tested;

[0014] A drawing module, used to draw a waveform corresponding to the collector current and a waveform corresponding to the first voltage respectively, to obtain a collector current waveform and a first voltage waveform;

[0015] A first determination module is used to determine a first moment and a second moment according to the collector current waveform, wherein the first moment is the moment when the collector current starts to decrease, and the second moment is the moment when the collector current decreases to a preset current;

[0016] A second determining module, configured to determine a third time corresponding to a voltage peak according to the first voltage waveform;

[0017] A third determining module, configured to determine, according to the collector current waveform, a fourth moment corresponding to a maximum rate of change of the collector current between the first moment and the second moment;

[0018] The fourth determining module is used to determine the delay time of the current probe relative to the voltage probe according to the fourth moment and the third moment.

[0019] In a third aspect, an embodiment of the present application provides an electronic device, comprising: a processor and a memory storing computer program instructions; when the processor executes the computer program instructions, the steps of the probe delay time determination method provided in the embodiment of the present application are implemented.

[0020] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the steps of the probe delay time determination method provided in the embodiment of the present application are implemented.

[0021] In a fifth aspect, an embodiment of the present application provides a computer program product, which includes computer program instructions. When the computer program instructions are executed by a processor, the steps of the probe delay time determination method provided in the embodiment of the present application are implemented.

[0022] In the embodiment of the present application, the collector current of the power semiconductor device to be tested in the double pulse test circuit detected by the current probe and the first voltage between the collector and the emitter of the power semiconductor device to be tested detected by the voltage probe are obtained; the collector current waveform corresponding to the collector current and the first voltage waveform corresponding to the first voltage are drawn respectively; according to the collector current waveform, the first moment when the collector current starts to decrease and the second moment when the collector current decreases to the preset current are determined; according to the first voltage waveform, the third moment corresponding to the voltage spike is determined; according to the collector current waveform, the fourth moment corresponding to the maximum rate of change of the collector current between the first moment and the second moment is determined; according to the fourth moment and the third moment, the delay time of the current probe relative to the voltage probe is determined. In this way, when the power semiconductor device to be tested is tested by the double pulse test circuit, the delay time of the current probe relative to the voltage probe can be determined, and there is no need to calibrate the voltage probe and the current probe offline, which can improve the calibration efficiency of the time delay between the voltage probe and the current probe, and thus improve the test efficiency of the transient characteristics of the power semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solution of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0024] Figure 1 It is a flowchart of a method for determining a probe delay time provided in an embodiment of the present application;

[0025] Figure 2 is a schematic diagram of the structure of a double pulse test circuit provided in an embodiment of the present application;

[0026] Figure 3 is a schematic diagram of an Ic waveform and a Vce waveform provided in an embodiment of the present application;

[0027] Figure 4 It is a schematic diagram of a Vce waveform and a Udc+Ls0×dIc / dt waveform provided in an embodiment of the present application;

[0028] Figure 5 Schematic diagram of the Vce waveform and the compensated Udc+Ls0×dIc / dt waveform provided in the embodiment of the present application;

[0029] Figure 6 is a schematic diagram of the structure of a probe delay time determination device provided in an embodiment of the present application;

[0030] Figure 7 It is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0031] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0032] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0033] The following, in conjunction with the accompanying drawings, describes in detail the probe delay time determination method, device, equipment, medium and product provided in the embodiments of the present application through specific embodiments and their application scenarios.

[0034] In some possible implementations of the present application, the probe delay time determination method provided by the present application embodiment can be applied to electronic devices. The electronic device can be a terminal, or other devices other than the terminal. Exemplary, the electronic device can be a mobile phone, a tablet computer, a laptop computer, a palmtop computer, a vehicle-mounted electronic device, a mobile Internet device (Mobile Internet Device, MID), an augmented reality (augmented reality, AR) / virtual reality (virtualreality, VR) device, a robot, a wearable device, an ultra-mobile personal computer (ultra-mobile personalcomputer, UMPC), a netbook or a personal digital assistant (personal digital assistant, PDA), etc., and can also be a server, a network attached storage (Network Attached Storage, NAS), a personal computer (personalcomputer, PC), a television (television, TV), a teller machine or a self-service machine, etc., and the present application embodiment is not specifically limited.

[0035] Figure 1 FIG. 1 is a flow chart of a method for determining a probe delay time provided in an embodiment of the present application. Figure 1 As shown, the probe delay time determination method may include:

[0036] Step 101: obtaining a collector current of a power semiconductor device to be tested in a double pulse test circuit detected by a current probe and a first voltage between the collector and the emitter of the power semiconductor device to be tested detected by a voltage probe, wherein the collector current and the first voltage are respectively a current and a voltage during a period in which a double pulse signal is sent to a gate of the power semiconductor device to be tested;

[0037] In some possible implementations of the embodiments of the present application, the double pulse test circuit provided in the embodiments of the present application is as follows: Figure 2 shown. Figure 2 Schematic diagram of the structure of the double pulse test circuit provided in the embodiment of the present application. Figure 2 In the figure, T1 is the power semiconductor device to be tested, T2 is the auxiliary test power semiconductor device, Udc is the DC bus voltage, Ls is the stray inductance in the loop, and Lload is the load.

[0038] In some possible implementations of the embodiments of the present application, the voltage probe in the embodiments of the present application may be a differential probe or an optical isolation probe.

[0039] In some possible implementations of the embodiments of the present application, when the collector current of the power semiconductor device to be tested in the double pulse test circuit is detected by a current probe, a Rogowski coil or a shunt may be used.

[0040] In some possible implementations of the embodiments of the present application, it is assumed that the period of the double pulse signal is a time period from time t0 to time t3. The double pulse signal includes: a pulse signal that turns on the power semiconductor device to be tested in the time period from time t0 to time t1, a pulse signal that turns off the power semiconductor device to be tested in the time period from time t1 to time t2, and a pulse signal that turns on the power semiconductor device to be tested in the time period from time t2 to time t3. In the time period from time t0 to time t3, the power semiconductor device to be tested is turned on twice and turned off once.

[0041] In some possible implementations of the embodiments of the present application, a double pulse signal can be sent to the gate of the power semiconductor device to be tested in the double pulse test circuit, the collector current of the power semiconductor device to be tested can be detected using a current probe, and the voltage between the collector and emitter of the power semiconductor device to be tested can be detected using a voltage probe.

[0042] Step 102: respectively plotting a waveform corresponding to the collector current and a waveform corresponding to the first voltage to obtain a collector current waveform and a first voltage waveform;

[0043] In some possible implementations of the embodiments of the present application, the collector current of the power semiconductor device to be tested is recorded as Ic, and the first voltage between the emitters of the power semiconductor device to be tested is recorded as Vce. Figure 3 As shown, Figure 3 It is a schematic diagram of the Ic waveform and the Vce waveform provided in the embodiment of the present application.

[0044] Step 103: determining a first moment and a second moment according to the collector current waveform, wherein the first moment is the moment when the collector current starts to decrease, and the second moment is the moment when the collector current decreases to a preset current;

[0045] In some possible implementations of the embodiments of the present application, the preset current in the embodiments of the present application can be set according to actual needs, for example, 10% of the load current.

[0046] according to Figure 3 The Ic waveform shown can determine the time T0 when Ic starts to decrease and the time T1 when Ic decreases to the preset current. Figure 3 T0 and T1 in.

[0047] Step 104: determining a third time corresponding to a voltage peak according to the first voltage waveform;

[0048] according to Figure 3 The Vce waveform shown can be used to obtain the third time T3 corresponding to the voltage peak Vcemax, see Figure 3 T3 in.

[0049] Step 105: determining a fourth moment corresponding to a maximum rate of change of the collector current between the first moment and the second moment according to the collector current waveform;

[0050] In some possible implementations of the embodiments of the present application, before step 105, the rate of change of the collector current at each moment between the first moment and the second moment may be determined according to the following formula (1):

[0051]

[0052] Wherein, in formula (1), dIc / dt(t) is the rate of change of the collector current corresponding to time t, Ic(t+t0) is the collector current at time t+t0, Ic(t) is the collector current at time t, t0 is the sampling interval. Time t is any time between the first time and the second time.

[0053] After determining the change rate of the collector current at each moment between the first moment and the second moment, the maximum change rate of the collector current between the first moment and the second moment can be determined, and then the fourth moment T4 corresponding to the maximum change rate of the collector current between the first moment and the second moment can be obtained.

[0054] Step 106: Determine the delay time of the current probe relative to the voltage probe according to the fourth moment and the third moment.

[0055] In some possible implementations of the embodiment of the present application, the difference between the fourth moment and the third moment may be determined as the delay time of the current probe relative to the voltage probe.

[0056] In the embodiment of the present application, the collector current of the power semiconductor device to be tested in the double pulse test circuit detected by the current probe and the first voltage between the collector and the emitter of the power semiconductor device to be tested detected by the voltage probe are obtained; the collector current waveform corresponding to the collector current and the first voltage waveform corresponding to the first voltage are drawn respectively; according to the collector current waveform, the first moment when the collector current starts to decrease and the second moment when the collector current decreases to the preset current are determined; according to the first voltage waveform, the third moment corresponding to the voltage spike is determined; according to the collector current waveform, the fourth moment corresponding to the maximum rate of change of the collector current between the first moment and the second moment is determined; according to the fourth moment and the third moment, the delay time of the current probe relative to the voltage probe is determined. In this way, when the power semiconductor device to be tested is tested by the double pulse test circuit, the delay time of the current probe relative to the voltage probe can be determined, and there is no need to calibrate the voltage probe and the current probe offline, which can improve the calibration efficiency of the time delay between the voltage probe and the current probe, and thus improve the test efficiency of the transient characteristics of the power semiconductor device.

[0057] In some possible implementations of the embodiments of the present application, due to the influence of the sampling interval, the accuracy of directly determining the difference between the fourth moment and the third moment as the delay time of the current probe relative to the voltage probe is not high. Based on this, the difference between the fourth moment and the third moment can be determined as the first delay time of the current probe relative to the voltage probe; the inductance value of the stray inductance in the double pulse test circuit is determined according to the maximum change rate, the voltage spike and the DC bus voltage in the double pulse test circuit; the second voltage waveform corresponding to the current probe is determined according to the inductance value, the change rate of the collector current corresponding to each moment between the first moment and the second moment, and the DC bus voltage; the second delay time of the current probe relative to the voltage probe is determined according to the second voltage waveform and the first voltage waveform; the final delay time of the current probe relative to the voltage probe is determined according to the first delay time and the second delay time.

[0058] In some possible implementations of the embodiments of the present application, a first delay time Δt1 of the current probe relative to the voltage probe is equal to T4 - T3.

[0059] In some possible implementations of the embodiments of the present application, the voltage spike is caused by the current change rate of the stray inductance (i.e., the change rate of the collector current), and the DC bus voltage, the voltage between the collector and the emitter of the power semiconductor device to be tested, the inductance value of the stray inductance, and the change rate of the collector current have a corresponding relationship as shown in the following formula (2):

[0060] Vce-Udc=Ls0×dIc / dt (2)

[0061] In formula (2), Vce is the voltage between the collector and the emitter of the power semiconductor device to be tested, Udc is the DC bus voltage, Ls0 is the inductance value of the stray inductance, and dIc / dt is the rate of change of the collector current.

[0062] It can be seen from formula (2) that when the DC bus voltage Udc and the inductance value Ls0 of the stray inductance remain unchanged, when the rate of change of the collector current reaches the maximum value dIcmax, the voltage between the collector and the emitter of the power semiconductor device to be tested reaches the voltage peak Vcemax. Based on this, the inductance value Ls0 of the stray inductance can be calculated according to the following formula (3):

[0063]

[0064] In formula (3), Ls0 is the inductance value of the stray inductance, Vcemax is the voltage peak, Udc is the DC bus voltage, and dIcmax is the maximum change rate of the collector current.

[0065] The voltage peak Vcemax can be obtained through the Vce waveform; after the change rate of the collector current at each moment between the first moment and the second moment is determined according to the above formula (1), the maximum change rate dIcmax of the collector current between the first moment and the second moment can be determined.

[0066] After the inductance value Ls0 of the stray inductance is determined, the waveform of the second voltage Udc+Ls0×dIc / dt corresponding to the current probe (i.e., the second voltage waveform) can be determined. Figure 4 As shown, Figure 4 It is a schematic diagram of the Vce waveform and the Udc+Ls0×dIc / dt waveform provided in the embodiment of the present application.

[0067] In some possible implementations of the embodiments of the present application, when determining the second delay time of the current probe relative to the voltage probe based on the second voltage waveform and the first voltage waveform, the second voltage waveform can be shifted in the opposite direction of the time axis by the first delay time to obtain a third voltage waveform; determine the time length corresponding to the change of the third voltage waveform to a fourth voltage waveform that matches the curve characteristics of the first voltage waveform; and determine the time length as the second delay time.

[0068] Assuming that the curve characteristics of the voltage waveform obtained by shifting the third voltage waveform in the opposite direction of the time axis for a period of time match the curve characteristics of the first voltage waveform, then the period of time is the second delay time, and the voltage waveform obtained by shifting the third voltage waveform in the opposite direction of the time axis for the second delay time is the fourth voltage waveform.

[0069] In some possible implementations of the embodiments of the present application, the time duration corresponding to changing the third voltage waveform into a fourth voltage waveform matching the curve characteristics of the first voltage waveform may be determined by using a post-interpolation optimization method or a direct observation method.

[0070] For example, in Figure 4 In the embodiment, according to the Vce waveform and the Udc+Ls0×dIc / dt waveform, it is determined that the second delay time of the current probe relative to the voltage probe is △t2.

[0071] In some possible implementations of the present application, the sum of the first delay time Δt1 and the second delay time Δt2 can be determined as the final delay time of the current probe relative to the voltage probe, that is, the final delay time of the current probe relative to the voltage probe Δt=Δt1+Δt2.

[0072] In the embodiment of the present application, the accuracy of calibrating the time delay between the voltage probe and the current probe can be improved.

[0073] After determining the final delay time △t of the current probe relative to the voltage probe, the current probe can be compensated to synchronize the detection time of the current probe and the voltage probe. For example, shift the Ic waveform to the left by △t time, and shift the Udc+Ls0×dIc / dt waveform to the left by △t time. Figure 5 As shown, Figure 5 It is a schematic diagram of the Vce waveform and the compensated Udc+Ls0×dIc / dt waveform provided in the embodiment of the present application.

[0074] In an embodiment of the present application, by performing time compensation on the current probe, the collector current waveform can be synchronized with the voltage waveform corresponding to the voltage between the collector and the emitter, which can reduce the error in calculating the switching loss of the power semiconductor device and improve the accuracy of the switching loss of the power semiconductor device.

[0075] Corresponding to the above method embodiment, the present application embodiment also provides a probe delay time determination device, such as Figure 6 shown. Figure 6 is a schematic diagram of the structure of a probe delay time determination device provided in an embodiment of the present application. The probe delay time determination device 600 may include:

[0076] An acquisition module 601 is used to acquire a collector current of a power semiconductor device to be tested in a double pulse test circuit detected by a current probe and a first voltage between a collector and an emitter of the power semiconductor device to be tested detected by a voltage probe, wherein the collector current and the first voltage are respectively a current and a voltage during a period in which a double pulse signal is sent to a gate of the power semiconductor device to be tested;

[0077] A drawing module 602 is used to draw a waveform corresponding to the collector current and a waveform corresponding to the first voltage respectively, to obtain a collector current waveform and a first voltage waveform;

[0078] A first determination module 603 is used to determine a first moment and a second moment according to the collector current waveform, wherein the first moment is the moment when the collector current starts to decrease, and the second moment is the moment when the collector current decreases to a preset current;

[0079] A second determining module 604, configured to determine a third time corresponding to a voltage peak according to the first voltage waveform;

[0080] A third determining module 605, configured to determine, based on the collector current waveform, a fourth moment corresponding to a maximum rate of change of the collector current between the first moment and the second moment;

[0081] The fourth determining module 606 is used to determine the delay time of the current probe relative to the voltage probe according to the fourth moment and the third moment.

[0082] In the embodiment of the present application, the collector current of the power semiconductor device to be tested in the double pulse test circuit detected by the current probe and the first voltage between the collector and the emitter of the power semiconductor device to be tested detected by the voltage probe are obtained; the collector current waveform corresponding to the collector current and the first voltage waveform corresponding to the first voltage are drawn respectively; according to the collector current waveform, the first moment when the collector current starts to decrease and the second moment when the collector current decreases to the preset current are determined; according to the first voltage waveform, the third moment corresponding to the voltage spike is determined; according to the collector current waveform, the fourth moment corresponding to the maximum rate of change of the collector current between the first moment and the second moment is determined; according to the fourth moment and the third moment, the delay time of the current probe relative to the voltage probe is determined. In this way, when the power semiconductor device to be tested is tested by the double pulse test circuit, the delay time of the current probe relative to the voltage probe can be determined, and there is no need to calibrate the voltage probe and the current probe offline, which can improve the calibration efficiency of the time delay between the voltage probe and the current probe, and thus improve the test efficiency of the transient characteristics of the power semiconductor device.

[0083] In some possible implementations of the embodiment of the present application, the fourth determining module 606 may include:

[0084] A first determining submodule, used for determining the difference between the fourth moment and the third moment as a first delay time of the current probe relative to the voltage probe;

[0085] A second determination submodule, for determining an inductance value of a stray inductance in a double pulse test circuit according to a maximum rate of change, a voltage spike, and a DC bus voltage in the double pulse test circuit;

[0086] A third determination submodule is used to determine a second voltage waveform corresponding to the current probe according to the inductance value, the rate of change of the collector current corresponding to each moment between the first moment and the second moment, and the DC bus voltage;

[0087] a fourth determination submodule, configured to determine a second delay time of the current probe relative to the voltage probe according to the second voltage waveform and the first voltage waveform;

[0088] The fifth determining submodule is used to determine a final delay time of the current probe relative to the voltage probe according to the first delay time and the second delay time.

[0089] In the embodiment of the present application, the accuracy of calibrating the time delay between the voltage probe and the current probe can be improved.

[0090] In some possible implementations of the embodiments of the present application, the second determining submodule may be specifically used to:

[0091] According to the above formula (3), the inductance value of the stray inductance in the double pulse test circuit is determined.

[0092] In some possible implementations of the embodiments of the present application, the fourth determining submodule may be specifically used to:

[0093] Shifting the second voltage waveform in the opposite direction of the time axis by the first delay time to obtain a third voltage waveform;

[0094] Determining a time duration corresponding to changing the third voltage waveform into a fourth voltage waveform matching a curve feature of the first voltage waveform;

[0095] This time duration is determined as the second delay time.

[0096] In some possible implementations of the embodiments of the present application, the fifth determining submodule may be specifically used to:

[0097] The sum of the first delay time and the second delay time is determined as a final delay time of the current probe relative to the voltage probe.

[0098] In some possible implementations of the embodiments of the present application, the probe delay time determination device provided in the embodiments of the present application may further include:

[0099] The fifth determination module is used to determine the rate of change of the collector current at each moment between the first moment and the second moment according to the above formula (1).

[0100] Figure 7 It is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application.

[0101] The electronic device may include a processor 701 and a memory 702 storing computer program instructions.

[0102] Specifically, the processor 701 may include a central processing unit (CPU), or an application specific integrated circuit (ASIC), or may be configured to implement one or more integrated circuits of the embodiments of the present application.

[0103] The memory 702 may include a large capacity memory for data or instructions. By way of example and not limitation, the memory 702 may include a hard disk drive (HDD), a floppy disk drive, a flash memory, an optical disk, a magneto-optical disk, a magnetic tape, or a universal serial bus (USB) drive or a combination of two or more of these. In appropriate cases, the memory 702 may include a removable or non-removable (or fixed) medium. In appropriate cases, the memory 702 may be inside or outside the electronic device. In some specific embodiments, the memory 702 is a non-volatile solid-state memory.

[0104] In some specific embodiments, the memory may include a read-only memory (ROM), a random access memory (RAM), a magnetic disk storage medium device, an optical storage medium device, a flash memory device, an electrical, optical or other physical / tangible memory storage device. Therefore, generally, the memory includes one or more tangible (non-transitory) computer-readable storage media (e.g., a memory device) encoded with software including computer executable instructions, and when the software is executed (e.g., by one or more processors), it is operable to perform the operations described with reference to the probe delay time determination method according to the present application.

[0105] The processor 701 reads and executes the computer program instructions stored in the memory 702 to implement the steps of the method for determining the probe delay time provided in the embodiment of the present application.

[0106] In one example, the electronic device may further include a communication interface 703 and a bus 710. Figure 7 As shown, the processor 701, the memory 702, and the communication interface 703 are connected via a bus 710 and communicate with each other.

[0107] The communication interface 703 is mainly used to implement communication between various modules, devices, units and / or equipment in the embodiments of the present application.

[0108] The bus 710 includes hardware, software or both, coupling the components of the electronic device to each other. For example, but not limitation, the bus may include an Accelerated Graphics Port (AGP) or other graphics bus, an Extended Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), a Hyper Transport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an InfiniBand interconnect, a Low Pin Count (LPC) bus, a memory bus, a Micro channel architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local Bus (VLB) bus or other suitable buses or a combination of two or more of these. Where appropriate, the bus 710 may include one or more buses. Although embodiments of the present application describe and illustrate a particular bus, the present application contemplates any suitable bus or interconnect.

[0109] The electronic device can execute the steps of the probe delay time determination method provided in the embodiment of the present application, thereby achieving the corresponding technical effects of the probe delay time determination method provided in the embodiment of the present application.

[0110] In addition, in combination with the probe delay time determination method in the above embodiment, the embodiment of the present application also provides a computer-readable storage medium for implementation. The computer-readable storage medium stores computer program instructions; when the computer program instructions are executed by the processor, the steps of the probe delay time determination method provided in the embodiment of the present application are implemented. Examples of computer-readable storage media include non-transitory computer-readable media, such as ROM, RAM, magnetic disk or optical disk, etc.

[0111] An embodiment of the present application provides a computer program product, which includes computer program instructions. When the computer program instructions are executed by a processor, the steps of the probe delay time determination method provided in the embodiment of the present application are implemented, and the same technical effect can be achieved. To avoid repetition, they will not be described here.

[0112] It should be clear that the present application is not limited to the specific configuration and processing described above and shown in the figures. For the sake of simplicity, a detailed description of the known method is omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the present application is not limited to the specific steps described and shown, and those skilled in the art can make various changes, modifications and additions, or change the order between the steps after understanding the spirit of the present application.

[0113] The functional blocks shown in the above-described block diagram can be implemented as hardware, software, firmware or a combination thereof. When implemented in hardware, it can be, for example, an electronic circuit, an application-specific integrated circuit (Application Specific Integrated Circuit, ASIC), appropriate firmware, plug-in, function card, etc. When implemented in software, the elements of the present application are programs or code segments used to perform the required tasks. The program or code segment can be stored in a machine-readable medium, or transmitted on a transmission medium or communication link by a data signal carried in a carrier. "Machine-readable medium" may include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable read-only memory (Erasable Read Only Memory, EROM), floppy disks, compact discs (Compact Disc Read-Only Memory, CD-ROM), optical disks, hard disks, optical fiber media, radio frequency (Radio Frequency, RF) links, etc. The code segment can be downloaded via a computer network such as the Internet, an intranet, etc.

[0114] It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, this application is not limited to the order of the above steps, that is, the steps can be performed in the order mentioned in the embodiment, or in a different order from the embodiment, or several steps can be performed simultaneously.

[0115] Aspects of the present disclosure are described above with reference to the flowchart and / or block diagram of the method, device (system) and computer program product according to the embodiment of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine so that these instructions executed by the processor of the computer or other programmable data processing device enable the implementation of the function / action specified in one or more boxes of the flowchart and / or block diagram. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field programmable logic circuit. It can also be understood that each box in the block diagram and / or flowchart and the combination of boxes in the block diagram and / or flowchart can also be implemented by dedicated hardware that performs a specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0116] The above is only a specific implementation of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included in the protection scope of this application.

Claims

1. A method for determining probe delay time, characterized in that: The method comprises: Acquire a collector current of a power semiconductor device to be tested in a double pulse test circuit detected by a current probe and a first voltage between the collector and the emitter of the power semiconductor device to be tested detected by a voltage probe, wherein the collector current and the first voltage are respectively a current and a voltage during a period in which a double pulse signal is sent to a gate of the power semiconductor device to be tested; Respectively plotting a waveform corresponding to the collector current and a waveform corresponding to the first voltage to obtain a collector current waveform and a first voltage waveform; Determine a first moment and a second moment according to the collector current waveform, wherein the first moment is the moment when the collector current starts to decrease, and the second moment is the moment when the collector current decreases to a preset current; determining a third time corresponding to a voltage spike according to the first voltage waveform; Determining, according to the collector current waveform, a fourth moment corresponding to a maximum rate of change of the collector current between the first moment and the second moment; A delay time of the current probe relative to the voltage probe is determined according to the fourth moment and the third moment.

2. The method according to claim 1, characterized in that: The step of determining the delay time of the current probe relative to the voltage probe according to the fourth moment and the third moment includes: Determine the difference between the fourth moment and the third moment as a first delay time of the current probe relative to the voltage probe; determining an inductance value of a stray inductance in the double pulse test circuit according to the maximum rate of change, the voltage spike, and a DC bus voltage in the double pulse test circuit; Determine a second voltage waveform corresponding to the current probe according to the inductance value, the rate of change of the collector current corresponding to each moment between the first moment and the second moment, and the DC bus voltage; determining a second delay time of the current probe relative to the voltage probe according to the second voltage waveform and the first voltage waveform; A final delay time of the current probe relative to the voltage probe is determined according to the first delay time and the second delay time.

3. The method according to claim 2, characterized in that Determining the inductance value of the stray inductance in the double pulse test circuit according to the maximum change rate, the voltage spike and the DC bus voltage in the double pulse test circuit includes: The inductance value is determined according to the following formula: Wherein, Ls0 is the inductance value, Vcemax is the voltage peak, Udc is the DC bus voltage, and dIcmax is the maximum change rate.

4. The method according to claim 2, characterized in that: Determining a second delay time of the current probe relative to the voltage probe according to the second voltage waveform and the first voltage waveform includes: Shifting the second voltage waveform in the opposite direction of the time axis by the first delay time to obtain a third voltage waveform; Determining a time duration corresponding to changing the third voltage waveform into a fourth voltage waveform matching a curve feature of the first voltage waveform; The duration is determined as the second delay time.

5. The method according to claim 2, characterized in that: The determining, according to the first delay time and the second delay time, a final delay time of the current probe relative to the voltage probe comprises: The sum of the first delay time and the second delay time is determined as the final delay time.

6. The method according to claim 1, characterized in that Before determining, based on the collector current waveform, a fourth moment corresponding to a maximum rate of change of the collector current between the first moment and the second moment, the method further comprises: The rate of change of the collector current at each moment between the first moment and the second moment is determined according to the following formula: Among them, dIc / dt(t) is the rate of change of the collector current corresponding to time t, Ic(t+t0) is the collector current at time t+t0, Ic(t) is the collector current at time t, and t0 is the sampling interval.

7. A probe delay time determination device, characterized in that: The device comprises: An acquisition module, used for acquiring a collector current of a power semiconductor device to be tested in a double pulse test circuit detected by a current probe and a first voltage between the collector and the emitter of the power semiconductor device to be tested detected by a voltage probe, wherein the collector current and the first voltage are respectively a current and a voltage during a period in which a double pulse signal is sent to a gate of the power semiconductor device to be tested; A drawing module, used for drawing a waveform corresponding to the collector current and a waveform corresponding to the first voltage respectively, to obtain a collector current waveform and a first voltage waveform; A first determining module, configured to determine a first moment and a second moment according to the collector current waveform, wherein the first moment is a moment when the collector current starts to decrease, and the second moment is a moment when the collector current decreases to a preset current; A second determining module, configured to determine a third time corresponding to a voltage peak according to the first voltage waveform; A third determining module, configured to determine, according to the collector current waveform, a fourth moment corresponding to a maximum rate of change of the collector current between the first moment and the second moment; The fourth determining module is used to determine the delay time of the current probe relative to the voltage probe according to the fourth moment and the third moment.

8. An electronic device, characterized in that: The electronic device comprises: a processor and a memory storing computer program instructions; The processor reads and executes the computer program instructions to implement the steps of the probe delay time determination method as described in any one of claims 1-6.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer program instructions, and when the computer program instructions are executed by a processor, the steps of the method for determining the probe delay time according to any one of claims 1 to 6 are implemented.

10. A computer program product, characterized in that The computer program product comprises computer program instructions, and when the computer program instructions are executed by a processor, the steps of the method for determining the probe delay time according to any one of claims 1 to 6 are implemented.

Images