Key thread bundle scheduling method and device

Abstract

The invention discloses a key thread bundle scheduling method and device, and relates to the technical field of GPGPU (General Purpose Graphics Processing Unit), a thread bundle which is executed in sequence and a thread bundle which is branched are scheduled at different frequencies, different scheduling schemes are appointed for the two types of thread bundles in the mode, the parallel performance of the sequence thread bundle is ensured not to be influenced to the greatest extent, and the scheduling efficiency is improved. And meanwhile, the operation of the branch thread bundles is accelerated, the problem that the operation time of the thread bundles is prolonged due to excessive thread branches is avoided, and the combining performance of the universal graphics processor is improved to a certain extent.

Description

Technical Field

[0001] The present invention relates to the field of GPGPU technology, and in particular to a key thread warp scheduling method and device. Background Art

[0002] Thread warp scheduling is a common concept in general-purpose graphics processing units (GPGPUs). A thread warp is a collection of a certain number of threads, which is the minimum execution granularity of a general-purpose graphics processor. The thread warp scheduler allocates the required storage resources and computing resources to the ready thread warps to ensure the correct execution of the thread warp tasks. The purpose of scheduling is to keep all resources busy, so that multiple thread warps can effectively share resources and improve the parallel performance of GPGPUs.

[0003] With the development of computer language and software technology (especially artificial intelligence technology), processors need to handle more and more branch judgments during real-time operation. Different from the design concept of CPU, which exchanges hardware resources for complex branch management, GPGPU concentrates the main resources on the computing core to improve the parallelism of calculations, and only implements branch management by serially executing each branch thread. In the application scenario of complex branch judgment, the serial execution of branch threads will not only reduce the utilization of hardware (at the same time, the threads of a branch in the thread bundle will occupy all resources), but also greatly extend the overall running time of the thread bundle as the number of branches increases, which ultimately affects the execution efficiency of the entire task. Summary of the invention

[0004] In order to overcome the deficiencies of the above technologies, the present invention provides a key thread warp scheduling method and device for meeting the efficient parallel computing requirements of GPGPU in complex branch judgment scenarios.

[0005] The technical solution adopted by the present invention to overcome the technical problems is:

[0006] A key warp scheduling method includes a branch management unit and a warp scheduling unit;

[0007] The scheduling method for sequentially executed thread warps is:

[0008] S1-1. The thread warp instructions executed sequentially are passed to the key thread warp discriminator of the branch management unit, and the key thread warp discriminator marks the sequentially executed threads as ordinary thread warps;

[0009] S1-2. The thread branch stack in the branch management unit stores the initial address of the thread marked as a normal thread warp as the instruction address of the next code to be executed in the stack entry, and stores the end address of the thread as the instruction address of the branch reunion point in the entry;

[0010] S1-3. The branch management unit sends the thread warp status and control information to the thread warp scheduling unit through the control interface;

[0011] S1-4. After receiving the control information, the thread warp scheduling unit identifies the thread warp as a normal thread warp, determines whether the thread warp is ready based on the computing and storage resources available in the current GPUGPU, and stores the ready thread warp in the scheduling queue of the thread warp scheduling unit;

[0012] The scheduling method for the thread warp of branch execution is:

[0013] S2-1. The thread warp instruction extracts the operand type by decoding, and the key thread warp discriminator marks the thread warp as a normal thread warp or a critical thread warp;

[0014] S2-2. The thread branch stack in the branch management unit stores the first instruction address of each branch marked as a normal warp or a critical warp as the instruction address of the next code to be executed in the stack entry, and the end address of the current branch at the end of the thread as the instruction address of the branch reunion point is stored in the entry;

[0015] S2-3. The branch management unit sends the thread warp status and control information to the thread warp scheduling unit through the control interface;

[0016] S2-4. After receiving the control information, the warp scheduling unit identifies whether the warp is a critical warp. The polling scheduler of the warp scheduling unit determines whether the warp is ready based on the computing and storage resources currently available in the GPGPU, and stores the ready warp in the scheduling queue of the warp scheduling unit.

[0017] Furthermore, in step S1-1, the critical warp discriminator decodes the sequentially executed warp instructions and extracts the operand type of the instructions. For the sequentially executed thread instructions, the operand is set to a non-branch jump type, and the critical warp discriminator marks the sequentially executed threads as ordinary warps.

[0018] Furthermore, in step S1-2, after the end address of the thread is stored in the entry as the instruction address of the branch reunion point, all bits of the thread mask in the entry are set to 1, and the key thread warp flag in the entry is set to 0.

[0019] Furthermore, in step S1-4, after receiving the control information, the thread warp scheduling unit identifies the thread warp as a normal thread warp and initializes the key thread warp counter corresponding to the thread warp in the thread warp scheduling unit to 0. The polling scheduler in the thread warp scheduling unit generates a scheduling ID according to the order in which the thread warps enter the thread warp scheduling unit and assigns the thread warp a normal priority.

[0020] Furthermore, in step S2-1, after the thread warp instruction extracts the operand type through decoding and before the first branch judgment occurs, the operand of the instruction is a non-branch jump type, and the critical thread warp discriminator marks the thread warp as a normal thread warp. When the first branch judgment occurs, the operand of the instruction is a branch jump type, and the critical thread warp discriminator marks the thread warp as a critical thread warp.

[0021] Furthermore, in step S2-1, the thread warp is marked as a critical thread warp before all branches are completed, and the initial state is restored after all branches are completed.

[0022] Furthermore, in step S2-2, a thread mask is set according to whether the thread needs to execute the branch. A thread mask bit of 1 indicates that the corresponding thread executes the branch, and a thread mask bit of 0 indicates that the corresponding thread does not execute the branch. The key thread bundle mark in the entry is defined according to the key thread bundle judgment result, the key thread bundle is 1, and the common thread bundle is 0.

[0023] Furthermore, in step S2-4, after the thread warp scheduling unit receives the control information and identifies whether the thread warp is a critical thread warp, it initializes the corresponding critical thread warp counter in the thread warp scheduling unit to half of the scheduling queue length; if the thread warp is identified as a critical thread warp, the initial value of the critical thread warp counter is reduced by half on the original basis; if the thread warp is identified as a common thread warp, the initial value of the critical thread warp counter is doubled on the original basis.

[0024] Furthermore, in step S2-4, when a thread warp completes one scheduling, the critical thread warp counter is reduced by 1. If the critical thread warp counter returns to zero, the corresponding thread warp is inserted into the front end of the scheduling queue again.

[0025] On the other hand, the present invention also relates to a key warp scheduling device, including a branch management unit and a warp scheduling unit;

[0026] The branch management unit includes:

[0027] The key warp discriminator is used to decode the warp instructions, identify the operands, and mark the warp type;

[0028] Thread branch stack, used to temporarily store thread warp state information stack;

[0029] The thread warp scheduling unit includes:

[0030] The polling scheduler is used to clear the initial value of the key thread bundle counter and store the thread information in the scheduling queue according to the polling scheduling strategy, waiting for scheduling;

[0031] Key warp counters, used to mark the warp type;

[0032] The scheduling queue is used to store the thread warp scheduling unit to clear the initial value of the key thread warp counter and store the thread information according to the polling scheduling policy.

[0033] The beneficial effects of the present invention are as follows: the scheduling strategy of the key thread bundle adopts the method of "marking the key thread bundle", marks the branch thread bundle and the sequential execution thread bundle as the key thread bundle and the ordinary thread bundle respectively, and executes different scheduling schemes. For the ordinary thread bundle, the scheduler assigns different scheduling IDs to them according to the order in which these thread bundles enter the scheduling unit, and assigns ordinary priorities, and selects the thread bundles in the ready state in turn to store them in the scheduling queue. For the key thread bundle, the scheduler adjusts the scheduling frequency of the thread bundle in real time according to the number of generated thread branches, and then inserts the ready key thread bundle into the scheduling queue preferentially. Finally, the two types of thread bundles are scheduled and executed in order at different frequencies. The core of the design is to schedule the thread bundles executed sequentially and the thread bundles with branches at different frequencies. This method specifies different scheduling schemes for the two types of thread bundles, which guarantees that the parallel performance of the sequential thread bundle is not affected to the greatest extent, and at the same time speeds up the operation of the branch thread bundle, avoids the problem of extending the thread bundle running time due to too many thread branches, and at the same time improves the parallel performance of the general graphics processor to a certain extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is an architecture diagram of the thread warp scheduling method of the present invention;

[0035] Figure 2 is a flow chart of a method for scheduling key thread warps of the present invention;

[0036] Figure 3 Provide a DC diagram for the complex threads of the present invention;

[0037] Figure 4 This is a diagram of the actual application of the scheduler of the present invention. DETAILED DESCRIPTION

[0038] The following is combined with Figure 1 To Attachment Figure 4 The preferred embodiments of the present invention are described in detail so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more definite definition of the protection scope of the present invention.

[0039] In the description of the present invention, it should be noted that the embodiments described in the present invention are only part of the embodiments of the present invention, rather than all of the embodiments; based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present invention.

[0040] The terms "first", "second", etc. in the specification and claims of this article and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of this article described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, device, product or equipment that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0041] Example 1

[0042] The critical thread bundle scheduling strategy adopts the method of "marking critical thread bundles", marking branch thread bundles and sequential execution thread bundles as critical thread bundles and ordinary thread bundles respectively, and executing different scheduling schemes. The specific scheduling strategy is that ordinary thread bundles are scheduled in a polling manner, and critical thread bundles have a higher scheduling frequency and are inserted into the scheduling queue with a higher priority to accelerate the execution of critical thread bundles. For ordinary thread bundles, the scheduler will assign different thread bundle IDs to them according to the order in which these thread bundles enter the scheduling unit, and assign them ordinary priorities, and select thread bundles in the ready state in turn to store them in the scheduling queue. For critical thread bundles, the scheduler adjusts the scheduling frequency of the thread bundle in real time according to the number of thread branches generated, and assigns a higher priority, and then inserts the ready critical thread bundle into the front of the scheduling queue. Finally, the two types of thread bundles are scheduled and executed at different frequencies and in an orderly manner. The core of this design is to schedule the sequentially executed thread bundles and the branched thread bundles at different frequencies. This method specifies different scheduling schemes for the two types of thread bundles, which maximizes the protection of the parallel performance of the sequential thread bundles. At the same time, it speeds up the operation of the branched thread bundles, avoids the problem of extended thread bundle execution time due to too many thread branches, and improves the parallel performance of the general-purpose graphics processor to a certain extent.

[0043] A key thread warp scheduling method of the present invention is as follows Figure 1 As shown in FIG. 1 , it includes a branch management unit and a warp scheduling unit. Figure 1It can be seen that the key warp scheduling method designed by the present invention consists of two parts: a branch management unit and a warp scheduling unit, wherein the branch management unit is implemented by a key warp discriminator and a thread branch stack; the warp scheduling unit is implemented by a polling scheduler, a key warp counter and a scheduling queue; the branch management unit and the warp scheduling unit are connected through a control interface.

[0044] As attached Figure 2 As shown in the figure, the branch management unit is mainly composed of a critical thread bundle discriminator and a thread branch stack. The critical thread bundle scheduler decodes the thread bundle instruction, extracts the operand type for judgment, and marks whether the thread bundle is a critical thread bundle. The thread branch stack is essentially a stack structure. The entries in the stack are pushed and popped, and the top pointer always points to the last entry that enters the stack. Each entry contains the following four fields: the instruction address of the branch reconvergence point (Reconvergence PC, RPC), whose value is determined by the address of the reconvergence point instruction that is executed first (for example, in Figure 3 After the execution of code block B in the thread branch flow graph, the three threads reunite at E after passing through two branch paths C and D. The E code block is called the first reunion point to be executed, i.e., the branch reunion point); the instruction address of the next code to be executed (Next PC, NPC), which stores the instruction address of the branch corresponding to the entry that needs to be executed; the thread mask, which represents whether each thread in the branch needs to be executed; the critical thread bundle mark, which is used to distinguish whether it is a critical thread bundle. The thread bundle scheduling unit mainly includes a polling scheduler, a critical thread bundle counter, and a scheduling queue. The polling scheduler is used to uniformly manage the scheduling of all thread bundles, the critical thread bundle counter is used to control the scheduling frequency of the two types of thread bundles (the critical thread bundle counter sets the initial value according to the thread bundle type, and dynamically adjusts it when a new branch is generated or the branch ends later), and the scheduling queue is used to store the thread bundles to be scheduled to realize the orderly execution of each thread bundle. The branch management unit and the thread bundle scheduling unit are connected by a control interface, which contains information such as the thread bundle status and the critical thread bundle identification result.

[0045] The scheduling method for sequentially executed thread warps is:

[0046] S1-1. The thread warp instructions executed sequentially are transmitted to the critical thread warp discriminator of the branch management unit, and the critical thread warp discriminator marks the sequentially executed threads as ordinary thread warps.

[0047] S1-2. The thread branch stack in the branch management unit stores the initial address of the thread marked as a normal thread bundle as the instruction address of the next code to be executed in the stack entry, and stores the end address of the thread as the instruction address of the branch reunion point in the entry.

[0048] S1-3. The branch management unit sends the thread warp status and control information to the thread warp scheduling unit through the control interface.

[0049] S1-4. After receiving the control information, the warp scheduling unit identifies the warp as a normal warp, determines whether the warp is ready based on the computing and storage resources currently available in the GPU, and stores the ready warp in the scheduling queue of the warp scheduling unit.

[0050] The scheduling method for the thread warp of branch execution is:

[0051] S2-1. The thread warp instruction is decoded to extract the operand type, and the critical thread warp discriminator marks the thread warp as a normal thread warp or a critical thread warp.

[0052] S2-2. The thread branch stack in the branch management unit stores the first instruction address of each branch marked as a normal thread bundle or a critical thread bundle as the instruction address of the next code to be executed in the stack entry, and stores the current branch end address of the thread as the instruction address of the branch reunion point in the entry.

[0053] S2-3. The branch management unit sends the thread warp status and control information to the thread warp scheduling unit through the control interface.

[0054] S2-4. After receiving the control information, the warp scheduling unit identifies whether the warp is a critical warp. The polling scheduler of the warp scheduling unit determines whether the warp is ready based on the computing and storage resources currently available in the GPGPU, and stores the ready warp in the scheduling queue of the warp scheduling unit.

[0055] In this embodiment, in step S1-1, the critical warp discriminator decodes the sequentially executed warp instructions and extracts the operand type of the instructions. For the sequentially executed thread instructions, the operand is set to a non-branch jump type, and the critical warp discriminator marks the sequentially executed threads as ordinary warps.

[0056] In this embodiment, after the end address of the thread is stored in the entry as the instruction address of the branch reunion point in step S1-2, all bits of the thread mask in the entry are set to 1 (sequential execution does not occur branches, and all threads execute the same instructions), and the key thread bundle mark in the entry is set to 0.

[0057] In this embodiment, after receiving the control information in step S1-4, the thread warp scheduling unit identifies the thread warp as a normal thread warp and initializes the key thread warp counter corresponding to the thread warp in the thread warp scheduling unit to 0 (indicating that the thread warp does not need to increase the calling frequency through technical methods), and the polling scheduler in the thread warp scheduling unit generates a scheduling ID according to the order in which the thread warps enter the thread warp scheduling unit and assigns the thread warp a normal priority.

[0058] In this embodiment, after the thread warp instruction in step S2-1 extracts the operand type by decoding and before the first branch judgment occurs, the operand of the instruction is a non-branch jump type, and the critical thread warp discriminator marks the thread warp as a normal thread warp. When the first branch judgment occurs, the operand of the instruction is a branch jump type, and the critical thread warp discriminator marks the thread warp as a critical thread warp.

[0059] In this embodiment, in step S2-1, the thread warp is marked as a critical thread warp before all branches are completed, and the initial state is restored after all branches are completed.

[0060] In this embodiment, in step S2-2, a thread mask is set according to whether the thread needs to execute the branch. A thread mask bit of 1 indicates that the corresponding thread executes the branch, and a thread mask bit of 0 indicates that the corresponding thread does not execute the branch. The critical thread bundle mark in the entry is defined according to the critical thread bundle judgment result, the critical thread bundle is 1, and the common thread bundle is 0.

[0061] In this embodiment, in step S2-4, after the thread warp scheduling unit receives the control information and identifies whether the thread warp is a critical thread warp, it initializes the corresponding critical thread warp counter in the thread warp scheduling unit to half of the scheduling queue length. If the thread warp is identified as a critical thread warp, the initial value of the critical thread warp counter is reduced by half on the original basis. If the thread warp is identified as a common thread warp, the initial value of the critical thread warp counter is doubled on the original basis. The calling frequency of the thread warp is changed by dynamically adjusting the initial value of the counter.

[0062] In this embodiment, in step S2-4, when the thread warp completes one scheduling, the critical thread warp counter is reduced by 1. If the critical thread warp counter is reset to zero (and then assigned an initial value and counted again), the corresponding thread warp is inserted into the front end of the scheduling queue again to achieve priority repeated scheduling.

[0063] As attached Figure 4As shown, the present invention will use a thread bundle scheduler constructed according to the critical thread bundle scheduling strategy to replace the basic polling scheduler, and the scheduler controls the calling frequency of different types of thread bundles to achieve efficient and orderly execution of each thread bundle. For thread bundles executed sequentially, the critical thread bundle scheduler reads a thread bundle instruction from the instruction cache, determines that the thread bundle is a common thread bundle, and sends the prepared thread bundle to the execution unit according to the basic polling rule. The execution unit completes the execution of all threads in the thread bundle within a single scheduling cycle, and then schedules other thread bundles in sequence; for thread bundles executed by branches, the critical thread bundle scheduler determines it as a critical thread bundle and sends it to the execution unit with a higher priority. The execution unit completes the execution of threads in a branch within a single scheduling cycle, and then schedules the thread bundle at a higher frequency until all branches in the thread bundle are completed.

[0064] Example 2

[0065] A key warp scheduling device includes a branch management unit and a warp scheduling unit;

[0066] The branch management unit includes:

[0067] The key warp discriminator is used to decode the warp instructions, identify the operands, and mark the warp type;

[0068] Thread branch stack, used to temporarily store thread warp state information stack;

[0069] The thread warp scheduling unit includes:

[0070] The polling scheduler is used to clear the initial value of the key thread bundle counter and store the thread information in the scheduling queue according to the polling scheduling strategy, waiting for scheduling;

[0071] Key warp counters, used to mark the warp type;

[0072] The scheduling queue is used to store the thread warp scheduling unit to clear the initial value of the key thread warp counter and store the thread information according to the polling scheduling policy.

[0073] When the scheduling system executes a sequential thread bundle, the key thread bundle discriminator decodes the thread bundle instruction, identifies the operand, and marks the type of the thread bundle; the branch management unit pushes the thread bundle status information into the thread branch stack for temporary storage, and transmits the control information of the thread bundle through the control interface; the thread bundle scheduling unit will clear the initial value of the key thread bundle counter, and store the thread information in the scheduling queue according to the polling scheduling strategy, waiting for scheduling. When the scheduling system executes a branch thread bundle, the key thread bundle discriminator marks the type of the thread bundle; the branch management unit first pushes the thread bundle status information into the thread branch stack, and then when the thread bundle generates a new branch or ends a branch, the management unit pushes or pops each branch thread into or out of the stack in turn, and transmits the control information of the thread bundle through the control interface; the thread bundle scheduling unit will set the initial value of the key thread bundle counter, and according to the value of the counter, insert the thread bundle into the front of the scheduling queue at a faster frequency and repeat the scheduling.

[0074] It should also be understood that in the embodiments of this article, the term "and / or" is only a description of the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0075] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this article.

[0076] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0077] In the several embodiments provided herein, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of the units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, or can be electrical, mechanical or other forms of connection.

[0078] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiments of this article.

[0079] In addition, each functional unit in each embodiment of this invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above integrated unit may be implemented in the form of hardware or in the form of software functional unit.

[0080] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this article is essentially or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of this article. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

[0081] Finally, it should be noted that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A critical thread warp scheduling method, characterized in that: Including a branch management unit and a warp scheduling unit; The scheduling method for sequentially executed thread warps is: S1-1. The thread warp instructions executed sequentially are passed to the key thread warp discriminator of the branch management unit, and the key thread warp discriminator marks the sequentially executed threads as ordinary thread warps; S1-2. The thread branch stack in the branch management unit stores the initial address of the thread marked as a normal thread warp as the instruction address of the next code to be executed in the stack entry, and stores the end address of the thread as the instruction address of the branch reunion point in the entry; S1-3. The branch management unit sends the thread warp status and control information to the thread warp scheduling unit through the control interface; S1-4. After receiving the control information, the thread warp scheduling unit identifies the thread warp as a normal thread warp, determines whether the thread warp is ready based on the computing and storage resources available in the current GPUGPU, and stores the ready thread warp in the scheduling queue of the thread warp scheduling unit; The scheduling method for the thread warp of branch execution is: S2-1. The thread warp instruction extracts the operand type by decoding, and the key thread warp discriminator marks the thread warp as a normal thread warp or a critical thread warp; S2-2. The thread branch stack in the branch management unit stores the first instruction address of each branch marked as a normal warp or a critical warp as the instruction address of the next code to be executed in the stack entry, and the end address of the current branch at the end of the thread as the instruction address of the branch reunion point is stored in the entry; S2-3. The branch management unit sends the thread warp status and control information to the thread warp scheduling unit through the control interface; S2-4. After receiving the control information, the warp scheduling unit identifies whether the warp is a critical warp. The polling scheduler of the warp scheduling unit determines whether the warp is ready based on the computing and storage resources currently available in the GPGPU, and stores the ready warp in the scheduling queue of the warp scheduling unit.

2. The critical thread warp scheduling method according to claim 1, characterized in that: In step S1-1, the critical warp discriminator decodes the sequentially executed warp instructions and extracts the operand type of the instructions. For the sequentially executed thread instructions, the operand is set to a non-branch jump type, and the critical warp discriminator marks the sequentially executed threads as ordinary warps.

3. The critical thread warp scheduling method according to claim 1, characterized in that: In step S1-2, the end address of the thread is stored in the entry as the instruction address of the branch reunion point, all bits of the thread mask in the entry are set to 1, and the key thread warp mark in the entry is set to 0.

4. The critical thread warp scheduling method according to claim 1, characterized in that: In step S1-4, after receiving the control information, the thread warp scheduling unit identifies the thread warp as a normal thread warp and initializes the key thread warp counter corresponding to the thread warp in the thread warp scheduling unit to 0. The polling scheduler in the thread warp scheduling unit generates a scheduling ID according to the order in which the thread warps enter the thread warp scheduling unit and assigns the thread warp a normal priority.

5. The critical thread warp scheduling method according to claim 1, characterized in that: In step S2-1, after the thread warp instruction extracts the operand type through decoding, before the first branch judgment occurs, the operand of the instruction is a non-branch jump type, and the critical thread warp discriminator marks the thread warp as a normal thread warp. When the first branch judgment occurs, the operand of the instruction is a branch jump type, and the critical thread warp discriminator marks the thread warp as a critical thread warp.

6. The critical thread warp scheduling method according to claim 5, characterized in that: In step S2-1, the thread warp is marked as a critical thread warp before all branches are completed, and the initial state is restored after all branches are completed.

7. The critical thread warp scheduling method according to claim 1, characterized in that: In step S2-2, a thread mask is set according to whether the thread needs to execute the branch. A thread mask bit of 1 indicates that the corresponding thread executes the branch, and a thread mask bit of 0 indicates that the corresponding thread does not execute the branch. The key thread warp mark in the entry is defined according to the key thread warp discrimination result, the key thread warp is 1, and the common thread warp is 0.

8. The critical thread warp scheduling method according to claim 1, characterized in that: In step S2-4, after the thread warp scheduling unit receives the control information and identifies whether the thread warp is a critical thread warp, it initializes the corresponding critical thread warp counter in the thread warp scheduling unit to half of the scheduling queue length. If the thread warp is identified as a critical thread warp, the initial value of the critical thread warp counter is reduced by half on the original basis. If the thread warp is identified as a common thread warp, the initial value of the critical thread warp counter is doubled on the original basis.

9. The critical thread warp scheduling method according to claim 1, characterized in that: In step S2-4, when the thread warp completes one scheduling, the critical thread warp counter is reduced by 1. If the critical thread warp counter returns to zero, the corresponding thread warp is inserted into the front end of the scheduling queue again.

10. A critical thread warp scheduling device, characterized in that: including a branch management unit and a warp scheduling unit; The branch management unit includes: The key warp discriminator is used to decode the warp instructions, identify the operands, and mark the warp type; Thread branch stack, used to temporarily store thread warp state information stack; The thread warp scheduling unit includes: The polling scheduler is used to clear the initial value of the key thread bundle counter and store the thread information in the scheduling queue according to the polling scheduling strategy, waiting for scheduling; Key warp counters, used to mark the warp type; The scheduling queue is used to store the thread warp scheduling unit to clear the initial value of the key thread warp counter and store the thread information according to the polling scheduling policy.

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