Data access method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention discloses a data access method and device, electronic equipment and a storage medium, storage data stored in a dynamic random access memory is copied, and the copied data is stored in other storage units different from the original storage data, so that under the condition that an access request is received, the data access efficiency is improved. In the embodiment of the invention, the corresponding target address is determined through the access address contained in the access request, the load information of the corresponding storage unit can be found, the load information is compared with the load information of the storage unit corresponding to the access address, and the storage unit with the minimum load is selected for data access. In this way, when the load of one storage unit is high, the other storage unit with the low load is selected for data access, the number of conflicts of the storage units can be reduced fundamentally, and therefore the delay of parallel data access of the dynamic random access memory is reduced.

Description

Technical Field

[0001] The present application relates to the field of data access, and in particular, to a data access method, device, electronic device and storage medium. Background Art

[0002] At present, with the continuous increase in CPU (Central Processing Unit) frequency, the delay in accessing DRAM (Dynamic Random Access Memory) has become a key bottleneck of the entire SoC (System-on-Chip) system, especially when multiple processes access DRAM in parallel.

[0003] In the related art, when multiple processes access DRAM in parallel, there may be a situation where read and write commands continuously access different rows in the same storage cell bank or storage cell group bank group, resulting in storage cell conflict bankconflict and storage cell group conflict bankgroup conflict, causing access delay to DRAM data access. Summary of the invention

[0004] To solve the above technical problems, embodiments of the present application provide a data access method, device, electronic device and storage medium, so as to reduce the access delay during parallel data access to a dynamic random access memory.

[0005] According to one aspect of an embodiment of the present application, a data access method is provided, comprising: upon receiving an access request, determining a target address that has a mapping relationship with the access address according to an access address for stored data contained in the access request; the target address is a storage address of copied data that is the same as the stored data, but the copied data and the stored data are respectively stored in different storage units; determining load information of the storage unit storing the copied data according to the target address, and determining load information of the storage unit storing the stored data according to the access address; comparing all acquired load information to determine the storage unit with the smallest load, and performing data access in the storage unit with the smallest load.

[0006] In some embodiments, before determining the corresponding target address according to the access address included in the access request, the method also includes: determining from historical data access records storage data whose access delay is greater than a preset delay threshold and whose access times are greater than a preset times threshold; copying the storage data to obtain copy data of the storage data; determining the storage address of the copy data of the storage data according to the storage address of the storage data; storing the copy data according to the storage address of the copy data, and establishing a mapping relationship between the storage address of the storage data and the storage address of the copy data.

[0007] In some embodiments, the data storage area includes multiple storage cell groups, each storage cell group includes multiple storage cells, each storage cell includes a first storage area and a second storage area, the first storage area is used to store storage data, and the second storage area is used to store copied data; the storage address includes a storage cell group address and a storage cell address; determining the storage address of the copied data based on the storage address of the storage data includes: performing a modulo operation on the storage cell group address and the storage cell address of the storage data, respectively, to obtain the storage cell group address and the storage cell address of the copied data; storing the copied data according to the storage address of the copied data includes: storing the copied data in an empty row in the second storage area corresponding to the storage cell group address and the storage cell address of the copied data.

[0008] In some embodiments, determining the load information of the storage unit storing the copied data according to the target address, and determining the load information of the storage unit storing the stored data according to the access address, includes: obtaining tag information corresponding to the target address; determining whether the copied data corresponding to the target address is valid data according to the tag information; if the copied data is valid data, determining the load information of the storage unit storing the copied data according to the target address, and determining the load information of the storage unit storing the stored data according to the access address.

[0009] In some embodiments, the method further includes: monitoring the data access bandwidth, and when the data access bandwidth is lower than a preset bandwidth threshold, counting the number of accesses to all replicated data; determining the replicated data with access times lower than the preset threshold as data to be updated, and updating the data to be updated.

[0010] In some embodiments, the updating of the data to be updated includes: determining from historical data access records new storage data whose access delay is greater than a preset delay threshold and whose access times are greater than a preset times threshold; copying the new storage data to obtain copy data of the new storage data; storing the copy data of the new storage data in the storage address of the data to be updated, and establishing a mapping relationship between the storage address of the new storage data and the storage address of the copy data of the new storage data.

[0011] In some embodiments, the method further includes: when a data rewrite instruction for a target storage unit is detected, obtaining load information of the target storage unit; wherein the target storage unit is two storage units storing the same data; when the load information of the two storage units is less than a preset load threshold, rewriting the data of the two storage units simultaneously; or, when only one storage unit has load information less than the preset load threshold, rewriting the data of the first storage unit less than the preset load threshold, and monitoring the load information of the second storage unit greater than the preset load threshold; when it is monitored that the load information of the second storage unit is less than the preset load threshold, reading the rewritten storage data from the first storage unit, and rewriting the data of the second storage unit according to the rewritten storage data. In some embodiments, According to one aspect of an embodiment of the present application, a data access device is provided, the device comprising: a first determination module, configured to, upon receiving an access request, determine a target address that has a mapping relationship with the access address according to an access address for stored data contained in the access request; the target address is a storage address of duplicate data that is the same as the stored data, but the duplicate data and the stored data are stored in different storage units; a second determination module, configured to determine load information of a storage unit storing the duplicate data according to the target address, and determine load information of a storage unit storing the stored data according to the access address; a data access module, configured to compare all acquired load information, determine the storage unit with the smallest load, and perform data access in the storage unit with the smallest load.

[0012] According to one aspect of an embodiment of the present application, an electronic device is provided, comprising: one or more processors; a storage device for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the electronic device implements the data access method as described above.

[0013] According to one aspect of an embodiment of the present application, a computer-readable storage medium is provided, on which computer-readable instructions are stored. When the computer-readable instructions are executed by a processor of a computer, the computer executes the above-mentioned data access method.

[0014] In the technical solution provided by the embodiment of the present application, the storage data stored in the dynamic random access memory is copied, and the copied data is stored in other storage units different from the original storage data. In this way, when an access request is received, the corresponding target address is determined by the access address included in the access request, and the load information of the corresponding storage unit can be found, and the load information is compared with the load information of the storage unit corresponding to the access address, and the storage unit with the smallest load is selected for data access. In this way, when the load of one storage unit is high, another storage unit with a lower load is selected for data access, which can fundamentally reduce the number of bank conflicts, thereby reducing the delay in parallel data access to the dynamic random access memory.

[0015] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work. In the drawings: Figure 1 is a schematic diagram of the structure of a DRAM shown in an exemplary embodiment of the present application; Figure 2 is an application schematic diagram of a storage unit access process shown in an exemplary embodiment of the present application; Figure 3 is a schematic diagram of an exemplary implementation environment of the present application; Figure 4 is a flow chart of a data access method shown in an exemplary embodiment of the present application; Figure 5 is a flow chart of a data access method shown in another exemplary embodiment of the present application; Figure 6 is a schematic diagram of the structure of a memory chip shown in an exemplary embodiment of the present application; Figure 7 is a flow chart of a data access method shown in another exemplary embodiment of the present application; Figure 8is a flow chart of a data access method shown in another exemplary embodiment of the present application; Fig. 9 is a flow chart of a data access method shown in another exemplary embodiment of the present application; Fig.10 is a structural diagram of a data access device according to an exemplary embodiment of the present application; Fig.11 It is a schematic diagram of the structure of a computer system of an exemplary electronic device of the present application. DETAILED DESCRIPTION

[0017] Here, exemplary embodiments will be described in detail, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments that are the same as the present application. Instead, they are only examples of devices and methods that are the same as some aspects of the present application as detailed in the attached claims.

[0018] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in the form of an application program, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0019] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0020] It should be noted that the "multiple" mentioned in this application refers to two or more than two. "And / or" describes the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship.

[0021] The following is an introduction and explanation of the technical terms and background technologies involved in this application: Cache (cache memory): located between the CPU (Central Processing Unit) and the main memory DRAM (Dynamic Random Access Memory), usually composed of SRAM (Static Random-Access Memory). The speed of CPU is much higher than that of memory. When CPU directly accesses data from memory, it has to wait for a certain clock cycle, while Cache has a fast access speed and can save part of the data that the CPU has just used or recycled. If the CPU needs to use this part of data again, it can directly call it from the cache, thus avoiding accessing data from memory with long delay, reducing the waiting time of CPU, and thus improving the efficiency of the system.

[0022] DRAM: Mainly used to store temporary data when the computer is running, including program code, variables, stacks, etc. DRAM, as the main memory of the computer, provides a relatively large storage capacity and moderate access speed. Compared with SRAM, DRAM has higher density and lower cost. This makes DRAM the main component of the main memory of modern computer systems.

[0023] See also Figure 1 and Figure 2 , Figure 1 is a schematic diagram of a DRAM structure shown in an exemplary embodiment of the present application, Figure 2 It is an application diagram of a storage unit access process shown in an exemplary embodiment of the present application; wherein, a DRAM physical address is composed of a channel, a rank, a bank group, a bank, a row, and a column, and the physical address determines the specific storage location of the read and write data.

[0024] When accessing a bank for reading or writing, the following process is involved: 1) The controller first sends an activation command, decodes the row address in the access address of the access request through the row address decoder, and then reads the storage data in the storage unit, for example, reads row0 in bank1 and puts it in the row buffer. Figure 2 As shown in the data flow ① in the figure, this process is called activation; 2) According to the physical address corresponding to the column, that is, the column address, the data is parsed from the row buffer through the Column Mux and returned to the controller; 3) When the row accessed by the access request is row1, the data stored in row0 in the row buffer needs to be written back to bank1 first, such as Figure 2 As shown in the data flow ②, this process is called precharge. In addition, continuous access to different rows in the same memory cell is called a bank conflict. 4) The controller then sends an activation command to read row 1 from bank 1 and put it in the row buffer. Finally, it reads and writes the row 1 data in the row buffer according to the physical address corresponding to the column.

[0025] Furthermore, when accessing the stored data in the bank, different banks, bank groups, rows, etc. have different time requirements for accessing them, as shown in Table 1, which is an example table of DRAM timing parameters.

[0026]

[0027] Table 1 In Table 1, the timing parameter tCCD_S is used to characterize the delay of consecutive identical read / write commands to banks in different bankgroups of the same rank, which is 4 cycles; the timing parameter tCCD_L is used to characterize the delay of consecutive identical read / write commands to banks in the same rank and same bankgroup, which is 8 cycles; the timing parameter tRTP is used to characterize the delay between read / write commands and charge commands in the same bank, which is 12 cycles; the timing parameter tRAS is used to characterize the delay between activate commands and precharge commands in the same bank, which is 56 cycles; the timing parameter tRP is used to characterize the delay between precharge commands and activate commands in the same bank, which is 22 cycles; the timing parameter tRCD is used to characterize the delay between activate commands and read / write commands in the same bank, which is 22 cycles. It can be seen that tRAS has the longest delay time, so when actually accessing DRAM, row switching of the same bank should be avoided as much as possible, that is, bank conflict should be avoided.

[0028] In the related art, since the lower physical address changes the fastest and the higher physical address changes the slowest, in order to reduce row conflicts, the row address is placed at the highest physical address, the column address is placed at the lowest physical address, and the bank address / bank group address is placed between the row address and the column address. This address mapping method will lead to poor bank group interleaving, and read and write requests will enter the same bank group, which will increase access conflicts between different bank groups and banks, reduce the actual throughput of the memory, and thus increase the access delay of the DRAM.

[0029] Based on this, the present application proposes a data access method, device, electronic device and storage medium, which copies the storage data stored in the DRAM and stores the copied data in other storage units different from the original storage data. In this way, when an access request is received, the corresponding target address is determined by the access address contained in the access request, and the load information of the corresponding storage unit can be found, and it is compared with the load information of the storage unit corresponding to the access address, and the storage unit with the smallest load is selected for data access. In this way, when the load of one storage unit is high, by selecting another storage unit with a lower load for data access, the number of bank conflicts and bank group conflicts can be fundamentally reduced, thereby reducing the delay in parallel data access to the dynamic random access memory.

[0030] See also Figure 3 , Figure 3 FIG. 1 is a schematic diagram of an exemplary implementation environment of the present application. Figure 3 As shown, the implementation environment includes a DRAM controller 110 and a DRAM 120. A communication connection is pre-established between the DRAM controller 110 and the DRAM 120.

[0031] The DRAM controller 110 is used to manage and plan the data transmission from the DRAM 120 to the CPU, ensuring that the data can flow accurately and efficiently between the two components. The DRAM controller 110 performs necessary control on the access to the DRAM 120 according to certain timing rules, including the control of address signals, data signals, and various command signals, so that the host device (such as the CPU) can access the stored data on the DRAM 120. For example, the DRAM controller receives the address signal from the CPU and decodes it into the storage address inside the DRAM 120. According to the read and write instructions of the CPU, the DRAM controller 110 exchanges data with the DRAM 120 through the data bus; in the read operation, the DRAM controller 110 reads data from the DRAM 120 and sends it to the CPU; in the write operation, the DRAM controller writes the data provided by the CPU into the DRAM 120. In addition, since the storage unit of the DRAM 120 is composed of capacitors and transistors, the capacitor has leakage, so it needs to be refreshed regularly to maintain the accuracy of the data. The DRAM controller 110 is used to control the execution of the refresh operation to ensure that the data in the DRAM 120 will not be lost.

[0032] The storage unit of DRAM 120 is composed of a capacitor and a transistor (or other switching circuit). The capacitor is used to store charge, while the transistor acts as a switch to control the charging and discharging process of the capacitor and the reading and writing of data. Since the capacitor leaks electricity, DRAM 120 needs to be refreshed regularly to maintain the accuracy of the data. The refresh operation is automatically performed by DRAM controller 110 to ensure that the data stored in DRAM 120 is not lost.

[0033] In some embodiments, upon receiving an access request, the DRAM controller 110 determines a target address that has a mapping relationship with the access address based on the access address for the stored data contained in the access request; the target address is a storage address of duplicate data that is the same as the stored data, but the duplicate data and the stored data are stored in different storage units; the DRAM controller 110 determines the load information of the storage unit that stores the duplicate data based on the target address, and determines the load information of the storage unit that stores the stored data based on the access address; the DRAM controller 110 compares all the acquired load information, determines the storage unit with the smallest load, and accesses data in the storage unit with the smallest load.

[0034] See also Figure 4 , Figure 4 1 is a flowchart of a data access method shown in an exemplary embodiment of the present application, which can be applied to an electronic device provided with a memory chip, the memory chip including a DRAM controller and a DRAM. The electronic device includes but is not limited to a computer, a server, a tablet computer or a mobile phone.

[0035] The data access method proposed in the embodiment of the present application is described in detail below using a computer as the specific execution subject.

[0036] like Figure 4 As shown, in an exemplary embodiment, the data access method at least includes steps S410 to S430, which are described in detail as follows: Step S410, when receiving an access request, determine a target address that is mapped to the access address according to the access address for the stored data included in the access request, wherein the target address is the storage address of the duplicate data that is the same as the stored data, but the duplicate data and the stored data are stored in different storage units.

[0037] It can be understood that the access request includes an access address, which is used to access data in the corresponding storage unit in the DRAM; the data storage area in the DRAM includes a first area and a second area, wherein the stored data is stored in the storage unit in the first area, and the copied data identical to the stored data is stored in the storage unit in the second area.

[0038] Step S420, determining the load information of the storage unit storing the copied data according to the target address, and determining the load information of the storage unit storing the stored data according to the access address.

[0039] It is understandable that in the embodiment of the present application, a storage unit status information library can be set in the DRAM controller, through which the real-time load information of each storage unit can be found, which makes it easier for the DRAM controller to select the storage unit with the smallest load for data access.

[0040] Exemplarily, determining the load information of the storage unit storing the copied data according to the target address includes: searching for the load information of the storage unit corresponding to the target address from a preset storage unit status information library, wherein the storage unit status information library stores the corresponding relationship between the target address and the load information of the storage unit.

[0041] Exemplarily, determining the load information of the storage unit storing the storage data according to the target address includes: searching for the load information of the storage unit corresponding to the access address from a preset storage unit status information library, wherein the storage unit status information library stores the corresponding relationship between the access address and the load information of the storage unit.

[0042] Step S430 , comparing all the acquired load information, determining the storage unit with the smallest load, and performing data access in the storage unit with the smallest load.

[0043] In the embodiment of the present application, by counting the number of times each storage unit is accessed in the access request in the historical data access record, frequently accessed data is copied and stored in different banks. When one of the banks is in a high access state, the bank with low load is accessed, so that data can be obtained faster. At the same time, the present application does not change any structure of DRAM, and only needs to adjust the address mapping method of the DRAM controller and add additional circuit logic to quickly access DRAM and obtain data faster. Combination Figure 5 As shown, Figure 5 is a flowchart of a data access method shown in another exemplary embodiment of the present application. Before the above step S410, the data access method at least further includes steps S510 to S540, which are described in detail as follows: S510, determining from historical data access records the storage data whose access delay is greater than a preset delay threshold and whose access times are greater than a preset times threshold.

[0044] S520, copy the storage data whose access delay is greater than a preset delay threshold and whose access times are greater than a preset times threshold, to obtain copy data of the storage data.

[0045] S530: Determine a storage address of duplicate data of the storage data according to the storage address of the storage data.

[0046] In the embodiment of the present application, the data storage area includes a plurality of storage unit groups, each storage unit group includes a plurality of storage units, each storage unit includes a first storage area and a second storage area, the first storage area is used to store the storage data, and the second storage area is used to store the duplicated data; the storage address includes the storage unit group address and the storage unit address. The bank address in the storage address of the storage data and the bank group address can be simply adjusted to obtain the storage address of the duplicated data, thereby reducing the complexity of the storage address of the duplicated data.

[0047] In some embodiments, the storage address of the duplicated data of the stored data can be determined according to the storage address of the stored data by performing a modulo operation on the storage unit group address and the storage unit address of the stored data to obtain the storage unit group address and the storage unit address of the duplicated data.

[0048] Exemplarily, the modulo operation includes: New_bank_addr = old_bank_addr + 1 (mod 4) and New_bg_addr = old_bg_addr + 1 (mod 4). Wherein, New_bank_addr is the storage unit address in the storage address of the copied data, old_bank_addr is the storage unit address in the storage address of the stored data, New_bg_addr is the storage unit group address in the storage address of the copied data, old_bg_addr is the storage unit group address in the storage address of the stored data, and (mod 4) is used to represent the modulo operation with a modulus of 4.

[0049] For example, the data storage area includes 4 bank groups, such as bank group 1, bank group 2, bank group 3 and bank group 4, and each bank group includes 4 banks, such as bank 1, bank 2, bank 3 and bank 4. When the storage unit group address of the data storage is bank group 4, it can be known through New_bg_addr = old_bg_addr + 1 (mod 4) that bank group 1+1 is bank group 5, but there is no bank group 5 in the data storage area, and the storage unit group address of the copied data is obtained as bank group 1; when the storage unit address of the data storage is bank 4, it can be known through New_bank_addr = old_bank_addr + 1 (mod 4) that bank 4+1 is bank 5, and the New_bank_addr is obtained as bank 1 modulo 4 for bank 5, and the storage unit address of the copied data is bank 1, so the copied data is stored in an empty row in the second storage area of ​​bank 2 in bank group 2. In this way, by adjusting both the storage unit group address and the storage unit address, the copied data can be stored in a different bank in a bank group different from the storage data, which can not only reduce the number of bank conflicts, but also reduce the number of bank group conflicts, thereby achieving a better effect of reducing access delay.

[0050] For example, it is also possible to perform a modulo operation on the storage unit address, thereby only adjusting the storage unit address so that the copied data can be stored in a different bank in the same bank group as the stored data, thereby reducing the number of bank conflicts and thus achieving the effect of reducing access delay.

[0051] It can be understood that the storage address in the embodiment of the present application includes a storage unit group address, a storage unit address, a row address and a column address, wherein the column address of the copied data remains unchanged, that is, the column address in the new storage address is the same as the column address in the original storage address; while the row address will change, and a preset area is divided in each bank specifically for storing the copied data, such as the area from row 65530 to row 65536 in the bank. In this way, after determining the bank group and the bank address, the copied data will be stored in the empty row in the area from row 65530 to row 65536 in the bank address, and when storing in the preset area, it can be randomly stored in any empty row, or stored in a preset order.

[0052] S540, storing the duplicate data according to the storage address of the duplicate data, and establishing a mapping relationship between the storage address of the stored data and the storage address of the duplicate data.

[0053] It can be understood that after the storage unit group address and the storage unit address are determined, the duplicate data is stored in an empty row in the second storage area corresponding to the storage unit group address and the storage unit address of the duplicate data.

[0054] In this way, in the embodiment of the present application, by copying frequently accessed data and then storing the frequently accessed data in different banks, it can be ensured that when one of them is in a high access state, a low-load bank can be accessed, thereby obtaining data faster and reducing access delays.

[0055] Combination Figure 6 As shown, Figure 6 is a schematic diagram of the structure of a memory chip shown in an exemplary embodiment of the present application; Figure 6 The memory chip includes a DRAM controller and a DRAM. The DRAM controller records the mapping relationship between the storage address of the stored data and the storage address of the copied data. The data storage area of ​​each storage unit in the DRAM includes a first storage area and a second storage area, wherein the first storage area is used for storing data and the second storage area is used for copying data. The size of the first storage area and the size of the second storage area can be set according to actual needs.

[0056] In some embodiments, a tag SRAM (Tag Static Random Access Memory) is pre-set in the DRAM controller. The tag SRAM is fully connected to record the mapping relationship between the storage address of the stored data and the storage address of the copied data. The mapping relationship can be recorded in the tag SRAM in the form of a cache line, such as Figure 6As shown in , the cacheline includes tag information, index information and offset information; wherein the tag information includes tag valid field, tag addr field, activate cnt field and col valid field; the tag valid field is used to indicate whether the entire row of data in the bank is valid, the tag addr field is used to indicate the storage address of the copied data, the activate cnt (activation count) field is used to indicate the number of page misses in the bank, and the col calid field is used to indicate whether the entire column of data in the bank is valid. In some embodiments, the copied data is valid data only when both the tag valid field and the col valid field are valid.

[0057] In this way, when the DRAM controller receives an access request, it will first search for the corresponding tag in the tag SRAM according to the access address contained in the access request. If there is a cache hit and the data is valid, it is considered that the access request has corresponding duplicate data. Then, it searches the storage unit status information library in the DRAM controller for the load information of the storage units corresponding to the duplicate data and the storage data, and then selects one of the storage units with the lowest load to access, thereby obtaining the corresponding data. The above table lookup process can obtain the result within 1 cycle, so the overall access time is shorter than the bank conflict time.

[0058] In some embodiments, the mapping relationship between the storage address of the stored data and the storage address of the copied data can also be stored in the DRAM, so that after the DRAM controller receives an access request, it searches the DRAM for the corresponding storage address of the copied data according to the address contained in the access request, and then obtains the load information of the corresponding storage unit, and then selects one of the storage units with the lowest load to access, thereby obtaining the corresponding data.

[0059] See also Figure 7 , Figure 7 is a flowchart of a data access method shown in another exemplary embodiment of the present application. Figure 7 As shown, in an exemplary embodiment, the data access method at least further includes steps S710 to S730, which are described in detail as follows: Step S710, obtaining label information corresponding to the target address.

[0060] Step S720: Determine whether the copied data corresponding to the target address is valid data according to the tag information.

[0061] In the embodiment of the present application, the tag information corresponding to the target address is used to indicate whether the copied data is valid data. Since the same data (i.e., the stored data, the copied data identical to the stored data) is stored in different banks, when the data in a bank is rewritten, the corresponding data in another bank also needs to be updated in time to ensure the consistency of the data; and if the data in a bank is inconsistent with the data in another corresponding bank, the copied data is invalid data.

[0062] Step S730: if the copied data is valid data, the load information of the storage unit storing the copied data is determined according to the target address, and the load information of the storage unit storing the stored data is determined according to the access address.

[0063] In the embodiment of the present application, by acquiring the load information of the corresponding storage unit when the copied data is valid data, data access can be performed more accurately, thereby improving the accuracy of data access while ensuring the data access speed.

[0064] It should be noted that the relevant step contents in the embodiments of the present application are consistent with the corresponding step contents recorded in the aforementioned embodiments. Therefore, for the detailed description of these steps, please refer to the records in the aforementioned embodiments, and the embodiments of the present application will not be repeated here.

[0065] See also Figure 8 , Figure 8 is a flowchart of a data access method shown in another exemplary embodiment of the present application. Figure 8 As shown, in an exemplary embodiment, the data access method at least further includes steps S810 to S820, which are described in detail as follows: Step S810: monitor the data access bandwidth, and when the data access bandwidth is lower than a preset bandwidth threshold, count the number of accesses to all the replicated data.

[0066] It is understandable that during the data access process to DRAM, if the data access bandwidth is large, the overall system bandwidth will be reduced, and if data is updated at this time, it is easy to affect the parallelism and efficiency of data access. Therefore, by updating data when the data access bandwidth is small, the parallelism and efficiency of data access can be guaranteed.

[0067] Step S820: determine the duplicate data whose access times are lower than a preset threshold as data to be updated, and update the data to be updated.

[0068] It is understandable that due to the limited tag SRAM space and the randomness of data access, when the tag SRAM is full, it is also necessary to consider replacing cache lines that are not frequently used. The replacement can be performed periodically, and the cache lines that are not frequently accessed can be deleted and then supplemented with new cache lines. And the invalid data in the datacache can be replaced at regular intervals. Of course, the replacement has flexible characteristics. For example, when there are few read and write requests, the number of replacements can be increased; when there are many read and write requests, the number of replacements can be reduced.

[0069] In the embodiment of the present application, the data to be updated may be updated through the following process, including: Step S821, determining from the historical data access records new stored data whose access delay is greater than a preset delay threshold and whose access times are greater than a preset times threshold; Step S822, copy the new stored data to obtain copy data of the new stored data; Step S823, storing the duplicate data of the newly stored data in the storage address of the data to be updated, and establishing a mapping relationship between the storage address of the newly stored data and the storage address of the duplicate data of the newly stored data.

[0070] In this way, by re-determining new frequently accessed data in the historical data access records, the infrequently accessed data in the storage unit can be replaced. Of course, the replacement has flexible characteristics. For example, when there are few read and write requests, the number of replacements can be increased; when there are many read and write requests, the number of replacements can be reduced. In this way, by replacing the infrequently accessed data in the storage unit, the data accessed can be the frequently accessed data, which can minimize the access delay and improve the user experience.

[0071] See also Fig. 9 , Fig. 9 is a flowchart of a data access method shown in another exemplary embodiment of the present application. Fig. 9 As shown, in an exemplary embodiment, the data access method at least further includes steps S910 to S930, which are described in detail as follows: Step S910, when a data rewrite instruction for a target storage unit is detected, load information of the target storage unit is obtained, wherein the target storage unit is two storage units storing the same data.

[0072] Step S920: When the load information of the two storage units is less than a preset load threshold, data is rewritten to the two storage units simultaneously.

[0073] Step S930, when only one storage unit has load information less than a preset load threshold, rewrite data of the first storage unit whose load information is less than the preset load threshold, and monitor the load information of the second storage unit whose load information is greater than the preset load threshold.

[0074] Step S940, when it is monitored that the load information of the second storage unit is less than a preset load threshold, the rewritten storage data is read from the first storage unit, and the data of the second storage unit is rewritten according to the rewritten storage data.

[0075] It is understandable that in the embodiment of the present application, since there is a situation where a certain data exists in different banks, when the data in a certain bank is rewritten, the corresponding data in another bank also needs to be updated in time to ensure data consistency. This process can be divided into the following situations. When the load of the two banks is small, the data corresponding to the two banks can be replaced at the same time. When the load of bank1 is small, the data in bank1 can be replaced first, and when the load of bank2 is small, the DRAM controller reads the data of bank1 and then writes it back to bank2 to replace the data in bank2, thereby ensuring the consistency of the copied data in bank1 and the data in bank2.

[0076] Combination Fig.10 As shown, Fig.10 A data access device is shown in an exemplary embodiment of the present application, and the device includes a first determination module 1010, a second determination module 1020 and a data access module 1030. The first determination module 1010 is configured to determine, when receiving an access request, a target address that has a mapping relationship with the access address according to the access address for the storage data contained in the access request; the target address is the storage address of the duplicate data that is the same as the storage data, but the duplicate data and the storage data are stored in different storage units; the second determination module 1020 is configured to determine the load information of the storage unit storing the duplicate data according to the target address, and determine the load information of the storage unit storing the storage data according to the access address; the data access module 1030 is configured to compare all the acquired load information, determine the storage unit with the smallest load, and perform data access in the storage unit with the smallest load.

[0077] In some embodiments, before determining the corresponding target address according to the access address included in the access request, the first determination module 1010 is further configured to determine, from historical data access records, storage data whose access delay is greater than a preset delay threshold and whose access times are greater than a preset times threshold; copy the storage data to obtain copy data of the storage data; determine the storage address of the copy data of the storage data according to the storage address of the storage data; store the copy data according to the storage address of the copy data, and establish a mapping relationship between the storage address of the storage data and the storage address of the copy data.

[0078] In some embodiments, the data storage area includes multiple storage cell groups, each storage cell group includes multiple storage cells; the storage address includes a storage cell group address and a storage cell address; according to the storage address of the stored data, the storage address of the copied data is determined, including: performing a modulo operation on the storage cell group address and the storage cell address of the stored data, respectively, to obtain the storage cell group address and the storage cell address of the copied data; storing the copied data according to the storage address of the copied data, including: storing the copied data in an empty row in the storage area corresponding to the storage cell group address and the storage cell address of the copied data.

[0079] In some embodiments, the second determination module 1020 is configured to determine the load information of the storage unit storing the copied data according to the target address, and determine the load information of the storage unit storing the stored data according to the access address in the following manner, including: obtaining tag information corresponding to the target address; determining whether the copied data corresponding to the target address is valid data according to the tag information; if the copied data is valid data, determining the load information of the storage unit storing the copied data according to the target address, and determining the load information of the storage unit storing the stored data according to the access address.

[0080] In some embodiments, the data access device further includes an update module, which is configured to count the number of accesses to all replicated data at every preset period; determine replicated data with access times lower than a preset threshold as data to be updated, and update the data to be updated.

[0081] In some embodiments, the update module is configured to update the data to be updated in the following manner, including: determining from historical data access records new storage data whose access delay is greater than a preset delay threshold and whose access times are greater than a preset times threshold; copying the new storage data to obtain copy data of the new storage data; storing the copy data of the new storage data in the storage address of the data to be updated, and establishing a mapping relationship between the storage address of the new storage data and the storage address of the copy data of the new storage data.

[0082] In some embodiments, the update module is further configured to obtain load information of the target storage unit when a data rewrite instruction for the target storage unit is detected; wherein the target storage units are two storage units storing the same data; when the load information of the two storage units are both less than a preset load threshold, data is rewritten on the two storage units at the same time; or, when only one storage unit has load information less than the preset load threshold, data is rewritten on the first storage unit less than the preset load threshold, and load information of the second storage unit greater than the preset load threshold is monitored; when it is monitored that the load information of the second storage unit is less than the preset load threshold, the rewritten storage data is read from the first storage unit, and data is rewritten on the second storage unit based on the rewritten storage data.

[0083] An embodiment of the present disclosure further provides an electronic device, including: a processor and a memory; the memory is used to store a computer program, and the processor is used to execute the computer program stored in the memory, so that the electronic device executes the above method.

[0084] Fig.11 The structure diagram of the computer system suitable for implementing the electronic device of the embodiment of the present application is shown. It should be noted that: Fig.11 The computer system 1100 of the electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0085] like Fig.11 As shown, the computer system 1100 includes a central processing unit (CPU) 1101, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 1102 or the program loaded from the storage part 1108 to the random access memory (RAM) 1103, such as executing the method in the above embodiment. In the random access memory 1103, various programs and data required for system operation are also stored. The central processing unit 1101, the read-only memory 1102 and the random access memory 1103 are connected to each other through a bus 1104. The input / output (I / O) interface 1105 is also connected to the bus 1104.

[0086] The following components are connected to the input / output interface 1105: an input section 1106 including a keyboard, a mouse, etc.; an output section 1107 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 1108 including a hard disk, etc.; and a communication section 1109 including a network interface card such as a LAN (Local Area Network) card, a modem, etc. The communication section 1109 performs communication processing via a network such as the Internet. A drive 1110 is also connected to the input / output interface 1105 as needed. A removable medium 1111, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 1110 as needed so that a computer program read therefrom is installed into the storage section 1108 as needed.

[0087] In particular, according to an embodiment of the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present application includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a computer program for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through the communication part 1109, and / or installed from a removable medium 1111. When the computer program is executed by the central processing unit (CPU) 1101, various functions defined in the system of the present application are executed.

[0088] The embodiment of the present disclosure further provides a computer-readable storage medium on which computer-readable instructions are stored. When the computer-readable instructions are executed by a processor of a computer, the computer executes the above-mentioned data access method.

[0089] It should be noted that the computer-readable medium shown in the embodiment of the present application may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier, which carries a computer-readable computer program. This propagated data signal may take a variety of forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. A computer program contained on a computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wired, etc., or any suitable combination of the above.

[0090] The flowchart and block diagram in the accompanying drawings illustrate the possible architecture, functions and operations of the system, method and computer program product according to various embodiments of the present application. Wherein, each box in the flowchart or block diagram can represent a module, a program segment, or a part of the code, and the above-mentioned module, program segment, or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0091] The units involved in the embodiments described in this application may be implemented by software or hardware, and the units described may also be set in a processor. The names of these units do not, in some cases, constitute limitations on the units themselves.

[0092] The present application also provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the data access method as described above is implemented. The computer-readable storage medium may be included in the electronic device described in the above embodiment, or may exist independently without being assembled into the electronic device.

[0093] The above content is only a preferred exemplary embodiment of the present application and is not intended to limit the implementation scheme of the present application. A person skilled in the art can easily make corresponding changes or modifications based on the main concept and spirit of the present application. Therefore, the scope of protection of the present application shall be based on the scope of protection required by the claims.

Claims

1. A data access method, characterized in that: include: In the case of receiving an access request, determining, according to an access address for storage data included in the access request, a target address having a mapping relationship with the access address; The target address is a storage address of duplicate data that is the same as the storage data, but the duplicate data and the storage data are stored in different storage units respectively; Determining load information of a storage unit storing the copied data according to the target address, and determining load information of a storage unit storing the stored data according to the access address; All acquired load information is compared to determine a storage unit with the smallest load, and data is accessed in the storage unit with the smallest load.

2. The method according to claim 1, characterized in that Before determining the corresponding target address according to the access address included in the access request, the method further includes: Determine from the historical data access records the storage data whose access delay is greater than a preset delay threshold and whose access times are greater than a preset times threshold; Copying the stored data to obtain copy data of the stored data; Determining a storage address of a copy of the stored data according to the storage address of the stored data; The copied data is stored according to the storage address of the copied data, and a mapping relationship between the storage address of the stored data and the storage address of the copied data is established.

3. The method according to claim 2, characterized in that The data storage area includes a plurality of storage unit groups, each storage unit group includes a plurality of storage units, each storage unit includes a first storage area and a second storage area, the first storage area is used to store storage data, and the second storage area is used to store duplicate data; The storage address includes a storage unit group address and a storage unit address; The step of determining the storage address of the copied data according to the storage address of the stored data comprises: Performing a modulo operation on the storage unit group address and the storage unit address of the storage data respectively to obtain the storage unit group address and the storage unit address of the copied data; Storing the copied data according to the storage address of the copied data includes: The copied data is stored in an empty row in a second storage area corresponding to the storage unit group address and the storage unit address of the copied data.

4. The method according to claim 1, characterized in that: The step of determining the load information of the storage unit storing the copied data according to the target address, and determining the load information of the storage unit storing the stored data according to the access address, comprises: Obtaining label information corresponding to the target address; Determine whether the copied data corresponding to the target address is valid data according to the tag information; If the copied data is valid data, the load information of the storage unit storing the copied data is determined according to the target address, and the load information of the storage unit storing the storage data is determined according to the access address.

5. The method according to claim 1, characterized in that: The method further comprises: Monitoring the data access bandwidth, and counting the number of accesses to all replicated data when the data access bandwidth is lower than a preset bandwidth threshold; The duplicate data whose access times are lower than a preset threshold are determined as data to be updated, and the data to be updated are updated.

6. The method according to claim 5, characterized in that The updating of the data to be updated includes: Determine from the historical data access records new stored data whose access delay is greater than a preset delay threshold and whose access times are greater than a preset times threshold; Copying the new stored data to obtain copy data of the new stored data; The duplicate data of the newly stored data is stored in the storage address of the data to be updated, and a mapping relationship is established between the storage address of the newly stored data and the storage address of the duplicate data of the newly stored data.

7. The method according to claim 1, characterized in that The method further comprises: When a data rewrite instruction for a target storage unit is detected, load information of the target storage unit is acquired; wherein the target storage units are two storage units storing the same data; When the load information of the two storage units is less than a preset load threshold, rewriting data of the two storage units simultaneously; Or, when the load information of only one storage unit is less than the preset load threshold, data is rewritten on the first storage unit whose load information is less than the preset load threshold, and the load information of the second storage unit whose load information is greater than the preset load threshold is monitored; when it is monitored that the load information of the second storage unit is less than the preset load threshold, the rewritten storage data is read from the first storage unit, and data is rewritten on the second storage unit according to the rewritten storage data.

8. A data access device, characterized in that: The device comprises: A first determination module is configured to determine, upon receiving an access request, a target address that is mapped to the access address according to the access address for the storage data included in the access request; the target address is a storage address of duplicate data that is the same as the storage data, but the duplicate data and the storage data are stored in different storage units; a second determination module configured to determine load information of a storage unit storing the copied data according to the target address, and to determine load information of a storage unit storing the stored data according to the access address; The data access module is configured to compare all the acquired load information, determine the storage unit with the smallest load, and perform data access in the storage unit with the smallest load.

9. An electronic device, characterized in that: include: one or more processors; A storage device for storing one or more programs, which, when executed by the one or more processors, enables the electronic device to implement the data access method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: Computer-readable instructions are stored thereon, and when the computer-readable instructions are executed by a processor of a computer, the computer is caused to execute the data access method according to any one of claims 1 to 7.

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