Data processing method, acceleration device and computing equipment

Abstract

The embodiment of the invention provides a data processing method, an acceleration device and computing equipment, and the method comprises the steps that the computing equipment connected with the acceleration device determines a plurality of first acceleration events corresponding to a plurality of hardware computing clusters of the acceleration device respectively, first data related to each first acceleration event is obtained by dividing task data of a hardware acceleration task, and the first data related to each first acceleration event is transmitted to a first memory connected with each hardware calculation cluster so as to be transmitted to each hardware calculation cluster; obtaining a first calculation result of each hardware calculation cluster from the acceleration device, the first calculation result being obtained by each hardware calculation cluster through the following steps: obtaining first data from a first memory, and processing the first data by using at least one hardware calculation unit included in the first memory; and determining a result of the hardware acceleration task based on the first calculation result of each hardware calculation cluster so as to improve the data operation speed.

Description

Technical Field

[0001] The embodiments of this specification relate to the field of computer technology, and in particular, to a data processing method, an acceleration device, and a computing device. Background Art

[0002] In the field of cryptography, the implementation of various cryptographic technologies generally involves a large amount of data operations. For example, in the implementation of Zero-Knowledge Proof (ZKP) in the field of cryptography, Multi-Scalar Multiplication (MSM) is a key step, where MSM involves multiplication operations of multiple scalars and elliptic curve points. The computational complexity and time of these operations are one of the main limitations affecting the performance of zero-knowledge proofs.

[0003] In view of the above situation, in order to better improve the performance of algorithms involving large amounts of data operations, currently, during the operation of a computing device, when running an algorithm involving large amounts of data operations, the computing device can call the FPGA to which it is connected for hardware acceleration. In this hardware acceleration process, the computing device will divide the data involved in the aforementioned algorithm based on the number of processing elements in the FPGA, obtain sub-data corresponding to each processing element, and send the sub-data corresponding to each processing element to each processing element; each processing element processes the sub-data it receives in parallel, obtains processing results, and feeds the processing results back to the computing device, and the computing device summarizes the processing results fed back by each processing unit to achieve hardware acceleration of algorithms involving large amounts of data operations.

[0004] In the above hardware acceleration process, if the number of processing units in the FPGA that the computing device needs to call is large, due to the limited resources provided by the FPGA, such as I / O ports for accessing memory resources, when too many processing units process data and request these resources at the same time, it will lead to resource competition (such as competition for I / O ports for accessing memory resources), thereby affecting data processing efficiency. Therefore, how to provide a data processing method that can better improve the computing speed of data operations has become an urgent problem to be solved. Summary of the invention

[0005] One or more embodiments of the present specification provide a data processing method, device, and acceleration device to increase the speed of data operations.

[0006] According to a first aspect, a data processing method is provided, the method being applied to a computing device, the computing device being connected to an acceleration device, the acceleration device being provided with a first memory and a plurality of hardware computing clusters, each of which includes at least one hardware computing unit, each of which is connected to the first memory, the method comprising:

[0007] Determine a plurality of first acceleration events corresponding to the plurality of hardware computing clusters, wherein first data related to each first acceleration event is obtained by dividing task data of the hardware acceleration task;

[0008] Transmitting first data related to each first acceleration event to the first memory for transmission to each hardware computing cluster;

[0009] Acquire a first calculation result of each hardware computing cluster from the acceleration device, wherein the first calculation result is obtained by each hardware computing cluster through the following steps: obtain the first data from the first memory, and process the first data using at least one hardware computing unit included therein;

[0010] Based on the first calculation results of each hardware calculation cluster, the result of the hardware acceleration task is determined.

[0011] According to a second aspect, a data processing method is provided, the method being applied to an acceleration device, the acceleration device being connected to a computing device, the acceleration device being provided with a first memory and a plurality of hardware computing clusters, each of which includes at least one hardware computing unit, each of which is connected to the first memory, the method comprising:

[0012] Each hardware computing cluster of the acceleration device obtains first data related to each first acceleration event from the first memory, wherein the first data is data transmitted to the first memory after the computing device determines each first acceleration event corresponding to each hardware computing cluster, so as to be transmitted to each hardware computing cluster, and each first data is obtained by the computing device by dividing the task data of the hardware acceleration task;

[0013] Processing the first data using at least one hardware computing unit included therein to obtain first computing results;

[0014] Each first calculation result is provided to the computing device through the first memory.

[0015] In a third aspect, an acceleration device is provided, wherein the acceleration device is connected to a computing device, the acceleration device is provided with a first memory and a plurality of hardware computing clusters, each hardware computing cluster includes at least one hardware computing unit, and each hardware computing cluster is connected to the first memory;

[0016] a second transmission interface, for storing first data related to each first acceleration event obtained from the computing device in the first memory, so as to transmit the first data to each hardware computing cluster, wherein the first data is transmitted to the first memory after the computing device determines each first acceleration event corresponding to each hardware computing cluster, and each first data is obtained by the computing device by dividing the task data of the hardware acceleration task;

[0017] The multiple hardware computing clusters of the acceleration device are used to obtain first data related to the corresponding first acceleration event from the first memory respectively, and use at least one hardware computing unit included therein to process the obtained first data to obtain a first computing result of each hardware computing cluster;

[0018] The first calculation result of each hardware calculation cluster is provided to the calculation device.

[0019] According to a fourth aspect, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed in a computer, the computer is caused to execute the method described in the first aspect.

[0020] According to a fourth aspect, a computing device is provided, comprising a memory and a processor, wherein the computing device is connected to an acceleration device, wherein the acceleration device is provided with a first memory and a plurality of hardware computing clusters, each of which comprises at least one hardware computing unit, and each of which is connected to the first memory; an executable code is stored in the memory, and when the processor executes the executable code, the method described in the first aspect is implemented.

[0021] According to the data processing method, acceleration device and computing device provided by the embodiment of this specification, the data processing method is applied to a computing device connected to an acceleration device, the acceleration device is provided with a first memory and multiple hardware computing clusters, each hardware computing cluster includes at least one hardware computing unit, each hardware computing cluster is connected to the first memory of the acceleration device, based on the hardware structure of the above-mentioned acceleration device, the computing device determines the first acceleration event corresponding to each hardware computing cluster, and transmits the first data involved in each first acceleration event to the first memory, so as to transmit it to each hardware computing cluster, so that each hardware computing cluster obtains its first data from the first memory, so as to reduce the number of data acquisition times for the first memory to a certain extent, and reduce the preemption of memory read and write resources to a certain extent, and then each hardware computing cluster uses at least one hardware computing unit included therein to process the first data, obtain the first calculation result, and feed it back to the computing device; the computing device determines the result of the hardware acceleration task based on each first calculation result, and realizes the hardware acceleration of the data. Through the combination of software and hardware in the above process, the rational use of hardware resources is realized, and the problem of competition for memory read and write resources is avoided to a certain extent, so that the hardware acceleration processing of data can be better realized and the data operation speed can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of this specification, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0023] Figure 1 A schematic diagram of an implementation framework of an embodiment disclosed in this specification;

[0024] Figure 2 A schematic diagram of a flow chart of a data processing method provided in an embodiment;

[0025] Figure 3 A schematic block diagram of a software architecture provided for an embodiment;

[0026] Figure 4 Another schematic flow chart of the data processing method provided in the embodiment;

[0027] Figure 5 Another schematic flow chart of the data processing method provided in the embodiment;

[0028] Figure 6 A schematic diagram of a framework of an acceleration device provided in an embodiment;

[0029] Figure 7A schematic block diagram of a data processing device provided in an embodiment. DETAILED DESCRIPTION

[0030] In order to enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below in conjunction with the drawings in the embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on the embodiments in this specification, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this specification.

[0031] The embodiments of this specification disclose a data processing method, an acceleration device, and a computing device. The application scenarios and technical concepts of the method are first introduced as follows:

[0032] As mentioned above, in the current hardware acceleration process, if the number of processing units in the FPGA that the computing device needs to call is large, due to the limited resources provided by the FPGA, such as I / O ports for accessing memory resources, when too many processing units process data and request these resources at the same time, it will lead to resource competition (such as competition for I / O ports for accessing memory resources), thereby affecting data processing efficiency. Therefore, how to provide a data processing method that can better improve the computing speed of data operations has become an urgent problem to be solved.

[0033] In view of this, the inventor proposes a data processing method. Figure 1 FIG. 1 is a schematic diagram of an implementation scenario according to an embodiment disclosed in this specification. In this exemplary implementation scenario, a computing device is connected to an acceleration device, and the acceleration device is provided with a first memory and a plurality of hardware computing clusters (such as Figure 1 As shown, the acceleration device 1 includes, for example, four hardware computing clusters, namely, hardware computing clusters 1-4), each of which includes at least one hardware computing unit (such as Figure 1 As shown, each hardware computing cluster includes the same number of hardware computing units, for example, 4, and each hardware computing cluster is connected to the first memory. Exemplarily, the hardware computing cluster can also be called a hardware acceleration computing cluster (Computer Group, CG). Figure 1 The schematic structure of the acceleration device and the computing device and the connection relationship between the two are only shown by way of example, and do not constitute a limitation on the physical sizes of the acceleration device and the computing device.

[0034] In some examples, the computing device and the acceleration device communicate with each other through a specific transmission interface (the specific transmission interface of the acceleration device is referred to as the second transmission interface later, and the third transmission interface on the computing device side is referred to as Figure 1The specific transmission interface may be, for example, an interface based on a PCIe (Peripheral Component Interconnect Express) bus protocol, or a USB (Universal Serial Bus) interface, or may be an interface based on other data transmission protocols for high-speed data transmission. The computing device transmits its data to the acceleration device through the specific transmission interface, and the acceleration device transmits its data to the computing device through the specific transmission interface.

[0035] The computing device runs a hardware acceleration program, and the hardware acceleration program can respond to the call of the specified software (such as the subsequent first software) and realize the processing of the relevant data that needs to be hardware accelerated for the specified software based on the hardware structure of the acceleration device. Exemplarily, the computing device distributes the relevant data that needs to be hardware calculated to the corresponding hardware computing clusters of the acceleration device through the hardware acceleration program through the aforementioned specific transmission interface, so that each hardware computing cluster uses at least one hardware computing unit included therein to process the data it receives in parallel, obtain the processing results of each data, and feed back each processing result to the computing device, thereby realizing parallel data processing between the hardware computing clusters, and data parallel processing based on at least one hardware computing unit in a single hardware computing cluster, so as to realize hardware accelerated processing of the relevant data that needs to be hardware accelerated for the specified software.

[0036] It can be understood that the number of hardware computing clusters in the acceleration device can be set according to the actual resource situation of the acceleration device; the number of hardware computing units in each hardware computing cluster can be set according to the actual resource situation; the number of hardware computing units included in different hardware computing clusters can be the same or different.

[0037] During the data processing process, when the computing device is running the first software involving hardware acceleration, if the first software determines that hardware acceleration is required, it can determine the task data that needs to be hardware accelerated, and trigger the hardware acceleration task for the task data. Accordingly, the computing device sends the hardware acceleration task to the hardware acceleration program through the first software; the computing device responds to the hardware acceleration task through the hardware acceleration program, and determines multiple first acceleration events corresponding to multiple hardware computing clusters respectively, and the first data involved in each first acceleration event is obtained by dividing the aforementioned task data; the computing device transmits the first data involved in each first acceleration event to the first memory connected to each hardware computing cluster through the hardware acceleration program, so as to transmit it to each hardware computing cluster; then, the computing device obtains the first calculation result of each hardware computing cluster from the acceleration device through the hardware acceleration program, and the first calculation result is obtained by each hardware computing cluster through the following steps: obtaining the first data from the first memory and processing the first data using at least one hardware computing unit included therein; then, the computing device determines the result of the hardware acceleration task based on the first calculation result of each hardware computing cluster through the hardware acceleration program.

[0038] In the above process, the acceleration device is provided with a first memory and a plurality of hardware computing clusters, each of which includes at least one hardware computing unit. Each hardware computing cluster in the acceleration device is connected to the first memory. On the basis of the hardware structure, the first memory is read and written in units of hardware computing clusters during data processing, providing a hardware basis for reducing the number of times the first memory is read and written during data processing. On the basis of the hardware structure of the above acceleration device, each first data is allocated to each hardware computing cluster through software, that is, the first data of each hardware computing cluster is transferred to the first memory, and each hardware computing cluster obtains the first data from the first memory and processes the first data based on at least one hardware computing unit included therein, so that the number of times data is obtained from the first memory can be reduced to a certain extent, and the preemption of memory read and write resources can be reduced to a certain extent, so as to realize the rational use of the hardware resources of the acceleration device, and to a certain extent avoid the problem of resource competition, so as to better realize the hardware accelerated processing of data and improve the data operation speed.

[0039] The data processing method provided in this specification is described in detail below in conjunction with specific embodiments.

[0040] Figure 2 A flow chart of a data processing method in an embodiment of the specification is shown. The method is applied to a computing device and an acceleration device connected to the computing device, the acceleration device is provided with a first memory and a plurality of hardware computing clusters, each of which includes at least one hardware computing unit, and each of which is connected to the first memory. The computing device can be implemented by any device, equipment, platform, device cluster, etc. having computing and processing capabilities.

[0041] In some possible examples, the acceleration device can be implemented based on FPGA (Field Programmable Gate Array). In some examples, multiple hardware computing clusters can be deployed on an acceleration chip (such as Figure 1 The acceleration chip can be implemented by an FPGA chip. The number of multiple hardware computing clusters provided by the acceleration device and the number of hardware computing units included in a single hardware computing cluster can be set according to the computing resources provided by the FPGA chip.

[0042] In some implementations, the FPGA chip may include multiple logic regions corresponding to multiple hardware computing clusters. Each hardware computing cluster may be respectively arranged in a logic region corresponding to it, that is, at least one hardware computing unit included in each hardware computing cluster is arranged in a logic region corresponding to the hardware computing cluster. Due to the structural characteristics of the logic region of the FPGA chip, for example, the physical distance between the components therein (for example, including each hardware computing unit, the first arbitrator mentioned later, etc.) is shorter, so that the data transmission distance in the logic region is shorter; high-density interconnection is performed in the logic region to include more connection points and smaller interconnection spacing, etc., to improve the data transmission rate in the logic region, so that more efficient data processing can be achieved inside each hardware computing cluster, and the hardware acceleration capability can be further improved.

[0043] In some other implementations, the FPGA chip may include a logic area, and multiple hardware computing clusters are deployed in the one logic area.

[0044] In some examples, in order to better improve the timing of data processing of each hardware computing cluster, the deployment location of each hardware computing cluster on the acceleration chip, i.e., the FPGA chip, is as close as possible to the chip data bus. Among them, the deployment location of each of the aforementioned hardware computing clusters on the acceleration chip is as close as possible to the chip data bus, which can also be considered as the deployment location as close as possible to the connected first memory.

[0045] Among them, the chip data bus deployed by the acceleration chip can be any bus that can provide efficient data transmission, for example, it can include but is not limited to: AXI bus, NoC bus. The AXI (Advanced eXtensible Interface) bus is a bus used in FPGA and ASIC (Application-Specific Integrated Circuit) design. The AXI bus supports complex data transmission operations, including burst transmission and data pipelines. The NoC (Network on Chip) bus is a communication protocol used in SoC (System on Chip) designs such as acceleration chips. It realizes data exchange between various components inside the chip by building a network-like structure inside the chip.

[0046] In some cases, each hardware computing cluster in the acceleration chip and the first memory can be connected through a data bus deployed by the board (e.g., FPGA board) where the cluster is located, and the data bus can be, for example, an AXI bus (AXI4 bus or other type of bus). In some specific examples, each hardware computing cluster in the acceleration chip can include a first transmission interface, and the first transmission interface of each hardware computing cluster is connected to a memory interface (the memory interface is, for example, an I / O port provided by the FPGA board), and is respectively connected to the first memory through the data bus of the FPGA board.

[0047] In some examples, the acceleration device may include one or more first memories. In the case of including one first memory, the first memory may provide corresponding memory spaces for multiple hardware computing clusters respectively, and the corresponding memory spaces between different hardware computing clusters are isolated from each other; in the case of including multiple first memories, the multiple first memories may be set to correspond to multiple hardware computing clusters respectively, and each first memory provides corresponding memory space for its corresponding hardware computing cluster. In some possible examples, the first memory connected to each hardware computing cluster may be provided by DDR (Double Data Rate) memory (also referred to as DDR memory).

[0048] During data processing, Figure 2 As shown, the method includes the following steps S210-S250:

[0049] In step S210, the computing device determines a plurality of first acceleration events corresponding to a plurality of hardware computing clusters, wherein first data related to each first acceleration event is obtained by dividing task data of a hardware acceleration task.

[0050] In some possible examples, the computing device can implement the data processing method provided in the embodiments of this specification by running a hardware acceleration program. Exemplarily, the hardware acceleration program can be associated with the first software that needs hardware acceleration so that it can receive the call of the first software and execute the data processing process. In one implementation, the hardware acceleration program can be provided with an acceleration interface. When the first software has a hardware acceleration requirement, the hardware acceleration program can be called through the acceleration interface, that is, a hardware acceleration task is sent to the hardware acceleration program through the acceleration interface to execute the data processing process.

[0051] The first software may be any software that requires hardware acceleration. For example, the first software may be software involving an algorithm that requires a large amount of data calculations. The algorithm may be an implementation algorithm of related cryptographic technologies such as zero-knowledge proof or other algorithms that require a large amount of data calculations.

[0052] In one implementation, when the computing device is running the first software and determines that a large amount of data operations need to be performed, it can be determined that hardware acceleration is required. The computing device calls the hardware acceleration program through the first software and issues a hardware acceleration task to the hardware acceleration program. Accordingly, the computing device responds to the hardware acceleration task through the hardware acceleration program and executes the data processing flow. Specifically, the computing device can determine multiple first acceleration events corresponding to multiple hardware computing clusters respectively through the hardware acceleration program, and the first data involved in each first acceleration event is obtained by dividing the task data of the hardware acceleration task.

[0053] It is understandable that during the power-on startup process of the computing device, the computing device enumerates and traverses the device information of each hardware device connected to it, and the hardware device includes an acceleration device (the acceleration device can be identified by the driver of the acceleration device). Accordingly, the device information includes the device information of the acceleration device, and the device information of the acceleration device may include but is not limited to the information of the hardware computing cluster set by the acceleration device (for example, including but not limited to the number of hardware computing clusters, the number of hardware computing units in the hardware computing cluster, whether it is available, etc.). In view of this, the computing device responds to the hardware acceleration task through the hardware acceleration program, and can determine multiple first acceleration events corresponding to multiple hardware computing clusters respectively.

[0054] It is understandable that the computing device can run the first software and the hardware acceleration program through its processor (such as a central processing unit CPU), as well as the driver of the acceleration device (for example, in the case where the acceleration device is implemented based on FPGA, the driver of the acceleration device can be an FPGA board device driver, and the acceleration device can be, for example, Figure 1As shown). After the computing device is started or the acceleration device is inserted into the computing device through a specific transmission interface, the computing device loads and starts the driver of the acceleration device through the processor, and the driver of the acceleration device provides a corresponding interface for the computing device (including the hardware acceleration program) to identify and manage the hardware resources of the acceleration device, and to perform data transmission with the acceleration device. For example, the corresponding interface provided by the driver of the acceleration device may include an interface for data transmission, and the interface for data transmission allows the hardware acceleration program to exchange data with the acceleration device through, for example, DMA (Direct Memory Access) transmission mode and other configured transmission modes.

[0055] In some possible examples, the hardware acceleration task may be a computing task involving multi-scalar multiplication (MSM), and accordingly, each first data includes multiple multiplication operations that need to be summed. In some other possible examples, the hardware acceleration task may be a computing task involving multi-data multiplication, and accordingly, each first data includes multiple data that need to be multiplied.

[0056] In order to better improve the portability of hardware acceleration programs and provide users with a more user-friendly experience, in some possible examples, such as Figure 3 As shown, the hardware acceleration program may include a software stack and a target program, wherein the target program may include a user-mode subroutine and a kernel-mode subroutine. In some examples, the software stack may be integrated into the first software so that the first software uses the acceleration device to provide hardware acceleration services for it through the software stack. Exemplarily, the software stack may exist in the form of a plug-in for the first software. The target program may exist as an independent software program, installed on a computing device, which is associated with the software stack. The software stack may be used to reasonably divide the data involved in the hardware acceleration request, and to determine whether it is necessary to use the acceleration device for hardware acceleration in response to the hardware acceleration request. The target program may be used to prepare in advance for the hardware acceleration process to help the hardware acceleration process; generate corresponding tasks for the data involved in the hardware acceleration request and allocate hardware computing clusters to each data to achieve hardware acceleration, etc.

[0057] Among them, exemplary ones are Figure 3As shown, the kernel state subroutine may include a memory management component, an event management component, a device management component and a data management component. Among them, the aforementioned memory management component, event management component and device management component are components belonging to the control path class, which are used to generate control data in the process of managing data processing. For example: the memory management component can maintain the allocation information of the memory space of the first memory. The device management component can provide relevant operations for each hardware in the acceleration device. Exemplarily, the acceleration device is also provided with a plurality of registers, and the device management component performs read and write operations on the plurality of registers in the acceleration device to maintain the space allocation of the first memory; when the hardware acceleration program is started, the acceleration device connected to the computing device is determined by calling the corresponding interface provided by the driver of the aforementioned acceleration device, and a corresponding acceleration event queue is created for the hardware computing cluster included in the acceleration device, and the acceleration event queue is used to store the acceleration events that the corresponding hardware computing cluster needs to process. Among them, the computing device can be connected to one or more acceleration devices.

[0058] The device management component can write information in the register and / or read information in the register through an interface for hardware reading and writing provided by the driver of the acceleration device.

[0059] The data management component is a component belonging to the data path class, which is used to manage and transmit data. Specifically, the data management component can manage data transmission in response to the triggering of the event management component or the device management component, that is, manage data transmission between the computing device and the acceleration device. In some examples, in order to ensure the safety of the acceleration device and avoid malicious attacks on the acceleration device (for example, malicious occupation of the hardware of the acceleration device, so that the acceleration device cannot provide hardware acceleration services for other software that really needs hardware acceleration), the computing device can first determine the legality of the data to be transmitted after determining the data to be transmitted through the data management component, such as detecting whether the storage location of the data to be transmitted in the computing device is legal (for example, determining whether the storage location belongs to the location provided by the second memory of the computing device mentioned later); if it is determined that the data to be transmitted is legal, it is determined that the data is transmitted, and if it is determined that the data to be transmitted is illegal, it is determined that the data is not transmitted. In the case of determining that the data to be transmitted is illegal, the computing device can also feedback the determination result of the illegality of the data to be transmitted and other relevant information (such as information about the process corresponding to the data) to the user through the data management component for user reference.

[0060] In some possible examples, data can be transmitted between the computing device and the acceleration device based on DMA technology to reduce the occupancy of the processor of the computing device. Accordingly, the aforementioned data management component can be referred to as a DMA management component. In some other possible examples, data can also be transmitted between the computing device and the acceleration device based on other data transmission protocols.

[0061] like Figure 3 As shown, the user-mode subroutine may include a memory application and release interface, an acceleration task creation and release interface, and a device information interface. Among them, the memory application and release interface corresponds to the memory management component, the acceleration task creation and release interface corresponds to the event management component, and the device information interface corresponds to the device management component. Each interface is configured in the following initialization process to provide a basis for the data processing flow.

[0062] Specifically, in order to better improve the hardware acceleration speed, the hardware acceleration program can be initialized in advance, that is, the hardware acceleration program can be initialized before the data processing process to provide a basis for the data processing process. In some possible examples, the computing device includes a second memory; the method can also include the following hardware acceleration program initialization process, including step 11; in step 11, when the computing device starts the first software, the software stack initializes the target program as follows:

[0063] In step 111, first memory spaces corresponding to each hardware computing cluster are configured for the memory application and release interface of the user-mode subroutine, and the first memory spaces are provided by the first memory.

[0064] In step 112, for the acceleration task of the user-mode subroutine, an acceleration task queue of each hardware computing cluster corresponding to each process of the first software of the interface configuration is created and released.

[0065] In step 113, a second memory space corresponding to each hardware computing cluster in the second memory is configured for the device information interface of the user-mode subroutine.

[0066] Among them, the second memory space corresponding to each hardware computing cluster is used to store the first computing result of each hardware computing cluster, and the acceleration task queue of each hardware computing cluster corresponding to each process is used to store the acceleration task of the process initially assigned to the corresponding hardware computing cluster.

[0067] In this implementation, when the first software is started, the first software triggers the software stack, and the corresponding software stack initializes the target program, that is, configures the interfaces of the user-mode subroutine of the target program to provide a basis for the subsequent data processing flow. Specifically, the first memory spaces corresponding to each hardware computing cluster are configured for the memory application and release interface of the user-mode subroutine. The first memory space is provided by the first memory. The corresponding relationship between the first memory spaces corresponding to the hardware computing clusters is maintained and managed by the memory management component. The first memory spaces are used to store the data (including the first data) assigned by the computing device to each hardware computing cluster for processing and the calculation results obtained after each hardware computing cluster processes its data.

[0068] For the acceleration task creation and release interface configuration of the user-mode subroutine, the acceleration task queues of each hardware computing cluster corresponding to each process of the first software are configured. In some implementations, the first software can be single-process or multi-process software. In the case of multi-process software, one or more of the processes have the need for hardware acceleration. Accordingly, in order to provide hardware acceleration services for each process in the first software that has the need for hardware acceleration, when the computing device starts the first software, the hardware acceleration program is called by the started first software for initialization, so as to create and release the acceleration task queues of each hardware computing cluster corresponding to each process of the first software (at least including the process that has the need for hardware acceleration) configured with the interface for the acceleration task. The acceleration task queue is used to store the acceleration tasks of the process that are initially assigned to the corresponding hardware computing cluster.

[0069] The device information interface of the user-mode subroutine configures the second memory space corresponding to each hardware computing cluster in the second memory, and each second memory space is used to store the calculation results obtained by each hardware computing cluster processing its data for acquisition by the computing device (processor). In some cases, the device information interface is also used for the first software to query the information of each hardware computing cluster.

[0070] Among them, Figure 1 As shown, the second memory of the computing device is the second memory corresponding to the processor of the computing device, in which data required for the processor of the computing device to run is stored. Exemplarily, the second memory can be implemented based on DDR (Double Data Rate) memory (also known as DDR memory).

[0071] In some possible cases, after the computing device stops running the first software, it can call the memory management component through the aforementioned memory application and release interface to release the first memory space provided by each hardware computing cluster. After the computing device determines to obtain the calculation results of each hardware computing cluster (the calculation results are obtained after the hardware computing cluster processes the data involved in its corresponding acceleration event), or after stopping running the first software, it can call the event management component through the aforementioned acceleration task creation and release interface to release the corresponding acceleration event.

[0072] In some possible examples, the acceleration device may also include multiple registers; the aforementioned initialization also includes step 114, in which the corresponding registers are configured for each hardware computing cluster so that each hardware computing cluster records the processing status of each hardware computing cluster and the storage location of its first computing result in the first memory space in its corresponding register.

[0073] The processing status of each hardware computing cluster and its first calculation result are stored in the storage location of the first memory space, which is used for data transmission between the computing device and the acceleration device. The device management component of the computing device can determine the status of each hardware computing cluster by reading the processing status of each hardware computing cluster recorded in its corresponding register. For example, if the hardware computing cluster A records the first mark value in its corresponding register, it can be represented that the hardware computing cluster A has completed the processing of the first data acquired by it and obtained the first calculation result. At this time, it is determined that data transmission can be performed, that is, the first calculation result recorded in the register at the storage location of the first memory space is transmitted to the computing device (for example, transmitted to the second memory space corresponding to the hardware computing cluster A in the second memory of the computing device); on the contrary, if the hardware computing cluster A does not record the first mark value in its corresponding register, it means that the hardware computing cluster A has not yet completed the processing of the first data acquired by it, and it is necessary to continue to wait for the hardware computing cluster A to process the first data.

[0074] In some cases, the aforementioned initialization may also include: configuring a register corresponding to the computing device itself for the computing device, and the computing device records in its corresponding register information indicating whether the data (including the first data and the second data mentioned later) transmitted to the acceleration device (each hardware computing cluster) has been transmitted, so that after the computing device records in its corresponding register information indicating that the data transmitted to the hardware computing cluster has been transmitted, the corresponding hardware computing cluster can obtain the data from its corresponding first memory space and process it.

[0075] In some possible examples, the multiple registers may include a status register and an address register, wherein the status register is used to record the processing status of each hardware computing cluster (and to record the aforementioned information indicating that the data transmission from the computing device to the acceleration device has been completed); and the address register is used to record the storage location of the calculation results obtained by processing the data of each hardware computing cluster.

[0076] In some examples, in order to better achieve hardware acceleration, after the computing device determines the hardware acceleration task through the hardware acceleration program, it can also first reasonably divide the task data involved in the hardware acceleration task to obtain multiple divided data (including the first data and the second data mentioned later), and then determine the hardware computing clusters corresponding to each divided data, that is, assign a corresponding hardware computing cluster to each divided data to generate an acceleration event. Exemplarily, the hardware acceleration program includes a software stack and a target program, and accordingly, in step S210, the following steps 21-23 can be included:

[0077] In step 21, the software stack responds to the hardware acceleration task issued by the first software, and based on the number of multiple hardware computing clusters, divides the task data to obtain a plurality of divided data, wherein the plurality of divided data includes the aforementioned first data.

[0078] In this step, the first software triggers the hardware acceleration task when determining that hardware acceleration is required. The software stack executes the data processing flow in response to the hardware acceleration task issued by the first software. Specifically, the software stack can divide the task data based on the number of multiple hardware computing clusters to obtain a number of divided data, and the number of divided data includes the aforementioned first data. In some examples, the first software can call the software stack through the acceleration interface to trigger the hardware acceleration task. In some possible examples, the first software can be multi-process software, and the hardware acceleration task can be triggered by any first process in the first software that is determined to need hardware acceleration.

[0079] For example, assuming that the acceleration device includes 10 hardware computing clusters, and the hardware acceleration task is a computing task involving multiple data multiplications, such as a multiplication operation of 300 data multiplications. At this time, the software stack can divide the task data based on the 10 hardware computing clusters to obtain 10 divided data, each divided data includes 30 multiplication data.

[0080] For another example, suppose that the acceleration device includes 10 hardware computing clusters, and the hardware acceleration task is a task involving multiple multiplication operations on 300 data. At this time, the software stack divides the task data based on the 10 hardware computing clusters to obtain 30 divided data, each of which includes 10 multiplied data. Subsequently, the computing device can send the 30 divided data to the acceleration device in 3 batches, wherein 10 divided data can be sent to the acceleration device in each batch. In some examples, the computing device can send every 10 divided data to the acceleration device in batches in the form of a pipeline to better improve the efficiency of hardware acceleration.

[0081] Exemplarily, when the software stack divides the task data, it can refer to the size of the first memory space corresponding to each hardware computing cluster to divide it, so as to avoid the size of a single divided data exceeding the size of the first memory space corresponding to the hardware computing cluster.

[0082] In some other examples, in response to the hardware acceleration task, the software stack may first determine whether it is necessary to trigger hardware acceleration for the hardware acceleration task based on the amount of task data involved in the hardware acceleration task, and divide the task data if it is determined that hardware acceleration is required. Specifically, step 21 may include the following steps 211-212:

[0083] In step 211, the software stack determines whether hardware acceleration is required based on the data volume of the task data, that is, whether an acceleration device is required to perform hardware acceleration. In some examples, a data volume threshold may be set, and the software stack determines that hardware acceleration is required when it determines that the data volume of the task data exceeds the data volume threshold, and determines that hardware acceleration is not required when it determines that the data volume of the task data does not exceed the data volume threshold. When it is determined that hardware acceleration is not required, the software stack may call a specified data operation program, and accordingly, the computing device performs calculations on the task data by running the specified data operation program.

[0084] Next, in step 212, when the software stack determines that hardware acceleration is required, the software stack divides the task data based on the number of multiple hardware computing clusters to obtain a plurality of divided data, wherein the plurality of divided data includes the aforementioned first data.

[0085] After obtaining a number of divided data, in step 22, the software stack calls the target program, and the target program determines the hardware computing cluster corresponding to each first data.

[0086] In some possible examples, the target program includes a user-mode subroutine and a kernel-mode subroutine; accordingly, the target program determines the hardware computing cluster corresponding to each first data, which may include steps 221-222:

[0087] In step 221, the software stack calls the acceleration task creation and release interface of the user-mode subroutine, generates a first acceleration task for each first data, and calls the event management component of the kernel-mode subroutine.

[0088] In step 222, the event management component determines the hardware computing cluster corresponding to each first acceleration task.

[0089] In one implementation, after the software stack determines a number of partitioned data, it can call an acceleration task creation and release interface, which generates an acceleration task for each partitioned data, and calls the event management component of the kernel state subroutine with the generated multiple acceleration tasks as input parameters. In response to the call, the event management component determines the hardware computing cluster corresponding to each acceleration task, and each acceleration task includes the first acceleration task corresponding to each of the aforementioned first data.

[0090] Among them, each of the aforementioned acceleration tasks can indicate information about its corresponding divided data, and the information indicated by a single acceleration task can, for example, include but is not limited to the following information: the storage location of the divided data involved in the acceleration task in the computing device (for example, the storage location in the second memory of the computing device), the length of the divided data, the identifier of the first software corresponding to the divided data, and the task identifier of the acceleration task (for example, the task ID), etc.; further, a single acceleration task can also indicate the identifier of the first process in the first software corresponding to the corresponding divided data, and the first process is the process that triggers the hardware acceleration task, and the divided data belongs to the task data involved in the hardware acceleration task.

[0091] In some examples, when the first software is a single-process software, the acceleration task creation and release interface is configured with the acceleration task queue corresponding to each hardware computing cluster corresponding to each process. After the corresponding acceleration task creation and release interface obtains each acceleration task, it can also perform initial allocation of each acceleration task, that is, evenly allocate each acceleration task to the acceleration task queue of each hardware computing cluster corresponding to the first process. Afterwards, the acceleration task creation and release interface calls the event management component with each generated acceleration task as the input parameter. The event management component determines the hardware computing cluster actually corresponding to each acceleration task. At this time, the hardware computing cluster actually corresponding to each acceleration task is the hardware computing cluster that actually processes the data involved in the corresponding acceleration task. For example, the initially allocated hardware computing cluster corresponding to each acceleration task can be used as the hardware computing cluster actually corresponding to each acceleration task.

[0092] In some other examples, when the first software is single-process software, after the acceleration task creation and release interface obtains each acceleration task, the event management component can be directly called with the generated acceleration tasks as input parameters, and the event management component determines the hardware computing cluster that actually corresponds to each acceleration task.

[0093] The event management component can configure the acceleration event queue corresponding to each hardware computing cluster. The above-mentioned event management component determines the hardware computing cluster that each acceleration task actually corresponds to, which can be: adding each acceleration task to the acceleration event queue corresponding to each hardware computing cluster respectively, so as to determine the hardware computing cluster that each acceleration task actually corresponds to, and then generating the acceleration event corresponding to each acceleration task based on the hardware computing cluster that each acceleration task actually corresponds to.

[0094] Among them, each acceleration task includes each first acceleration task, each first acceleration task corresponds to a different hardware computing cluster, and the first data involved is the data of the same batch that needs to be sent to each hardware computing cluster. For example, when the computing device has not yet transmitted the divided data involved in each acceleration task to the acceleration device, each acceleration task at the first position in the queue corresponding to each hardware computing cluster can be determined as the first acceleration task, and the divided data involved in each first acceleration task can be determined as the first data.

[0095] In some examples, for software that includes multiple processes, multiple processes may have the need for hardware acceleration. In order to meet the hardware acceleration needs of multiple processes in the multi-process software, facilitate the orderly management of data of each process, and improve the speed of hardware acceleration, the acceleration task creation and release interface manages the acceleration task queues corresponding to each hardware computing cluster created for each process, and evenly distributes each acceleration task of each process to the acceleration task queues of each hardware computing cluster corresponding to each process.

[0096] Taking the first process as an example, the acceleration task creation and release interface can call the event management component with the generated acceleration tasks of the first process as the input parameters. If the event management component determines that each hardware computing cluster is in the data processing state (at this time, the acceleration task of another process is being processed), the acceleration tasks of the first process can be added to the acceleration event queue of each hardware computing cluster, that is, the acceleration tasks of the first process are waiting to be processed by the event management component; the event management component can add the acceleration tasks in the acceleration task queue corresponding to each hardware computing cluster corresponding to the first process (the first process is the process that first requests processing among all processes waiting to be processed) to the acceleration event queue of the hardware computing cluster that meets the preset conditions, based on the actual state of each hardware computing cluster. In this way, the event management component can evenly allocate the actual corresponding hardware computing clusters to each acceleration task according to the actual state of each hardware computing cluster to generate each acceleration event, and each acceleration event is waiting to be processed by the hardware computing cluster of the actual corresponding hardware computing cluster. Afterwards, the event management component may determine a plurality of first acceleration events corresponding to the plurality of hardware computing clusters, and perform subsequent processing on the first data involved in each first acceleration task.

[0097] Exemplarily, the acceleration tasks in the acceleration task queue corresponding to the hardware computing cluster that meets the preset conditions may be preferentially added to the acceleration event queue of the hardware computing cluster that meets the preset conditions.

[0098] In some other implementations, the event management component can determine whether the acceleration event queue corresponding to the hardware computing cluster is full in a preset manner. For example, the event management component can determine whether the acceleration event queue corresponding to the hardware computing cluster is full by the maximum number of events in each acceleration event queue pre-stored in a preset position and the size of the number of acceleration events in each acceleration event queue.

[0099] In another exemplary embodiment, the event management component can determine the hardware computing cluster corresponding to each first acceleration task based on the result of the initial allocation of each first acceleration task by the acceleration task creation and release interface. For example, the hardware computing cluster in the result of the initial allocation of each first acceleration task is determined as the hardware computing cluster actually corresponding to each first acceleration task.

[0100] Then, in step 23, the target program generates each first acceleration event based on the hardware computing cluster corresponding to each first acceleration task. In this step, the event management component of the target program generates each first acceleration event based on the hardware computing cluster corresponding to each first acceleration task. Among them, each first acceleration event (taking the first acceleration event i as an example) can indicate the following information: the storage location of the first data i corresponding to the first acceleration event i in the computing device, the data length of the first data i, the identifier of the first software (and the first process) corresponding to the first data i, the storage location to which the first data i needs to be transmitted, and the event identifier of the first acceleration event i (the event identifier of the first acceleration event i can be the same as or different from the task identifier of the first acceleration task corresponding to the first acceleration event i). The storage location to which the first data i needs to be transmitted belongs to the first memory space corresponding to the hardware computing cluster corresponding to the first acceleration event i. In some examples, the event management component of the target program can generate each acceleration event for each acceleration task in the acceleration event queue corresponding to each hardware computing cluster it manages, and each acceleration task in the acceleration event queue corresponding to each hardware computing cluster includes each first acceleration task, so as to generate the first acceleration event.

[0101] Among them, the acceleration event queue corresponding to each hardware computing cluster can be that when the computing device starts the hardware acceleration program, the computing device calls the corresponding interface provided by the driver of the aforementioned acceleration device through the device management component of the hardware acceleration program to determine the acceleration device to which the computing device is connected, and is created for the multiple hardware computing clusters included in the acceleration device.

[0102] Exemplarily, the event management component can obtain the first memory space (i.e., the address of the first memory space) corresponding to the hardware computing cluster corresponding to the first acceleration event i through the memory management component, and determine the storage location to which the first data i needs to be transmitted based on the first memory space corresponding to the hardware computing cluster corresponding to the first acceleration event i.

[0103] In some possible implementations, after the memory management component is scheduled by the event management component, it can determine the specific storage location to which the first data i needs to be transmitted from the first memory space corresponding to the hardware computing cluster corresponding to the first acceleration event i, and feed back the determined specific storage location to which the first data i needs to be transmitted to the event management component. The specific storage location to which the first data i needs to be transmitted can be determined by the memory management component based on a specific data processing storage algorithm or protocol, so as to avoid overwriting data that has not been processed by the hardware computing cluster i or calculation results that have not been transmitted to the computing device after the first data i is transmitted to the first memory space corresponding to the corresponding hardware computing cluster i, thereby causing data loss.

[0104] In some possible examples, the first memory space i corresponding to each hardware computing cluster (taking hardware computing cluster i as an example) may include a first subspace and a second subspace, the first subspace being used to store data (including first data) transmitted by the computing device to the hardware computing cluster i, and the second subspace being used to store calculation results obtained by the hardware computing cluster i.

[0105] In some cases, the first subspace and the second subspace may store data in an overlay storage manner. Accordingly, the storage location to which the aforementioned first data i needs to be transmitted may be the aforementioned first subspace. Subsequently, the hardware computing cluster i obtains the first data i from the first subspace.

[0106] In some other cases, the first subspace may include two storage areas, and the two storage areas may take turns storing data transmitted by the computing device to the hardware computing cluster i. For example, the data transmitted by the computing device to the hardware computing cluster i last time is stored in the storage area 1 of the first subspace. Correspondingly, the storage location to which the aforementioned first data i needs to be transmitted is the storage area 2 of the first subspace. Subsequently, the hardware computing cluster obtains the first data from the storage area 2 of the first subspace.

[0107] After the computing device determines a plurality of first acceleration events corresponding to the plurality of hardware computing clusters, in step S220, the computing device transmits first data related to each first acceleration event to the first memory for transmission to each hardware computing cluster.

[0108] In the acceleration device, multiple hardware computing clusters are respectively connected to the first memory. Correspondingly, the first memory connected to the hardware computing cluster provides each hardware computing cluster with its own corresponding first memory space to store the data (including the first data) required to be processed by the hardware computing cluster and the calculation results obtained by the hardware computing cluster processing the data. In step S220, it is specifically configured that the computing device transmits the first data involved in each first acceleration event to the first memory space corresponding to each hardware computing cluster, so as to transmit it to each hardware computing cluster. In this step, the computing device can transmit the first data involved in each first acceleration event to the first memory space corresponding to each hardware computing cluster based on any transmission method configured between it and the acceleration device, through a specific transmission interface between the computing device and the acceleration device (i.e., Figure 1 The third transmission interface and the second transmission interface shown in the figure) transmit the first data related to each first acceleration event to the first memory space corresponding to each hardware computing cluster, so as to be transmitted to each hardware computing cluster.

[0109] In some implementations, the acceleration device may include one or more first memories. In the case of including one first memory, the first memory may provide corresponding first memory spaces for multiple hardware computing clusters, respectively, and the corresponding data storage spaces between different hardware computing clusters are isolated from each other; in the case of including multiple first memories, the multiple first memories may be set to correspond to multiple hardware computing clusters, respectively, and each first memory provides a corresponding first memory space for its corresponding hardware computing cluster.

[0110] Exemplarily, after the event management component generates each first acceleration event, each first acceleration event can be transmitted to the data management component to call the data management component. Based on each first acceleration event, the data management component transmits the first data involved in each first acceleration event to the first memory (i.e., the first memory space corresponding to each hardware computing cluster) in accordance with any transmission method configured between the computing device and the acceleration device, so as to transmit it to each hardware computing cluster.

[0111] In some possible examples, data can be transmitted between the computing device and the acceleration device through DMA transmission to reduce the occupancy of the processor of the computing device. Exemplarily, each hardware computing cluster in the acceleration device can correspond to a DMA controller (hereinafter referred to as the first DMA controller), and the first DMA controller corresponding to each hardware computing cluster, the first memory and the aforementioned second transmission interface can be connected through a data bus deployed by the board (such as an FPGA board) where the acceleration device is located.

[0112] Specifically, the event management component transmits each first acceleration event to the data management component to call the data management component. The data management component creates a DMA request corresponding to each first acceleration event (hereinafter referred to as the first DMA request) based on each first acceleration event. Then, the data management component sends the first DMA request corresponding to each first acceleration event to the first DMA controller corresponding to the hardware computing cluster corresponding to each first acceleration event, so that each first DMA controller transfers the first data involved in the corresponding first acceleration event from the storage location of the computing device (i.e., the second memory) to the storage location to which the first data needs to be transferred (e.g., the first memory space corresponding to the hardware computing cluster corresponding to the first DMA controller) based on the information indicated by the first DMA request received by it, so as to transmit it to each hardware computing cluster.

[0113] Among them, the information indicated by the first DMA request corresponding to the j-th first acceleration event may include the storage location of the first data j involved in the j-th first acceleration event in the computing device (for example, the storage location of the first data j in the second memory of the computing device, which is the source address of the first data j in this case), the data length of the first data j and the storage location to which the first data j needs to be transferred (for example, it needs to be transferred to the first memory space corresponding to the hardware computing cluster corresponding to the j-th first acceleration event, which is the destination address of the first data j in this case), the identifier of the first software (and the first process) corresponding to the first data j involved in the j-th first acceleration event, and the event identifier of the j-th first acceleration event.

[0114] Also exemplarily, after the data management component creates a first DMA request corresponding to each first acceleration event based on each first acceleration event, each first DMA request can be sent to a DMA controller deployed by the computing device (hereinafter referred to as the second DMA controller), so that the second DMA controller transfers the first data involved in each first acceleration event from the storage location of the computing device (i.e., the second memory) to the first memory space corresponding to each hardware computing cluster in the first memory based on the aforementioned information indicated by the first DMA request corresponding to each first acceleration event, so as to transmit it to each hardware computing cluster.

[0115] Among them, exemplarily, the process of the data management component sending the first DMA request corresponding to each first acceleration event to each first DMA controller (or second DMA controller) may include the data management component calling the driver of the acceleration device based on the interface for data transmission provided by the driver of the aforementioned acceleration device, so as to send the first DMA request corresponding to each first acceleration event to each first DMA controller (or second DMA controller) through the driver of the acceleration device.

[0116] In the above example, each first DMA controller (or second DMA controller) is used to transfer each first data from the second memory of the computing device to the first memory of the acceleration device, so as to reduce the occupancy of the processor of the computing device.

[0117] In some other possible examples, data may be transmitted between the computing device and the acceleration device through other data transmission methods (for example, a transmission method based on the PCIe bus protocol). For example, the computing device may call the data management component through the event management component, and the data management component may transfer the first data involved in each first acceleration event from the storage location of the computing device (i.e., the second memory) to the first memory space corresponding to each hardware computing cluster in the first memory based on the other data transmission method, so as to transmit it to each hardware computing cluster.

[0118] In some possible examples, in order to better improve the hardware acceleration efficiency, the data management component transmits the divided data obtained by dividing the task data involved in the hardware acceleration task in batches, and transmits each batch of divided data to the acceleration device in a pipeline form. Accordingly, after the first data involved in each first acceleration event is transmitted to the first memory for transmission to each hardware computing cluster, the method may further include the following step 31:

[0119] In step 31, in the process in which each subsequent hardware computing cluster obtains the first data from the first memory and processes the first data using at least one hardware computing unit included therein, the computing device transmits the second data involved in each second acceleration event to the first memory for transmission to each hardware computing cluster, wherein the second data involved in each second acceleration event is obtained by dividing the task data.

[0120] Following the above example, assuming that the acceleration device includes 10 hardware computing clusters, and the hardware acceleration task is a task involving multiple multiplication operations of 300 data, the computing device divides the task data based on the 10 hardware computing clusters through the software stack to obtain 30 divided data, each divided data includes 10 multiplied data. The computing device can generate 30 acceleration events for the 30 divided data through the event management component, and use 10 of the acceleration events as 10 first acceleration events corresponding to the 10 hardware computing clusters, and transmit the first data involved (i.e., divided data) to the first memory to transmit to each hardware computing cluster. Afterwards, in the process of each hardware computing cluster obtaining the first data from the first memory and using at least one hardware computing unit included therein to process the first data, the computing device can use the 10 acceleration events that have not been transmitted as 10 second acceleration events corresponding to the 10 hardware computing clusters, and transmit the second data involved (i.e., divided data) to the first memory to transmit to each hardware computing cluster, so as to hide the data transmission process to a certain extent, so as to better improve the hardware acceleration speed and efficiency.

[0121] In a specific example, there are three acceleration events queued in the 10 acceleration event queues corresponding to the 10 hardware computing clusters managed by the event management component. The event management component can respectively use the 10 acceleration events ranked first in the 10 acceleration event queues as 10 first acceleration events, and call the data management component corresponding to the 10 first acceleration events. Based on each first acceleration event, the data management component transmits the first data involved in each first acceleration event to the first memory space corresponding to each hardware computing cluster according to any transmission method configured between the computing device and the acceleration device, so as to transmit it to each hardware computing cluster. Subsequently, the event management component can respectively use the 10 acceleration events ranked in the middle position in the 10 acceleration event queues as 10 second acceleration events, and call the data management component corresponding to the 10 second acceleration events. Based on each second acceleration event, the data management component transmits the second data involved in each second acceleration event to the first memory space corresponding to each hardware computing cluster according to any transmission method configured between the computing device and the acceleration device, so as to transmit it to each hardware computing cluster, and so on.

[0122] After the computing device transmits the first data to the first memory for transmission to each hardware computing cluster, in step S230, each hardware computing cluster of the acceleration device respectively obtains the first data related to each first acceleration event from the first memory. And in step S240, each hardware computing cluster of the acceleration device processes the first data using at least one hardware computing unit included therein to obtain each first computing result.

[0123] In some possible examples, after the data management component of the computing device transfers the first data involved in each first acceleration event to the first memory for transmission to each hardware computing cluster, each hardware computing cluster determines that the transmission of each first data has been completed, that is, after each first data is stored in the first memory, each hardware computing cluster obtains the first data involved in each first acceleration event from the first memory. Exemplarily, the aforementioned first memory provides each hardware computing cluster with its corresponding first memory space; accordingly, the aforementioned each hardware computing cluster obtains the first data involved in each first acceleration event from the first memory, which may include: each hardware computing cluster obtains its corresponding first data from the first memory space corresponding to each hardware computing cluster.

[0124] Among them, each hardware computing cluster can determine that each first data has been transmitted based on any determination method in the relevant technology. For example: the aforementioned first DMA controller (or second DMA controller) can send a specified notification to each hardware computing cluster after transmitting each first data to the first memory connected to each hardware computing cluster to notify each hardware computing cluster that the first data has been transmitted; or, the computing device (data management component) can record the corresponding information in the register corresponding to the aforementioned computing device after determining that the first DMA controller (or second DMA controller) transmits each first data to the first memory connected to each hardware computing cluster to notify each hardware computing cluster that the first data has been transmitted; each corresponding hardware computing cluster determines that the first data has been transmitted after detecting the corresponding information recorded in the register corresponding to the computing device. It can be understood that the aforementioned is only an exemplary explanation of the way in which each hardware computing cluster determines that each first data has been transmitted. Each hardware computing cluster can also determine whether each first data has been transmitted through other determination methods, which will not be repeated here.

[0125] Next, each hardware computing cluster processes the first data using at least one hardware computing unit included therein to obtain each first computing result. It can be understood that the manner in which each hardware computing cluster in the plurality of hardware computing clusters processes the first data is similar, and the following takes any first hardware computing cluster as an example to introduce the process of the hardware computing cluster processing the first data.

[0126] In some possible examples, the aforementioned multiple hardware computing clusters include a first hardware computing cluster, and the first hardware computing cluster also includes a first transmission interface and a first arbitrator (such as Figure 1 As shown, each hardware computing cluster includes its first transmission interface and a first arbitrator), and the first hardware computing cluster obtains its corresponding first data from the first memory (the first memory space corresponding to the first hardware computing cluster) based on the first transmission interface through the first arbitrator; accordingly, in step S240, it includes:

[0127] The first hardware computing cluster divides the first data through the first arbitrator based on the number of first hardware computing units included in the first hardware computing cluster, determines the first sub-data corresponding to each first hardware computing unit, processes each first sub-data respectively through each first hardware computing unit to obtain a first sub-result of each first sub-data; and summarizes each first sub-result through the first arbitrator to obtain a first computing result of the first hardware computing cluster.

[0128] In some possible examples, the aforementioned first transmission interface may be a DMA interface, and accordingly, the first hardware computing cluster may obtain its first data from the first memory space corresponding to the first hardware computing cluster in the first memory (and subsequently transmit the first calculation result to the first memory space corresponding to the first hardware computing cluster in the first memory) through the first arbitrator based on the first transmission interface and using a DMA transmission method. In the above example, the first transmission interface of the first hardware computing cluster may be controlled by a third DMA controller for DMA transmission of data between the first hardware computing cluster and the first memory. The third DMA controller may be the same physical device as the first DMA controller corresponding to the aforementioned first hardware computing cluster.

[0129] In some other possible examples, the aforementioned first transmission interface may also be other types of transmission interfaces. For example, the acceleration device also includes a specific controller for transmitting data between the hardware computing cluster and the first memory. The first transmission interface may be a data transmission interface provided by the specific controller. Accordingly, the first arbitrator of the first hardware computing cluster may realize data transmission between the first hardware computing cluster and the first memory through the first transmission interface provided by the feature controller.

[0130] In some other possible examples, the first transmission interface is a direct connection interface, that is, the first transmission interface and the first memory are directly connected through a data bus deployed on the board where the acceleration device is located. Accordingly, the first arbitrator of the first hardware computing cluster reads the first data from the first memory (the first memory space corresponding to the first hardware computing cluster) based on the first transmission interface and the aforementioned data bus (and subsequently transmits the first calculation result to the first memory space corresponding to the first hardware computing cluster in the first memory).

[0131] After the first arbitrator of the first hardware computing cluster obtains the first data corresponding to it (i.e., the first data involved in the first acceleration event corresponding to it) from the first memory based on the first transmission interface, the first arbitrator divides the first data based on the number of first hardware computing units included in the first hardware computing cluster, determines the first sub-data corresponding to each first hardware computing unit, and distributes the first sub-data corresponding to each first hardware computing unit to each first hardware computing unit. Then, each first hardware computing unit processes each first sub-data respectively to obtain the first sub-result of each first sub-data, and feeds back the first sub-result of each first sub-data to the first arbitrator; subsequently, the first arbitrator of the first hardware computing cluster summarizes each first sub-result to obtain the first computing result of the first hardware computing cluster. In the process of dividing the first data, the division is performed in a uniform division manner.

[0132] In some possible examples, after obtaining each first calculation result in step S240, the method may further include steps 41-42: in step 41, each hardware computing cluster stores its first calculation result in a first memory space corresponding to each hardware computing cluster. Specifically, the first arbiter of each hardware computing cluster stores its first calculation result in the first memory space corresponding to each hardware computing cluster based on its first transmission interface.

[0133] In some possible examples, the first arbitrator of each hardware computing cluster can determine the specific storage location of the first computing result of each hardware computing cluster in the first memory space corresponding to each hardware computing cluster based on a specific data processing storage algorithm or protocol, so as to avoid overwriting the next batch of data that has not been processed by each hardware computing cluster and stored in the first memory space corresponding to each hardware computing cluster when storing the first computing result of each hardware computing cluster, or overwriting the computing results of the previous batch of data that has not been transmitted to the computing device, thereby causing data loss.

[0134] Exemplarily, the first memory space corresponding to each hardware computing cluster (taking hardware computing cluster i as an example) includes a first subspace and a second subspace, wherein the first subspace is used to store data (including first data) transmitted by the computing device to hardware computing cluster i, and the second subspace is used to store calculation results obtained by hardware computing cluster i.

[0135] In one case, hardware computing cluster i stores its first calculation result in the second subspace of the first memory space corresponding to hardware computing cluster i through its first arbitrator based on its first transmission interface. When hardware computing cluster i stores its first calculation result in the second subspace of the first memory space corresponding to it, the calculation result before the first calculation result of hardware computing cluster i has been transmitted to the second memory of the computing device (i.e., the second memory space corresponding to hardware computing cluster i in the second memory). At this time, hardware computing cluster i stores its first calculation result in the second subspace of the first memory space corresponding to hardware computing cluster i in an overwritten storage manner. Subsequently, the data management component can transmit the first calculation result stored in the second subspace of the first memory space corresponding to hardware computing cluster i to the second memory of the computing device (the second memory space corresponding to hardware computing cluster i in the second memory).

[0136] In another case, the second subspace of the first memory space corresponding to the hardware computing cluster i may include two storage areas (respectively storage areas 3 and 4), and the two storage areas may store the first calculation result calculated by the hardware computing cluster i in turn. For example, the calculation result before the first calculation result is stored in the storage area 3 of the second subspace of the first memory space corresponding to the hardware computing cluster i. Correspondingly, the hardware computing cluster i stores its first calculation result in the storage area 4 of the second subspace of the first memory space corresponding to the hardware computing cluster i. Subsequently, the data management component transmits the first calculation result stored in the storage area 4 in the second subspace of the first memory space corresponding to the hardware computing cluster i to the second memory of the computing device (the second memory space corresponding to the hardware computing cluster i in the second memory).

[0137] In some implementations, the acceleration device may include the aforementioned multiple registers, and the multiple registers include registers that have a corresponding relationship with each hardware computing cluster; the corresponding relationship between the register and the hardware computing cluster is configured for each hardware computing cluster by the hardware acceleration program when it is initialized. Accordingly, in step 42, the first mark value and the storage location of its first calculation result in its corresponding first memory space are recorded in the register corresponding to each hardware computing cluster, and the first mark value indicates that the hardware computing cluster obtains the first calculation result (that is, the processing status of the hardware computing cluster is marked as processing to obtain its first calculation result). This allows the data management component of the computing device to know that each hardware computing cluster has completed processing of each first data and obtained the first calculation result of each first data.

[0138] Exemplarily, after each of the aforementioned hardware computing clusters stores its first computing result in the first memory corresponding to each hardware computing cluster through its first arbitrator based on its first transmission interface, the first arbitrator of each hardware computing cluster may perform the action of the above step 42. Also exemplarily, when the first transmission interface is a DMA interface, the first arbitrator of each hardware computing cluster or the DMA controller involved in the DMA interface may also perform the action of the above step 42.

[0139] As another example, when the first transmission interface is a data transmission interface provided by the aforementioned specific controller, the specific controller performs the action of step 42 above.

[0140] Continuing with the above example, when each hardware computing cluster (taking hardware computing cluster i as an example) stores its first calculation result in the second subspace of the first memory space corresponding to hardware computing cluster i in an overwritten storage manner, the storage position of the first calculation result of hardware computing cluster i in the first memory space corresponding to it can be a storage position in the second subspace of the first memory space corresponding to hardware computing cluster i (for example, the starting position is a specified starting position of the second subspace, the calculation results are all stored starting from the specified starting position, and the ending position is the position corresponding to the sum of the specified starting position and the length of the first calculation result).

[0141] In the case where hardware computing cluster i stores its first calculation result to storage area 4 of the second subspace of the first memory space corresponding to hardware computing cluster i, the storage location of the first calculation result of hardware computing cluster i in the first memory space corresponding to it can be storage area 4 of the second subspace of the first memory space corresponding to hardware computing cluster i (for example, the starting position is the specified starting position of storage area 4, the calculation results are all stored starting from the specified starting position, and the ending position is the position corresponding to the sum of the specified starting position and the length of the first calculation result).

[0142] Subsequently, at step S250, the computing device obtains the first computing result of each hardware computing cluster from the acceleration device, and at step S260, the computing device determines the result of the hardware acceleration task based on the first computing result of each hardware computing cluster.

[0143] Each hardware computing cluster of the acceleration device obtains its first computing result respectively, and after transmitting each first computing result to the first memory space corresponding to each hardware computing cluster in the first memory to which it is connected, in some examples, when the register corresponding to each hardware computing cluster records the first tag value and the storage position of the first computing result of each hardware computing cluster in its corresponding first memory space, the computing device can periodically or non-periodically traverse the registers corresponding to each hardware computing cluster through the device management component of the hardware acceleration program. When the device management component determines that the register corresponding to each hardware computing cluster records the first tag value and the storage position of the first computing result of each hardware computing cluster in its corresponding first memory space, the device management component reads the storage position of the first computing result of the hardware computing cluster in its corresponding first memory space from the register corresponding to the hardware computing cluster, and transmits the storage position read to the data management component, so as to obtain each first computing result from the acceleration device through the data management component based on the storage position read by the device management component.

[0144] Specifically, after the data management component obtains the storage location of the first calculation result of each hardware computing cluster in its corresponding first memory space from the device management component, it can obtain the second memory space corresponding to each hardware computing cluster from the device information interface; then, for the first calculation result of each hardware computing cluster, a corresponding DMA request (hereinafter referred to as the second DMA request) is created, and then the data management component sends each second DMA request to the first DMA controller corresponding to each hardware computing cluster (or the second DMA controller on the computing device side mentioned above), so that each first DMA controller (or second DMA controller) transfers the first calculation result of its corresponding hardware computing cluster from the corresponding storage location in the first memory space to the second memory space corresponding to each hardware computing cluster based on the information indicated by the second DMA request it receives, so as to provide the first calculation result of each hardware computing cluster to the computing device.

[0145] Among them, the information indicated by each second DMA request (taking the second DMA request q created for the first calculation result q of the hardware computing cluster q as an example) may include the storage location of the first calculation result q in the first memory space corresponding to the hardware computing cluster q, which is the source address of the first calculation result q at this time), the data length of the first calculation result q and the storage location to which the first calculation result q needs to be transmitted (that is, the second memory space corresponding to the hardware computing cluster q, which is the destination address of the first calculation result q at this time), the event identifier of the first acceleration event involving the first data corresponding to the first calculation result q, and the identifier of the first software (and the first process) corresponding to the first calculation result q (that is, the identifier of the first software (and the first process) corresponding to the first data corresponding to the first calculation result q).

[0146] Exemplarily, the data management component (or the aforementioned first DMA controllers) can manage the processing process of each first data, and can determine the correspondence between each first data and its first calculation result. Accordingly, based on which software (and process) each first data belongs to and which event it involves, it can be determined which acceleration event the first calculation result corresponding to each first data involves and which software (and process) it belongs to, that is, the event identifier corresponding to the first calculation result and the identifier of the first software (and first process) can be determined.

[0147] In another exemplary embodiment, when the computing device transmits each first data to the first memory for transmission to each hardware computing cluster, the data can be transmitted in the form of a data stream. A data stream can carry a first data corresponding to it and an event identifier of a first acceleration event corresponding to the first data, and can also carry an identifier of a first software corresponding to the first data (or an identifier of a first process involved), so as to indicate which acceleration event, software (process) the first data belongs to.

[0148] The following description is made by taking an example in which a data stream carries a first data corresponding to the data stream and an event identifier of a first acceleration event corresponding to the first data.

[0149] The computing device can transmit a data stream carrying the first data corresponding to each hardware computing cluster and the event identifier of the first acceleration event corresponding to the first data to the first memory for transmission to each hardware computing cluster. Accordingly, the first memory space corresponding to each hardware computing cluster can store the first data corresponding to it and the event identifier of the first acceleration event corresponding to the first data, and each corresponding hardware computing cluster can know which acceleration event the first data processed by it belongs to. Subsequently, after each hardware computing cluster completes processing of its first data and obtains the first calculation result corresponding to the first data, it can identify the first calculation result corresponding to the first data based on the event identifier of the first acceleration event corresponding to the first data, so as to identify the correspondence between the first data and the first calculation result, and identify the correspondence between the first calculation result and the event identifier of the first acceleration event.

[0150] Correspondingly, the software stack of the computing device can determine whether to obtain the first calculation results of all the first data of the task data (and determine whether to obtain the calculation results of other divided data of the task data based on the event identifier corresponding to each first calculation result (and the identifier of the corresponding first software (or the identifier of the first process involved)). After determining that the calculation results of all the divided data of the task data are obtained, the calculation results of all the divided data of the task data are obtained from the second memory space corresponding to each hardware computing cluster in the second memory, and the calculation results of all the divided data of the task data are summarized to obtain the result corresponding to the task data (i.e., the hardware acceleration task).

[0151] Among them, the hardware acceleration task indicates a method of summarizing the calculation results of all the divided data of the task data to obtain the result corresponding to the task data (i.e., the hardware acceleration task). The software stack can adopt this method to summarize the calculation results of all the divided data of the task data to obtain the result corresponding to the task data (i.e., the hardware acceleration task). For example: if the hardware acceleration task is a task involving multi-data multiplication, it is necessary to multiply the calculation results of all the divided data of the task data to obtain the result of the hardware acceleration task; for example, if the hardware acceleration task is a task involving multi-scalar multiplication, it is necessary to add the calculation results of all the divided data of the task data to obtain the result of the hardware acceleration task.

[0152] Exemplarily, in the process of the aforementioned data management component creating a second DMA request for each first calculation result, the data management component calls the driver of the acceleration device based on the interface for data transmission provided by the driver of the aforementioned acceleration device, so as to create a second DMA request for each first calculation result through the driver of the acceleration device.

[0153] In the above example, the computing device can determine whether to perform data transmission by detecting the processing status of each hardware computing cluster recorded in its corresponding register. For example, when the computing device detects through the device management component that the processing status of the hardware computing cluster recorded in the corresponding register of the hardware computing cluster is processing completed (for example, recording the first mark value), the calculation result of the hardware computing cluster can be obtained from the storage location (i.e., the first memory corresponding to the hardware computing cluster) based on the storage location of the calculation result of the hardware computing cluster recorded in the corresponding register of the hardware computing cluster; for another example, the device management component detects that the processing status of the hardware computing cluster recorded in the corresponding register of the hardware computing cluster is processing, then the device management component periodically or non-periodically detects whether the processing status of the hardware computing cluster recorded in the corresponding register of the hardware computing cluster is processing completed (i.e., whether the first mark value is recorded), until it is detected that the processing status of the hardware computing cluster recorded in the corresponding register of the hardware computing cluster is processing completed (i.e., recording the first mark value), based on the storage location of the calculation result of the hardware computing cluster recorded in the corresponding register of the hardware computing cluster, the calculation result of the hardware computing cluster is obtained from the storage location (i.e., the first memory corresponding to the hardware computing cluster).

[0154] In some examples, each hardware computing cluster of the acceleration device obtains its first computing result respectively, and after transmitting each first computing result to the first memory to which it is connected, an interrupt signal can be sent to the computing device to notify the computing device that each hardware computing cluster has completed processing its first data and obtained the corresponding first computing result. Accordingly, the computing device can obtain the interrupt signal through the device management component, and then call the data management component to obtain each first computing result from the acceleration device based on the storage location of the first computing result of each hardware computing cluster in its corresponding first memory through the data management component, and store it in the second memory space corresponding to each hardware computing cluster in the second memory of the computing device.

[0155] In this embodiment, the acceleration device is provided with a first memory and multiple hardware computing clusters, each of which includes at least one hardware computing unit, and each of which is connected to the first memory of the acceleration device. Based on the hardware structure of the acceleration device, each first data is allocated to each hardware computing cluster through software, that is, the first data of each hardware computing cluster is transmitted to the first memory, and each hardware computing cluster obtains the first data from the first memory and processes the first data based on at least one hardware computing unit included therein, so as to reduce the number of data acquisition times for the first memory to a certain extent, reduce the preemption of memory read and write resources to a certain extent, so as to realize the rational use of the resources of the acceleration device, avoid the problem of resource competition to a certain extent, so as to better realize the hardware acceleration processing of data and improve the data operation speed.

[0156] In addition, the hardware acceleration program is divided into various components (such as a software stack and a target program, wherein the target program includes a user-mode subroutine and a kernel-mode subroutine), which makes it easier to transplant the hardware acceleration program and more user-friendly. For example, for software that has hardware acceleration requirements, the software stack in the hardware acceleration program can be embedded in the software, its acceleration interface can be set to be callable by the software, and the target program associated with the software stack can be installed in the computing device where the software is located. In some cases, the relevant data for hardware acceleration can also be modified according to the needs of the software to adapt to the division method of the task data.

[0157] In addition, in the above example, the hardware acceleration program configures the acceleration task queues of each hardware computing cluster corresponding to at least one process of the first software through the acceleration task creation and release interface in the user-state subroutine, thereby realizing the storage of the acceleration tasks of each process and the initial allocation of the hardware computing clusters corresponding to each acceleration task; and configures the acceleration event queues corresponding to each hardware computing cluster through the kernel-state subroutine, so that the allocation of the hardware computing clusters actually corresponding to the acceleration tasks of each process can be realized based on the task triggering sequence of each process and in turn based on the status of each hardware computing cluster, so as to facilitate the orderly management of data involved in hardware acceleration tasks between multiple processes to a certain extent, and better improve the hardware acceleration processing speed.

[0158] In some possible examples, in order to provide users with better services, the hardware acceleration program also provides users with information query services so that users can obtain information about the acceleration device. Specifically, the method may further include step 51:

[0159] In step 51, the software stack responds to the query request issued by the first software indicating the query of the information of each hardware computing cluster, calls the device information interface of the user-mode subroutine, the device information interface calls the device management component of the kernel-mode subroutine, the device management component obtains the information of each hardware computing cluster through the driver of the acceleration device, and feeds back to the first software through the device information interface. In this example, the first software can provide a trigger to the user to instruct the query of the information of each hardware computing cluster. In response to the user's trigger, the first software generates a query request indicating the query of the information of each hardware computing cluster, and sends it to the software stack. The software stack responds to the query request issued by the first software and calls the device information interface. Then, the device information interface calls the device management component. The device management component obtains the information of each hardware computing cluster through the driver of the acceleration device, and feeds back to the first software through the device information interface. The first software provides it to the user for the user to view.

[0160] Corresponding to the above method embodiment, the embodiment of this specification provides another data processing method, which is applied to a computing device, wherein the computing device is connected to an acceleration device, wherein the acceleration device is provided with a plurality of hardware computing clusters, each of which includes a first memory and at least one hardware computing unit, and each of which is connected to the first memory. Figure 4 As shown, the method may include the following steps S410-S440:

[0161] In step S410, a plurality of first acceleration events corresponding to the plurality of hardware computing clusters are determined, wherein first data related to each first acceleration event is obtained by dividing task data of the hardware acceleration task;

[0162] In step S420, first data related to each first acceleration event is transmitted to a first memory, so as to be transmitted to each hardware computing cluster;

[0163] In step S430, a first calculation result of each hardware calculation cluster is obtained from the acceleration device, and the first calculation result is obtained by each hardware calculation cluster through the following steps: obtaining first data from a first memory and processing the first data using at least one hardware calculation unit included therein;

[0164] In step S440, the result of the hardware acceleration task is determined based on the first calculation result of each hardware calculation cluster.

[0165] In some possible implementations, the first memory provides each hardware computing cluster with its own corresponding first memory space; the first data related to each first acceleration event is transmitted to the first memory for transmission to each hardware computing cluster, including: the first data related to each first acceleration event is transmitted to the first memory space corresponding to each hardware computing cluster for transmission to each hardware computing cluster.

[0166] In some possible implementations, it also includes: in the process of each hardware computing cluster obtaining the first data from the first memory and processing the first data using at least one hardware computing unit included therein, the second data involved in each second acceleration event is transmitted to the first memory for transmission to each hardware computing cluster, wherein the second data involved in each second acceleration event is obtained by dividing the task data.

[0167] In some possible implementations, the acceleration device further includes a plurality of registers, and each hardware computing cluster is configured with a corresponding register; after each hardware computing cluster obtains the first computing result, it records in its corresponding register a first mark value indicating that its data processing is completed, and records a storage location of its first computing result in the first memory;

[0168] The obtaining the first calculation result of each hardware calculation cluster from the acceleration device includes:

[0169] Based on the first tag value recorded in the register corresponding to each hardware computing cluster and the storage position of the first computing result in the first memory, the first computing result of each hardware computing cluster is obtained.

[0170] In some possible implementations, the method is performed by a hardware acceleration program, the hardware acceleration program includes a software stack and a target program; and determining first acceleration events corresponding to a plurality of hardware computing clusters respectively includes:

[0171] In response to the hardware acceleration task issued by the first software, the software stack divides the task data based on the number of the multiple hardware computing clusters to obtain a plurality of divided data, wherein the plurality of divided data includes the first data;

[0172] The target program is called, and the target program determines the hardware computing cluster corresponding to each first data; and generates each first acceleration event based on the hardware computing cluster corresponding to each first acceleration task.

[0173] In some possible implementations, the target program includes a user-mode subroutine and a kernel-mode subroutine;

[0174] The calling of the target program, wherein the target program determines the hardware computing cluster corresponding to each first data, includes:

[0175] The software stack calls the acceleration task creation and release interface of the user-mode subroutine, generates a first acceleration task for each first data, and calls the event management component of the kernel-mode subroutine;

[0176] The event management component determines a hardware computing cluster corresponding to each first acceleration task.

[0177] In some possible implementations, the dividing the task data based on the number of the multiple hardware computing clusters includes: determining whether hardware acceleration is required based on the data volume of the task data; and if it is determined that hardware acceleration is required, dividing the task data based on the number of the multiple hardware computing clusters.

[0178] In some possible implementations, the computing device includes a second memory; and the method further includes:

[0179] When the first software is started, the software stack initializes the target program as follows:

[0180] The memory application and release interface of the user-mode subroutine is configured with first memory spaces corresponding to each hardware computing cluster, wherein the first memory space is provided by the first memory; the acceleration task creation and release interface of the user-mode subroutine is configured with acceleration task queues of each hardware computing cluster corresponding to each process of the first software; and the device information interface of the user-mode subroutine is configured with second memory spaces corresponding to each hardware computing cluster in the second memory, wherein the second memory space corresponding to each hardware computing cluster is used to store the first computing results of each hardware computing cluster, and the acceleration task queues of each hardware computing cluster corresponding to each process are used to store the acceleration tasks of the process that are initially assigned to the corresponding hardware computing cluster.

[0181] In some possible implementations, the acceleration device further includes a plurality of registers;

[0182] The initialization further includes: configuring corresponding registers for each hardware computing cluster, so that each hardware computing cluster records the processing status of each hardware computing cluster and the storage location of the first computing result in the first memory space in the corresponding register.

[0183] In some possible implementations, it also includes: the software stack responds to the query request issued by the first software to query the information of each hardware computing cluster, calls the device information interface of the user state subroutine, the device information interface calls the device management component of the kernel state subroutine, the device management component obtains the information of each hardware computing cluster through the driver of the acceleration device, and feeds back to the first software through the device information interface.

[0184] Corresponding to the above method embodiment, the embodiment of this specification provides another data processing method, which is applied to an acceleration device, the acceleration device is connected to a computing device, the acceleration device is provided with a first memory and a plurality of hardware computing clusters, each hardware computing cluster includes at least one hardware computing unit, each hardware computing cluster is connected to the first memory, such as Figure 5As shown, the method may include the following steps S510-S520:

[0185] In step S510, each hardware computing cluster of the acceleration device obtains first data related to each first acceleration event from the first memory, wherein the first data is data transmitted to the first memory after the computing device determines each first acceleration event corresponding to each hardware computing cluster, so as to be transmitted to each hardware computing cluster, and each first data is obtained by the computing device by dividing the task data of the hardware acceleration task; in step S520, the first data is processed by using at least one hardware computing unit included therein to obtain each first calculation result, and each first calculation result is provided to the computing device.

[0186] In some possible implementations, the first memory provides each hardware computing cluster with its own corresponding first memory space; and obtaining the first data related to each first acceleration event from the first memory respectively includes: obtaining the corresponding first data from the first memory space corresponding to each hardware computing cluster respectively.

[0187] In some possible implementations, the multiple hardware computing clusters include a first hardware computing cluster, the first hardware computing cluster also includes a first transmission interface and a first arbitrator, and the first hardware computing cluster obtains the first data corresponding to it from the first memory through its first arbitrator based on the first transmission interface;

[0188] The process of using at least one hardware computing unit included therein to process the first data and obtain a first computing result includes: the first hardware computing cluster divides the first data through the first arbitrator based on the number of first hardware computing units included in the first hardware computing cluster, determines the first sub-data corresponding to each first hardware computing unit, and processes each first sub-data respectively through each first hardware computing unit to obtain a first sub-result of each first sub-data; and summarizes each first sub-result through the first arbitrator to obtain the first computing result of the first hardware computing cluster.

[0189] In some possible implementations, the acceleration device further includes a plurality of registers, the plurality of registers including registers corresponding to each hardware computing cluster; the first memory provides each hardware computing cluster with its respective first memory space; after obtaining each first computing result, the method further includes: each hardware computing cluster stores its first computing result in the first memory space corresponding to each hardware computing cluster; recording a first tag value and a storage location of the first computing result in the first memory space corresponding to each hardware computing cluster in the register corresponding to each hardware computing cluster, the first tag value indicating that the hardware computing cluster obtains the first computing result.

[0190] The foregoing describes certain embodiments of the present specification, and other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims may be performed in an order different from that in the embodiments, and the desired results may still be achieved. In addition, the processes depicted in the accompanying drawings do not necessarily have to be performed in the specific order or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0191] Corresponding to the above method embodiment, the present specification embodiment provides an acceleration device, wherein the acceleration device is connected to a computing device, such as Figure 6 As shown, the acceleration device is provided with a first memory 610 and a plurality of hardware computing clusters 620, each of which includes at least one hardware computing unit, and each of which is connected to the first memory 610 of the acceleration device;

[0192] The second transmission interface 630 is used to obtain first data related to each first acceleration event from the computing device, store it in the first memory 610, and transmit it to each hardware computing cluster. The first data is transmitted to the first memory after the computing device determines each first acceleration event corresponding to each hardware computing cluster. Each first data is obtained by the computing device by dividing the task data of the hardware acceleration task.

[0193] The multiple hardware computing clusters 620 of the acceleration device are used to obtain the first data related to the corresponding first acceleration event from the first memory 610 respectively, use at least one hardware computing unit included therein to process the obtained first data to obtain the first computing result of each hardware computing cluster; and provide the first computing result of each hardware computing cluster to the computing device.

[0194] Corresponding to the above method embodiment, the embodiment of this specification provides a data processing device 700, which is deployed on a computing device, the computing device is connected to an acceleration device, the acceleration device is provided with a first memory and a plurality of hardware computing clusters, each of which includes at least one hardware computing unit, each of which is connected to the first memory, and the schematic block diagram of the data processing device 700 is as follows: Figure 7As shown, it includes: a first determination module 710, configured to determine multiple first acceleration events corresponding to multiple hardware computing clusters, wherein the first data involved in each first acceleration event is obtained by dividing the task data of the hardware acceleration task; a transmission module 720, configured to transmit the first data involved in each first acceleration event to the first memory, so as to transmit it to each hardware computing cluster; an acquisition module 730, configured to obtain the first calculation result of each hardware computing cluster from the acceleration device, and the first calculation result is obtained by each hardware computing cluster through the following steps: obtaining the first data from the first memory and processing the first data using at least one hardware computing unit included therein; a second determination module 740, configured to determine the result of the hardware acceleration task based on the first calculation result of each hardware computing cluster.

[0195] The above device embodiments correspond to the method embodiments. For specific descriptions, please refer to the description of the method embodiments, which will not be repeated here. The device embodiments are obtained based on the corresponding method embodiments and have the same technical effects as the corresponding method embodiments. For specific descriptions, please refer to the corresponding method embodiments.

[0196] The embodiments of the present specification also provide a computer-readable storage medium on which a computer program is stored. When the computer program is executed in a computer, the computer is caused to execute the data processing method provided in the present specification.

[0197] An embodiment of the present specification also provides a computing device, including a memory and a processor, wherein the memory stores executable code, and when the processor executes the executable code, the data processing method provided in the present specification is implemented.

[0198] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the storage medium and computing device embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0199] In the 1990s, improvements to a technology could be clearly distinguished as hardware improvements (for example, improvements to the circuit structure of diodes, transistors, switches, etc.) or software improvements (improvements to the method flow). However, with the development of technology, many improvements to the method flow today can be regarded as direct improvements to the hardware circuit structure. Designers almost always obtain the corresponding hardware circuit structure by programming the improved method flow into the hardware circuit. Therefore, it cannot be said that an improvement in a method flow cannot be implemented using a hardware entity module. For example, a programmable logic device (PLD) (such as a field programmable gate array (FPGA)) is such an integrated circuit whose logical function is determined by the user's programming of the device. Designers can "integrate" a digital system on a PLD by programming it themselves, without having to ask a chip manufacturer to design and produce a dedicated integrated circuit chip. Moreover, nowadays, instead of manually making integrated circuit chips, this kind of programming is mostly implemented by "logic compiler" software, which is similar to the software compiler used when developing and writing programs, and the original code before compilation must also be written in a specific programming language, which is called hardware description language (HDL). There is not only one HDL, but many kinds, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, RHDL (Ruby Hardware Description Language), etc. The most commonly used ones are VHDL (Very-High-Speed ​​Integrated Circuit Hardware Description Language) and Verilog. Those skilled in the art should also know that it is only necessary to program the method flow slightly in the above-mentioned hardware description languages ​​and program it into the integrated circuit, and then it is easy to obtain the hardware circuit that implements the logic method flow.

[0200] The controller can be implemented in any appropriate manner, for example, the controller can take the form of a microprocessor or processor and a computer-readable medium storing a computer-readable program code (such as software or firmware) that can be executed by the (micro)processor, a logic gate, a switch, an application-specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller. Examples of controllers include, but are not limited to, the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicone Labs C8051F320. The memory controller can also be implemented as part of the control logic of the memory. Those skilled in the art also know that in addition to implementing the controller in a purely computer-readable program code manner, the controller can be implemented in the form of a logic gate, a switch, an application-specific integrated circuit, a programmable logic controller, and an embedded microcontroller by logically programming the method steps. Therefore, this controller can be considered as a hardware component, and the devices included therein for implementing various functions can also be regarded as structures within the hardware component. Or even, the devices for implementing various functions can be regarded as both software modules for implementing the method and structures within the hardware component.

[0201] The systems, devices, modules or units described in the above embodiments may be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a server system. Of course, the present application does not exclude that with the development of computer technology in the future, the computer that implements the functions of the above embodiments may be, for example, a personal computer, a laptop computer, a vehicle-mounted human-computer interaction device, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0202] Although one or more embodiments of the present specification provide method operation steps as described in the embodiments or flow charts, more or less operation steps may be included based on conventional or non-creative means. The order of steps listed in the embodiments is only one way of executing the order of many steps, and does not represent the only execution order. When the device or terminal product in practice is executed, it can be executed in sequence or in parallel according to the method shown in the embodiments or the drawings (for example, a parallel processor or a multi-threaded processing environment, or even a distributed data processing environment). The term "include", "include" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, product or equipment including a series of elements includes not only those elements, but also includes other elements that are not explicitly listed, or also includes elements inherent to such a process, method, product or equipment. In the absence of more restrictions, it is not excluded that there are other identical or equivalent elements in the process, method, product or equipment including the elements. For example, if the words first, second, etc. are used to represent the name, they do not represent any specific order.

[0203] For the convenience of description, the above devices are described in various modules according to their functions. Of course, when implementing one or more of the present specification, the functions of each module can be implemented in the same or more software and / or hardware, or the module implementing the same function can be implemented by a combination of multiple sub-modules or sub-units, etc. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0204] This specification is described with reference to the flowcharts and / or block diagrams of the methods, apparatus (systems), and computer program products according to the embodiments of this specification. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0205] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0206] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0207] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0208] The memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0209] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic disk storage, graphene storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0210] It should be understood by those skilled in the art that one or more embodiments of the present specification may be provided as a method, system or computer program product. Therefore, one or more embodiments of the present specification may take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware. Moreover, one or more embodiments of the present specification may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0211] One or more embodiments of the present specification may be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. One or more embodiments of the present specification may also be practiced in distributed computing environments where tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules may be located in local and remote computer storage media, including storage devices.

[0212] Each embodiment in this specification is described in a progressive manner, and the same and similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment. In the description of this specification, the description of the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of this specification. In this specification, the schematic representation of the above terms does not necessarily target the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples without contradiction.

[0213] The above description is only an example of one or more embodiments of the present specification and is not intended to limit one or more embodiments of the present specification. For those skilled in the art, one or more embodiments of the present specification may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present specification shall be included in the scope of the claims.

Claims

1. A data processing method, the method is applied to a computing device, the computing device is connected to an acceleration device, the acceleration device is provided with a first memory and a plurality of hardware computing clusters, each hardware computing cluster includes at least one hardware computing unit, each hardware computing cluster is connected to the first memory, the method include: Determine a plurality of first acceleration events corresponding to the plurality of hardware computing clusters, wherein first data related to each first acceleration event is obtained by dividing task data of the hardware acceleration task; Transmitting first data related to each first acceleration event to the first memory for transmission to each hardware computing cluster; Acquire a first calculation result of each hardware computing cluster from the acceleration device, wherein the first calculation result is obtained by each hardware computing cluster through the following steps: obtain the first data from the first memory, and process the first data using at least one hardware computing unit included therein; Based on the first calculation results of each hardware calculation cluster, the result of the hardware acceleration task is determined.

2. The method according to claim 1, in, The first memory provides each hardware computing cluster with its corresponding first memory space; The transmitting the first data related to each first acceleration event to the first memory for transmitting to each hardware computing cluster includes: The first data related to each first acceleration event is transmitted to the first memory space corresponding to each hardware computing cluster, so as to be transmitted to each hardware computing cluster.

3. The method according to claim 1, further comprising: include: In the process of each hardware computing cluster obtaining the first data from the first memory and processing the first data using at least one hardware computing unit included therein, the second data involved in each second acceleration event is transmitted to the first memory to be transmitted to each hardware computing cluster, wherein the second data involved in each second acceleration event is obtained by dividing the task data.

4. The method according to claim 1, in, The acceleration device further includes a plurality of registers, each hardware computing cluster being configured with a corresponding register; after each hardware computing cluster obtains the first computing result, it records in its corresponding register a first mark value indicating that its data processing is completed, and records a storage location of its first computing result in the first memory; The obtaining the first calculation result of each hardware calculation cluster from the acceleration device includes: Based on the first tag value recorded in the register corresponding to each hardware computing cluster and the storage position of the first computing result in the first memory, the first computing result of each hardware computing cluster is obtained.

5. The method according to any one of claims 1 to 4, in, The method is performed by a hardware acceleration program, the hardware acceleration program includes a software stack and a target program; the determining of first acceleration events corresponding to a plurality of hardware computing clusters respectively includes: In response to the hardware acceleration task issued by the first software, the software stack divides the task data based on the number of the multiple hardware computing clusters to obtain a plurality of divided data, wherein the plurality of divided data includes the first data; The target program is called, and the target program determines the hardware computing cluster corresponding to each first data; and generates each first acceleration event based on the hardware computing cluster corresponding to each first acceleration task.

6. The method according to claim 5, in, The target program includes a user-mode subroutine and a kernel-mode subroutine; The calling of the target program, wherein the target program determines the hardware computing cluster corresponding to each first data, includes: The software stack calls the acceleration task creation and release interface of the user-mode subroutine, generates a first acceleration task for each first data, and calls the event management component of the kernel-mode subroutine; The event management component determines a hardware computing cluster corresponding to each first acceleration task.

7. The method of claim 5, wherein the task data is divided based on the number of the plurality of hardware computing clusters. include: Determining whether hardware acceleration is required based on the data volume of the task data; When it is determined that hardware acceleration is required, the task data is divided based on the number of the multiple hardware computing clusters.

8. The method according to claim 6, in, The computing device includes a second memory; The method further comprises: When the first software is started, the software stack initializes the target program as follows: configuring first memory spaces corresponding to each hardware computing cluster for a memory application and release interface of the user-mode subroutine, wherein the first memory spaces are provided by the first memory; Creating and releasing interfaces for the acceleration tasks of the user-mode subroutine to configure acceleration task queues of each hardware computing cluster corresponding to each process of the first software; and The second memory space corresponding to each hardware computing cluster in the second memory is configured according to the device information interface of the user-mode subroutine. Among them, the second memory space corresponding to each hardware computing cluster is used to store the first computing result of each hardware computing cluster, and the acceleration task queue of each hardware computing cluster corresponding to each process is used to store the acceleration task of the process initially assigned to the corresponding hardware computing cluster.

9. The method of claim 8, wherein the acceleration device further comprises a plurality of registers; The initialization also include: A corresponding register is configured for each hardware computing cluster, so that each hardware computing cluster records the processing state of each hardware computing cluster and the storage location of the first computing result in the first memory space in the corresponding register.

10. The method according to claim 6, further comprising: include: The software stack responds to the query request issued by the first software to query the information of each hardware computing cluster, calls the device information interface of the user-mode subroutine, and the device information interface calls the device management component of the kernel-mode subroutine. The device management component obtains the information of each hardware computing cluster through the driver of the acceleration device and feeds it back to the first software through the device information interface.

11. A data processing method, the method is applied to an acceleration device, the acceleration device is connected to a computing device, the acceleration device is provided with a first memory and a plurality of hardware computing clusters, each hardware computing cluster includes at least one hardware computing unit, each hardware computing cluster is connected to the first memory, the method include: Each hardware computing cluster of the acceleration device obtains first data related to each first acceleration event from the first memory, wherein the first data is data transmitted to the first memory after the computing device determines each first acceleration event corresponding to each hardware computing cluster, so as to be transmitted to each hardware computing cluster, and each first data is obtained by the computing device by dividing the task data of the hardware acceleration task; The first data is processed by at least one hardware computing unit included therein to obtain each first computing result, and each first computing result is provided to the computing device.

12. The method according to claim 11, in, The first memory provides each hardware computing cluster with its corresponding first memory space; The obtaining first data related to each first acceleration event from the first memory respectively includes: The first data corresponding to each hardware computing cluster is obtained from the first memory space corresponding to each hardware computing cluster.

13. The method according to claim 11, in, The multiple hardware computing clusters include a first hardware computing cluster, the first hardware computing cluster also includes a first transmission interface and a first arbitrator, and the first hardware computing cluster obtains the first data corresponding to it from the first memory through its first arbitrator based on the first transmission interface; The process of using at least one hardware computing unit included therein to process the first data to obtain a first computing result includes: The first hardware computing cluster divides the first data through the first arbitrator based on the number of first hardware computing units included in the first hardware computing cluster, determines the first sub-data corresponding to each first hardware computing unit, processes each first sub-data respectively through each first hardware computing unit to obtain a first sub-result of each first sub-data; and summarizes each first sub-result through the first arbitrator to obtain a first computing result of the first hardware computing cluster.

14. The method according to claim 11, in, The acceleration device further includes a plurality of registers, wherein the plurality of registers include registers corresponding to each hardware computing cluster; The first memory provides each hardware computing cluster with its corresponding first memory space; After obtaining each first calculation result, the method further includes: Each hardware computing cluster stores its first computing result in a first memory space corresponding to each hardware computing cluster; A first tag value and a storage location of the first calculation result in the corresponding first memory space are recorded in a register corresponding to each hardware calculation cluster, wherein the first tag value indicates that the hardware calculation cluster obtains the first calculation result.

15. An acceleration device, in, The acceleration device is connected to a computing device, and is provided with a first memory and a plurality of hardware computing clusters, each of which includes at least one hardware computing unit, and each of which is connected to the first memory; a second transmission interface, for storing first data related to each first acceleration event obtained from the computing device in the first memory, so as to transmit the first data to each hardware computing cluster, wherein the first data is transmitted to the first memory after the computing device determines each first acceleration event corresponding to each hardware computing cluster, and each first data is obtained by the computing device by dividing the task data of the hardware acceleration task; The multiple hardware computing clusters of the acceleration device are used to obtain first data related to the corresponding first acceleration event from the first memory respectively, and use at least one hardware computing unit included therein to process the obtained first data to obtain a first computing result of each hardware computing cluster; The first calculation result of each hardware calculation cluster is provided to the calculation device.

16. The acceleration device according to claim 15, in, The acceleration device is implemented based on FPGA, and the FPGA includes multiple logic areas corresponding to the multiple hardware computing clusters.

17. A computing device, comprising a memory and a processor, wherein the computing device is connected to an acceleration device, wherein the acceleration device is provided with a first memory and multiple hardware computing clusters, each hardware computing cluster comprises at least one hardware computing unit, and each hardware computing cluster is connected to the first memory; executable code is stored in the memory, and when the processor executes the executable code, the method described in any one of claims 1 to 10 is implemented.

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