Resource scheduling system, method, device, equipment, medium and product

Abstract

The embodiments of the present application provide a resource scheduling system, method, apparatus, device, medium and product. The resource scheduling system includes a host end and a baseboard management controller chip. The baseboard management controller chip is equipped with a video data processing submodule, a random access memory management control module and a random access memory resource overall management control scheduling module. Each video data processing submodule is correspondingly provided with a random access memory management control module, and the random access memory resource information corresponding to each video data processing submodule is obtained; according to the random access memory resource information, a public random access memory corresponding to each video data processing submodule is determined to store the video data to be diverted. The present application manages and controls the random access memory resources inside each submodule in the video processing path as a whole resource, avoiding the disadvantage that the random access memory resources inside each submodule can only be used by the current submodule.

Description

Technical Field

[0001] The present application relates to the technical field of resource scheduling, and in particular to a resource scheduling system, method, device, equipment, medium and product. Background Art

[0002] The traditional server management and control chip processes video in the following way: the original video data on the host side is transmitted to the VGA module inside the baseboard management and control chip through PCIe. The original video data in RGB format generated by VGA is processed and sent to the remote end for display through the EMAC network function of the baseboard management and control chip, thereby realizing the function of remote management and control.

[0003] However, in the above-mentioned related technologies, since there is great uncertainty in the occupancy of the bus when the output control module of the last stage of the video processing path is input to the DDR, the AXI bus on the DDR side may not pull up AWready and Wready for a long time, resulting in the compressed data cannot be written into the DDR in time. The data needs to be back-pressed step by step in the processing path. In order to minimize the frame loss rate, in actual use, the large-capacity on-chip random access memory resources in the video compression path are in a situation where the random access memory resources of the current module are about to be exhausted, while the random access memory resources of the previous and next stages are idle. Therefore, it causes a great waste of random access memory resources and reduces the overall work efficiency. Summary of the invention

[0004] The purpose of the embodiments of the present application is to provide a resource scheduling system, method, device, equipment, medium and product. The specific technical solutions are as follows:

[0005] In a first aspect of the implementation of the present application, a resource scheduling system is first provided, the resource scheduling system includes a host end and a baseboard management controller chip, the baseboard management controller chip is equipped with a plurality of video data processing submodules, a random access memory management control module and a random access memory resource overall management control scheduling module, each of the video data processing submodules is correspondingly provided with a random access memory management control module, and the random access memory management control module is communicatively connected with the random access memory resource overall management control scheduling module;

[0006] The baseboard management controller chip is used to receive the video data to be diverted sent by the host end;

[0007] The random access memory management control module is used to obtain random access memory resource information corresponding to each of the video data processing submodules;

[0008] The random access memory resource overall management control scheduling module is used to determine the common random access memory corresponding to each of the video data processing submodules according to the random access memory resource information, and the common random access memory is used to store the video data to be diverted.

[0009] Optionally, the resource scheduling system further includes a memory, and a video memory space is provided in the target storage space corresponding to the memory.

[0010] Optionally, the baseboard management controller chip further includes a random access memory data bus;

[0011] The video data to be distributed is stored in the common random access memory through a random access memory data bus.

[0012] Optionally, the video data processing submodule includes any one of a color data capture module, a color space conversion module, a conversion module and an output control module. The color data capture module is correspondingly provided with a first random access memory management control module, the color space conversion module is correspondingly provided with a second random access memory management control module, the conversion module is correspondingly provided with a third random access memory management control module, and the output control module is correspondingly provided with a fourth random access memory management control module.

[0013] Optionally, the baseboard management controller chip further includes a video compression module, and the video compression module is communicatively connected with the conversion module and the output control module respectively.

[0014] Optionally, the random access memory resource overall management control scheduling module is used to perform overall scheduling of random access memory resource information corresponding to all the video data processing sub-modules on the video path of the resource scheduling system based on preset scheduling rules.

[0015] In a second aspect of the implementation of the present application, a resource scheduling method is further provided, which is applied to a baseboard management controller chip in any resource scheduling system described in the first aspect, and the method comprises:

[0016] Receive the video data to be split sent by the host;

[0017] Acquire random access memory resource information corresponding to each of the video data processing submodules;

[0018] Determining a common random access memory corresponding to each of the video data processing submodules according to the random access memory resource information;

[0019] The video data to be distributed is stored in the common random access memory through a random access memory data bus.

[0020] Optionally, the acquiring random access memory resource information corresponding to each of the video data processing submodules includes:

[0021] Obtain random access memory resource information corresponding to each of the video data processing submodules in a preset time period.

[0022] Optionally, the acquiring the random access memory resource information corresponding to each of the video data processing submodules in a preset time period includes:

[0023] The random access memory depth, the random access memory remaining space, the random access memory writing speed within a preset time period, and the random access memory reading speed within a preset time period corresponding to each of the video data processing submodules are obtained.

[0024] Optionally, determining the common random access memory corresponding to each of the video data processing submodules according to the random access memory resource information includes:

[0025] Get the preset adjustment level;

[0026] The common random access memory corresponding to each of the video data processing submodules is determined according to the random access memory depth corresponding to each of the video data processing submodules, the remaining space of the random access memory, the random access memory write speed within a preset time period, the random access memory read speed within a preset time period, and the adjustment level.

[0027] Optionally, the preset adjustment levels include a first adjustment level, a second adjustment level and a third adjustment level.

[0028] Optionally, the first public random access memory ratio corresponding to the first adjustment level is smaller than the second public random access memory ratio corresponding to the second adjustment level, and the second public random access memory ratio corresponding to the second adjustment level is smaller than the third public random access memory ratio corresponding to the third adjustment level.

[0029] Optionally, the baseboard management controller chip is equipped with a random access memory management control module and a random access memory resource overall management control scheduling module. After the step of storing the video data to be diverted to the public random access memory through a random access memory data bus, the method further includes:

[0030] When it is detected that the remaining space of the random access memory corresponding to the video data processing submodule is less than a preset threshold, a random access memory resource application signal is sent to the random access memory resource overall management control scheduling module through the random access memory management control scheduling module, so that the random access memory resource overall management control scheduling module allocates a target public random access memory space to the video data processing submodule in the public random access memory based on the random access memory resource application signal.

[0031] Optionally, before the step of sending a random access memory resource application signal to the random access memory resource overall management control scheduling module through the random access memory management control module, the method includes:

[0032] When it is detected that the remaining space of the random access memory corresponding to the video data processing submodule is less than a preset threshold value, and the write speed of the random access memory within a preset time period is less than the read speed of the random access memory within the preset time period, the level corresponding to the random access memory resource request signal is determined according to the difference between the write speed of the random access memory and the read speed of the random access memory.

[0033] Optionally, determining the level corresponding to the random access memory resource request signal according to the difference between the random access memory write speed and the random access memory read speed comprises:

[0034] When it is detected that the difference between the random access memory write speed and the random access memory read speed is less than a first threshold, setting the random access memory resource request signal as a first random access memory resource request signal;

[0035] When it is detected that the difference between the random access memory write speed and the random access memory read speed is greater than or equal to the first threshold and less than the second threshold, setting the random access memory resource request signal to a second random access memory resource request signal;

[0036] When it is detected that the difference between the random access memory write speed and the random access memory read speed is greater than or equal to a third threshold, the random access memory resource request signal is set to a third random access memory resource request signal.

[0037] In a third aspect of the implementation of the present application, a resource scheduling method is further provided, which is applied to a random access memory resource overall management control scheduling module in the resource scheduling system described in any one of the first aspects, and the method includes:

[0038] In the case where it is detected that the baseboard management controller chip receives the video data to be shunted sent by the host end, receiving the random access memory resource information corresponding to each of the video data processing submodules sent by the random access memory management control module;

[0039] A common random access memory corresponding to each of the video data processing submodules is determined according to the random access memory resource information, and the common random access memory is used to store the video data to be diverted.

[0040] In a fourth aspect of the implementation of the present application, a resource scheduling device is also provided, the device comprising:

[0041] A receiving module, used for receiving the video data to be diverted sent by the host end;

[0042] An acquisition module, used for acquiring random access memory resource information corresponding to each of the video data processing submodules;

[0043] A determination module, configured to determine a common random access memory corresponding to each of the video data processing submodules according to the random access memory resource information;

[0044] The storage module is used to store the video data to be distributed into the common random access memory through a random access memory data bus.

[0045] In a fifth aspect of the implementation of the present application, there is also provided a communication device, comprising: a transceiver, a memory, a processor, and a program stored in the memory and executable on the processor;

[0046] The processor is used to read the program in the memory to implement the resource scheduling method as described in any one of the second aspect or the third aspect.

[0047] In the sixth aspect of the implementation of the present application, a computer-readable storage medium is also provided, in which instructions are stored. When the computer-readable storage medium is executed on a computer, the computer implements the resource scheduling method as described in any one of the second aspect or the third aspect.

[0048] In the seventh aspect of the implementation of the present application, a computer program product is also provided, including a computer program / instruction, which, when executed by a processor, implements the resource scheduling method as described in any one of the second aspect or the third aspect.

[0049] The resource scheduling system provided in the embodiment of the present application includes a host end and a baseboard management controller chip, the baseboard management controller chip is equipped with a plurality of video data processing submodules, a random access memory management control module and a random access memory resource overall management control scheduling module, each of the video data processing submodules is correspondingly provided with a random access memory management control module, and the random access memory management control module and the random access memory resource overall management control scheduling module are communicatively connected; the baseboard management controller chip is used to receive the video data to be diverted sent by the host end; the random access memory management control module is used to obtain the random access memory resource information corresponding to each of the video data processing submodules; the random access memory resource overall management control scheduling module is used to determine the common random access memory corresponding to each of the video data processing submodules according to the random access memory resource information, and the common random access memory is used to store the video data to be diverted, that is, in the embodiment of the present application, the random access memory resources inside each submodule in the video processing path are managed and controlled as a whole resource, avoiding the disadvantage that the random access memory resources inside each submodule in the traditional solution can only be used by the current submodule. The resource scheduling system integrates multiple video data processing submodules, random access memory management and control modules, and random access memory resource overall management, control and scheduling modules on the baseboard management controller chip, thereby realizing efficient management and scheduling of the video data to be diverted sent by the host. The random access memory management and control module corresponding to each video data processing submodule can obtain random access memory resource information in real time, and the random access memory resource overall management, control and scheduling module intelligently determines the public random access memory corresponding to each submodule based on this information, ensuring that the video data to be diverted can be reasonably stored and allocated. This design not only improves the efficiency and flexibility of video data processing, but also optimizes the utilization of random access memory resources, reduces resource waste, thereby improving the performance and response speed of the entire system, greatly improving the overall scheduling of random access memory resources on the video processing path, greatly improving the utilization rate of random access memory resources, reducing the frame loss rate, and improving the overall performance of the baseboard management control chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art are briefly introduced below.

[0051] Figure 1 A system block diagram of a resource scheduling system provided in an embodiment of the present application;

[0052] Figure 2A flowchart of a resource scheduling method provided in an embodiment of the present application;

[0053] Figure 3 A flowchart of another resource scheduling method provided in an embodiment of the present application;

[0054] Figure 4 It is a structural diagram of a resource scheduling device provided in an embodiment of the present application;

[0055] Figure 5 It is a schematic diagram of a communication device provided in an embodiment of the present application;

[0056] Figure 6 This is a schematic diagram of random access memory resource scheduling provided in an embodiment of the present application. DETAILED DESCRIPTION

[0057] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, each embodiment of the present application will be described in detail below in conjunction with the accompanying drawings. However, it will be appreciated by those skilled in the art that in each embodiment of the present application, many technical details are proposed in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present application can also be implemented. The division of the following embodiments is for the convenience of description, and the specific implementation of the present application should not constitute any limitation, and the various embodiments can be combined with each other and referenced to each other without contradiction.

[0058] It should be noted that in the embodiment of the present application, in order to improve the overall efficiency and avoid the RAM resources inside each sub-module being only used by the current sub-module, the present application manages and controls the RAM resources inside each sub-module in the video processing path as a whole resource.

[0059] Reference Figure 1 , shows a system block diagram of a resource scheduling system provided by an embodiment of the present application, the resource scheduling system includes a host end and a baseboard management controller chip, the baseboard management controller chip is equipped with a plurality of video data processing submodules, a random access memory management control module and a random access memory resource overall management control scheduling module, each of the video data processing submodules is correspondingly provided with a random access memory management control module, the random access memory management control module and the random access memory resource overall management control scheduling module are communicatively connected;

[0060] The baseboard management controller chip is used to receive the video data to be diverted sent by the host end;

[0061] The random access memory management control module is used to obtain random access memory resource information corresponding to each of the video data processing submodules;

[0062] The random access memory resource overall management control scheduling module is used to determine the common random access memory corresponding to each of the video data processing submodules according to the random access memory resource information, and the common random access memory is used to store the video data to be diverted.

[0063] First of all, it should be noted that RAM (Random Access Memory) is a type of memory. In the embodiment of the present application, each of the video data processing submodules is provided with RAM.

[0064] It should be noted that in the embodiments of the present application, reference is made to Figure 1 It can be seen that in the embodiment of the present application, the resource scheduling system includes a host end and a baseboard management controller chip. The host end is used to send original video data, for example, original RGB video data. In the embodiment of the present application, since there is subsequent diversion processing, it is also the video data to be diverted.

[0065] Furthermore, based on the shunted video data and the random access memory management control module, the random access memory resource information corresponding to each of the video data processing sub-modules is obtained, and the random access memory resource overall management control scheduling module determines the public random access memory corresponding to each of the video data processing sub-modules according to the random access memory resource information, and the public random access memory is used to store the video data to be shunted.

[0066] For details, please refer to Figure 6 ,In the random access memory resource scheduling process, it includes the remaining space statistics, and the subsequent ,division of public RAM resources, as well as the demand detection of RAM resources, and ,subsequent continuous detection, thus constituting the overall RAM resource ,comprehensive scheduling and management process.

[0067] The baseboard management controller chip is equipped with various modules, specifically, including several video data processing sub-modules, a random access memory management control module and a random access memory resource overall management control scheduling module. In an embodiment of the present application, each of the video data processing sub-modules is correspondingly provided with a random access memory management control module.

[0068] Furthermore, the video data processing submodule includes any one of a color data capture module, a color space conversion module, a conversion module and an output control module. The color data capture module is correspondingly provided with a first random access memory management control module, the color space conversion module is correspondingly provided with a second random access memory management control module, the conversion module is correspondingly provided with a third random access memory management control module, and the output control module is correspondingly provided with a fourth random access memory management control module.

[0069] Specifically, a RAM_CTRL module is separately set for the RAM inside each sub-module in the processing path. Specifically, the color data capture module is correspondingly provided with a first random access memory management control module, that is, the color space conversion module is correspondingly provided with a second random access memory management control module, the conversion module is correspondingly provided with a third random access memory management control module, and the output control module is correspondingly provided with a fourth random access memory management control module, in order, namely Figure 1 The random access memory management control module A, the random access memory management control module B, the random access memory management control module C, and the random access memory management control module D implement the function of counting the usage of RAM resources within a preset time period T0.

[0070] It should be noted that in the embodiment of the present application, the four sub-modules on the video processing path, the color data capture module, the color space conversion module, the conversion module and the output control module respectively obtain a public random access memory, namely Public_RAM_Space, which can be recorded as Public_RAM_Space_A, Public_RAM_Space_B, Public_RAM_Space_C, and Public_RAM_Space_D.

[0071] It should be noted that in the embodiments of the present application, reference can be made to Figure 1 ,It can be seen that each module communicates and connects in sequence according to the functional order.

[0072] Furthermore, the resource scheduling system also includes a memory, and a video memory space is set in the target storage space corresponding to the memory.

[0073] Specifically, the memory in the present application is DDR, and a portion of the space in the DDR memory is set as video memory, that is, it can be understood that a portion of the DDR memory is shared with the GPU.

[0074] Specifically, the video data to be diverted on the host side is written to the video memory space A in the DDR through PCIe, and the VGA module of the baseboard management control chip reads the data in the video memory A. After processing inside the VGA, the original RGB format data is generated, and the RGB data is processed by the data conversion module.

[0075] Among them, the function of the color data capture module is to obtain the original RGB video data. Specifically, it can be done in two ways. The first can be DVI mode, which is to receive the DVI interface output of VGA. The main signals are R_DATA, G_DATA, B_DATA, line synchronization signal Hs, field synchronization signal Vs and signal Data_en indicating that the data is valid; the second can be active capture mode, which means that the color data capture module actively reads the original RGB video data in the video memory in DDR. At the same time, there is an on-chip cache resource RAM_A in the color data capture module.

[0076] Furthermore, a RAM is provided on each of the video data processing submodules.

[0077] The color space conversion module is used to convert the video data to be diverted (original RGB video data) from RGB format to YUV format. The conversion process can be completed through a matrix conversion formula. The specific formula can refer to the following formulas 1-3, which correspond to the conversion of the three channels of Y, U, and V respectively.

[0078] Y = (0.257*R) + (0.504*G) + (0.098*B) + 16 (Formula 1)

[0079] U = 0.148*R–0.291*G + 0.439*B +128 (Formula 2)

[0080] V = 0.439*R-0.368*G-0.071*B+128 (Formula 3)

[0081] At the same time, there is an on-chip cache resource RAM_B in the color space conversion module.

[0082] The conversion module is used to convert the YUV data that has completed the color space conversion into a BLOCK format.

[0083] Specifically, it is converted into 16*16 or 8*8 BLOCK data and then transmitted to the next stage. The so-called BLOCK format refers to caching the data input by line in the original video stream into the RAM array, and then controlling the read and write control of the RAM array to generate 16*16, 8*8 BLOCK format data. Therefore, 16 Y_RAMs, 16 U_RAMs, and 16 V_RAMs are required for data caching.

[0084] Furthermore, the baseboard management controller chip also includes a video compression module, and the video compression module is communicatively connected with the conversion module and the output control module respectively.

[0085] The video compression module is used to input the YUV BLOCK data into the CMP IP to complete the video compression, write the compressed data into the DDR, and the compressed data will be input into the output control module.

[0086] Further, the baseboard management controller chip also includes a random access memory data bus;

[0087] The video data to be distributed is stored in the common random access memory through a random access memory data bus.

[0088] Furthermore, the random access memory resource overall management control scheduling module is used to perform overall scheduling of random access memory resource information corresponding to all the video data processing submodules on the video path of the resource scheduling system based on preset scheduling rules.

[0089] Therefore, after counting the usage of RAM resources in the preset time period T0, the Public_RAM (i.e., public RAM) that can be divided by the current submodule can be divided according to the adjustment level set by the random access memory resource overall management control scheduling module (RAM_CTRL_TOP, RAM resource overall management control scheduling module).

[0090] Specifically, the RAM resource overall management control scheduling module realizes the division of on-chip Public_RAM resources for the sub-modules to be diverted data according to the information provided by each random access memory management control module, so that the data to be diverted is stored in the Public_RAM through the RAM_DATA_BUS (RAM data bus), and at the same time, the RAM_CTRL information is detected in real time to realize real-time dynamic management of the diverted data and RAM resources, which greatly improves the overall scheduling of RAM resources on the video processing path, greatly improves the utilization rate of RAM resources, reduces the frame loss rate, and improves the overall performance of the baseboard management and control chip.

[0091] It should be noted that in the embodiment of the present application, RAM_CTRL_TOP is the overall management control scheduling module of the RAM resources. The function implemented by this scheduling module is to collect the Public_RAM applications and application types (for example, Apply_0, Apply_1, Apply_2) of each sub-module, and then perform overall scheduling of the RAM resources on the entire video path based on the Public_RAM resources Public_RAM_Space_A, Public_RAM_Space_B, Public_RAM_Space_C, and Public_RAM_Space_D reported by each sub-module.

[0092] Furthermore, the preset scheduling rules include:

[0093] Select the Public_RAM_Space of a single submodule as the requested Public_RAM of the single submodule, and select the Public_RAM_Space with a larger space as the request response;

[0094] Select the one with the larger Public_RAM_Space value as the submodule to request the processing of the higher Public_RAM level;

[0095] Continue to detect the submodule that reports the request. After giving a response, if the request is still reported, RAM_CTRL_TOP readjusts the Adjust_Level of the submodule corresponding to Public_RAM.

[0096] If the submodule corresponding to Public_RAM continues to report requests after readjusting Adjust_Level, you need to set the Public_RAM of multiple submodules to the submodule that reports the request;

[0097] If it is detected that the submodule that reported the request no longer reports the request after giving the response, then after the T1 time period, the allocation of the Public_RAM of the current submodule is revoked.

[0098] Specifically, the principles are as follows:

[0099] First, the Public_RAM_Space of a single submodule is preferentially selected as the Public_RAM processing of the request of a single submodule, and the Public_RAM_Space with a larger space is selected as the request response. For example, for the application reported in RGB_YUV, both YUV_BLOCK and DATA_OUT_CTRL have Public_RAM, and the Public_RAM_Space of YUV_BLOCK is 200, and the Public_RAM_Space of DATA_OUT_CTRL, then the Public_RAM of YUV_BLOCK is selected as the response to the application reported in RGB_YUV.

[0100] Second, give priority to the submodule with a large Public_RAM_Space value to request a high Public_RAM level. For example, the application level reported in RGB_YUV is Apply_2, and the application level of DATA_OUT_CTRL is Apply_0. At this time, the Public_RAM_Space of RGB_CAP = 100, and the Public_RAM_Space of YUV_BLOCK = 50. Then the Public_RAM of RGB_CAP is used as the response to the application reported in RGB_YUV, and the Public_RAM of YUV_BLOCK is used as the response to the application reported in DATA_OUT_CTRL.

[0101] Third, the submodule that continuously detects the reporting request, and after giving a response, if the reporting request is still continued, RAM_CTRL_TOP readjusts the Adjust_Level of the submodule corresponding to Public_RAM, for example, adjusting Adjust_Level from Mode_0 to Mode_2.

[0102] It should be noted that in the embodiment of the present application, the sub-module that continuously detects the reporting request, and in this process after giving a response, the sub-module that handles the response, that is, applies for Public_RAM, and how to change the data path after receiving the corresponding response.

[0103] Specifically, through Figure 1The RAM_DATA_BUS (RAM data bus) shown writes the data of the submodule applying for Public_RAM resources into the corresponding address of the RAM in the submodule providing Public_RAM resources under the cooperation of the corresponding RAM_CTRL (such as RAM_CTRL_A) and the RAM_CTRL (RAM_CTRL_C) corresponding to the submodule providing Public_RAM (the address range information RAM_CTRL (such as RAM_CTRL_C) is provided to RAM_CTRL_TOP when providing Public_RAM, and then forwarded by RAM_CTRL_TOP to RAM_CTRL (such as RAM_CTRL_A) applying for Public_RAM, and at the same time controls the reading of RAM data.

[0104] Fourth, if the submodule corresponding to Public_RAM continues to report requests after readjusting Adjust_Level, you need to set the Public_RAM of multiple submodules to the submodule that reports the request (for example, adjust the Public_RAM of RGB_CAP and YUV_BLOCK to the DATA_OUT_CTRL submodule for use, and adjust the corresponding Adjust_Level in real time).

[0105] Fifth, if it is detected that the submodule that reports the request no longer reports the request after giving a response, the allocation of the Public_RAM of the current submodule is revoked after the T1 time period. T1 can adopt the default value or can be changed by the user register configuration.

[0106] The resource scheduling system provided in the embodiment of the present application includes a host end and a baseboard management controller chip, the baseboard management controller chip is equipped with a plurality of video data processing submodules, a random access memory management control module and a random access memory resource overall management control scheduling module, each of the video data processing submodules is correspondingly provided with a random access memory management control module, and the random access memory management control module and the random access memory resource overall management control scheduling module are communicatively connected; the baseboard management controller chip is used to receive the video data to be diverted sent by the host end; the random access memory management control module is used to obtain the random access memory resource information corresponding to each of the video data processing submodules; the random access memory resource overall management control scheduling module is used to determine the common random access memory corresponding to each of the video data processing submodules according to the random access memory resource information, and the common random access memory is used to store the video data to be diverted, that is, in the embodiment of the present application, the random access memory resources inside each submodule in the video processing path are managed and controlled as a whole resource, avoiding the disadvantage that the random access memory resources inside each submodule in the traditional solution can only be used by the current submodule. The resource scheduling system integrates multiple video data processing submodules, random access memory management and control modules, and random access memory resource overall management, control and scheduling modules on the baseboard management controller chip, thereby realizing efficient management and scheduling of the video data to be diverted sent by the host. The random access memory management and control module corresponding to each video data processing submodule can obtain random access memory resource information in real time, and the random access memory resource overall management, control and scheduling module intelligently determines the public random access memory corresponding to each submodule based on this information, ensuring that the video data to be diverted can be reasonably stored and allocated. This design not only improves the efficiency and flexibility of video data processing, but also optimizes the utilization of random access memory resources, reduces resource waste, thereby improving the performance and response speed of the entire system, greatly improving the overall scheduling of random access memory resources on the video processing path, greatly improving the utilization rate of random access memory resources, reducing the frame loss rate, and improving the overall performance of the baseboard management control chip.

[0107] Reference Figure 2 , shows a flow chart of the steps of a resource scheduling method provided by an embodiment of the present application, which is applied to a baseboard management controller chip in a resource scheduling system. The method may include:

[0108] Step 101, receiving the video data to be split sent by the host end;

[0109] Step 102, obtaining random access memory resource information corresponding to each of the video data processing submodules;

[0110] Step 103, determining a common random access memory corresponding to each of the video data processing submodules according to the random access memory resource information;

[0111] Step 104: store the video data to be distributed into the common random access memory via a random access memory data bus.

[0112] It should be noted that, in the embodiment of the present application, the above steps 101-104 refer to the previous discussion and will not be repeated here.

[0113] Further, the obtaining of random access memory resource information corresponding to each of the video data processing submodules includes:

[0114] Obtain random access memory resource information corresponding to each of the video data processing submodules in a preset time period.

[0115] Further, the obtaining of random access memory resource information corresponding to each of the video data processing submodules in a preset time period includes:

[0116] The random access memory depth, the random access memory remaining space, the random access memory writing speed within a preset time period, and the random access memory reading speed within a preset time period corresponding to each of the video data processing submodules are obtained.

[0117] Further, the determining, according to the random access memory resource information, a common random access memory corresponding to each of the video data processing submodules comprises:

[0118] Get the preset adjustment level;

[0119] The common random access memory corresponding to each of the video data processing submodules is determined according to the random access memory depth corresponding to each of the video data processing submodules, the remaining space of the random access memory, the random access memory write speed within a preset time period, the random access memory read speed within a preset time period, and the adjustment level.

[0120] It should be noted that, in the embodiment of the present application, the partition control logic of the PUBLIC_RAM of each video data processing submodule includes:

[0121] (Implemented in RAM_CTRL(A / B / C / D)) Statistics on the usage of RAM resources in the T0 time period of this submodule. Other T0 can be configured by the user through registers or by default values. The RAM depth Cur_RAM_Depth of the current module, the remaining space Cur_RAM_Remain_Space of the RAM of the current module, the write speed Wr_Speed ​​and read speed Rd_Speed ​​of the RAM in the T0 segment of the current module are used to calculate the Public_RAM space that can be divided out of the current submodule, and Cur_RAM_Remain_Space is required to be greater than the minimum safety threshold (RAM_Safe_Space). RAM_Safe_Space can use the default value or be configured by the user through registers.

[0122] Specifically, please refer to the following formula 4.

[0123] Public_RAM_Space = Cur_RAM_Remain_Space * (1+(Rd_Speed-Wr_Speed) / (Rd_Speed+Wr_Speed))*Cur_RAM_Remain_Space / Cur_RAM_Depth * Param_MDY * Adjust_Level (Formula 4)

[0124] In the above formula 4, (1+(Rd_Speed-Wr_Speed) / (Rd_Speed+Wr_Speed)) is used to ensure that when the read speed is greater than the write speed, more of the remaining space can be divided as Public_RAM, and when the write speed is greater than the read speed, the remaining space divided as Public_RAM should be relatively reduced. The reason why (Rd_Speed+Wr_Speed) is used as the denominator of the proportional formula is to use the RAM processing speed of the current module as a reference factor, that is, the faster the data processing speed, the smaller the remaining space is divided into Public_RAM, and when the data processing speed is relatively slower, the larger the remaining space is divided into Public_RAM. The reason for introducing Cur_RAM_Remain_Space / Cur_RAM_Depth is to use the overall space of the current RAM as a factor to affect the division of the remaining space into Public_RAM. That is, when Cur_RAM_Remain_Space is fixed, the larger the Cur_RAM_Depth value is, the smaller the remaining space is divided into Public_RAM, and when the Cur_RAM_Depth value is smaller, the larger the remaining space is divided into Public_RAM. Param_MDY is a correction parameter that ensures that the value of (1+(Rd_Speed-Wr_Speed) / (Rd_Speed+Wr_Speed))*Cur_RAM_Remain_Space / Cur_RAM_Depth is less than 1.

[0125] Further, the preset adjustment levels include a first adjustment level, a second adjustment level, and a third adjustment level.

[0126] Furthermore, the proportion of the first public random access memory corresponding to the first adjustment level is smaller than the proportion of the second public random access memory corresponding to the second adjustment level, and the proportion of the second public random access memory corresponding to the second adjustment level is smaller than the proportion of the third public random access memory corresponding to the third adjustment level.

[0127] It should be noted that, in the embodiment of the present application, the preset adjustment level is Adjust_Level, and Adjust_Level can be set to 3 levels, namely, a first adjustment level mode_0, a second adjustment level mode_1, and a third adjustment level mode_2.

[0128] Among them, mode_0 refers to the abundant level, that is, a small amount of Cur_RAM_Remain_Space is allocated as Public_RAM, for example, it is set to 1 / 3.

[0129] Among them, mode_1 refers to the normal level, that is, an appropriate amount of Cur_RAM_Remain_Space is allocated as Public_RAM, for example, it is set to 1 / 2.

[0130] Among them, mode_2 refers to the highest level, that is, a large amount of Cur_RAM_Remain_Space is allocated as Public_RAM, for example, it is set to 3 / 4.

[0131] It should be noted that the above settings of 1 / 3, 1 / 2, and 3 / 4 are not the direct multiplication of Cur_RAM_Remain_Space by 1 / 3, 1 / 2, and 3 / 4, but the multiplication of Cur_RAM_Remain_Space * (1+(Rd_Speed-Wr_Speed) / (Rd_Speed+Wr_Speed))*Cur_RAM_Remain_Space / Cur_RAM_Depth * Param_MDY by 1 / 3, 1 / 2, and 3 / 4.

[0132] Furthermore, the baseboard management controller chip is equipped with a random access memory management control module and a random access memory resource overall management control scheduling module. After the step of storing the video data to be diverted to the public random access memory through the random access memory data bus, the method further includes:

[0133] When it is detected that the remaining space of the random access memory corresponding to the video data processing submodule is less than a preset threshold, a random access memory resource application signal is sent to the random access memory resource overall management control scheduling module through the random access memory management control scheduling module, so that the random access memory resource overall management control scheduling module allocates a target public random access memory space to the video data processing submodule in the public random access memory based on the random access memory resource application signal.

[0134] Furthermore, before the step of sending a random access memory resource application signal to the random access memory resource overall management control scheduling module through the random access memory management control module, the method includes:

[0135] When it is detected that the remaining space of the random access memory corresponding to the video data processing submodule is less than a preset threshold value, and the write speed of the random access memory within the preset time period is less than the read speed of the random access memory within the preset time period, the level corresponding to the random access memory resource request signal is determined according to the difference between the write speed of the random access memory and the read speed of the random access memory.

[0136] Further, determining the level corresponding to the random access memory resource application signal according to the difference between the random access memory write speed and the random access memory read speed includes:

[0137] In the case where the difference between the random access memory write speed and the random access memory read speed is detected to be less than the first threshold, setting the random access memory resource application signal as the first random access memory resource application signal;

[0138] In the case where the difference between the random access memory write speed and the random access memory read speed is detected to be greater than or equal to the first threshold and less than the second threshold, setting the random access memory resource application signal as the second random access memory resource application signal;

[0139] In the case where the difference between the random access memory write speed and the random access memory read speed is detected to be greater than or equal to the third threshold, setting the random access memory resource application signal as the third random access memory resource application signal.

[0140] It should be noted that in the embodiment of the present application, in addition to implementing the division of the public random access memory Public_RAM, an important function of the random access memory control module is to initiate a random access memory resource application signal to the overall management and control scheduling module of the random access memory resources when the RAM resources in this sub-module are about to be used up. The so-called about to be used up means that Cur_RAM_Remain_Space is less than the agreed minimum threshold of the remaining space (RAM_Safe_Space), and Wr_Speed > Rd_Speed, and according to the difference between Wr_Speed and Rd_Speed, that is, (Wr_Speed - Rd_Speed).

[0141] Therefore, in the embodiment of the present application, the applications are divided into three categories, including: the first random access memory resource application signal Apply_0, the second random access memory resource application signal Apply_1, and the third random access memory resource application signal Apply_2.

[0142] Among them, when Wr_Speed - Rd_Speed < PARAM_0, a request for setting the level of application Apply_0 is made; when Wr_Speed - Rd_Speed >= PARAM_0 and less than PARAM_1, a request for setting the level of application Apply_1 is made; when Wr_Speed - Rd_Speed >= PARAM_2, a request for setting the level of application Apply_2 is made.

[0143] In the embodiment of the present application, the random access memory resources inside each submodule in the video processing path are managed and controlled as a whole resource, avoiding the disadvantage that the random access memory resources inside each submodule in the traditional solution can only be used by the current submodule. The resource scheduling system integrates multiple video data processing submodules, random access memory management and control modules, and random access memory resource overall management control scheduling modules on the baseboard management controller chip, so as to realize the efficient management and scheduling of the video data to be diverted sent by the host end. The random access memory management and control module corresponding to each video data processing submodule can obtain random access memory resource information in real time, and the random access memory resource overall management control scheduling module intelligently determines the public random access memory corresponding to each submodule according to this information, ensuring that the video data to be diverted can be reasonably stored and allocated. This design not only improves the efficiency and flexibility of video data processing, but also optimizes the utilization of random access memory resources, reduces resource waste, thereby improving the performance and response speed of the entire system, greatly improving the overall scheduling of random access memory resources on the video processing path, greatly improving the utilization rate of random access memory resources, reducing the frame loss rate, and improving the overall performance of the baseboard management control chip.

[0144] Reference Figure 3 , shows a flowchart of the steps of another resource scheduling method provided by an embodiment of the present application, which is applied to a random access memory resource overall management control scheduling module in a resource scheduling system. The method may include:

[0145] Step 201, receiving random access memory resource information corresponding to each of the video data processing submodules sent by the random access memory management control module when it is detected that the baseboard management controller chip receives the video data to be shunted sent by the host end;

[0146] Step 202: Determine a common random access memory corresponding to each of the video data processing submodules according to the random access memory resource information, wherein the common random access memory is used to store the video data to be distributed.

[0147] It should be noted that the above steps 201-202 refer to the previous discussion and will not be repeated here.

[0148] In the embodiment of the present application, the random access memory resources inside each submodule in the video processing path are managed and controlled as a whole resource, avoiding the disadvantage that the random access memory resources inside each submodule in the traditional solution can only be used by the current submodule. The resource scheduling system integrates multiple video data processing submodules, random access memory management and control modules, and random access memory resource overall management control scheduling modules on the baseboard management controller chip, so as to realize the efficient management and scheduling of the video data to be diverted sent by the host end. The random access memory management and control module corresponding to each video data processing submodule can obtain random access memory resource information in real time, and the random access memory resource overall management control scheduling module intelligently determines the public random access memory corresponding to each submodule according to this information, ensuring that the video data to be diverted can be reasonably stored and allocated. This design not only improves the efficiency and flexibility of video data processing, but also optimizes the utilization of random access memory resources, reduces resource waste, thereby improving the performance and response speed of the entire system, greatly improving the overall scheduling of random access memory resources on the video processing path, greatly improving the utilization rate of random access memory resources, reducing the frame loss rate, and improving the overall performance of the baseboard management control chip.

[0149] Reference Figure 4 , shows a schematic diagram of the structure of a resource scheduling device provided in an embodiment of the present application, the device comprising:

[0150] The receiving module 301 is used to receive the video data to be split sent by the host end;

[0151] An acquisition module 302 is used to acquire random access memory resource information corresponding to each of the video data processing submodules;

[0152] A determination module 303, configured to determine a common random access memory corresponding to each of the video data processing submodules according to the random access memory resource information;

[0153] The storage module 304 is used to store the video data to be distributed into the common random access memory via a random access memory data bus.

[0154] In the embodiment of the present application, the random access memory resources inside each submodule in the video processing path are managed and controlled as a whole resource, avoiding the disadvantage that the random access memory resources inside each submodule in the traditional solution can only be used by the current submodule. The resource scheduling system integrates multiple video data processing submodules, random access memory management and control modules, and random access memory resource overall management control scheduling modules on the baseboard management controller chip, so as to realize the efficient management and scheduling of the video data to be diverted sent by the host end. The random access memory management and control module corresponding to each video data processing submodule can obtain random access memory resource information in real time, and the random access memory resource overall management control scheduling module intelligently determines the public random access memory corresponding to each submodule according to this information, ensuring that the video data to be diverted can be reasonably stored and allocated. This design not only improves the efficiency and flexibility of video data processing, but also optimizes the utilization of random access memory resources, reduces resource waste, thereby improving the performance and response speed of the entire system, greatly improving the overall scheduling of random access memory resources on the video processing path, greatly improving the utilization rate of random access memory resources, reducing the frame loss rate, and improving the overall performance of the baseboard management control chip.

[0155] The present application also provides a communication device, such as Figure 5 As shown, it includes a processor 401, a communication interface 402, a memory 403 and a communication bus 404, wherein the processor 401, the communication interface 402, and the memory 403 communicate with each other through the communication bus 404.

[0156] Memory 403, used for storing computer programs;

[0157] The processor 401, when used to execute the program stored in the memory 403, can implement the following steps:

[0158] Receive the video data to be split sent by the host;

[0159] Acquire random access memory resource information corresponding to each of the video data processing submodules;

[0160] Determining a common random access memory corresponding to each of the video data processing submodules according to the random access memory resource information;

[0161] The video data to be distributed is stored in the common random access memory through a random access memory data bus.

[0162] or,

[0163] In the case where it is detected that the baseboard management controller chip receives the video data to be shunted sent by the host end, receiving the random access memory resource information corresponding to each of the video data processing submodules sent by the random access memory management control module;

[0164] A common random access memory corresponding to each of the video data processing submodules is determined according to the random access memory resource information, and the common random access memory is used to store the video data to be diverted.

[0165] Among them, the memory and the processor are connected in a bus manner, and the bus may include any number of interconnected buses and bridges, and the bus connects various circuits of one or more processors and memories together. The bus can also connect various other circuits such as peripheral devices, voltage regulators, and power management circuits together, which are all well known in the art, so this article will not further describe them. The bus interface provides an interface between the bus and the transceiver. The transceiver can be one element or multiple elements, such as multiple receivers and transmitters, providing a unit for communicating with various other devices on a transmission medium. The data processed by the processor can be transmitted on a wired medium or on a wireless medium through an antenna. Further, the antenna also receives data and transmits the data to the processor. The processor is responsible for managing the bus and general processing, and can also provide various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions. The memory can be used to store data used by the processor when performing operations.

[0166] The communication bus mentioned in the above terminal can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0167] The communication interface is used for communication between the above terminal and other devices.

[0168] The memory may include a random access memory (RAM) or a non-volatile memory, such as at least one disk memory. Optionally, the memory may also be at least one storage device located away from the aforementioned processor.

[0169] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0170] In another embodiment provided in the present application, a computer-readable storage medium is provided, in which instructions are stored. When the computer-readable storage medium is executed on a computer, the computer executes the resource scheduling method described in any one of the above embodiments.

[0171] In another embodiment provided by the present application, a computer program product including instructions is also provided, which, when executed on a computer, enables the computer to execute the resource scheduling method described in any one of the above embodiments.

[0172] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website site, a computer, a server or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or a data center that includes one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive Solid State Disk (SSD)), etc.

[0173] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0174] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0175] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. A resource scheduling system, characterized in that: The resource scheduling system includes a host end and a baseboard management controller chip, the baseboard management controller chip is equipped with a plurality of video data processing submodules, a random access memory management control module and a random access memory resource overall management control scheduling module, each of the video data processing submodules is correspondingly provided with a random access memory management control module, and the random access memory management control module is communicatively connected with the random access memory resource overall management control scheduling module; The baseboard management controller chip is used to receive data sent by the host end to the video data processing submodule; the baseboard management controller chip also includes a random access memory data bus, and the data of the video data processing submodule is stored in a common random access memory through the random access memory data bus; The random access memory management control module is used to obtain random access memory resource information corresponding to each of the video data processing submodules; The random access memory resource overall management control scheduling module is used to determine the common random access memory corresponding to each of the video data processing sub-modules according to the random access memory resource information and a preset adjustment level. The common random access memory is used to store data of the video data processing sub-module. The common random access memory is obtained by dividing the random access memory resource overall management control scheduling module in each of the video data processing sub-modules according to the random access memory resource information and a preset adjustment level.

2. The system according to claim 1, characterized in that The resource scheduling system further includes a memory, and a video memory space is arranged in the target storage space corresponding to the memory.

3. The system according to claim 1, characterized in that The video data processing submodule includes any one of a color data capture module, a color space conversion module, a conversion module and an output control module. The color data capture module is correspondingly provided with a first random access memory management control module, the color space conversion module is correspondingly provided with a second random access memory management control module, the conversion module is correspondingly provided with a third random access memory management control module, and the output control module is correspondingly provided with a fourth random access memory management control module.

4. The system according to claim 3, characterized in that The baseboard management controller chip also includes a video compression module, and the video compression module is communicatively connected with the conversion module and the output control module respectively.

5. The system according to claim 1, characterized in that The random access memory resource overall management control scheduling module is used to perform overall scheduling of random access memory resource information corresponding to all the video data processing submodules on the video path of the resource scheduling system based on preset scheduling rules.

6. A resource scheduling method, characterized in that: A baseboard management controller chip used in a resource scheduling system as described in any one of claims 1 to 5, the method comprising: Receiving data sent by the host end to the video data processing submodule; Acquire random access memory resource information corresponding to each of the video data processing submodules; Determine a common random access memory corresponding to each of the video data processing submodules according to the random access memory resource information and the preset adjustment level; the common random access memory is obtained by dividing in each of the video data processing submodules according to the random access memory resource information and the preset adjustment level; The data of the video data processing submodule is stored in the common random access memory through a random access memory data bus.

7. The method according to claim 6, characterized in that The acquiring of random access memory resource information corresponding to each of the video data processing submodules includes: Obtain random access memory resource information corresponding to each of the video data processing submodules in a preset time period.

8. The method according to claim 7, characterized in that The obtaining of random access memory resource information corresponding to each of the video data processing submodules in a preset time period includes: The random access memory depth, the random access memory remaining space, the random access memory writing speed within a preset time period, and the random access memory reading speed within a preset time period corresponding to each of the video data processing submodules are obtained.

9. The method according to claim 8, characterized in that The step of determining the common random access memory corresponding to each of the video data processing submodules according to the random access memory resource information comprises: Get the preset adjustment level; The common random access memory corresponding to each of the video data processing submodules is determined according to the random access memory depth corresponding to each of the video data processing submodules, the remaining space of the random access memory, the random access memory write speed within a preset time period, the random access memory read speed within a preset time period, and the adjustment level.

10. The method according to claim 9, characterized in that The preset adjustment levels include a first adjustment level, a second adjustment level, and a third adjustment level.

11. The method according to claim 10, characterized in that The proportion of the first public random access memory corresponding to the first adjustment level is smaller than the proportion of the second public random access memory corresponding to the second adjustment level, and the proportion of the second public random access memory corresponding to the second adjustment level is smaller than the proportion of the third public random access memory corresponding to the third adjustment level.

12. The method according to claim 6, characterized in that The baseboard management controller chip is equipped with a random access memory management control module and a random access memory resource overall management control scheduling module. After the step of storing the data of the video data processing submodule in the public random access memory through the random access memory data bus, the method further includes: When it is detected that the remaining space of the random access memory corresponding to the video data processing submodule is less than a preset threshold, a random access memory resource application signal is sent to the random access memory resource overall management control scheduling module through the random access memory management control scheduling module, so that the random access memory resource overall management control scheduling module allocates a target public random access memory space to the video data processing submodule in the public random access memory based on the random access memory resource application signal.

13. The method according to claim 12, characterized in that Before the step of sending a random access memory resource application signal to the random access memory resource overall management control scheduling module through the random access memory management control module, the method includes: When it is detected that the remaining space of the random access memory corresponding to the video data processing submodule is less than a preset threshold value, and the write speed of the random access memory within a preset time period is less than the read speed of the random access memory within the preset time period, the level corresponding to the random access memory resource request signal is determined according to the difference between the write speed of the random access memory and the read speed of the random access memory.

14. The method according to claim 13, characterized in that The step of determining the level corresponding to the random access memory resource request signal according to the difference between the random access memory write speed and the random access memory read speed comprises: When it is detected that the difference between the random access memory write speed and the random access memory read speed is less than a first threshold, setting the random access memory resource request signal as a first random access memory resource request signal; When it is detected that the difference between the random access memory write speed and the random access memory read speed is greater than or equal to the first threshold and less than the second threshold, setting the random access memory resource request signal to a second random access memory resource request signal; When it is detected that the difference between the random access memory write speed and the random access memory read speed is greater than or equal to a third threshold, the random access memory resource request signal is set to a third random access memory resource request signal.

15. A resource scheduling method, characterized in that: A random access memory resource overall management control scheduling module applied to a resource scheduling system as described in any one of claims 1 to 5, the method comprising: In the case where it is detected that the baseboard management controller chip receives the data sent by the host end to the video data processing submodule, receiving the random access memory resource information corresponding to each of the video data processing submodules sent by the random access memory management control module; The common random access memory corresponding to each of the video data processing submodules is determined according to the random access memory resource information and the preset adjustment level, and the common random access memory is used to store the data of the video data processing submodule; the common random access memory is obtained by dividing the random access memory resource overall management control scheduling module in each of the video data processing submodules according to the random access memory resource information and the preset adjustment level.

16. A resource scheduling device, characterized in that: A baseboard management controller chip used in a resource scheduling system as claimed in any one of claims 1 to 5, wherein the resource scheduling system comprises a plurality of video data processing submodules, and the device comprises: A receiving module, used for receiving data sent by the host end to the video data processing submodule; An acquisition module, used for acquiring random access memory resource information corresponding to each of the video data processing submodules; A determination module, configured to determine a common random access memory corresponding to each of the video data processing submodules according to the random access memory resource information and a preset adjustment level; the common random access memory is obtained by dividing in each of the video data processing submodules according to the random access memory resource information and the preset adjustment level; The storage module is used to store the data of the video data processing submodule into the common random access memory through a random access memory data bus.

17. A communication device, characterized in that: include: A transceiver, a memory, a processor, and a program stored on the memory and executable on the processor; The processor is used to read the program in the memory to implement the resource scheduling method as described in any one of claims 6 to 14, or the resource scheduling method as described in claim 15.

18. A readable storage medium for storing a program, characterized in that: When the program is executed by a processor, it implements the resource scheduling method as described in any one of claims 6 to 14, or the resource scheduling method as described in claim 15.

19. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instructions are executed by a processor, the resource scheduling method as described in any one of claims 6 to 14 or the resource scheduling method as described in claim 15 is implemented.

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