Semiconductor structure and forming method thereof

Abstract

The embodiment of the invention provides a semiconductor structure and a forming method thereof, and the forming method comprises the steps: providing a substrate which comprises a device region and a marking region, the marking region of the substrate is internally provided with a groove, and the substrate is provided with a marking material layer covering the groove and an interconnection layer located on the marking material layer; and an opening is formed in the interconnection layer of the mark area, the depth of the opening is smaller than or equal to the thickness of the interconnection layer, and the mark material layer covered by the opening serves as an alignment mark. By adopting the technical scheme, the intensity of the alignment signal can be improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the rapid development of integrated circuits, the characteristic size of semiconductor structures continues to shrink. When performing the photolithography process, how to control the overlay error between graphics of different layers has become a crucial step in the photolithography process.

[0003] Currently, in the process of forming a semiconductor structure, an alignment mark is usually formed, and the position of the alignment mark is detected to improve the overlay accuracy between different process layers.

[0004] However, the current scheme for forming alignment marks still needs to be improved. Summary of the invention

[0005] In view of this, an embodiment of the present invention provides a semiconductor structure and a method for forming the same, which can improve the strength of an alignment signal.

[0006] An embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a device area and a marking area, the marking area of ​​the substrate having a groove, the substrate having a marking material layer covering the groove, and an interconnection layer located on the marking material layer; forming an opening in the interconnection layer of the marking area, the depth of the opening being less than or equal to the thickness of the interconnection layer, and using the marking material layer covered by the opening as an alignment mark.

[0007] Optionally, before forming the opening in the interconnect layer of the marking area, the forming method further comprises:

[0008] Determine the depth of the opening according to the ratio of the sum of the intensity of the reflected light and the intrinsic loss of the light intensity to the intensity of the detection light, the product of the transmittance of the material of the interconnection layer and the thickness of the interconnection layer, and the product of the transmittance of the material of the marking material layer and the thickness of the marking material layer;

[0009] The reflected light is formed by the detection light being reflected by the substrate, the marking material layer and the interconnection layer.

[0010] Optionally, the depth of the opening is determined using the following formula:

[0011]

[0012] Among them, h represents the depth of the opening, d1 represents the thickness of the interconnection layer before forming the opening, T1 represents the transmittance of the material of the interconnection layer, d2 represents the thickness of the marking material layer before forming the opening, T2 represents the transmittance of the material of the marking material layer, cd1 represents the intensity of the reflected light, cd2 represents the inherent loss of light intensity, and cd represents the intensity of the detection light.

[0013] Optionally, the thickness of the marking material layer is 0.5 μm to 2 μm; the material of the marking material layer is one or more of silicate glass, phosphosilicate glass or borophosphosilicate glass.

[0014] Optionally, the thickness of the interconnection layer is 3 μm to 5 μm; and the material of the interconnection layer is AlSi or AlSiCu.

[0015] Optionally, the transmittance of the marking material layer to the detection light is greater than the transmittance of the substrate to the detection light.

[0016] Optionally, the step of forming an opening in the interconnect layer of the marking area comprises:

[0017] The interconnection layer in the marking area is patterned to form the opening.

[0018] Optionally, the patterning step includes:

[0019] forming a photoresist having a pattern opening on the interconnection layer, wherein the pattern opening at least exposes the interconnection layer located in the mark area;

[0020] Etching the interconnection layer in the marking area along the graphic opening to remove at least a portion of the thickness of the interconnection layer exposed by the photoresist to form the opening;

[0021] The photoresist is removed.

[0022] Optionally, along a direction parallel to the substrate surface, a width of the opening is greater than a width of the marking area.

[0023] Optionally, along a direction parallel to the surface of the substrate, a width of the opening is 550 μm to 650 μm.

[0024] Optionally, along the normal direction of the substrate surface, the depth of the groove is 120 nm.

[0025] Correspondingly, an embodiment of the present invention also provides a semiconductor structure, comprising: a substrate, the substrate comprising a device area and a marking area, the marking area of ​​the substrate having a groove; a marking material layer, located above the substrate and filling the groove; an interconnection layer, located above the marking material layer; an opening, located in the interconnection layer of the marking area, the depth of the opening is less than or equal to the thickness of the interconnection layer, and the marking material layer covered by the opening serves as an alignment mark.

[0026] Optionally, the thickness of the marking material layer is 0.5 μm to 2 μm;

[0027] The material of the marking material layer is one or more of silicate glass, phosphosilicate glass or borophosphosilicate glass.

[0028] Optionally, the thickness of the interconnection layer is 3 μm to 5 μm; and the material of the interconnection layer is AlSi or AlSiCu.

[0029] Optionally, the transmittance of the marking material layer to the detection light is greater than the transmittance of the substrate to the detection light.

[0030] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0031] In a method for forming a semiconductor structure provided by an embodiment of the present invention, a substrate includes a device area and a marking area, a groove is provided in the marking area of ​​the substrate, and a marking material layer covering the groove is provided on the substrate, and an interconnection layer is located on the marking material layer. By forming an opening in the interconnection layer, the blocking of the detection light by the interconnection layer can be reduced, so that most of the detection light can be transmitted to the marking material layer covered by the opening, and the marking material layer covered by the opening serves as an alignment mark, so that after the detection light is reflected by the alignment mark, the intensity of the reflected light can be increased, thereby increasing the intensity of the alignment signal.

[0032] Furthermore, by determining the ratio of the sum of the reflected light intensity and the lost light intensity to the intensity of the detected light, the product of the light transmittance of the material of the interconnection layer and the first thickness of the interconnection layer, and the product of the light transmittance of the marking material layer and the second thickness of the marking material layer, the depth of the opening can be accurately determined, and the removal thickness of the interconnection layer can be accurately determined. This can reduce the removal time of the interconnection layer and improve manufacturing efficiency while increasing the intensity of the alignment signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments of the present invention or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0034] Figures 1 to 4 is a schematic structural diagram corresponding to each step in the first embodiment of the method for forming a semiconductor structure of the present invention;

[0035] Figure 5 is a schematic structural diagram corresponding to each step in the second embodiment of the method for forming a semiconductor structure of the present invention;

[0036] Figure 6 It is a schematic diagram of the detection principle of an alignment mark. DETAILED DESCRIPTION

[0037] As can be seen from the background technology, the current scheme for forming alignment marks still needs to be improved. This is because: in the formation process of a semiconductor structure, a thicker interconnection layer needs to be grown to achieve the connection between the semiconductor structure and the external circuit and / or device. In this way, under the obstruction of the thicker interconnection layer, only a small part of the detection light can be reflected, resulting in a low intensity of the received reflected light, and the position of the alignment mark cannot be correctly judged, and subsequent operations cannot be performed; and the interconnection layer is formed after being deposited and annealed at a high temperature and then cooled to the ambient temperature. During the cooling process, due to the existence of stress, the surface of the interconnection layer becomes uneven, and a part of the detection light is directly reflected by the interconnection layer without irradiating the alignment mark, which further reduces the intensity of the reflected light.

[0038] Furthermore, for some semiconductor devices, the energy of the detection light emitted by them is weak, and the intensity of the reflected light formed by reflection is even lower. When matching the intensity of the obtained reflected light with the set standard intensity, it is far from meeting the requirements.

[0039] For example, for one type of lithography machine, when the ratio between the intensity of the reflected light and the set standard intensity reaches 70%, it is considered that the alignment operation is successful and the lithography machine can perform the lithography process; otherwise, the alignment operation fails and the lithography machine cannot perform the lithography process.

[0040] In order to solve the above technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a device area and a marking area, the marking area of ​​the substrate having a groove, the substrate having a marking material layer covering the groove, and an interconnection layer located on the marking material layer; forming an opening in the interconnection layer in the marking area, the depth of the opening being less than or equal to the thickness of the interconnection layer, and using the marking material layer covered by the opening as an alignment mark.

[0041] In other words, by forming an opening in the interconnection layer, the thickness of the interconnection layer can be reduced, thereby reducing the blocking of the detection light by the interconnection layer, so that most of the detection light can be transmitted to the marking material layer covered by the opening. Therefore, after the detection light is reflected by the alignment mark, the intensity of the reflected light can be increased, thereby increasing the intensity of the alignment signal.

[0042] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are exemplarily described below in conjunction with the accompanying drawings.

[0043] Figures 1 to 4 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0044] See also Figure 1 , providing a substrate 100, the substrate 100 includes a device area I and a marking area II, the marking area II of the substrate 100 has a groove (not marked in the figure), the substrate 100 has a marking material layer 102 covering the groove, and an interconnection layer 104 located on the marking material layer 102.

[0045] The substrate 100 may provide a process operation basis for a formation process of a semiconductor structure.

[0046] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as silicon on insulator substrate or germanium on insulator substrate. The material of the substrate may be a material suitable for process requirements or easy to integrate.

[0047] In this embodiment, a groove is formed in the substrate 100 , and the marking material layer 102 in the groove can be used as an alignment mark.

[0048] In this embodiment, a groove is formed in the substrate 100 by using a dry etching process or a wet etching process.

[0049] In this embodiment, when the detection light is irradiated onto the alignment mark, the formation of a reflection signal corresponding to the alignment mark is mainly achieved based on the depth of the groove, or the height difference of the substrate surface. Therefore, along the normal direction of the substrate 100, the depth of the groove can be 100nm to 140nm. In this way, the reflection signal reflected by the two step surfaces of the groove has a higher degree of distinction, which can further enhance the intensity of the reflection signal.

[0050] In this embodiment, the device region I of the substrate 100 is used to prepare and form a semiconductor device (eg, a transistor), and the mark region II of the substrate 100 is used to form an alignment mark.

[0051] In this embodiment, the structures of the substrate 100 in the device area I and the marking area II are different, wherein device structures such as source-drain doping layers and isolation layers are formed on the substrate 100 in the device area I, while device structures such as source-drain doping layers and isolation layers are not formed on the substrate 100 in the marking area II.

[0052] The mark material layer 102 is used to provide a process basis for the subsequent formation of alignment marks.

[0053] In this embodiment, the thickness d2 of the marking material layer 102 is 0.5 μm to 2 μm.

[0054] By making the thickness d2 of the marking material layer 102 greater than or equal to 0.5 μm, the breakdown voltage of the semiconductor structure can be enhanced; by making the thickness d2 of the marking material layer 102 less than or equal to 2 μm, the optical path of the detection light can be reduced, the light loss can be reduced, the intensity of the reflected light can be increased, and the alignment accuracy can be improved.

[0055] It should be noted that the thickness d2 in this embodiment is a value based on the surface of the substrate 100 located on the device region I.

[0056] In this embodiment, the material of the marking material layer 102 is one or more of silicate glass, phosphosilicate glass or borophosphosilicate glass.

[0057] In a specific embodiment, the material of the marking material layer 102 is borophosphosilicate glass. Compared with common silicon oxide, borophosphosilicate glass has better hole filling ability and lower reflow temperature, which can improve the density of the marking material layer 102 .

[0058] In this embodiment, the detection light is reflected at the interface between the marking material layer 102 and the substrate 100. To increase the intensity of the reflected light, the transmittance of the marking material layer 102 to the detection light can be made greater than the transmittance of the substrate 100 to the detection light. In this way, most of the detection light can be reflected and the intensity of the reflected light is higher.

[0059] The interconnection layer 104 is used to realize the connection between the substrate 100 and a subsequently formed semiconductor device.

[0060] In this embodiment, the thickness d1 of the interconnection layer 104 is 3 μm to 5 μm.

[0061] By making the thickness d1 of the interconnection layer 104 greater than or equal to 3 μm, the semiconductor structure can meet the designed electrical requirements; by making the thickness d1 of the interconnection layer 104 less than or equal to 5 μm, the time for subsequent removal of the interconnection layer 104 can be reduced, the formation efficiency of the semiconductor structure can be improved, and the blocking of the detection light can be reduced, so as to further improve the intensity of the reflected light.

[0062] It should be noted that the thickness d1 in this embodiment is a value based on the surface of the marking material layer 102 located on the device region I.

[0063] In this embodiment, the material of the interconnection layer 104 is AlSi or AlSiCu.

[0064] In a specific embodiment, the material of the interconnect layer 104 is AlSi.

[0065] It can be seen from the foregoing that only a small portion of the detection light can be reflected due to the blocking of the interconnection layer 104 , resulting in a lower intensity of the received reflected light. Therefore, the intensity of the reflected light can be increased by removing at least a portion of the thickness of the interconnection layer 104 .

[0066] In this embodiment, refer to Figure 6 As shown in the schematic diagram of the detection principle of an alignment mark, the detection light L1 passes through the interconnection layer 104 and the marking material layer 102 on the marking area II in sequence, and is reflected at the top surface of the substrate 100, and the formed reflected light L2 is received after passing through the marking material layer 102 and the interconnection layer 104 again.

[0067] In this process, the intensity of the detection light L1 is determined by the semiconductor device itself, while the intensity of the reflected light L2 is related to the inherent loss of light intensity, the detection light L1, the marking material layer 102 and the interconnection layer 104. Furthermore, the alignment operation can be considered successful only when the matching degree between the intensity of the reflected light L2 and the intensity of the detection light L1 reaches a preset value, so the removal thickness of the interconnection layer 104 can be determined based on the intensity of the detection light L1, the parameters of the marking material layer 102 and the interconnection layer 104, and the intensity requirement of the reflected light L2.

[0068] Based on this, before removing the interconnection layer 104 of the marking area II (or before forming an opening in the interconnection layer 104 of the marking area II), the forming method further includes:

[0069] The removal thickness of the interconnection layer 104, that is, the depth of the opening is determined based on the ratio of the sum of the light intensity of the reflected light L2 and the inherent light intensity loss to the light intensity of the detection light L1, the product of the transmittance of the material of the interconnection layer 104 and the thickness of the interconnection layer 104, and the product of the transmittance of the material of the marking material layer 102 and the thickness of the marking material layer 102.

[0070] By adopting the above method, the performance of the device itself, the transmittance and thickness parameters of the interconnection layer 104 and the marking material layer 102 are taken into consideration at the same time, so that the depth of the opening can be accurately determined, and then the removal thickness of the interconnection layer 104 can be accurately determined. In this way, the removal time of the interconnection layer 104 can be reduced while improving the strength of the alignment signal, thereby improving the formation efficiency of the semiconductor structure.

[0071] In a specific embodiment, the removal thickness of the interconnection layer 104, that is, the depth of the opening, is determined using the following formula:

[0072]

[0073] Among them, h represents the depth of the opening, d1 represents the thickness of the interconnection layer before the opening is formed, T1 represents the transmittance of the material of the interconnection layer, d2 represents the thickness of the marking material layer before the opening is formed, T2 represents the transmittance of the material of the marking material layer, cd1 represents the intensity of the reflected light, cd2 represents the inherent loss of light intensity, and cd represents the intensity of the detection light.

[0074] It can be seen from the above formula that the greater the intensity of the detection light, the smaller the depth of the opening, and the smaller the thickness of the removed interconnect layer. Alternatively, when the intensity of the detection light is a constant, if the intensity of the reflected light is increased, the depth of the opening must be increased, and the thickness of the removed interconnect layer will be greater.

[0075] It should be noted that, first, Figure 6 The illustrated optical paths of the detection light L1 and the reflected light L2 are only examples, which are used to indicate the film layers through which the detection light L1 and the reflected light L2 pass. In actual processes, both the detection light L1 and the reflected light L2 may produce multiple reflections, refractions or transmissions, which cannot be understood as limitations on the present invention. Second, the inherent loss of light intensity may refer to the loss caused by the light passing through a reflector or a convex lens in the optical path, which reduces the intensity after conversion by the photoelectric signal converter. For the same device, when the intensity and optical path of the detection light are fixed, the inherent loss of light intensity remains unchanged. Third, the intensity of the reflected light in the above formula refers to the intensity when the alignment requirements are met. Fourth, the reflected light in this embodiment may be formed by the detection light being reflected by the substrate, the marking material layer and the interconnection layer.

[0076] In the above manner, after determining the thickness of the interconnection layer 104 to be removed, an opening G may be formed in the interconnection layer 104 in the marking region II.

[0077] In this embodiment, the depth of the opening G is less than the thickness of the interconnection layer 104 , and the marking material layer 102 covered by the opening G can be used as an alignment mark.

[0078] By making the depth of the opening G smaller than the thickness of the interconnection layer 104, on the one hand, the thickness of the interconnection layer 104 can be reduced, so that most of the detection light can be transmitted to the marking material layer 102 covered by the opening G, so as to improve the strength of the alignment signal; on the other hand, since there is no need to completely remove the interconnection layer 104, the removal time of the interconnection layer 104 can be reduced, thereby improving manufacturing efficiency.

[0079] In this embodiment, see Figures 2 to 4 The step of forming the opening G in the interconnection layer 104 of the marking area II includes: patterning the interconnection layer 104 of the marking area II to form the opening G.

[0080] In this embodiment, the patterning process includes:

[0081] See also Figure 2 , a photoresist 106 having a pattern opening K is formed on the interconnection layer 104, and the pattern opening K at least exposes the interconnection layer 104 located in the mark area II.

[0082] The photoresist 106 can serve as a barrier layer to protect the interconnection layer 104 on the device area I and prevent the interconnection layer 104 on the device area I from being patterned, thereby improving the surface quality of the interconnection layer 104. When an external device or circuit is connected through the interconnection layer 104, the resistance of the contact interface can be reduced, thereby improving the performance of the semiconductor structure.

[0083] In this embodiment, the step of forming a photoresist 106 having a graphic opening K on the interconnection layer 104 may include: forming a photoresist material layer on the interconnection layer 104; removing the photoresist material layer on at least the interconnection layer 104 located in the marking area II by development, and using the remaining part of the photoresist material layer as the photoresist 106.

[0084] In this embodiment, the thickness of the photoresist 106 is 4 μm to 4.5 μm.

[0085] By making the thickness of the photoresist 106 greater than or equal to 4 μm, damage to the interconnection layer 104 when removing the photoresist material layer on the interconnection layer 104 located in the marking area II can be avoided or reduced, thereby improving the flatness of the surface of the interconnection layer 104; by making the thickness of the photoresist 106 less than or equal to 4.5 μm, the time for removing the photoresist material layer on the interconnection layer 104 in the marking area II can be reduced, thereby improving the formation efficiency of the semiconductor structure.

[0086] In this embodiment, the photoresist 106 may be a positive photoresist. In some other embodiments, the photoresist 106 may be a negative photoresist.

[0087] In this embodiment, the development time is 90s to 180s. By controlling the development time, the removal thickness of the photoresist material layer can be accurately controlled, so that a graphic opening K exposing the top surface of the interconnection layer 104 can be formed in the photoresist 106 .

[0088] In this embodiment, the graphic opening K also exposes part of the interconnection layer 104 on the device area I, so that the formed opening G can completely cover the marking material layer 102 in the marking area II, thereby increasing the incident area of ​​the detection light, so that the detection light can be correctly transmitted to the marking material layer 102 in the marking area II.

[0089] See also Figure 3 , the interconnection layer 104 of the marking area II is etched along the pattern opening K to remove at least a portion of the thickness of the interconnection layer 104 exposed by the pattern opening K, thereby forming an opening G.

[0090] In this embodiment, at least one of wet etching and dry etching is used to remove at least a portion of the thickness of the interconnection layer 104 exposed by the pattern opening K.

[0091] In a specific embodiment, when a wet etching process is adopted, the solution is a mixture of nitric acid and phosphoric acid, and the etching time can be set according to the thickness of the interconnect layer 104 to be removed.

[0092] In an optional example, a wet etching process is used, and the etching time can be 180 seconds to 300 seconds.

[0093] In a specific embodiment, when a dry etching process is adopted, the dry etching process can be plasma etching, and the parameters of the plasma etching can include: the etching gas is Cl2 / BCl3 gas, the temperature is 200 to 250, and the etching time can be set according to the thickness of the interconnect layer 104 to be removed.

[0094] In an optional example, a dry etching process is used, and the etching time can be 50 seconds to 100 seconds.

[0095] In this embodiment, along the direction parallel to the surface of the substrate 100, the width of the opening G is greater than the width of the marking area II, so that the opening G can completely cover the marking material layer 102 in the marking area II, thereby increasing the incident area of ​​the detection light, so that the detection light can be correctly transmitted to the marking material layer 102 in the marking area II.

[0096] In a specific embodiment, along a direction parallel to the surface of the substrate 100 , the width of the opening G is 550 μm to 650 μm.

[0097] By making the width of the opening G greater than or equal to 550 μm, the opening G can completely cover the marking material layer 102 in the marking area II; by making the width of the opening G less than or equal to 650 μm, the space occupied on the device area I is smaller, which is conducive to forming other structures on the device area I.

[0098] In some other embodiments, along a direction parallel to the surface of the substrate 100 , the width of the opening G is the same as the width of the marking region II.

[0099] See also Figure 4 , remove the photoresist 106.

[0100] In this embodiment, a plasma stripping process is used to remove the photoresist 106 on the interconnection layer 104 .

[0101] In a specific embodiment, the parameters of the plasma stripping process include: gas is H2O / O2, temperature is 200-250°C, and duration is 50s to 100s.

[0102] In some other embodiments, an ashing process may be used to remove the photoresist 106 on the interconnection layer 104 .

[0103] In this embodiment, after removing the photoresist 106 , a cleaning step may be performed to remove polymer impurities generated during the patterning process.

[0104] Figure 5 It is a structural schematic diagram of a second embodiment of a method for forming a semiconductor structure of the present invention.

[0105] The similarities between this embodiment and the above-mentioned embodiment are not repeated here. The difference between this embodiment and the above-mentioned embodiment is that when the opening G is formed in the interconnection layer 104 of the mark area II, the interconnection layer 104 in the mark area II is completely removed, that is, the depth of the opening G is the same as the thickness of the interconnection layer 104, which can further increase the intensity of the reflected light, thereby improving the intensity of the alignment signal.

[0106] The invention also provides a semiconductor structure. Figure 4 It is a structural schematic diagram corresponding to an embodiment of a semiconductor structure of the present invention.

[0107] See also Figure 4 The semiconductor structure of this embodiment includes: a substrate 100, wherein the substrate 100 includes a device region I and a marking region II, wherein the marking region II of the substrate 100 has a groove (not shown in the figure); a marking material layer 102, which is located above the substrate 100 and fills the groove; an interconnection layer 104, which is located above the marking material layer 102; an opening G, which is located in the interconnection layer 104 of the marking region II, wherein the depth of the opening G is less than the thickness of the interconnection layer 104, and the marking material layer 102 covered by the opening G serves as an alignment mark.

[0108] The substrate 100 may provide a process operation basis for a formation process of a semiconductor structure.

[0109] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as silicon on insulator substrate or germanium on insulator substrate. The material of the substrate may be a material suitable for process requirements or easy to integrate.

[0110] In this embodiment, a groove is formed in the substrate 100 , and the marking material layer 102 in the groove can be used as an alignment mark.

[0111] In this embodiment, when the detection light is irradiated onto the alignment mark, the formation of a reflection signal with the alignment mark is mainly achieved based on the depth of the groove, or the height difference of the substrate surface. Therefore, along the normal direction of the substrate 100, the depth of the groove can be 100nm to 140nm. This can make the reflection signal reflected by the two step surfaces of the groove have a higher degree of distinction, and can further enhance the intensity of the reflection signal.

[0112] In this embodiment, the device region I of the substrate 100 is used to prepare and form a semiconductor device (eg, a transistor), and the mark region II of the substrate 100 is used to form an alignment mark.

[0113] In this embodiment, the structures of the substrate 100 in the device area I and the marking area II are different, wherein device structures such as source-drain doping layers and isolation layers are formed on the substrate 100 in the device area I, while device structures such as source-drain doping layers and isolation layers are not formed on the substrate 100 in the marking area II.

[0114] The mark material layer 102 is used to provide a process basis for the subsequent formation of alignment marks.

[0115] In this embodiment, the thickness d2 of the marking material layer 102 is 0.5 μm to 2 μm.

[0116] By making the thickness d2 of the marking material layer 102 greater than or equal to 0.5 μm, the breakdown voltage of the semiconductor structure can be enhanced; by making the thickness d2 of the marking material layer 102 less than or equal to 2 μm, the optical path of the detection light can be reduced, the light loss can be reduced, the intensity of the reflected light can be increased, and the alignment accuracy can be improved.

[0117] It should be noted that the thickness d1 in this embodiment is a value based on the surface of the substrate 100 located on the device region I.

[0118] In this embodiment, the material of the marking material layer 102 is one or more of silicate glass, phosphosilicate glass or borophosphosilicate glass.

[0119] In a specific embodiment, the material of the marking material layer 102 is borophosphosilicate glass. Compared with common silicon oxide, borophosphosilicate glass has better hole filling ability and lower reflow temperature, which can improve the density of the marking material layer 102 .

[0120] In this embodiment, the detection light is reflected at the interface between the marking material layer 102 and the substrate 100. To increase the intensity of the reflected light, the transmittance of the marking material layer 102 to the detection light can be made greater than the transmittance of the substrate 100 to the detection light. In this way, most of the detection light can be reflected and the intensity of the reflected light is higher.

[0121] The interconnection layer 104 is used to realize the connection between the substrate 100 and a subsequently formed semiconductor device.

[0122] In this embodiment, the thickness d1 of the interconnection layer 104 is 3 μm to 5 μm.

[0123] By making the thickness d1 of the interconnection layer 104 greater than or equal to 3 μm, the semiconductor structure can meet the designed electrical requirements; by making the thickness d1 of the interconnection layer 104 less than or equal to 5 μm, the time for subsequent removal of the interconnection layer 104 can be reduced, the formation efficiency of the semiconductor structure can be improved, and the blocking of the detection light can be reduced, so as to further improve the intensity of the reflected light.

[0124] It should be noted that the thickness d2 in this embodiment is a value based on the surface of the marking material layer 102 located on the device region I.

[0125] In this embodiment, the material of the interconnection layer 104 is AlSi or AlSiCu.

[0126] In a specific embodiment, the material of the interconnect layer 104 is AlSi.

[0127] It can be seen from the foregoing that only a small portion of the detection light can be reflected due to the blocking of the interconnection layer 104 , resulting in a lower intensity of the received reflected light. Therefore, the intensity of the reflected light can be increased by removing at least a portion of the thickness of the interconnection layer 104 .

[0128] In this embodiment, the depth of the opening G is less than the thickness of the interconnection layer 104 , and the marking material layer 102 covered by the opening G can be used as an alignment mark.

[0129] By making the depth of the opening G smaller than the thickness of the interconnection layer 104, on the one hand, the thickness of the interconnection layer 104 can be reduced, so that most of the detection light can be transmitted to the marking material layer 102 covered by the opening G, so as to improve the strength of the alignment signal; on the other hand, since there is no need to completely remove the interconnection layer 104, the removal time of the interconnection layer 104 can be reduced, thereby improving manufacturing efficiency.

[0130] In this embodiment, along the direction parallel to the surface of the substrate 100, the width of the opening G is greater than the width of the marking area II, so that the opening G can completely cover the marking material layer 102 in the marking area II, thereby increasing the incident area of ​​the detection light, so that the detection light can be correctly transmitted to the marking material layer 102 in the marking area II.

[0131] In a specific embodiment, along a direction parallel to the surface of the substrate 100 , the width of the opening G is 550 μm to 650 μm.

[0132] By making the width of the opening G greater than or equal to 550 μm, the opening G can completely cover the marking material layer 102 in the marking area II; by making the width of the opening G less than or equal to 650 μm, the space occupied on the device area I is smaller, which is conducive to forming other structures on the device area I.

[0133] In some other embodiments, along a direction parallel to the surface of the substrate 100 , the width of the opening G is the same as the width of the marking region II.

[0134] Figure 5 It is a structural schematic diagram corresponding to another embodiment of the semiconductor structure of the present invention.

[0135] The differences between this embodiment and the above embodiment are that the depth of the opening G is the same as the thickness of the interconnection layer 104, which can further increase the intensity of the reflected light and thus improve the intensity of the alignment signal.

[0136] It should be noted that the semiconductor structure described in this embodiment can be formed by the formation method described in the previous embodiment, or by other formation methods. For the specific description of the semiconductor structure described in this embodiment, reference can be made to the corresponding description in the previous embodiment, and this embodiment will not be repeated here.

[0137] Although the embodiments of the present invention are disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, It is characterized in that include: Providing a substrate, the substrate comprising a device area and a marking area, the marking area of ​​the substrate having a groove, the substrate having a marking material layer covering the groove, and an interconnection layer located on the marking material layer; An opening is formed in the interconnection layer of the mark area, the depth of the opening is less than or equal to the thickness of the interconnection layer, and the mark material layer covered by the opening is used as an alignment mark.

2. The method for forming a semiconductor structure according to claim 1, It is characterized in that Before forming the opening in the interconnect layer of the marking area, the forming method further comprises: Determine the depth of the opening according to the ratio of the sum of the intensity of the reflected light and the intrinsic loss of the light intensity to the intensity of the detection light, the product of the transmittance of the material of the interconnection layer and the thickness of the interconnection layer, and the product of the transmittance of the material of the marking material layer and the thickness of the marking material layer; The reflected light is formed by the detection light being reflected by the substrate, the marking material layer and the interconnection layer.

3. The method for forming a semiconductor structure according to claim 2, It is characterized in that The depth of the opening is determined using the following formula: Where h is the depth of the opening, d 1 represents the thickness of the interconnect layer before forming the opening, T 1 represents the light transmittance of the material of the interconnect layer, d 2 represents the thickness of the marking material layer before forming the opening, T 2 Indicates the light transmittance of the marking material layer, cd 1 Indicates the intensity of reflected light, cd 2 represents the inherent loss of light intensity, and cd represents the intensity of the detection light.

4. The method for forming a semiconductor structure according to claim 2, It is characterized in that The thickness of the marking material layer is 0.5 μm to 2 μm; The material of the marking material layer is one or more of silicate glass, phosphosilicate glass or borophosphosilicate glass.

5. The method for forming a semiconductor structure according to claim 2, It is characterized in that The thickness of the interconnection layer is 3 μm to 5 μm; The material of the interconnection layer is AlSi or AlSiCu.

6. The method for forming a semiconductor structure according to claim 1, It is characterized in that The transmittance of the marking material layer to the detection light is greater than the transmittance of the substrate to the detection light.

7. The method for forming a semiconductor structure according to claim 1, It is characterized in that The step of forming an opening in the interconnect layer of the marking area comprises: The interconnection layer in the marking area is patterned to form the opening.

8. The method for forming a semiconductor structure according to claim 7, It is characterized in that The patterning process comprises: forming a photoresist having a pattern opening on the interconnection layer, wherein the pattern opening at least exposes the interconnection layer located in the mark area; Etching the interconnection layer in the marking area along the graphic opening to remove at least a portion of the thickness of the interconnection layer exposed by the photoresist to form the opening; The photoresist is removed.

9. The method for forming a semiconductor structure according to claim 1, It is characterized in that Along a direction parallel to the substrate surface, the width of the opening is greater than the width of the marking area.

10. The method for forming a semiconductor structure according to claim 8, It is characterized in that Along a direction parallel to the surface of the substrate, a width of the opening is 550 μm to 650 μm.

11. The method for forming a semiconductor structure according to claim 1, It is characterized in that Along the normal direction of the substrate surface, the depth of the groove is 100 nm to 140 nm.

12. A semiconductor structure, It is characterized in that include: A substrate, the substrate comprising a device area and a marking area, and the marking area of ​​the substrate has a groove; a marking material layer, located above the substrate and filling the groove; an interconnect layer, located above the marking material layer; The opening is located in the interconnection layer of the mark area, the depth of the opening is less than or equal to the thickness of the interconnection layer, and the mark material layer covered by the opening serves as an alignment mark.

13. The semiconductor structure according to claim 12, It is characterized in that The thickness of the marking material layer is 0.5 μm to 2 μm; The material of the marking material layer is one or more of silicate glass, phosphosilicate glass or borophosphosilicate glass.

14. The semiconductor structure according to claim 12, It is characterized in that The thickness of the interconnection layer is 3 μm to 5 μm; The material of the interconnection layer is AlSi or AlSiCu.

15. The semiconductor structure according to claim 12, It is characterized in that The transmittance of the marking material layer to the detection light is greater than the transmittance of the substrate to the detection light.

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