Packaging structure for improving Wafer warping in Chiplet packaging

Abstract

The invention belongs to the technical field of chip production and processing, and particularly relates to a packaging structure for improving Wafer warping in Chiplet packaging, which comprises a packaging assembly, the packaging assembly comprises a stainless steel carrier, the top of the stainless steel carrier is provided with a UV adhesive film, the top of the UV adhesive film is provided with rigid supports, a chip main body is arranged between the rigid supports, and the chip main body is arranged between the rigid supports. A plastic package filler layer is arranged between the chip main body and the rigid support, PI1 insulation protection films are arranged at the top of the chip main body, RDL is arranged between the PI1 insulation protection films, PI2 insulation protection films are arranged at the tops of the PI1 insulation protection films, PAD is arranged between the PI2 insulation protection films, and bump solder balls are arranged at the tops of the PAD. The warping can be ensured to be within a reasonable range, enough flatness is kept, subsequent installation work of a chip on a PCB and other substrates is facilitated, and the yield and the process stability are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip production and processing, and in particular to a packaging structure for improving chiplet packaging wafer warping. Background Art

[0002] Chiplet technology is to split a chip die with rich functions and large area into multiple core particles (chiplets), and combine these core particles with specific functions through advanced packaging to finally form a system chip. Chiplet technology divides large chips into smaller chips, which helps to improve the yield rate and thus reduce manufacturing costs. Compared with traditional SoC solutions, the chiplet model has three advantages: design flexibility, low cost, and short time to market. Therefore, splitting the SoC into several key chiplets can better balance the R&D costs and avoid the huge losses caused by insufficient shipments after a large SoC chip is designed, thereby shortening the R&D cycle and R&D personnel investment. During the chiplet technology packaging process, wafer reconstruction technology needs to be used to integrate chips with different functions into one chip. The current mainstream practice is to grind and cut chips with different functions, and then mount them with the PAD side facing down on a stainless steel carrier with tape to form a die with a completed functional module, and then use EMC plastic encapsulation material to encapsulate them from the back. Due to the different sizes of chips and the CTE mismatch between mainstream silicon substrate chips and plastic packaging materials EMC, after the plastic packaging is completed, the reconstructed Wafer after removing the stainless steel carrier is severely warped. The subsequent RDL rewiring and PI high-temperature curing process on the machine will seriously aggravate the warping, making the process difficult to carry out effectively and seriously affecting the yield.

[0003] Based on the above problems, we propose a packaging structure to improve the chiplet packaging wafer warpage. Summary of the invention

[0004] The purpose of this section is to summarize some aspects of the embodiments of the present invention and briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this section and the specification abstract and the invention title of this application to avoid blurring the purpose of this section, the specification abstract and the invention title, and such simplifications or omissions cannot be used to limit the scope of the present invention.

[0005] In view of the problems existing in the existing clamps, the present invention is proposed.

[0006] Therefore, the purpose of the present invention is to provide a packaging structure for improving the warpage of chiplet packaging wafer, which can ensure that the warpage is within a reasonable range and maintain sufficient flatness, which is beneficial to the subsequent installation of chips on substrates such as PCBs to improve the yield and process stability.

[0007] To solve the above technical problems, according to one aspect of the present invention, the present invention provides the following technical solutions:

[0008] A packaging structure for improving chiplet packaging wafer warpage, comprising a packaging component;

[0009] The packaging component includes a stainless steel carrier, a UV adhesive film is arranged on the top of the stainless steel carrier, a rigid bracket is arranged on the top of the UV adhesive film, a chip body is arranged between the rigid brackets, a plastic sealing filler layer is arranged between the chip body and the rigid brackets, a PI1 insulating protective film is arranged on the top of the chip body, an RDL is arranged between the PI1 insulating protective films, a PI2 insulating protective film is arranged on the top of the PI1 insulating protective film, a PAD is arranged between the PI2 insulating protective films, and a bump solder ball is arranged on the top of the PAD.

[0010] As a preferred solution of the packaging structure for improving chiplet packaging wafer warpage according to the present invention, the use steps are as follows:

[0011] Step 1: Attach the UV film to the surface of the stainless steel carrier;

[0012] Step 2: Attach the rigid bracket to the top of the UV film;

[0013] Step 3: Place the chip body face down between the rigid brackets;

[0014] Step 4: Fill the space between the rigid support and the chip body with plastic filling material to form a plastic filling material layer;

[0015] Step 5: After the plastic packing layer is formed, remove the stainless steel carrier and UV film;

[0016] Step 6: Rearrange the PI1 insulating protective film and RDL on the top of the chip body;

[0017] Step 7: Arrange the PI2 insulating protective film and PAD on top of the PI1 insulating protective film;

[0018] Step 8: Place bump solder balls on top of the PAD and perform electroplating.

[0019] Step 9: Cutting completes the system chip package.

[0020] Compared with the prior art, the beneficial effects of the present invention are: the support of the rigid bracket not only ensures that the warping of the reconstructed RDL and PI and the bump formation process is within a reasonable range, but also ensures that a collection of single-function chips such as Die1 Die2 Die3 constitute a system chip, and the rigid bracket support maintains sufficient flatness, which is beneficial to the subsequent chip installation work on substrates such as PCB to improve the yield and process stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the present invention will be described in detail below in combination with the accompanying drawings and detailed embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor. Among them:

[0022] Figure 1 It is a schematic diagram of the structure of the present invention;

[0023] Figure 2 This is a schematic diagram of the final packaging structure of the present invention.

[0024] In the figure; 100: packaging component, 110: stainless steel carrier, 120: UV adhesive film, 130: rigid bracket, 140: chip body, 150: plastic sealing filler layer, 160: PI1 insulating protective film, 161: RDL, 170: PI2 insulating protective film, 171: PAD, 180 bump solder ball. DETAILED DESCRIPTION

[0025] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0026] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0027] Secondly, the present invention is described in detail with reference to schematic diagrams. When describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0028] In order to make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0029] The present invention provides the following technical solution: a packaging structure for improving the warpage of a chiplet packaging wafer, which can ensure that the warpage is within a reasonable range and maintain sufficient flatness during use, which is beneficial to the subsequent installation of chips on substrates such as PCBs to improve the yield and process stability;

[0030] Example 1

[0031] A packaging structure for improving chiplet packaging wafer warpage, including a packaging component 100;

[0032] The packaging component 100 includes a stainless steel carrier 110, a UV film 120 is installed on the top of the stainless steel carrier 110, a rigid bracket 130 is installed on the top of the UV film 120, a chip body 140 is installed between the rigid brackets 130, a plastic sealing filler layer 150 is filled between the chip body 140 and the rigid brackets 130, a PI1 insulating protective film 160 is installed on the top of the chip body 140, an RDL 161 is installed between the PI1 insulating protective films 160, a PI2 insulating protective film 170 is installed on the top of the PI1 insulating protective film 160, a PAD 171 is installed between the PI2 insulating protective films 170, and a bump solder ball 180 is installed on the top of the PAD 171.

[0033] The steps to use are as follows:

[0034] Step 1: Attach the UV film 120 to the surface of the stainless steel carrier 110;

[0035] Step 2: attach the rigid bracket 130 to the top of the UV film 120;

[0036] Step 3: Place the chip body 140 face down between the rigid brackets 130;

[0037] Step 4: Filling a plastic filling material between the rigid support 130 and the chip body 140 to form a plastic filling material layer 150;

[0038] Step 5: After the plastic packing layer 150 is formed, the stainless steel carrier 110 and the UV film 120 are removed;

[0039] Step 6: Rearrange the PI1 insulating protection film 160 and the RDL 161 on the top of the chip body 140;

[0040] Step 7: Arrange the PI2 insulating protection film 170 and the PAD 171 on top of the PI1 insulating protection film 160;

[0041] Step 8: Place a bump solder ball 180 on top of PAD 171 and perform electroplating operation;

[0042] Step 9: Cutting completes the system chip package.

[0043] Working principle: The support of the rigid bracket not only ensures that the warpage of the reconstructed RDL, PI and bump formation process is within a reasonable range, but also ensures that the system chip composed of a collection of single-function chips such as Die1 Die2 Die3 can maintain sufficient flatness, which is beneficial to the subsequent installation of chips on substrates such as PCB to improve the yield and process stability.

[0044] Although the present invention has been described above with reference to the embodiments, various modifications may be made thereto and parts thereof may be replaced by equivalents without departing from the scope of the present invention. In particular, as long as there is no structural conflict, the various features in the embodiments disclosed in the present invention may be used in combination with each other in any manner, and the fact that these combinations are not exhaustively described in this specification is only for the sake of omitting space and saving resources. Therefore, the present invention is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A packaging structure for improving chiplet packaging wafer warpage, characterized in that: It includes a packaging assembly (100); The packaging component (100) comprises a stainless steel carrier (110), a UV adhesive film (120) is arranged on the top of the stainless steel carrier (110), a rigid support (130) is arranged on the top of the UV adhesive film (120), a chip body (140) is arranged between the rigid supports (130), a plastic sealing filler layer (150) is arranged between the chip body (140) and the rigid support (130), a PI1 insulating protective film (160) is arranged on the top of the chip body (140), an RDL (161) is arranged between the PI1 insulating protective films (160), a PI2 insulating protective film (170) is arranged on the top of the PI1 insulating protective film (160), a PAD (171) is arranged between the PI2 insulating protective films (170), and a bump solder ball (180) is arranged on the top of the PAD (171).

2. According to claim 1, a packaging structure for improving chiplet packaging wafer warpage, characterized in that: The steps to use are as follows: Step 1: attaching a UV adhesive film (120) to the surface of a stainless steel carrier (110); Step 2: attaching the rigid support (130) to the top of the UV adhesive film (120); Step 3: Place the chip body (140) face down between the rigid brackets (130); Step 4: Filling a plastic encapsulation filler between the rigid support (130) and the chip body (140) to form a plastic encapsulation filler layer (150); Step 5: After the plastic sealing filler layer (150) is formed, the stainless steel carrier (110) and the UV adhesive film (120) are removed; Step 6: Rearrange the PI1 insulating protection film (160) and the RDL (161) on the top of the chip body (140); Step 7: Arrange the PI2 insulating protective film (170) and the PAD (171) on top of the PI1 insulating protective film (160); Step 8: Placing a bump solder ball (180) on top of the PAD (171) and performing an electroplating operation; Step 9: Cutting completes the system chip package.

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