Silicon carbide super-junction UMOS with high-K gate dielectric and blocking junction

Abstract

The invention discloses a silicon carbide super-junction UMOS with a high-K dielectric layer and a blocking junction, and belongs to the technical field of semiconductors. Comprising a drain electrode, an N-type substrate layer, a first N-type auxiliary region, a P-type auxiliary region, a second N-type auxiliary region, an N column region, a first P column region, a second P column region, an N-type drainage layer, a P-type base region, a P-type source region, an N-type source region, a high-K gate insulating dielectric layer, a thermal buffer layer, a polycrystalline silicon gate electrode, a source electrode and a P-type shielding layer. According to the invention, the internal electric field of the UMOS is modulated by using the high-K gate insulating dielectric layer, the reverse breakdown voltage of the device is increased, the on-resistance is reduced, and the static characteristic of the device is improved; the P-type auxiliary region and the second N-type auxiliary region are utilized to form an auxiliary layer with a blocking junction property and an N-type variable doping characteristic, so that the soft reverse recovery characteristic and the high breakdown voltage capability are enhanced; the N-type drainage layer and the P-type base region are utilized to form a secondary blocking junction, reverse recovery is enhanced, current distribution in an N column is improved, and characteristic on-resistance is reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors, and in particular relates to a silicon carbide superjunction UMOS structure with a high-K dielectric layer and a blocking junction. Background Art

[0002] As the frequency of power device applications continues to increase, contemporary power systems are also increasingly demanding on the device's dynamic performance, such as switching speed and reverse recovery characteristics. This puts forward new requirements for the device's dynamic characteristics optimization design. As a representative of new power MOSFET devices, superjunction power MOSFET devices achieve ultra-low specific on-resistance through unique charge compensation technology, significantly improving device efficiency and greatly reducing system power losses.

[0003] The superjunction structure plays a charge compensation role by alternating the P / N columns in the drift region. This design achieves high withstand voltage while maintaining a relatively thin drift region, and significantly reduces the characteristic on-resistance of the device, breaking through the theoretical limitations of traditional unipolar devices. Therefore, it has attracted widespread attention in the industry and has gradually been applied to the development of SiC power devices. However, the superjunction structure needs to solve the problem of charge imbalance. Once charge imbalance occurs, the breakdown voltage may be greatly reduced. Since high-K dielectric materials modulate the electric field, the impact of charge imbalance is minimized, which has become a hot research direction.

[0004] At the same time, in superjunction UMOSFET, the staggered structure of P and N columns can induce the JFET (junction field effect transistor) effect in some cases, that is, the narrow channel formed between the P and N columns limits the flow of current. This effect usually increases the on-resistance of the device and reduces efficiency. Summary of the invention

[0005] In view of the above-mentioned deficiencies in the prior art, the present invention provides a silicon carbide superjunction UMOS with a high-K dielectric layer and a blocking junction, which solves the problems of charge imbalance and JFET effect in the superjunction structure.

[0006] In order to achieve the above-mentioned invention object, the technical solution adopted by the present invention is: a silicon carbide super junction UMOS with a high-K dielectric layer and a blocking junction, including: a drain, an N-type substrate layer, a first N-type auxiliary region, a P-type auxiliary region, a second N-type auxiliary region, an N-column region, a first P-column region, a second P-column region, an N-type drain layer, a P-type base region, a P-type source region, an N-type source region, a high-K gate insulating dielectric layer, a thermal buffer layer, a polysilicon gate, a source and a P-type shielding layer;

[0007] The N-type substrate layer is located above the drain, the first N-type auxiliary region is located above the N-type substrate layer, the P-type auxiliary region is located above the first N-type auxiliary region, the second N-type auxiliary region is located above the P-type auxiliary region, the N-column region is located in the middle above the second N-type auxiliary region, the first P-column region is located above the second N-type auxiliary region and on both sides of the N-column region, the second P-column region is located above the first P-column region, the N-type drain layer is located above the second P-column region, the P-type base region is located above the N-type drain layer, the P-type source region and the N-type source region are adjacent and both are located above the P-type base region, the P-type shielding layer is located in the upper trench of the N-column region, the thermal buffer layer is located above the P-type shielding layer and is in contact with the N-type drain layer, the P-type base region and the N-type source region, the high-K gate insulating dielectric layer is located above the thermal buffer layer, the polysilicon gate is embedded in the high-K gate insulating dielectric layer, and the source electrode is located above the P-type source region, the N-type source region, the high-K gate insulating dielectric layer and the thermal buffer layer, and is in direct contact with each other;

[0008] The drain, N-type substrate layer, first N-type auxiliary region, P-type auxiliary region, second N-type auxiliary region, N-column region, P-type base region, N-type source region and source electrode constitute an electron flow region.

[0009] The beneficial effects of the present invention are as follows: the present invention replaces the conventional gate dielectric insulating layer with a high-K dielectric, and forms a MIS metal-insulating layer-semiconductor structure with a high-K gate insulating dielectric layer, a thermal buffer layer, a polysilicon gate and an N-column region, and uses the high-K dielectric to modulate the internal electric field of the UMOS device, thereby increasing the reverse breakdown voltage of the device, reducing the on-resistance, and improving the static characteristics of the device; at the same time, a P-type auxiliary region and a second N-type auxiliary region are used to form an auxiliary layer with a blocking junction property and an N-type variable doping characteristic, thereby enhancing the soft reverse recovery characteristics and high breakdown voltage capability of the device; a superjunction structure is formed by using the N-column region, the first P-column region and the second P-column region, and then a high-doping concentration N-type drain layer is deposited, thereby reducing the non-uniform flow of current and reducing the characteristic on-resistance.

[0010] Furthermore: the doping concentrations in the first N-type auxiliary region and the second N-type auxiliary region are different, and both show a trend of continuously decreasing from bottom to top;

[0011] The P-type auxiliary region and the second N-type auxiliary region constitute an auxiliary layer and form a blocking junction;

[0012] The thickness of the P-type auxiliary region is set to 0.65-0.8 μm, and the doping concentration is set to be high.

[0013] The beneficial effects of the above further scheme are: the doping concentrations in the first N-type auxiliary region and the second N-type auxiliary region are different, which can make the electric field change more gentle and improve the breakdown voltage of the UMOS device; the P-type auxiliary region and the second N-type auxiliary region constitute an auxiliary layer, which has a blocking junction property and N-type variable doping characteristics, can reduce the flow of carriers, has a high blocking voltage capability, and enables the UMOS device to have a higher breakdown voltage; the thickness of the P-type auxiliary region is set to 0.65-0.8μm, which can reduce the JFET effect and prevent the current from being blocked.

[0014] Further: the N column region, the first P column region and the second P column region form a super junction structure;

[0015] The first P column region and the second P column region form a P column region, which is used to assist the depletion of the N column region and form a potential barrier in the N column region to isolate the gate and the high electric field generated by the current flow in the N column region;

[0016] The doping concentrations in the first P column region and the second P column region are different, and both show a trend of continuously decreasing from bottom to top.

[0017] The beneficial effect of the above further solution is that the voltage tolerance of the UMOS device can be improved and the characteristic on-resistance can be reduced by forming a super junction structure through the N column region, the first P column region and the second P column region.

[0018] Further: the N-type drain layer and the P-type base region form a secondary blocking junction;

[0019] The N-type drain layer is set to have a high doping concentration to form a low-resistance path;

[0020] The N-type drain layer is located above the super junction structure composed of the N column region, the first P column region and the second P column region, and is located below the P-type base region.

[0021] The beneficial effects of the above further solution are: by forming a sub-type blocking junction, the breakdown voltage of the UMOS device can be increased. At the same time, setting the N-type drain layer to a high doping concentration can reduce the non-uniform current flow of the P column and the N column and reduce the characteristic on-resistance.

[0022] Further: the P-type source region and the adjacent N-type source region form a body diode;

[0023] The N-type source region is set to have a high doping concentration.

[0024] The beneficial effect of the above further solution is that a body diode is formed by the P-type source region and the adjacent N-type source region, so that the gate can more effectively control the flow of electrons in the channel region, thereby improving the switching characteristics of the UMOS device.

[0025] Further: the high-K gate insulating dielectric layer, the thermal buffer layer, the polysilicon gate and the N column region form a MIS metal-insulating layer-semiconductor structure;

[0026] The high-K gate insulating dielectric layer is provided with a high dielectric constant.

[0027] The beneficial effect of the above further scheme is: the high-K gate insulating dielectric layer, thermal buffer layer, polysilicon gate and N-column region form a MIS metal-insulating layer-semiconductor structure, and the high-K dielectric is used to modulate the internal electric field of the device, which can increase the reverse breakdown voltage of the UMOS device, reduce the on-resistance, and improve the static characteristics of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A structural diagram of a silicon carbide superjunction UMOS having a high-K dielectric layer and a blocking junction provided by the present invention;

[0029] Figure 2 Schematic diagram of the longitudinal electric field distribution of the UMOS device provided by the present invention, the conventional SiC UMOS device and the common super junction SiC UMOS device;

[0030] Figure 3 A schematic diagram of longitudinal current density distribution of the UMOS device provided by the present invention, a conventional SiC UMOS device and a common super junction SiC UMOS device;

[0031] Figure 4 A breakdown voltage distribution curve diagram of the UMOS device provided by the present invention, a conventional SiC UMOS device and a common super junction SiC UMOS device;

[0032] Figure 5 Output characteristic curves of the UMOS device provided by the present invention, conventional SiC UMOS device and common super junction SiC UMOS device;

[0033] Figure 6 Reverse recovery characteristic curves of the UMOS device provided by the present invention, a conventional SiC UMOS device and a common super junction SiC UMOS device;

[0034] Among them: 1-drain; 2-N-type substrate layer; 3-first N-type auxiliary region; 4-P-type auxiliary region; 5-second N-type auxiliary region; 6-N column region; 7-first P column region; 8-second P column region; 9-N-type drainage layer; 10-P-type base region; 11-P-type source region; 12-N-type source region; 13-high-K gate insulating dielectric layer; 14-thermal buffer layer; 15-polysilicon gate; 16-source; 17-P-type shielding layer. DETAILED DESCRIPTION

[0035] The specific implementation modes of the present invention are described below so that those skilled in the art can understand the present invention. However, it should be clear that the present invention is not limited to the scope of the specific implementation modes. For those of ordinary skill in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the attached claims, these changes are obvious, and all inventions and creations utilizing the concept of the present invention are protected.

[0036] Example 1

[0037] like Figure 1 As shown, a silicon carbide super junction UMOS structure with a high-K dielectric layer and a blocking junction includes: a drain 1, an N-type substrate layer 2, a first N-type auxiliary region 3, a P-type auxiliary region 4, a second N-type auxiliary region 5, an N-column region 6, a first P-column region 7, a second P-column region 8, an N-type drain layer 9, a P-type base region 10, a P-type source region 11, an N-type source region 12, a high-K gate insulating dielectric layer 13, a thermal buffer layer 14, a polysilicon gate 15, a source 16 and a P-type shielding layer 17;

[0038] The N-type substrate layer 2 is located above the drain 1, the first N-type auxiliary region 3 is located above the N-type substrate layer 2, the P-type auxiliary region 4 is located above the first N-type auxiliary region 3, the second N-type auxiliary region 5 is located above the P-type auxiliary region 4, the N-column region 6 is located in the middle above the second N-type auxiliary region 5, the first P-column region 7 is located above the second N-type auxiliary region 5 and on both sides of the N-column region 6, the second P-column region 8 is located above the first P-column region 7, the N-type drain layer 9 is located above the second P-column region 8, the P-type base region 10 is located above the N-type drain layer 9, and the P-type The source region 11 and the N-type source region 12 are both located above the P-type base region 10, the P-type shielding layer 17 is located in the groove above the N-column region 6, the thermal buffer layer 14 is located above the P-type shielding layer 17, and is in contact with the N-type drain layer 9, the P-type base region 10 and the N-type source region 12, the high-K gate insulating dielectric layer 13 is located above the thermal buffer layer 14, the polysilicon gate 15 is embedded in the high-K gate insulating dielectric layer 13, and the source 16 is located above the P-type source region 11, the N-type source region 12, the high-K gate insulating dielectric layer 13 and the thermal buffer layer 14, and is in direct contact with them.

[0039] In one embodiment of the present invention, the drain 1, the N-type substrate layer 2, the first N-type auxiliary region 3, the P-type auxiliary region 4, the second N-type auxiliary region 5, the N-column region 6, the P-type base region 10, the N-type source region 12 and the source 16 constitute an electron flow region for conduction.

[0040] In a UMOS (Ultra-thin Oxide MOSFET, metal oxide semiconductor field effect transistor with ultra-thin oxide layer) device, a PN structure between the source and the drain forms a body diode inside the UMOS. The body diode has a reverse recovery characteristic. When the UMOS device is in a switching state, the body diode will also experience a reverse recovery time. In high-frequency and high-performance applications, the reverse recovery process of the body diode will increase switching losses and reduce the overall switching performance of the device. By introducing a P-type auxiliary region 4 and adding artificial holes in the second N-type auxiliary region 5, the UMOS device has a soft reverse recovery characteristic, and the stored minority carriers of the body diode switching from the forward conduction state to the reverse blocking state are reduced, thereby accelerating the charge recombination process, obtaining a smooth current, and reducing the peak electric field caused by the current spike generated by the reverse recovery.

[0041] In one embodiment of the present invention, the doping concentrations in the first N-type auxiliary region 3 and the second N-type auxiliary region 5 are different, and both show a trend of continuously decreasing from bottom to top, so that the potential change presents a trapezoidal effect, making the electric field change more gentle, thereby increasing the breakdown voltage of the UMOS device and improving the performance. The P-type auxiliary region 4 and the second N-type auxiliary region 5 form an auxiliary layer with blocking junction properties and N-type variable doping characteristics, which is used to reduce the flow of carriers; in the forward bias state, the current can pass freely, and in the reverse bias state, the P-type auxiliary region 4 and the second N-type auxiliary region 5 form a depletion region with a high blocking voltage capability, so that the UMOS device has a higher breakdown voltage.

[0042] At the same time, the first N-type auxiliary region 3 and the P-type auxiliary region 4 will form a blocking PN junction, and the resulting depletion region will hinder the conduction of current and produce a JFET effect. In order to reduce the JFET effect, the P-type auxiliary region 4 needs to be very thin and highly doped. In this embodiment, the thickness of the P-type auxiliary region 4 is set to 0.65-0.8μm.

[0043] In one embodiment of the present invention, a lower concentration of doping is used in the second N-type auxiliary region 5, so that the depletion region of the UMOS device can be expanded wider when reverse biased, which is convenient for dispersing the electric field, reducing the electric field strength, and further improving the breakdown voltage of the UMOS device; using a higher concentration of doping in the P-type auxiliary region 4 can further reduce the forward on-resistance and improve the conduction characteristics of the UMOS device when forward biased.

[0044] In one embodiment of the present invention, the N column region 6, the first P column region 7 and the second P column region 8 form a super junction structure, which work together to improve the voltage tolerance of the UMOS device and reduce the characteristic on-resistance;

[0045] Among them, the N column region 6 serves as the main electron conduction path when the UMOS device is turned on. When the gate voltage exceeds the threshold voltage, the electrons in the N column region 6 are enriched into a conductive channel due to the super junction structure, allowing current to flow from the drain to the source;

[0046] The first P column region 7 and the second P column region 8 together form a P column region, which does not participate in the conduction in the super junction structure, and is staggered with the N column region to form a charge-neutral structure, assisting the depletion of the N column region 6 to achieve charge balance. At the same time, the P column region can form an electric potential barrier in the N column region 6 to isolate the high electric field generated by the current flow of the gate and the N column region 6, which helps to guide the flow of electrons when the UMOS device is turned on;

[0047] The first P column region 7 and the second P column region 8 are doped with different doping concentrations. By implementing layered doping, the potential change is trapezoidal, avoiding the formation of a local peak electric field at the bottom of the trench, increasing the breakdown voltage of the device, and improving the overall performance.

[0048] In one embodiment of the present invention, the N-type drain layer 9 and the P-type base region 10 form a secondary blocking junction, which improves the uniform distribution of current in the N column, plays a rectifying role and reduces the characteristic on-resistance; in the forward bias state, the current can pass freely, and in the reverse bias state, it has a high blocking voltage capability, so that the UMOS device has a higher breakdown voltage.

[0049] At the same time, in the super junction structure formed by the staggered P columns and N columns, there are tiny discontinuous or unevenly doped areas between the columns, which makes the current flow non-uniformly. An N-type drainage layer 9 is arranged on the top, and the N-type drainage layer 9 is set to a high doping concentration, which can increase the carrier concentration and form a low-resistance path, so that the current is more effectively distributed to the N column area, reducing the increase in characteristic on-resistance caused by the uneven flow of current, while reducing the formation of local overload and hot spots, and improving the conduction performance and thermal stability of the UMOS device.

[0050] It should be emphasized that the N-type drain layer 9 should be located above the P-column and the N-column, below the P-type base region 10, and between the two. This allows the P-column region and the N-type drain layer 9 to be in a body diode blocking state when the device is forward-conducted, so that the electron flow is fixed in the N-column region.

[0051] In one embodiment of the present invention, the P-type source region 11 is located above the P-type base region 10 and below the source 16; the P-type source region 11 and the adjacent N-type source region 12 form a body diode. When the UMOS device is in the on state, the P-type source region 11 can adjust and control the threshold voltage of the gate. Through the structural interaction of the N-type source region 12, the gate can more effectively control the flow of electrons in the channel region, thereby improving the switching characteristics of the device.

[0052] In one embodiment of the present invention, the N-type source region 12 is located above the P-type base region 10 and below the source 16. The N-type source region 12 is in direct contact with the source 16, and the N-type source region 12 is set to a high doping concentration, which can reduce the contact resistance between the source 16 metal and the SiC material; at the same time, when the device is turned on, the N-type source region 12 improves the electron injection capability, accelerates the formation of a conductive channel, further reduces the characteristic on-resistance, and optimizes the conductive performance of the UMOS device.

[0053] In one embodiment of the present invention, the high-K gate insulating dielectric layer 13, the thermal buffer layer 14, the polysilicon gate 15 and the N column region 6 constitute a MIS structure, that is, a metal-insulating layer-semiconductor structure. The high-K gate insulating dielectric layer 13 has a high dielectric constant and can modulate the electric field at the bottom of the trench, reduce the peak electric field at the bottom of the trench, and improve the breakdown voltage of the device; at the same time, when the device is forward-conducting, the high-K gate insulating dielectric layer 13 can increase the amount of charge on the surface of the N column region 6, form a low-resistance path, and reduce the characteristic on-resistance; since the energy band gap of the high-K gate insulating dielectric layer 13 is very narrow, when the UMOS device is reverse blocked, the possibility of carriers tunneling through the dielectric is greatly increased, resulting in an increase in gate leakage current. At this time, adding a thin thermal buffer layer 14 between the high-K gate insulating dielectric layer 13 and the N column region 6 can reduce thermal stress and reduce the carrier tunneling effect. The thermal buffer layer 14 can use SiO2 as a material.

[0054] In one embodiment of the present invention, the P-type shielding layer 17 is located at the bottom of the groove above the N-column region 6. The P-type shielding layer 17 can attract electrons in the groove area, increase the electron density when the channel is formed, and improve the control ability of the gate, so that the gate can more effectively control the opening and closing of the channel, thereby reducing the threshold voltage of the device and increasing the switching speed; at the same time, the P-type shielding layer 17 can optimize the electric field distribution, especially in the groove above the N-column region 6, which can effectively smooth the electric field gradient, reduce the formation of the peak electric field, and increase the breakdown voltage of the UMOS device.

[0055] The beneficial effects of the present invention are as follows: the present invention replaces the conventional gate dielectric insulating layer with a high-K dielectric, and forms a MIS metal-insulating layer-semiconductor structure with a high-K gate insulating dielectric layer, a thermal buffer layer, a polysilicon gate and an N-column region, and uses the high-K dielectric to modulate the internal electric field of the UMOS device, thereby increasing the reverse breakdown voltage of the device, reducing the on-resistance, and improving the static characteristics of the device; at the same time, a P-type auxiliary region and a second N-type auxiliary region are used to form an auxiliary layer with a blocking junction property and an N-type variable doping characteristic, thereby enhancing the soft reverse recovery characteristics and high breakdown voltage capability of the device; a superjunction structure is formed by using the N-column region, the first P-column region and the second P-column region, and then a high-doping concentration N-type drain layer is deposited, thereby reducing the non-uniform flow of current and reducing the characteristic on-resistance.

[0056] Example 2

[0057] The present invention proposes a silicon carbide super junction UMOS device with a high-K dielectric layer and a blocking junction, comprising: a drain 1, an N-type substrate layer 2, a first N-type auxiliary region 3, a P-type auxiliary region 4, a second N-type auxiliary region 5, an N-column region 6, a first P-column region 7, a second P-column region 8, an N-type drain layer 9, a P-type base region 10, a P-type source region 11, an N-type source region 12, a high-K gate insulating dielectric layer 13, a thermal buffer layer 14, a polysilicon gate 15, a source 16 and a P-type shielding layer 17;

[0058] In one embodiment of the present invention, various structural parameters and doping concentrations in the UMOS device are shown in Table 1.

[0059] Table 1

[0060] structure parameter unit The length of the first N-type auxiliary region 1.5 μm N-type buffer 1 concentration <![CDATA[2.5×10 15 ]]> <![CDATA[cm -3 ]]> P-type auxiliary area length 0.8 μm P-type auxiliary region concentration <![CDATA[2.8×10 16 ]]> <![CDATA[cm -3 ]]> The length of the second N-type auxiliary region 1.5 μm The concentration of the second N-type auxiliary region <![CDATA[8×10 14 ]]> <![CDATA[cm -3 ]]> N-type drainage layer length 0.65 μm N-type drainage layer concentration <![CDATA[5×10 16 ]]> <![CDATA[cm -3 ]]> High K gate dielectric layer thickness 0.1 μm

[0061] like Figure 2 As shown, it is a schematic diagram of the longitudinal electric field distribution of the UMOS device provided by the present invention, the conventional SiC UMOS device and the conventional super junction SiC UMOS device; wherein, Conv SiC UMOS is a conventional SiC UMOS device, SiC SJ UMOS is a conventional super junction SiC UMOS device, Hk SiC BJSJ UMOS is a UMOS device provided by the present invention, the abscissa is the vertical length, the unit is μm, and the ordinate is the electric field distribution, the unit is MV·cm -1 ; As can be seen from the figure, the conventional SiC UMOS device has a relatively sharp electric field intensity in the drift region; the electric field intensity shown by the ordinary superjunction SiC UMOS device is reduced, so that the peak electric field is alleviated, indicating that the superjunction structure can effectively disperse and even the electric field and reduce the electric field concentration; and the UMOS device provided by the present invention has the most gentle electric field intensity distribution. While combining the advantages of the superjunction structure, the high-K gate insulating medium provides better electric field regulation, further reduces the electric field peak in the drift region, and shows the best electric field distribution performance. At the same time, when the thickness of the drift region is the substrate position, the electric field intensity distribution of the UMOS device provided by the present invention is also the lowest among the three structures. By adding a blocking junction and a variable doping structure, the potential change can be made to have a trapezoidal effect, the electric field change can be smoothed, and the withstand voltage performance of the UMOS device can be improved.

[0062] like Figure 3As shown, it is a schematic diagram of the longitudinal current density distribution of the UMOS device provided by the present invention, the conventional SiC UMOS device and the conventional super junction SiC UMOS device; wherein, Conv SiC UMOS is a conventional SiC UMOS device, SiC SJ UMOS is a conventional super junction SiC UMOS device, Hk SiC BJSJ UMOS is a UMOS device provided by the present invention, the abscissa is the vertical length, the unit is μm, and the ordinate is the electric field distribution, the unit is A·cm -2 ; As can be seen from the figure, the conventional SiC UMOS device exhibits a lower current density in the entire drift region; the ordinary superjunction SiC UMOS device FET shows a higher current density, especially in the trench area. The superjunction structure improves the uniformity of the electric field distribution through the staggered P columns and N columns, allowing a higher current density to flow; and the UMOS device provided by the present invention shows the highest current density in the entire drift region, and also shows the highest current density in the trench area. While combining the advantages of the superjunction structure, the present invention also uses a high-K gate insulating medium to modulate the electric field, further increasing the current density and improving the conductivity and efficiency of the device.

[0063] It can also be seen from the figure that when the thickness of the drift region is the substrate position and the P-type base region, the current density of the UMOS structure provided by the present invention is the highest, indicating that the addition of a blocking junction structure and the use of a high doping concentration in the present invention can significantly reduce the forward on-resistance, increase the current density, and improve the conduction characteristics.

[0064] It can be seen that the high-K gate dielectric of the structure of the present invention achieves the highest current density through more effective electric field modulation and current transmission control, demonstrating its advantages in optimizing current transmission and increasing power handling capability; at the same time, the auxiliary layer having a blocking junction and N-type variable doping characteristics can reduce the forward on-resistance, increase the current density, and enhance the conduction characteristics.

[0065] like Figure 4As shown, it is a breakdown voltage distribution curve diagram of the UMOS device provided by the present invention, the conventional SiC UMOS device and the ordinary super junction SiC UMOS device; wherein, Conv SiC UMOS is a conventional SiC UMOS device, SiC SJ UMOS is an ordinary super junction SiC UMOS device, Hk SiC BJSJ UMOS is a UMOS device provided by the present invention, the abscissa is the Drain Voltage, the unit is V, and the ordinate is the Drain Current, the unit is A; it can be seen from the figure that the breakdown voltage of the conventional SiC UMOS device is the lowest, and the breakdown voltages of the other two structures are improved. Specifically, it can be seen from the comparison that the breakdown voltage of the UMOS device provided by the present invention is increased by 23.4% relative to the conventional SiC UMOS device, and is increased by 27.8% relative to the ordinary super junction SiCUMOS device.

[0066] like Figure 5 As shown, it is an output characteristic curve diagram of the UMOS device provided by the present invention, the conventional SiC UMOS device and the conventional super junction SiC UMOS device; wherein, Conv SiC UMOS is a conventional SiC UMOS device, SiC SJ UMOS is a conventional super junction SiC UMOS device, Hk SiC BJSJ UMOS is a UMOS device provided by the present invention, the abscissa is the Drain Voltage, the unit is V, the ordinate is the Drain Current, the unit is A, V g is the gate voltage; it can be seen from the figure that the drain current increases with the increase of the gate voltage; for the same gate voltage, the UMOS device provided by the present invention has a maximum drain current, so the structure designed in this article can reduce the device characteristic on-resistance while maintaining a higher breakdown voltage. Specifically, it can be seen from the comparison that the UMOS device provided by the present invention is reduced by 31.1% and 14.6% compared with the conventional SiC UMOS device and the ordinary super junction SiC UMOS device, respectively.

[0067] like Figure 6 As shown, it is a reverse recovery characteristic curve of the UMOS device provided by the present invention, the conventional SiC UMOS device and the conventional super junction SiC UMOS device; wherein, Conv SiC UMOS is the conventional SiC UMOS device, SiC SJ UMOS is the conventional super junction SiC UMOS device, Hk SiC BJSJ UMOS is the UMOS device provided by the present invention, the abscissa is Time, the unit is S, and the ordinate is Current current density, the unit is A / cm 2 As can be seen from the figure, the conventional SiC UMOS device and the ordinary super junction SiC UMOS device have The value is large, and the voltage fluctuation is more severe; and the UMOS device provided by the present invention has The value is significantly reduced, and the voltage fluctuation is significantly slowed down; the softness coefficient S of the conventional SiC UMOS device is 0.35, the common super junction SiC UMOS device is 0.5, and the UMOS device provided by the present invention is 0.74. Compared with the previous structure, the softness coefficient of the present invention is increased by 69% and 48% respectively.

Claims

1. A silicon carbide superjunction UMOS having a high-K dielectric layer and a blocking junction, characterized in that: include: A drain electrode (1), an N-type substrate layer (2), a first N-type auxiliary region (3), a P-type auxiliary region (4), a second N-type auxiliary region (5), an N-column region (6), a first P-column region (7), a second P-column region (8), an N-type drain layer (9), a P-type base region (10), a P-type source region (11), an N-type source region (12), a high-K gate insulating dielectric layer (13), a thermal buffer layer (14), a polysilicon gate (15), a source electrode (16), and a P-type shielding layer (17); The N-type substrate layer (2) is located above the drain (1); the first N-type auxiliary region (3) is located above the N-type substrate layer (2); the P-type auxiliary region (4) is located above the first N-type auxiliary region (3); the second N-type auxiliary region (5) is located above the P-type auxiliary region (4); the N-column region (6) is located in the middle above the second N-type auxiliary region (5); the first P-column region (7) is located above the second N-type auxiliary region (5) and on both sides of the N-column region (6); the second P-column region (8) is located above the first P-column region (7); the N-type drain layer (9) is located above the second P-column region (8); the P-type base region (10) is located above the N-type drain layer (9); The P-type source region (11) and the N-type source region (12) are adjacent and both are located above the P-type base region (10); the P-type shielding layer (17) is located in a groove above the N-column region (6); the thermal buffer layer (14) is located above the P-type shielding layer (17) and is in contact with the N-type drain layer (9), the P-type base region (10) and the N-type source region (12); the high-K gate insulating dielectric layer (13) is located above the thermal buffer layer (14); the polysilicon gate (15) is embedded in the high-K gate insulating dielectric layer (13); and the source electrode (16) is located above the P-type source region (11), the N-type source region (12), the high-K gate insulating dielectric layer (13) and the thermal buffer layer (14) and is in direct contact with them; The drain (1), the N-type substrate layer (2), the first N-type auxiliary region (3), the P-type auxiliary region (4), the second N-type auxiliary region (5), the N-column region (6), the P-type base region (10), the N-type source region (12) and the source (16) constitute an electron flow region.

2. The silicon carbide superjunction UMOS with a high-K dielectric layer and a blocking junction according to claim 1, characterized in that: The doping concentrations in the first N-type auxiliary region (3) and the second N-type auxiliary region (5) are different, and both show a trend of continuously decreasing from bottom to top; The P-type auxiliary region (4) and the second N-type auxiliary region (5) form an auxiliary layer and form a blocking junction; The thickness of the P-type auxiliary region (4) is set to 0.65-0.8 μm, and is set to a high doping concentration.

3. The silicon carbide super junction UMOS with a high-K dielectric layer and a blocking junction according to claim 1, characterized in that: The N column region (6), the first P column region (7) and the second P column region (8) form a super junction structure; The first P column region (7) and the second P column region (8) form a P column region, which is used to assist the depletion of the N column region (6) and form a potential barrier in the N column region (6) to isolate the gate and the high electric field generated by the current flow in the N column region (6); The doping concentrations in the first P column region (7) and the second P column region (8) are different, and both show a trend of continuously decreasing from bottom to top.

4. The silicon carbide superjunction UMOS with a high-K dielectric layer and a blocking junction according to claim 1, characterized in that: The N-type drain layer (9) and the P-type base region (10) form a secondary blocking junction; The N-type drain layer (9) is set to have a high doping concentration to form a low-resistance path; The N-type drain layer (9) is located above the super junction structure composed of the N column region (6), the first P column region (7) and the second P column region (8), and is located below the P-type base region (10).

5. The silicon carbide super junction UMOS with a high-K dielectric layer and a blocking junction according to claim 1, characterized in that: The P-type source region (11) and the adjacent N-type source region (12) form a body diode; The N-type source region (12) is set to have a high doping concentration.

6. The silicon carbide super junction UMOS with a high-K dielectric layer and a blocking junction according to claim 1, characterized in that: The high-K gate insulating dielectric layer (13), the thermal buffer layer (14), the polysilicon gate (15) and the N column region (6) form a MIS metal-insulating layer-semiconductor structure; The high-K gate insulating dielectric layer (13) is provided with a high dielectric constant.

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