High crosstalk suppression circuit for high-voltage half-bridge gate drive circuit

Abstract

The invention discloses a high-crosstalk suppression circuit for a high-voltage half-bridge gate drive circuit. The high-crosstalk suppression circuit comprises a high-side crosstalk suppression circuit and a low-side crosstalk suppression circuit. On the basis of a traditional driving circuit, bridge arm crosstalk is suppressed by controlling on-off of an MOS tube, compared with a traditional suppression method, the on-off speed of a power tube is not affected, no extra power source is added, and cost is saved; the crosstalk suppression circuit and the delay circuit are simple in structure and remarkable in suppression effect, and complexity of the circuit is avoided.

Description

Technical Field

[0001] The present invention belongs to the technical field of half-bridge driving, and relates to a high-voltage half-bridge gate driving circuit in a high-voltage power integrated circuit, and in particular to a high crosstalk suppression circuit for a high-voltage half-bridge gate driving circuit. Background Art

[0002] Power switching devices are widely used in power electronics, automotive electronics, communication systems, and switching power supplies, and are the key to achieving power conversion and control. The third-generation semiconductor materials represented by SiC and GaN have the advantages of high breakdown electric field, high thermal conductivity, and high electron saturation rate. Power semiconductors based on this substrate have the characteristics of high voltage resistance, fast switching speed, low on-resistance, and good heat dissipation. They have received widespread attention in the fields of high voltage, high frequency, and high power density. However, as the switching speed increases, the di / dt and dv / dt in the switching process also increase. Due to the presence of parasitic inductance and parasitic capacitance in the switching loop, and the large di / dt and dv / dt, the voltage and current stress of the switch tube increases, which also brings more serious EMI problems. Especially in bridge circuit applications, such as bidirectional DC-DC converters, half-bridge and full-bridge converters, the high di / dt and dv / dt of power MOSFET during high-frequency switching will not only aggravate gate crosstalk due to parasitic parameters, but also generate drain voltage and current spikes and oscillations, deteriorating the turn-off performance. Positive crosstalk spikes exceeding the power tube turn-on threshold will cause bridge arm shoot-through, and negative crosstalk spikes below the gate-source minimum voltage threshold will damage the power tube.

[0003] like Figure 1 As shown in the figure, the principle of the bridge arm crosstalk problem in the bridge circuit is analyzed. When the lower tube is turned off, the upper tube enters the on state from the off state, and the voltage at VS suddenly changes, generating high dv / dt at the source and drain of the lower tube. The gate-drain parasitic capacitance Cgd_L and the drain-source parasitic capacitance Cds_L are quickly charged. The charging current flows through the gate-source parasitic capacitance Cgs_L, causing a positive voltage spike at the gate-source level. If this spike exceeds the threshold voltage of the MOSFET, it will cause the lower tube QL to be mis-conducted, causing the half-bridge circuit to be directly turned on, and damaging the MOSFET. When the lower tube is turned off, the upper tube changes from the on state to the off state, and the voltage at VS changes suddenly, generating high dv / dt at the source and drain of the lower tube. The gate-drain parasitic capacitance Cgd_L and the drain-source parasitic capacitance Cds_L gradually discharge, and the charging current flows through the gate-source parasitic capacitance Cgs_L, resulting in a negative voltage spike at the gate-source. If this spike exceeds the negative threshold voltage of the MOSFET, the lower tube will be broken down. From the simulation results of Figure 2, it can be seen that the positive crosstalk voltage can reach about 2V, and the negative crosstalk voltage is about -0.7V, which may cause the lower power tube to be turned on by mistake.

[0004] In order to reduce the impact of crosstalk, the traditional solution is to connect a capacitor larger than the parasitic capacitance Cgs of the power MOSFET in parallel to the gate source of the power MOSFET. Figure 3 As shown in the figure, during the crosstalk generation process, the increased gate capacitance bypasses the Miller current generated, which can effectively suppress the voltage spike at the gate and source of the MOSFET. The parallel external capacitor C1 can share part of the Miller current for the gate-source parasitic capacitance Cgs and reduce the voltage peak generated by the gate and source. However, this method will reduce the switching speed during the switching process, increase the switching time, and thus increase the switching loss. Summary of the invention

[0005] In order to better suppress the bridge arm crosstalk problem, the present invention provides a high crosstalk suppression circuit for a high-voltage half-bridge gate drive circuit. The present invention can effectively suppress the crosstalk problem without affecting the switching speed of the circuit, thereby improving the reliability of the circuit.

[0006] A high crosstalk suppression circuit for a high-voltage half-bridge gate drive circuit comprises a high-side crosstalk suppression circuit and a low-side crosstalk suppression circuit.

[0007] The high-side crosstalk suppression circuit includes a high-side delay circuit and a high-side second NMOS tube Q H The high-side delay circuit input end is connected to the high-side drive output end of the high-voltage half-bridge gate drive circuit, and the high-side delay circuit output end is connected to the high-side second NMOS tube Q H The gate terminal of the high-side second NMOS tube Q H The drain end is connected to the gate end of the high-side power tube model, and the high-side second NMOS tube Q H The source end and substrate end of the device are connected to the high-side floating ground VS;

[0008] Furthermore, the high-side delay circuit includes a high-side first PMOS transistor MP_H, a high-side first NMOS transistor MN_H and a high-side resistor R H The gate end of the high-side first PMOS tube MP_H is connected to the high-side drive output end of the high-voltage half-bridge gate drive circuit, and the drain end of the high-side first PMOS tube MP_H is connected to the high-side resistor R H The source and substrate ends of the high-side first PMOS tube MP_H are connected to the high-side floating power supply VB, the gate end of the high-side first NMOS tube MN_H is connected to the high-side drive output end of the high-voltage half-bridge gate drive circuit, and the drain end of the high-side first NMOS tube MN_H is connected to the high-side second NMOS tube Q H The gate end of the high-side first NMOS tube MN_H is connected, the source end and the substrate end of the high-side first NMOS tube MN_H are connected to the high-side floating ground VS, and the high-side resistor R HThe other end is connected to the drain end of the high-side first NMOS tube MN_H and the high-side second NMOS tube Q H The gate terminal is connected;

[0009] The low-side crosstalk suppression circuit includes a low-side delay circuit and a low-side fourth NMOS tube Q L The input end of the low-side delay circuit is connected to the low-side drive output end of the high-voltage half-bridge gate drive circuit, and the output end of the low-side delay circuit is connected to the low-side fourth NMOS tube Q L The gate terminal of the low-side fourth NMOS tube Q L The drain end is connected to the gate end of the low-side power tube model, and the low-side fourth NMOS tube Q L The source end and substrate end of the device are connected to the low-side power ground COM;

[0010] Furthermore, the low-side delay circuit includes a low-side second PMOS transistor MP_L, a low-side third NMOS transistor MN_L and a low-side resistor R L The gate end of the second low-side PMOS tube MP_L is connected to the low-side drive output end of the high-voltage half-bridge gate drive circuit, and the drain end of the second low-side PMOS tube MP_L is connected to the low-side resistor R L The source and substrate ends of the low-side second PMOS tube MP_L are connected to the low-side power supply VCC, the gate end of the low-side third NMOS tube MN_L is connected to the low-side drive output end of the high-voltage half-bridge gate drive circuit, and the drain end of the low-side third NMOS tube MN_L is connected to the low-side fourth NMOS tube Q L The gate end of the low-side third NMOS tube MN_L is connected, the source end and the substrate end of the low-side third NMOS tube MN_L are connected to the low-side power supply ground COM, and the low-side resistor R L The other end is connected to the drain end of the third low-side NMOS tube MN_L and the fourth low-side NMOS tube Q L The gate terminal is connected.

[0011] The beneficial effects of the present invention are as follows:

[0012] The present invention provides a high crosstalk suppression circuit for a high-voltage half-bridge gate drive circuit. On the basis of a traditional drive circuit, the bridge arm crosstalk is suppressed by controlling the on and off of a MOS tube. Compared with the traditional suppression method, the present invention does not affect the switching speed of the power tube, and does not add an additional power supply, thus saving costs. The crosstalk suppression circuit and the delay circuit have simple structures, significant suppression effects, and avoid the complexity of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 Analysis of the crosstalk mechanism of bridge circuit;

[0014] Figure 2 (a) Forward crosstalk simulation waveform;

[0015] Figure 2(b) Reverse crosstalk simulation waveform;

[0016] Figure 3 Gate-source parallel external capacitor suppression method;

[0017] Figure 4 A simulation model of a high crosstalk suppression circuit according to an embodiment of the present invention;

[0018] Figure 5 Simulation waveform of the high crosstalk suppression circuit according to the embodiment of the present invention. DETAILED DESCRIPTION

[0019] The technical solution of the present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0020] like Figure 4 As shown, the present invention provides a high crosstalk suppression circuit for a high-voltage half-bridge gate drive circuit, comprising a high-side crosstalk suppression circuit and a low-side crosstalk suppression circuit.

[0021] The high-side crosstalk suppression circuit includes a high-side delay circuit and a high-side second NMOS tube Q H The high-side delay circuit input end is connected to the high-side drive output end of the high-voltage half-bridge gate drive circuit, and the high-side delay circuit output end is connected to the high-side second NMOS tube Q H The gate terminal of the high-side second NMOS tube Q H The drain end is connected to the gate end of the high-side power tube model, and the high-side second NMOS tube Q H The source end and substrate end of the device are connected to the high-side floating ground VS;

[0022] The high-side delay circuit includes a high-side first PMOS transistor MP_H, a high-side first NMOS transistor MN_H and a high-side resistor R H The gate end of the high-side first PMOS tube MP_H is connected to the high-side drive output end of the high-voltage half-bridge gate drive circuit, and the drain end of the high-side first PMOS tube MP_H is connected to the high-side resistor R H The source and substrate ends of the high-side first PMOS tube MP_H are connected to the high-side floating power supply VB, the gate end of the high-side first NMOS tube MN_H is connected to the high-side drive output end of the high-voltage half-bridge gate drive circuit, and the drain end of the high-side first NMOS tube MN_H is connected to the high-side second NMOS tube Q H The gate end of the high-side first NMOS tube MN_H is connected, the source end and the substrate end of the high-side first NMOS tube MN_H are connected to the high-side floating ground VS, and the high-side resistor R H The other end is connected to the drain end of the high-side first NMOS tube MN_H and the high-side second NMOS tube Q H The gate terminal is connected;

[0023] The low-side crosstalk suppression circuit includes a low-side delay circuit and a low-side fourth NMOS tube Q L The input end of the low-side delay circuit is connected to the low-side drive output end of the high-voltage half-bridge gate drive circuit, and the output end of the low-side delay circuit is connected to the low-side fourth NMOS tube Q L The gate terminal of the low-side fourth NMOS tube Q L The drain end is connected to the gate end of the low-side power tube model, and the low-side fourth NMOS tube Q L The source end and substrate end of the device are connected to the low-side power ground COM;

[0024] The low-side delay circuit includes a low-side second PMOS tube MP_L, a low-side third NMOS tube MN_L and a low-side resistor R L The gate end of the second low-side PMOS tube MP_L is connected to the low-side drive output end of the high-voltage half-bridge gate drive circuit, and the drain end of the second low-side PMOS tube MP_L is connected to the low-side resistor R L The source and substrate ends of the low-side second PMOS tube MP_L are connected to the low-side power supply VCC, the gate end of the low-side third NMOS tube MN_L is connected to the low-side drive output end of the high-voltage half-bridge gate drive circuit, and the drain end of the low-side third NMOS tube MN_L is connected to the low-side fourth NMOS tube Q L The gate end of the low-side third NMOS tube MN_L is connected, the source end and the substrate end of the low-side third NMOS tube MN_L are connected to the low-side power supply ground COM, and the low-side resistor R L The other end is connected to the drain end of the third low-side NMOS tube MN_L and the fourth low-side NMOS tube Q L The gate terminal is connected.

[0025] Its working principle is:

[0026] Low-side crosstalk suppression circuit section:

[0027] The low-side second PMOS tube MP_L, the low-side third NMOS tube MN_L and the low-side resistor R L The low-side delay circuit composed of the low-side resistor R L Different resistance values ​​produce the required delay time. When the low-side drive output of the high-voltage half-bridge gate drive circuit is at a low level, the high-side drive output changes from a low level to a high level. At this time, the low-side power tube MOS_L of the low-side power tube characteristic model is in the off state, and the high-side power tube MOS_H of the high-side power tube characteristic model changes from the off state to the on state. Before the high-side power tube MOS_H is turned on, the drain-source voltage V DS When the high-side power tube MOS_H is turned on, the drain-source voltage V DSWhen the voltage rises to VS, the Miller current generated by the rapid change of the source-drain voltage of the low-side power tube MOS_L passes through the low-side fourth NMOS tube Q which is turned on after a delay. L Discharge to the ground, thereby avoiding excessive forward crosstalk voltage on the gate of the low-side power tube MOS_L and avoiding the bridge arm direct-through problem.

[0028] When the low-side drive output of the high-voltage half-bridge gate drive circuit is at a low level, and the high-side drive output changes from a high level to a low level, the low-side power tube MOS_L of the low-side power tube characteristic model is in the off state, and the high-side power tube MOS_H of the high-side power tube characteristic model changes from the on state to the off state. Before the high-side power tube MOS_H is turned off, the drain-source voltage V DS Close to VS. When the high-side power tube MOS_H is turned off, the drain-source voltage V DS The rapid change of the source-drain voltage of the low-side power tube MOS_L generates a Miller current that passes through the low-side fourth NMOS tube Q which is turned on after a delay. L Discharge to ground to avoid excessive negative crosstalk voltage on the gate of the low-side power tube MOS_L and to avoid exceeding the maximum gate negative voltage allowed by the switching tube device.

[0029] High-side crosstalk suppression circuit section:

[0030] The high-side first PMOS transistor MP_H, the high-side first NMOS transistor MN_H and the high-side resistor R H The high-side delay circuit composed of the high-side resistor R L Different resistance values ​​produce the required delay time. When the high-side drive output of the high-voltage half-bridge gate drive circuit is low, the low-side drive output changes from low to high. At this time, the high-side power tube MOS_H of the high-side power tube characteristic model is in the off state, and the low-side power tube MOS_L of the low-side power tube characteristic model changes from the off state to the on state. Before the low-side power tube characteristic model is turned on, the drain-source voltage V DS Close to VS. When the low-side power tube MOS_L is turned on, the drain-source voltage V DS The voltage drops to zero, and the Miller current generated by the rapid change of the source-drain voltage of the high-side power tube MOS_H passes through the high-side second NMOS tube Q which is turned on after a delay. H Discharge to the ground, thereby avoiding excessive forward crosstalk voltage on the gate of the high-side power tube MOS_H and avoiding the bridge arm direct-through problem.

[0031] When the high-side drive output of the high-voltage half-bridge gate drive circuit is at a low level, the low-side drive output changes from a high level to a low level. At this time, the high-side power tube MOS_H of the high-side power tube characteristic model is in the off state, and the low-side power tube MOS_L of the low-side power tube characteristic model changes from the on state to the off state. Before the low-side power tube MOS_L is turned off, the drain-source voltage V DS When the low-side power tube MOS_L is turned off, the drain-source voltage V DS When the voltage rises to VS, the Miller current generated by the rapid change of the source-drain voltage of the high-side power tube MOS_H passes through the high-side second NMOS tube Q which is turned on after a delay. H Discharge to ground to avoid excessive negative crosstalk voltage on the gate of the high-side power tube MOS_H and to avoid exceeding the maximum gate negative voltage allowed by the switching tube device.

[0032] Based on the Virtuoso software simulation platform, a pulse test was performed on the high crosstalk suppression circuit of the present invention, and the simulation model constructed is as follows: Figure 4 As shown in the figure, in the high-side crosstalk suppression circuit, the input terminal is connected to a square wave signal as the high-side drive output of the high-voltage half-bridge gate drive circuit; in the low-side crosstalk suppression circuit, the input terminal is connected to a square wave signal with a phase opposite to that of the input terminal of the high-side crosstalk suppression circuit as the low-side drive output of the high-voltage half-bridge gate drive circuit. The high and low test power tube models both use SiC MOSFET power tubes with a withstand voltage of 200V. The high and low test power tube models include the Miller capacitor (gate-drain capacitor) C connected to the gate and drain terminals of the MOSFET. gd , the gate-source capacitance C connected to the gate and source of the MOSFET gs , the drain-source capacitor C connected to the drain and source of the MOSFET ds And the body diode Dz connected to the drain and source terminals of the MOSFET.

[0033] Figure 5 The following is the working waveform of this design when driving a 100V load. In the period from 3μs to 3.6μs, the low-side power tube MOS_L is in the off state. At the moment when the high-side power tube MOS_H is turned on, the drain-source voltage V DS Increase the Miller capacitance C of the low-side power tube MOS_L gd_L and drain-source capacitance C ds_L Charging, the Miller current generated by crosstalk flows through the resistor R g_L The low-side delay circuit will make the fourth NMOS tube Q L It is turned on, providing a discharge path for the Miller current, effectively suppressing the gate forward crosstalk voltage peak of the low-side power tube;

[0034] In the period from 13μs to 13.6μs, the low-side power tube MOS_L is in the off state. At the moment when the high-side power tube MOS_H is turned off, the drain-source voltage V DS The Miller capacitance C of the low-side power tube MOS_L gd_L Discharge, generate reverse Miller current, the low-side power tube MOS_L will generate negative crosstalk voltage, although it will not cause shoot-through problem, but it may exceed the maximum negative gate bias voltage allowed by the switch tube device, and in severe cases, it will cause the switch tube to fail. At this time, the Miller current flows through the resistor R g_L The low-side delay circuit will make the fourth NMOS tube Q L It is turned on, which also provides a discharge path for the Miller current and suppresses the negative gate voltage peak of the low-side power tube MOS_L.

[0035] This experiment focuses on the situation when the low-side power tube is turned off and the high-side power tube is turned on and off. Similarly, the same test conditions can be used to test the situation when the high-side power tube is turned off and the low-side power tube is turned on and off. Theoretically, the two will produce the same results.

[0036] The above contents are further detailed descriptions of the present invention in combination with specific / preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, they can also make several substitutions or modifications to these described embodiments without departing from the concept of the present invention, and these substitutions or modifications should be regarded as belonging to the protection scope of the present invention.

[0037] Parts of the present invention that are not described in detail belong to the well-known technologies of those skilled in the art.

Claims

1. A high crosstalk suppression circuit for a high voltage half-bridge gate drive circuit, characterized in that: Including a high-side crosstalk suppression circuit and a low-side crosstalk suppression circuit; The high-side crosstalk suppression circuit includes a high-side delay circuit and a high-side second NMOS tube Q H The high-side delay circuit input end is connected to the high-side drive output end of the high-voltage half-bridge gate drive circuit, and the high-side delay circuit output end is connected to the high-side second NMOS tube Q H The gate terminal of the high-side second NMOS tube Q H The drain end is connected to the gate end of the high-side power tube model, and the high-side second NMOS tube Q H The source end and substrate end of the device are connected to the high-side floating ground VS; The low-side crosstalk suppression circuit includes a low-side delay circuit and a low-side fourth NMOS tube Q L The input end of the low-side delay circuit is connected to the low-side drive output end of the high-voltage half-bridge gate drive circuit, and the output end of the low-side delay circuit is connected to the low-side fourth NMOS tube Q L The gate terminal of the low-side fourth NMOS tube Q L The drain end is connected to the gate end of the low-side power tube model, and the low-side fourth NMOS tube Q L The source end and substrate end are connected to the low-side power ground COM.

2. The high crosstalk suppression circuit for a high voltage half-bridge gate drive circuit according to claim 1, characterized in that: The high-side delay circuit includes a high-side first PMOS transistor MP_H, a high-side first NMOS transistor MN_H and a high-side resistor R H The gate end of the high-side first PMOS tube MP_H is connected to the high-side drive output end of the high-voltage half-bridge gate drive circuit, and the drain end of the high-side first PMOS tube MP_H is connected to the high-side resistor R H The source and substrate ends of the high-side first PMOS tube MP_H are connected to the high-side floating power supply VB, the gate end of the high-side first NMOS tube MN_H is connected to the high-side drive output end of the high-voltage half-bridge gate drive circuit, and the drain end of the high-side first NMOS tube MN_H is connected to the high-side second NMOS tube Q H The gate end of the high-side first NMOS tube MN_H is connected, the source end and the substrate end of the high-side first NMOS tube MN_H are connected to the high-side floating ground VS, and the high-side resistor R H The other end is connected to the drain end of the high-side first NMOS tube MN_H and the high-side second NMOS tube Q H The gate terminal is connected.

3. The high crosstalk suppression circuit for a high voltage half-bridge gate drive circuit according to claim 1, characterized in that: The low-side delay circuit includes a low-side second PMOS tube MP_L, a low-side third NMOS tube MN_L and a low-side resistor R L The gate end of the second low-side PMOS tube MP_L is connected to the low-side drive output end of the high-voltage half-bridge gate drive circuit, and the drain end of the second low-side PMOS tube MP_L is connected to the low-side resistor R L The source and substrate ends of the low-side second PMOS tube MP_L are connected to the low-side power supply VCC, the gate end of the low-side third NMOS tube MN_L is connected to the low-side drive output end of the high-voltage half-bridge gate drive circuit, and the drain end of the low-side third NMOS tube MN_L is connected to the low-side fourth NMOS tube Q L The gate end of the low-side third NMOS tube MN_L is connected, the source end and the substrate end of the low-side third NMOS tube MN_L are connected to the low-side power supply ground COM, and the low-side resistor R L The other end is connected to the drain end of the third low-side NMOS tube MN_L and the fourth low-side NMOS tube Q L The gate terminal is connected.

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