Display device

Abstract

A display device includes: a substrate including a display area and a non-display area; a transistor positioned in the display area; a light emitting element electrically connected to the transistor; and a common voltage transmission line positioned in the non-display area and including a recess; first and second dams positioned in the non-display area and spaced apart from each other, and the first and second dams surrounding at least a portion of the display area; and a covering organic layer overlapping an edge of the recess, where the edge of the recess is positioned between the first dam and the second dam.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and all benefits arising from Korean Patent Application No. 10-2023-0074706, filed on Jun. 12, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates to a display device, and more particularly, to a display device configured to prevent moisture penetration. Background Art

[0004] The display device is a device that displays an image, and includes a liquid crystal display device (LCD), a light emitting diode (LED) display device, and the like.

[0005] Such display devices are used in various electronic devices such as mobile phones, navigation devices, digital cameras, electronic books, portable game machines, and terminals.

[0006] A light-emitting display device, which is a self-emitting display device, does not require a separate light source, so it can be driven with a low voltage, can be configured to be light and thin, and has high-quality characteristics such as a wide viewing angle, high contrast, and fast response speed, and has attracted much attention as a display device. Summary of the invention

[0007] The present embodiment includes a display device having an enhanced function for preventing penetration of moisture or oxygen from the outside.

[0008] A display device according to an embodiment includes: a substrate including a display area and a non-display area; a transistor positioned in the display area; a light emitting element electrically connected to the transistor; a common voltage transmission line positioned in the non-display area and including a recess; a first dam and a second dam positioned in the non-display area and spaced apart from each other, wherein the first dam and the second dam surround at least a portion of the display area; and a covering organic layer overlapping an edge of the recess, wherein the edge of the recess is positioned between the first dam and the second dam.

[0009] In an embodiment, the common voltage transmission line may include a first region having a first width and a second region having a second width, wherein the first width may be greater than the second width.

[0010] In an embodiment, the second region may be more concave in shape than the first region.

[0011] In an embodiment, the common voltage transmission line includes a first edge and a second edge, wherein the first edge is positioned adjacent to the first dam, the second edge is positioned adjacent to the second dam, and at least a portion of the second edge may overlap with the second dam.

[0012] In an embodiment, the second edge may include a protruding portion extending toward the first edge, wherein the protruding portion may overlap the capping organic layer.

[0013] In an embodiment, a display area includes: a first semiconductor layer on the substrate; a first gate conductive layer on the first semiconductor layer; a second gate conductive layer on the first gate conductive layer; a second semiconductor layer positioned on the second gate conductive layer; a third gate conductive layer positioned on the second semiconductor layer; a first data conductive layer positioned on the third gate conductive layer; and a layer positioned on the first data conductive layer, wherein the layer positioned on the first data conductive layer may include a second data conductive layer positioned on the first data conductive layer and a first electrode positioned on the second data conductive layer.

[0014] In an embodiment, the common voltage transmission line may include at least one of a first layer positioned on the same layer as the first data conductive layer and a second layer positioned on the same layer as the second data conductive layer.

[0015] In an embodiment, the display device may further include an alignment key overlapping at least a portion of the recess in a plane.

[0016] In an embodiment, the alignment key may be positioned on the same layer as the third gate conductive layer.

[0017] In an embodiment, the display device may also include: a first gate insulating layer on the first semiconductor layer; a second gate insulating layer on the first gate conductive layer; a first interlayer insulating layer on the second gate conductive layer; a third gate insulating layer on the second semiconductor layer; a second interlayer insulating layer on the third gate conductive layer; a first organic layer on the first data conductive layer; a second organic layer and a third organic layer; and a pixel defining layer and a spacer positioned on the first electrode.

[0018] In an embodiment, the capping organic layer may include the same material as at least one of the second organic layer and the third organic layer.

[0019] In embodiments, the capping organic layer may be connected to the second dam.

[0020] In embodiments, the first dam and the capping organic layer may be spaced apart from each other.

[0021] In an embodiment, the capping organic layer may have a planar shape protruding toward the first dam.

[0022] A display device according to an embodiment includes: a substrate including a display area and a non-display area; a transistor positioned in the display area; a light emitting element electrically connected to the transistor; a common voltage transmission line positioned in the non-display area; a first dam and a second dam positioned in the display area, the first dam and the second dam surrounding at least a portion of the display area, and the first dam and the second dam being spaced apart from each other; a covering organic layer protruding from a portion of the second dam, and the covering organic layer being spaced apart from the first dam, wherein the organic covering layer covers at least a portion of an edge of the common voltage transmission line.

[0023] In an embodiment, the common voltage transmission line may include a first edge adjacent to the first dam and a second edge adjacent to the second dam, wherein the second edge may include a portion protruding toward the first dam.

[0024] In an embodiment, the cover organic layer may cover a protruding portion of the second edge.

[0025] In an embodiment, at least a portion of the second edge may overlap the second dam.

[0026] In an embodiment, the common voltage transmission line may include a first region having a first width and a second region having a second width, wherein the first width may be greater than the second width.

[0027] In an embodiment, the display device may further include an alignment key overlapping at least a portion of the second dam.

[0028] According to the embodiment, it is possible to prevent moisture or oxygen from the outside from penetrating into the display device by blocking the connection between adjacent organic layers in the non-display area.

[0029] In an embodiment, a display device having improved reliability may be provided by preventing moisture penetration. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other advantages and features of the present invention will become more apparent by describing the embodiments of the present invention in further detail with reference to the accompanying drawings.

[0031] Figure 1 is an exploded perspective view of a display device according to an embodiment.

[0032] Figure 2 is a schematic top plan view of a display panel according to an embodiment.

[0033] Figure 3 is a circuit diagram of one pixel of a display panel according to an embodiment.

[0034] Figure 4 is a schematic cross-sectional view of a display panel according to an embodiment.

[0035] Figure 5 According to the embodiment Figure 2 An enlarged top plan view of Area A.

[0036] Figure 6 According to the embodiment along Figure 5 A cross-sectional view taken along line AA'.

[0037] Figure 7 According to the embodiment along Figure 5 A cross-sectional view taken along line BB'. DETAILED DESCRIPTION

[0038] Hereinafter, various embodiments will be described in detail with reference to the accompanying drawings so that those having ordinary skill in the art can easily implement the present invention.

[0039] The present invention may be embodied in many different forms and is not limited to the embodiments set forth herein.

[0040] In order to clearly describe the present invention, parts irrelevant to the present description are omitted, and the same or similar reference numerals are assigned to the same or similar constituent elements throughout the specification. In the drawings and text of the present disclosure, reference numerals indicating elements in the singular form may also be used to refer to multiple singular elements.

[0041] Furthermore, since the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of explanation, the present invention is not necessarily limited to the size and thickness of each component shown.

[0042] In the drawings, the thickness is shown exaggeratedly in order to clearly show each layer and region.

[0043] Also, in the drawings, the thicknesses of some layers and regions are exaggerated for convenience of explanation.

[0044] In addition, when a part (such as a layer, film, region or plate) is referred to as being related to another part (such as "above" or "on" the other part), this includes not only the case where the part is "directly on" the other part, but also the case where another part exists between the part and the other part.

[0045] In contrast, when a part is referred to as being related to another part (such as being "directly on" another part), this means that there are no other parts between the part and the other part.

[0046] Furthermore, “above” or “on” a reference portion means positioned above or below the reference portion, and does not necessarily mean “above” or “on” the reference portion in the opposite direction to the gravity direction.

[0047] In addition, throughout the specification, unless otherwise stated, when a specific part is referred to as "comprising", it means that it may further include other components, rather than excluding the other components.

[0048] In addition, throughout the specification, when reference is made to a “plan view”, this means when a target portion is viewed from above, and when reference is made to a “cross-sectional view”, this means a vertically cut cross section in which the target portion is viewed from the side.

[0049] It will be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, areas, layers and / or parts, these elements, components, areas, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, area, layer or part from another element, component, area, layer or part. Therefore, without departing from the teachings herein, the "first element", "first component", "first area", "first layer" or "first part" discussed below may be named "second element", "second component", "second area", "second layer" or "second part".

[0050] The terms used herein are only used for the purpose of describing specific embodiments, and are not intended to be restrictive. Unless the context clearly indicates otherwise, "one (person)", "a kind of", "the (said)" and "at least one (person / kind)" as used herein do not indicate the limitation of quantity, and are intended to include both the singular and the plural. For example, unless the context clearly indicates otherwise, "an element" has the same meaning as "at least one element". "At least one (person / kind)" is not interpreted as limiting "one (person)" or "a kind". "Or" means "and / or". As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items. In addition, unless explicitly described to the contrary, the word "include" and variations such as "include" or "have" will be understood to mean to include the elements stated, but do not exclude any other elements.

[0051] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0052] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will be further understood that, unless explicitly defined as such herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their context in the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense.

[0053] Embodiments are described herein with reference to cross-sectional views as schematic diagrams of idealized embodiments. Thus, variations in the shapes of the diagrams due to, for example, manufacturing techniques and / or tolerances are anticipated. Therefore, the embodiments described herein should not be construed as being limited to the specific shapes of the zones shown herein, but will include deviations in shape due to, for example, manufacturing. For example, a zone shown or described as flat may typically have rough and / or nonlinear features. In addition, the sharp corners shown may be rounded. Therefore, the zones shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the zones, and are not intended to limit the scope of the claims.

[0054] In the following, reference will be made to Figure 1 A schematic structure of a display device is described.

[0055] Figure 1 is an exploded perspective view of a display device according to an embodiment.

[0056] Reference Figure 1 The display device 1000 according to the embodiment is a device for displaying video (e.g., dynamic images or static images), and can be used as a display screen for various products such as mobile phones, smart phones, tablet personal computers, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigators, ultra mobile PCs (UMPCs), televisions, notebook computers, monitors, billboards, and Internet of Things (IoT) devices.

[0057] In addition, the display apparatus 1000 according to the embodiment may be used for wearable devices such as a smart watch, a watch phone, a glasses type display, and a head mounted display (HMD).

[0058] In addition, the display device 1000 according to the embodiment can be used in a car as a dashboard of the car, a central information display (CID) placed on the central dashboard or instrument panel of the car, an indoor rearview mirror display replacing the side mirror of the car, and a display placed on the back of the front seat for rear seat entertainment.

[0059] In the embodiments, for the convenience of explanation, Figure 1 It is shown that the display device 1000 is used as a smartphone.

[0060] In an embodiment, the display device 1000 may display an image toward a third direction DR3 on a display surface parallel to both the first direction DR1 and the second direction DR2 .

[0061] In an embodiment, a display surface displaying a video may correspond to a front surface of the display device 1000 , and may correspond to a front surface of the cover window WU.

[0062] In an embodiment, a video may include not only dynamic images but also static images.

[0063] In an embodiment, a front surface or an upper surface and a rear surface or a lower surface of each member are defined based on a direction in which an image is displayed.

[0064] In an embodiment, the front surface and the rear surface are opposite to each other in the third direction DR3, and a normal direction of each of the front surface and the rear surface may be parallel to the third direction DR3.

[0065] In an embodiment, a spacing distance between the front surface and the rear surface in the third direction DR3 may correspond to a thickness of the display panel in the third direction DR3.

[0066] In an embodiment, the display apparatus 1000 according to the embodiment may detect an input of an authorized user from the outside.

[0067] In an embodiment, the user's input may include various types of external inputs, such as a part of the user's body, light, heat, or pressure.

[0068] In embodiments, user input may be provided in various forms.

[0069] Furthermore, in an embodiment, the display apparatus 1000 may detect a user's input applied to a side or rear surface of the display apparatus 1000 depending on the structure of the display apparatus 1000 .

[0070] In an embodiment, the display device 1000 may include a cover window WU, a housing HM, a display panel DP, and an optical device ES.

[0071] In an embodiment, the cover window WU and the housing HM may be combined to form the appearance of the display device 1000 .

[0072] In an embodiment, the cover window WU may include an insulating panel.

[0073] For example, in an embodiment, the cover window WU may be made of glass, plastic, or a combination thereof.

[0074] In an embodiment, the front surface of the cover window WU may define the front surface of the display device 1000 .

[0075] In an embodiment, the transmission area TA may be an optically transparent area.

[0076] For example, in an embodiment, the transmission area TA may be a region having a visible light transmittance greater than about 90%.

[0077] In an embodiment, the blocking area BA may define the shape of the transmission area TA.

[0078] In an embodiment, the blocking area BA is located adjacent to the transmission area TA and may surround the transmission area TA.

[0079] In an embodiment, the blocking area BA may be a region having relatively low light transmittance compared to the transmitting area TA.

[0080] In an embodiment, the blocking area BA may include an opaque material that blocks light.

[0081] In an embodiment, the blocking area BA may have a specific color.

[0082] In an embodiment, the blocking area BA may be defined by a bezel layer separated from the transparent substrate defining the transmission area TA, or the blocking area BA may be defined by an ink layer embedded or dyed into the transparent substrate.

[0083] In an embodiment, the display panel DP may include a front surface including a display area DA and a non-display area PA.

[0084] In an embodiment, the display area DA may be a region where pixels operate according to electrical signals and emit light.

[0085] In an embodiment, the non-display area PA of the display panel DP may include a driving part (or a driving unit) 50 .

[0086] In an embodiment, the display area DA is a region where an image is displayed, including pixels, and at the same time, the touch sensor may be positioned on the pixels in the third direction DR3, and the display area DA may be a region where an external input is detected.

[0087] In an embodiment, the transmission area TA of the cover window WU may at least partially overlap the display area DA of the display panel DP.

[0088] For example, in an embodiment, the transmission area TA may overlap with the front surface of the display area DA, or may overlap with at least a portion of the display area DA.

[0089] Therefore, in an embodiment, a user may observe an image through the transmissive area TA, or provide an external input based on the image.

[0090] However, the present invention is not limited thereto.

[0091] For example, in an embodiment, within the display area DA, a region where an image is displayed and a region where an external input is sensed may be separated from each other.

[0092] In an embodiment, the non-display area PA of the display panel DP may at least partially overlap the blocking area BA of the cover window WU.

[0093] In an embodiment, the non-display area PA may be an area covered by the blocking area BA.

[0094] In an embodiment, the non-display area PA is positioned adjacent to the display area DA, and may surround the display area DA.

[0095] In an embodiment, the non-display area PA is an area where an image is not displayed, and may be an area where a driving circuit or wiring for operating the display area DA is arranged.

[0096] In an embodiment, the non-display area PA may include a first non-display area PA1 positioned outside the display area DA and a second non-display area PA2 including the driving part 50 , the connection wiring, and the bending area.

[0097] In an embodiment, the first non-display area PA1 is positioned at three sides of the display area DA, and the second non-display area PA2 is positioned at the remaining one side of the display area DA.

[0098] In an embodiment, the display panel DP may be assembled in a flat state such that the display area DA and the non-display area PA face the cover window WU.

[0099] However, the present invention is not limited thereto.

[0100] In an embodiment, a portion of the non-display area PA of the display panel DP may be bent.

[0101] In an embodiment, a portion of the non-display area PA is directed toward the back of the display device 1000, which can reduce the visible blocking area BA at the front of the display device 1000, and Figure 1In the embodiment, the second non-display area PA2 may be assembled after being bent to be positioned at the back of the display area DA.

[0102] Furthermore, in an embodiment, the display panel DP may include an assembly area EA, and specifically, may include a first assembly area EA1 and a second assembly area EA2.

[0103] In an embodiment, the first component area EA1 and the second component area EA2 may be at least partially surrounded by the display area DA.

[0104] In the embodiment, the first component area EA1 and the second component area EA2 are described as being separated from each other, but the first component area EA1 and the second component area EA2 are not limited thereto and may be at least partially connected.

[0105] In embodiments, the first component area EA1 and the second component area EA2 may be areas where components using infrared light, visible light, and / or sound are positioned below.

[0106] In an embodiment, the display area DA is formed of a plurality of light emitting diodes and a plurality of pixel circuits that generate and transmit a light emitting current to each of the light emitting diodes.

[0107] Here, according to an embodiment, a single light emitting diode and a single pixel circuit portion corresponding thereto are referred to as a pixel PX.

[0108] In the embodiment, in the display area DA, one pixel circuit unit and one light emitting diode are formed in a one-to-one correspondence.

[0109] In an embodiment, the first component area EA1 may include a transmission portion through which light and / or sound may pass and a display portion including a plurality of pixels.

[0110] In an embodiment, the transmissive part is positioned between adjacent pixels and consists of a layer through which light and / or sound can pass.

[0111] In embodiments, the transmissive portion may be positioned between adjacent pixels, and depending on embodiments, a layer that does not transmit light, such as a light blocking member, may overlap the first assembly area EA1.

[0112] In an embodiment, the number of pixels per unit area (also referred to as resolution of pixels) of pixels included in the display area DA (also referred to as regular pixels) and pixels included in the first component area EA1 (also referred to as first component pixels) may be the same.

[0113] In an embodiment, the second component area EA2 includes an area (also referred to as a transmissive area) made of a transparent layer to allow light to pass through the second component area EA2, wherein a layer (e.g., a pixel defining layer and / or a light blocking member) may include an opening that overlaps a position corresponding to the second component area EA2 so as not to block light.

[0114] In an embodiment, the number of pixels per unit area of ​​pixels (also referred to as second component pixels) included in the second component area EA2 may be smaller than the number of pixels per unit area of ​​regular pixels included in the display area DA.

[0115] Therefore, in an embodiment, the resolution of the second component pixels may be lower than the resolution of the regular pixels.

[0116] In an embodiment, the driving unit 50 may be mounted on the display panel DP in the second non-display area PA2, and may be mounted on the bending unit or positioned at both sides of the bending unit.

[0117] In an embodiment, the driving unit 50 may be provided in the form of a chip.

[0118] In an embodiment, the driving unit 50 is electrically connected to the display area DA, and may transmit an electrical signal to the display area DA.

[0119] For example, in an embodiment, the driving unit 50 may provide a data signal to the pixels PX positioned in the display area DA.

[0120] Alternatively, in an embodiment, the driving unit 50 may include one touch driving circuit and may be electrically connected to a touch sensor positioned in the display area DA.

[0121] In an embodiment, the driving unit 50 may be designed to include various circuits other than the aforementioned circuits, or to provide various electrical signals to the display area DA.

[0122] In an embodiment, the display device 1000 may have a pad unit positioned at an end of the second non-display area PA2 and may be electrically connected to a flexible printed circuit board (FPCB) including a driving chip through the pad unit.

[0123] In an embodiment, the driving chip positioned on the printed circuit board herein may include various driving circuits for driving the display device 1000 and a connector for power supply.

[0124] According to an embodiment, a rigid printed circuit board (PCB) may be used instead of a flexible printed circuit board.

[0125] In an embodiment, the optical device ES may be placed under the display panel DP.

[0126] In an embodiment, the optical device ES may include a first optical device ES1 overlapping the first assembly area EA1 and a second optical device ES2 overlapping the second assembly area EA2.

[0127] In an embodiment, the first optical device ES1 may be an electronic component using light and / or sound.

[0128] For example, in an embodiment, the first optical device ES1 can be a sensor that receives and uses light (such as an infrared sensor), a sensor that outputs and detects light or sound to measure distance and / or identify fingerprints, and / or a small lamp that outputs light, and / or the first optical device ES1 can be a speaker that outputs sound, etc.

[0129] In an embodiment, an electronic component using light (light of various wavelength bands such as visible light, infrared light, and ultraviolet light, for example) may be used.

[0130] In an embodiment, the second optical device ES2 may be at least one of a camera (eg, an infrared camera (IR camera)), a dot projector, an infrared illuminator (IR illuminator), and a time-of-flight sensor (ToF sensor).

[0131] In an embodiment, the housing HM may be combined with a cover window WU.

[0132] In an embodiment, the cover window WU may be placed at the front of the housing HM.

[0133] In an embodiment, the housing HM may be combined with the cover window WU to provide a specific accommodation space.

[0134] In an embodiment, the display panel DP and the optical device ES may be accommodated in a specific accommodation space provided between the housing HM and the cover window WU.

[0135] In an embodiment, the housing HM may include a material having relatively high rigidity.

[0136] For example, in an embodiment, the housing HM may include a plurality of frames and / or panels made of glass, plastic, metal, or a combination thereof.

[0137] In an embodiment, the housing HM may stably protect components of the display device 1000 accommodated in the inner space (accommodating space) from external impact.

[0138] In the following, reference will be made to Figure 2 A structure of a display panel according to an embodiment is described.

[0139] Figure 2 is a schematic top plan view of a display panel according to an embodiment.

[0140] In the examples and with reference to Figure 2 , the display panel DP may include a display area DA, an assembly area EA, and a non-display area PA, wherein the non-display area PA may be defined along a boundary of the display area DA.

[0141] In an embodiment, the non-display area PA may include a first non-display area PA1 positioned outside the display area DA and a second non-display area PA2 including the data driving part 50 , the connection wiring, and the bending area.

[0142] In an embodiment, the display panel DP includes a plurality of pixels PX.

[0143] In an embodiment, a plurality of pixels PX may be placed within the display area DA.

[0144] In an embodiment, each of the pixels PX includes a light emitting element and a pixel circuit unit connected to the light emitting element.

[0145] In an embodiment, each pixel PX may emit, for example, red light, green light, blue light, or white light, and may include, for example, an organic light emitting diode.

[0146] In an embodiment, the display panel DP may include a plurality of signal lines and a pad unit.

[0147] In an embodiment, the plurality of signal lines may include scan lines SL extending in the first direction DR1 , data lines DL and driving voltage lines PL extending in the second direction DR2 , and the like.

[0148] In an embodiment, a scan driving unit (or a scan driver or a scan driving part) 20 is positioned at both sides of the display area DA, and the scan driving unit 20 generates a scan signal and transmits the scan signal to each pixel PX through a scan line SL.

[0149] In an embodiment, the pixel PX may receive scan signals together from two scan drivers 20 positioned at the left and right sides.

[0150] In an embodiment, the pad unit PAD (also referred to as a circuit board pad unit) is positioned at one end of the second non-display area PA2 of the display panel DP and may include terminals PAD1 , PAD2 , PAD3 , and PAD4 .

[0151] In the embodiment, since the pad unit PAD is not covered by the insulating layer and is exposed, the pad unit PAD may be electrically connected to the flexible printed circuit board FPCB.

[0152] In an embodiment, the pad unit PAD may be electrically connected to a pad unit of the flexible printed circuit board FPCB.

[0153] In an embodiment, the flexible printed circuit board FPCB may transmit a signal or power from an integrated circuit (IC) driving chip 40 to the pad unit PAD.

[0154] In an embodiment, the IC driving chip 40 converts a plurality of video signals transmitted from the outside into a plurality of video data signals, and transmits the converted signals to the data driving unit 50 through the terminal PAD1 .

[0155] In addition, in an embodiment, the IC driver chip 40 can receive a vertical synchronization signal, a horizontal synchronization signal and a clock signal to generate a control signal for controlling the operation of the scan driving part 20 and the data driving part 50, and transmit the control signal to the scan driving part 20 and the data driving part 50 through terminals PAD3 and PAD1, respectively.

[0156] In the embodiment, the IC driving chip 40 transmits the driving voltage to the driving voltage supply wiring 60 through the terminal PAD2 .

[0157] Furthermore, in an embodiment, the IC driving chip 40 may transmit the common voltage to each common voltage transmission line 70 through the terminal PAD4 .

[0158] In an embodiment, the data driving unit 50 is placed in the second non-display area PA2 and generates a data voltage to be applied to each pixel PX and transmits the data voltage to each data line DL.

[0159] In an embodiment, the data driving unit 50 may be positioned at one side of the display panel DP, for example, the data driving unit 50 may be placed between the pad unit PAD and the display area DA.

[0160] In an embodiment, the data lines DL connected to the remaining pixels PX except for the pixels PX positioned at the upper and lower sides of the assembly area EA in the second direction DR2 may extend along the second direction DR2 and may have a straight line structure.

[0161] In contrast, in an embodiment, the data lines DL connected to the pixels PX positioned above and below the component area EA may extend in the second direction DR2, but in the vicinity of the component area EA, the data lines DL connected to the pixels PX positioned above and below the component area EA may also include a portion extending along the periphery of the component area EA.

[0162] In an embodiment, the driving voltage supply wiring 60 is arranged in the first non-display area PA1.

[0163] For example, in an embodiment, the driving voltage supply wiring 60 may be placed between the data driving part 50 and the display area DA.

[0164] In an embodiment, the driving voltage supply wiring 60 supplies a driving voltage to the pixel PX.

[0165] In an embodiment, the driving voltage supply wiring 60 is arranged in the first direction DR1 and may be connected to a plurality of driving voltage lines PL arranged in the second direction DR2 .

[0166] In an embodiment, the common voltage transmitting line 70 is arranged in the first non-display area PA1.

[0167] In an embodiment, the common voltage transmitting line 70 may have a shape surrounding the substrate 110 .

[0168] In an embodiment, the common voltage transmission line 70 transmits a common voltage to one electrode (eg, a cathode of a light emitting element included in the pixel PX).

[0169] In an embodiment, the second non-display area PA2 may include a bending region.

[0170] In an embodiment, the bending region may be positioned between the display area DA and the pad unit PAD.

[0171] In an embodiment, multiple inorganic layers may be removed in the bending region.

[0172] In an embodiment, no inorganic layer is included in the bending region.

[0173] In an embodiment, an insulating layer made of an organic material may be positioned in the bending region.

[0174] In an embodiment, in the bending region, an insulating layer made of an organic material may be positioned at an outermost portion.

[0175] In the following, reference will be made to Figure 3 and Figure 4 A pixel positioned in a display area according to an embodiment is described.

[0176] Figure 3 is a circuit diagram of one pixel of a display panel according to an embodiment, and Figure 4 is a schematic cross-sectional view of a display panel according to an embodiment.

[0177] First, refer to Figure 3 According to the embodiment, one pixel includes a plurality of transistors T1, T2, T3, T4, T5, T6 and T7 connected to a plurality of wirings 127, 128, 151, 152, 153, 155, 171, 172 and 741, a storage capacitor Cst, a boost capacitor C boost and light emitting diodes LED.

[0178] Here, the transistor and the capacitor except the light emitting diode LED constitute a pixel circuit unit.

[0179] In an embodiment, the boost capacitor C can be omitted boost .

[0180] In an embodiment, an additional capacitor or a boost capacitor may be formed.

[0181] In the embodiment, a plurality of wirings 127 , 128 , 151 , 152 , 153 , 155 , 171 , 172 , and 741 are connected to one pixel PX.

[0182] In an embodiment, the plurality of wirings 127, 128, 151, 152, 153, 155, 171, 172 and 741 include a first initialization voltage line 127, a second initialization voltage line 128, a first scan line 151, a second scan line 152, an initialization control line 153, a light emitting control line 155, a data line 171, a driving voltage line 172 and a common voltage line 741.

[0183] In an embodiment, the first scan line 151 is connected to a scan driving part (not shown), and transmits a first scan signal GW to the second transistor T2 and the seventh transistor T7.

[0184] In an embodiment, simultaneously with the signal of the first scan line 151 , the second scan line 152 may be applied with a voltage having a polarity opposite to that of the voltage applied to the first scan line 151 .

[0185] For example, in an embodiment, when a negative voltage is applied to the first scan line 151 , a positive voltage may be applied to the second scan line 152 .

[0186] In an embodiment, the second scan line 152 transmits the second scan signal GC to the third transistor T3.

[0187] In an embodiment, the initialization control line 153 transmits the initialization control signal GI to the fourth transistor T4.

[0188] In an embodiment, the light emitting control line 155 transmits the light emitting control signal EM to the fifth transistor T5 and the sixth transistor T6 .

[0189] In an embodiment, the data line 171 is a wiring for transmitting a data voltage DATA generated from a data driving part (not shown), thereby changing the size of a light emitting current transmitted to the light emitting diode LED, which in turn changes the brightness of the light emitting diode LED.

[0190] In an embodiment, the driving voltage line 172 applies a driving voltage ELVDD.

[0191] In an embodiment, the first initialization voltage line 127 transmits a first initialization voltage VINT, and the second initialization voltage line 128 transmits a second initialization voltage VAINT.

[0192] In an embodiment, the common voltage line 741 applies the common voltage ELVSS to the cathode of the light emitting diode LED.

[0193] In an embodiment, voltages applied to the driving voltage line 172 , the first and second initialization voltage lines 127 and 128 , and the common voltage line 741 may each be a constant voltage.

[0194] In an embodiment, the driving transistor T1 , also referred to as a first transistor, is a p-type transistor and has a silicon semiconductor (also referred to as a polycrystalline semiconductor or a first semiconductor) as a semiconductor layer.

[0195] In an embodiment, the driving transistor T1 is a transistor that adjusts the magnitude of the light emitting current output to the anode of the light emitting diode LED according to the magnitude of the voltage of the gate electrode of the driving transistor T1 (ie, the voltage stored in the storage capacitor Cst).

[0196] In an embodiment, the brightness of the light emitting diode LED may be adjusted depending on the amount of light emitting current output to the anode of the light emitting diode LED, and thus, the light intensity of the light emitting diode LED may be adjusted according to the data voltage DATA applied to the pixel PX.

[0197] In an embodiment, the first electrode of the driving transistor T1 is arranged to receive the driving voltage ELVDD and is connected to the driving voltage line 172 via the fifth transistor T5 .

[0198] Furthermore, in an embodiment, the first electrode of the driving transistor T1 is connected to the second electrode of the second transistor T2 and receives the data voltage DATA via the second transistor T2 .

[0199] In an embodiment, the second electrode of the driving transistor T1 outputs the light emitting current to the light emitting diode LED, and is connected to the anode of the light emitting diode LED via the sixth transistor T6 (also referred to as an output control transistor).

[0200] In an embodiment, the second electrode of the driving transistor T1 is connected to the third transistor T3 , and the second electrode of the driving transistor T1 transfers the data voltage DATA applied to the first electrode of the driving transistor T1 to the third transistor T3 .

[0201] In an embodiment, the gate electrode of the driving transistor T1 is connected to one electrode (also referred to as a second storage electrode) of the storage capacitor Cst.

[0202] In an embodiment, the other electrode (also referred to as a first storage electrode) of the storage capacitor Cst receives the driving voltage ELVDD.

[0203] In an embodiment, the voltage of the gate electrode of the driving transistor T1 changes according to the voltage stored in the storage capacitor Cst, and the light emitting current output by the driving transistor T1 changes accordingly.

[0204] In an embodiment, the storage capacitor Cst is used to keep the voltage of the gate electrode of the driving transistor T1 constant during one frame.

[0205] In an embodiment, the gate electrode of the driving transistor T1 may be connected to the third transistor T3 , allowing the data voltage DATA applied to the first electrode of the driving transistor T1 to be transmitted to the gate electrode of the driving transistor T1 through the third transistor T3 .

[0206] In an embodiment, a gate electrode of the driving transistor T1 may be connected to the fourth transistor T4 and initialized by receiving the first initialization voltage VINT.

[0207] In an embodiment, the second transistor T2 is a p-type transistor and has a silicon semiconductor as a semiconductor layer.

[0208] In an embodiment, the second transistor T2 is a transistor receiving the data voltage DATA within the pixel PX.

[0209] In an embodiment, the gate electrode of the second transistor T2 is connected to the first scan line 151 and the boosting capacitor C boost An electrode (also called the lower boost electrode).

[0210] In an embodiment, the boost capacitor C boost The other electrode of is connected to the gate electrode of the driving transistor T1 and the second storage electrode of the storage capacitor Cst.

[0211] In an embodiment, a first electrode of the second transistor T2 is connected to the data line 171 , and a second electrode of the second transistor T2 is connected to the first electrode of the driving transistor T1 .

[0212] In an embodiment, when the second transistor T2 is turned on by a voltage of a negative polarity among the first scan signal GW transmitted through the first scan line 151, the data voltage DATA transmitted through the data line 171 is transmitted to the first electrode of the driving transistor T1, and finally, the data voltage DATA is transmitted to the gate electrode of the driving transistor T1 and stored in the storage capacitor Cst.

[0213] In an embodiment, the third transistor T3 is an n-type transistor, and its semiconductor layer is composed of an oxide semiconductor (also referred to as a second semiconductor).

[0214] In an embodiment, the third transistor T3 electrically connects the second electrode of the driving transistor T1 and the gate electrode of the driving transistor T1 .

[0215] As a result, in an embodiment, the third transistor T3 is a transistor that compensates for the threshold voltage of the driving transistor T1 by the data voltage DATA and stores it in the second storage electrode of the storage capacitor Cst.

[0216] In an embodiment, a gate electrode of the third transistor T3 is connected to the second scan line 152 , and a first electrode of the third transistor T3 is connected to the second electrode of the driving transistor T1 .

[0217] In an embodiment, a second electrode of the third transistor T3 is connected to the second storage electrode of the storage capacitor Cst, the gate electrode of the driving transistor T1, and the boosting capacitor Cst. boost The other electrode (also called the boost electrode).

[0218] In an embodiment, the third transistor T3 is turned on by the positive voltage of the second scan signal GC transmitted through the second scan line 152, connects the gate electrode of the driving transistor T1 and the second electrode of the driving transistor T1, and transfers the voltage applied to the gate electrode of the driving transistor T1 to the second storage electrode of the storage capacitor Cst to store it in the storage capacitor Cst.

[0219] At this time, in the embodiment, the voltage stored in the storage capacitor Cst is the voltage of the gate electrode of the driving transistor T1 when the driving transistor T1 is turned off, which is stored in a state where the threshold voltage (Vth) value of the driving transistor T1 is compensated.

[0220] In an embodiment, the fourth transistor T4 is an n-type transistor, and a semiconductor layer of the fourth transistor T4 is composed of an oxide semiconductor.

[0221] In an embodiment, the fourth transistor T4 is used to initialize the gate electrode of the driving transistor T1 and the second storage electrode of the storage capacitor Cst.

[0222] In an embodiment, a gate electrode of the fourth transistor T4 is connected to the initialization control line 153 , and a first electrode of the fourth transistor T4 is connected to the first initialization voltage line 127 .

[0223] In an embodiment, the second electrode of the fourth transistor T4 is connected to the second electrode of the third transistor T3, the second storage electrode of the storage capacitor Cst, the gate electrode of the driving transistor T1, and the boosting capacitor Cst.boost The rising voltage electrode.

[0224] In an embodiment, the fourth transistor T4 is turned on by the positive voltage of the initialization control signal GI received through the initialization control line 153, and at this time, T4 transmits the first initialization voltage VINT to the gate electrode of the driving transistor T1, the second storage electrode of the storage capacitor Cst and the boosting electrode of the boosting capacitor Cboost for initialization.

[0225] In the embodiment, the fifth transistor T5 and the sixth transistor T6 are p-type transistors, and each of the fifth transistor T5 and the sixth transistor T6 has a silicon semiconductor as a semiconductor layer.

[0226] In an embodiment, the fifth transistor T5 is used to transmit the driving voltage ELVDD to the driving transistor T1 .

[0227] In an embodiment, a gate electrode of the fifth transistor T5 is connected to the light emission control line 155 , a first electrode of the fifth transistor T5 is connected to the driving voltage line 172 , and a second electrode of the fifth transistor T5 is connected to the first electrode of the driving transistor T1 .

[0228] In an embodiment, the sixth transistor T6 is used to transmit the light emitting current output from the driving transistor T1 to the light emitting diode LED.

[0229] In an embodiment, a gate electrode of the sixth transistor T6 is connected to the light emission control line 155 , a first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T1 , and a second electrode of the sixth transistor T6 is connected to the anode of the light emitting diode LED.

[0230] In an embodiment, the seventh transistor T7 may be a p-type transistor or an n-type transistor, and a semiconductor layer of the seventh transistor T7 may be composed of a silicon semiconductor or an oxide semiconductor. In an embodiment, the seventh transistor T7 is a p-type transistor including a silicon semiconductor.

[0231] In the embodiment, the seventh transistor T7 is used to initialize the anode of the light emitting diode LED.

[0232] In an embodiment, a gate electrode of the seventh transistor T7 is connected to the first scan line 151 , a first electrode of the seventh transistor T7 is connected to the anode of the light emitting diode LED, and a second electrode of the seventh transistor T7 is connected to the second initialization voltage line 128 .

[0233] In an embodiment, the gate electrode of the seventh transistor T7 is connected to the first scan line 151 of the adjacent pixel PX, and the gate electrode of the seventh transistor T7 and the gate electrode of the second transistor T2 belonging to the same pixel PX are not connected to the same first scan line 151, but the gate electrode of the seventh transistor T7 can be connected to the same first scan line 151 as the gate electrode of the second transistor T2 of the adjacent pixel PX.

[0234] In an embodiment, when the seventh transistor T7 is turned on by the voltage of the first scan line 151 , the second initialization voltage VAINT is applied to the anode of the light emitting diode LED, and the anode of the light emitting diode LED is initialized.

[0235] In an embodiment, the gate electrode of the seventh transistor T7 may also be individually controlled by a bypass signal GB transmitted through a separate bypass control line, and may be controlled by a wiring separate from the first scan line 151 .

[0236] Furthermore, according to an embodiment, the second initialization voltage line 128 to which the second initialization voltage VAINT is applied may be the same as the first initialization voltage line 127 to which the first initialization voltage VINT is applied.

[0237] In an embodiment, one pixel PX includes seven transistors T1 to T7 and two capacitors (a storage capacitor Cst and a boost capacitor Cst). boost ), but is not limited thereto, and according to different embodiments, the boost capacitor C may not be included boost .

[0238] Furthermore, according to an embodiment, an additional boosting capacitor may be formed between the gate electrode of the third transistor T3 and the gate electrode of the driving transistor T1 .

[0239] Furthermore, in the embodiment, although the third transistor T3 and the fourth transistor T4 are formed as n-type transistors, one of the third transistor T3 and the fourth transistor T4 may be formed as an n-type transistor, or other transistors (such as the seventh transistor T7) may also be formed as n-type transistors.

[0240] As described above, in the embodiment, the pixel of the display device includes two types of semiconductors positioned on different layers, and the two types of semiconductors are a polycrystalline semiconductor (also referred to as a first semiconductor) and an oxide semiconductor (also referred to as a second semiconductor).

[0241] In an embodiment, each of these semiconductors is included in a transistor, and hereinafter, a transistor including a polycrystalline semiconductor is referred to as a polycrystalline transistor (e.g., a low-temperature polycrystalline silicon thin film transistor (LTPS TFT)), and a transistor including an oxide semiconductor is referred to as an oxide transistor (e.g., an oxide thin film transistor (oxide TFT)).

[0242] In an embodiment, one pixel may include both a poly transistor and an oxide transistor, and the driving transistor T1 that supplies a driving current to the light emitting diode LED is formed as a poly transistor.

[0243] In an embodiment, all transistors except the driving transistor T1 are also referred to as switching transistors, and the switching transistors may be classified into polycrystalline switching transistors and oxide switching transistors.

[0244] In the following, reference will be made to Figure 4 A stack structure of a display area according to an embodiment is described.

[0245] In an embodiment, the display device may be mainly divided into a lower panel layer and an upper panel layer, wherein the lower panel layer is the portion where light-emitting diodes and pixel circuits constituting pixels are positioned, and may also include an encapsulation layer 400 covering the light-emitting diodes and pixel circuits constituting pixels.

[0246] In an embodiment, the pixel circuit includes the second organic layer 182 and the third organic layer 183 , the pixel circuit refers to an underlying structure, and the light emitting diode is positioned on an upper portion of the third organic layer 183 , and the light emitting diode may refer to a structure positioned on a lower portion of the encapsulation layer 400 .

[0247] In an embodiment, a structure positioned on an upper portion of the encapsulation layer 400 may correspond to an upper panel layer, and it may include a color filter or a color conversion layer according to an embodiment.

[0248] Furthermore, in embodiments, the third organic layer 183 may not be included.

[0249] First, in an embodiment, the metal layer BML is positioned on the substrate 110 .

[0250] In an embodiment, substrate 110 may include a non-bending material such as glass or a flexible material that can bend such as plastic or polyimide.

[0251] In an embodiment, in the case of a flexible substrate, a double-layered polyimide and a barrier layer formed thereon of an inorganic insulating material may have a double-layered structure.

[0252] In an embodiment, the metal layer BML may be formed at a position overlapping with a channel and a plane of a driving transistor in a subsequent first semiconductor layer ACT1 , and the metal layer BML is also referred to as a bottom shielding layer.

[0253] In embodiments, the metal layer BML may include a metal or a metal alloy such as copper (Cu), molybdenum (Mo), aluminum (Al), and titanium (Ti).

[0254] Here, in an embodiment, the driving transistor may refer to a transistor that generates a current transmitted to a light emitting diode.

[0255] In an embodiment, on top of the substrate 110 and the metal layer BML, there is a buffer layer 111 covering the substrate 110 and the metal layer BML.

[0256] In an embodiment, the buffer layer 111 is used to prevent impurities from penetrating into the first semiconductor layer ACT1, and may be a layer containing silicon oxide (SiO x ), Silicon Nitride (SiN x ) or silicon oxynitride (SiO x N y ) of an inorganic insulating layer.

[0257] In an embodiment, on top of the buffer layer 111 is a first semiconductor layer ACT1 including a silicon semiconductor such as polycrystalline silicon (P-Si).

[0258] In an embodiment, the first semiconductor layer ACT1 includes a channel of a polycrystalline transistor (including a driving transistor) and first and second regions positioned at both sides of the channel.

[0259] Here, in an embodiment, the polycrystalline transistor may include a plurality of polycrystalline switching transistors and a driving transistor.

[0260] Furthermore, in the embodiment, the first and second regions corresponding to both sides of the channel of the first semiconductor layer ACT1 have regions having conductive layer characteristics by plasma treatment or doping, thereby serving as first and second electrodes of the transistor.

[0261] In an embodiment, on top of the first semiconductor layer ACT1 , a first gate insulating layer 141 may be positioned.

[0262] In an embodiment, the first gate insulating layer 141 may include silicon oxide (SiO x ), Silicon Nitride (SiN x ) or silicon oxynitride (SiO x N y ) and other inorganic insulating layers.

[0263] In embodiments, a first gate conductive layer including a gate electrode GE1 of a poly transistor may be positioned on top of the first gate insulating layer 141 .

[0264] In an embodiment, in addition to the gate electrode GE1 of the polycrystalline transistor, a scan line or an emission control line may be further formed in the first gate conductive layer.

[0265] In an embodiment, the first gate conductive layer formed of different materials may be divided into a 1-1 gate conductive layer and a 1-2 gate conductive layer.

[0266] In an embodiment, after forming the first gate conductive layer, the exposed region of the first semiconductor layer may be made conductive by performing a plasma treatment or a doping process.

[0267] That is, in the embodiment, a portion of the first semiconductor layer ACT1 covered by the first gate conductive layer is non-conductive, and a portion of the first semiconductor layer ACT1 not covered by the first gate conductive layer has the same characteristics as the conductive layer.

[0268] In an embodiment, on top of the first gate conductive layer and the first gate insulating layer 141 , a second gate insulating layer 142 may be positioned.

[0269] In an embodiment, the second gate insulating layer 142 may include silicon oxide (SiO x ), Silicon Nitride (SiN x ) or silicon oxynitride (SiO x N y ) of an inorganic insulating layer.

[0270] In an embodiment, the second gate insulating layer 142 may be positioned between the storage capacitor Cst (see Figure 3 ), the storage capacitor Cst has a first electrode CE positioned on the second gate insulating layer.

[0271] In an embodiment, the first electrode CE of the storage capacitor Cst forms the storage capacitor Cst by overlapping the gate electrode GE1 of the driving transistor.

[0272] According to an embodiment, the second gate conductive layer may further include a lower shielding layer BML-1 of the oxide transistor.

[0273] In an embodiment, the lower shielding layer BML-1 of the oxide transistor may be positioned under the channel of each oxide transistor, and the lower shielding layer BML-1 of the oxide transistor may be used to shield light or electromagnetic interference provided from the bottom to the channel.

[0274] According to an embodiment, the second gate conductive layer may further include a scan line, a control line and / or a voltage line.

[0275] In an embodiment, the second gate conductive layer may include a metal or a metal alloy such as copper (Cu), molybdenum (Mo), aluminum (Al), or titanium (Ti), and may consist of a single layer or a multilayer.

[0276] In an embodiment, on top of the second gate conductive layer, a first interlayer insulating layer 161 may be positioned.

[0277] In an embodiment, the first interlayer insulating layer 161 may include silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ) or the like, and according to the embodiment, a thick inorganic insulating material can be formed.

[0278] In an embodiment, on top of the first interlayer insulating layer 161 , there may be a second semiconductor layer ACT2 (also referred to as an oxide semiconductor layer) including an oxide semiconductor.

[0279] In an embodiment, the oxide semiconductor may include a monometallic oxide (such as indium oxide (In oxide), tin oxide (Sn oxide), or zinc oxide (Zn oxide)), a binary metal oxide (such as In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In-Mg oxide, or In-Ga oxide), a ternary metal oxide (such as In-Ga-Zn oxide, In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide, At least one of In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide or In-Lu-Zn ​​oxide) and quaternary metal oxides (such as In-Sn-Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al-Zn oxide, In-Sn-Hf-Zn oxide or In-Hf-Al-Zn oxide).

[0280] For example, in an embodiment, the second semiconductor layer ACT2 may include indium gallium zinc oxide (IGZO) among In—Ga—Zn oxides.

[0281] In an embodiment, the second semiconductor layer ACT2 may include at least one of indium gallium zinc oxide (IGZO), indium zinc tin (IZTO), indium gallium zinc tin (IGZTO), and indium gallium oxide (IGO).

[0282] In embodiments, the third gate insulating layer 143 may be positioned on top of the second semiconductor layer ACT2 .

[0283] In embodiments, the third gate insulating layer 143 may be positioned on top of the second semiconductor layer ACT2 and the first interlayer insulating layer 161 .

[0284] In an embodiment, the third gate insulating layer 143 may include silicon oxide SiO x ), Silicon Nitride (SiN x ) or silicon oxynitride (SiO x N y ) of an inorganic insulating layer.

[0285] In an embodiment, on top of the third gate insulating layer 143 , there may be a third gate electrode layer including the gate electrode GE3 of the oxide transistor.

[0286] In embodiments, the gate electrode GE3 of the oxide transistor may overlap the channel.

[0287] In an embodiment, the third gate conductive layer may include an additional scan line or a control line.

[0288] In an embodiment, the third gate conductive layer may include a metal or a metal alloy such as copper (Cu), molybdenum (Mo), aluminum (Al), and titanium (Ti), and may consist of a single layer or a multi-layer.

[0289] In an embodiment, the second interlayer insulating layer 162 may be positioned on the third gate conductive layer.

[0290] In an embodiment, the second interlayer insulating layer 162 may have a single layer or a multi-layer.

[0291] According to an embodiment, the second interlayer insulating layer 162 may include an inorganic insulating material such as silicon nitride (SiN x ), silicon oxide (SiO x ) and silicon oxynitride (SiO x N y ), and may include organic materials.

[0292] In embodiments, the first data conductive layer including connection members C1 , C2 , C3 , and C4 respectively connectable to first and second regions of the poly transistor and first and second regions of the oxide transistor may be positioned on the second interlayer insulating layer 162 .

[0293] In an embodiment, the first data conductive layer may include a metal or a metal alloy such as aluminum (Al), copper (Cu), molybdenum (Mo), or titanium (Ti), and may consist of a single layer or a multi-layer.

[0294] In an embodiment, the first organic layer 181 may be positioned on the first data conductive layer.

[0295] In an embodiment, the first organic layer 181 may be an organic insulating layer including an organic material, and the organic material may include at least one material selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenolic resin.

[0296] In embodiments, the second data conductive layer including the anode connection member ACM2 may be positioned on top of the first organic layer 181 .

[0297] In an embodiment, the second data conductive layer may include a data line or a driving voltage line.

[0298] In an embodiment, the second data conductive layer may include a metal or a metal alloy such as aluminum (Al), copper (Cu), molybdenum (Mo), and titanium (Ti), and may consist of a single layer or a multi-layer.

[0299] In an embodiment, the anode connection member ACM2 is connected to the first data conductive layer through the opening OP3 positioned on the first organic layer 181 .

[0300] In an embodiment, over the second data conductive layer, there are second and third organic layers 182 and 183 , and the second and third organic layers 182 and 183 have an opening OP4 formed for an anode connection.

[0301] In an embodiment, the anode connection member ACM2 is electrically connected to the anode through the opening OP4 for anode connection.

[0302] In an embodiment, the second organic layer 182 and the third organic layer 183 may be organic insulating layers, and may include one or more substances selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenolic resin.

[0303] According to an embodiment, the third organic layer 183 may be omitted.

[0304] In an embodiment, on top of the anode, there may be a pixel defining layer 380 having an opening OP exposing the anode while covering at least a portion of the anode.

[0305] The pixel defining layer 380 may be a black pixel defining layer formed of a black organic material to prevent externally applied light from being reflected back to the outside, or may be formed of a transparent organic material according to an embodiment.

[0306] According to an embodiment, spacer 385 is positioned over pixel defining layer 380 .

[0307] In an embodiment, the spacer 385 may be formed of a transparent organic insulating material.

[0308] According to an embodiment, the spacer 385 may be formed of a positive-type transparent organic material.

[0309] In an embodiment, the spacer 385 may include two portions 385 - 1 and 385 - 2 having different heights, the higher portion 385 - 1 performs a role of a spacer, and the lower portion 385 - 2 can improve adhesive properties between the spacer and the pixel defining layer 380 .

[0310] In an embodiment, on top of the anode, the spacer 385, and the pixel defining layer 380, a functional layer FL and a cathode are sequentially formed, and the functional layer FL and the cathode may be positioned in the entire region.

[0311] In an embodiment, between the functional layers FL, the light emitting layer EML exists, and the light emitting layer EML may be positioned only within the opening OP of the pixel defining layer 380 .

[0312] Hereinafter, according to an embodiment, a combination of the functional layer FL and the light emitting layer EML may be referred to as an intermediate layer.

[0313] In an embodiment, the functional layer FL may include at least one of auxiliary layers such as an electron injection layer, an electron transport layer, a hole transport layer, and a hole injection layer, and the hole injection layer and the hole transport layer are positioned below the light-emitting layer EML, and the electron transport layer and the electron injection layer may be positioned on the light-emitting layer EML.

[0314] In an embodiment, on top of the cathode, there is an encapsulation layer 400 .

[0315] In an embodiment, the encapsulation layer 400 includes at least one inorganic layer and at least one organic layer, and may have a triple-layer structure including a first inorganic encapsulation layer EIL1 , an organic encapsulation layer EOL, and a second inorganic encapsulation layer EIL2 .

[0316] In an embodiment, the encapsulation layer 400 may serve to protect the light emitting layer EML from moisture or oxygen that may be introduced from the outside.

[0317] According to an embodiment, the encapsulation layer 400 may include a structure in which an inorganic layer and an organic layer are sequentially stacked.

[0318] In an embodiment, on top of the encapsulation layer 400 , there are detection insulating layers 501 , 510 , and 511 and a plurality of sensing electrodes 540 and 541 for touch detection.

[0319] In an embodiment, using two sensing electrodes 540 and 541 , a touch may be capacitively detected.

[0320] Specifically, in an embodiment, over the encapsulation layer 400 , a first detection insulating layer 501 is formed, and a plurality of sensing electrodes 540 and 541 are formed on top of the first detection insulating layer 501 .

[0321] In an embodiment, the plurality of sensing electrodes 540 and 541 may be insulated from each other by the second sensing insulating layer 510 , and some of the plurality of sensing electrodes 540 and 541 may be electrically connected through openings positioned in the sensing insulating layer 510 .

[0322] In an embodiment, the sensing electrodes 540 and 541 may include a metal or a metal alloy such as aluminum (Al), copper (Cu), silver (Ag), gold (Au), molybdenum (Mo), titanium (Ti), and tantalum (Ta), and may be composed of a single layer or a multilayer.

[0323] In an embodiment, on top of the sensing electrode 540 , a third detection insulating layer 511 is formed.

[0324] In an embodiment, although no configuration is shown on the third detection insulating layer 511, a layer including a polarizing plate may be attached to reduce reflection of external light, or a color filter or a color conversion layer may also be formed to improve color quality.

[0325] In an embodiment, the light blocking portion may be positioned between color filters or between color conversion layers.

[0326] Furthermore, in an embodiment, a layer including a material capable of absorbing some wavelengths of external light (also referred to as a reflection adjusting material) may be further included.

[0327] Furthermore, in embodiments, the front surface of the light emitting display device may be planarized by being covered with an additional organic layer (also referred to as a planarization layer).

[0328] In the following, reference will be made to Figures 5 to 7 describe Figure 2 Area A.

[0329] According to an embodiment, Figure 5 According to the embodiment Figure 2 An enlarged top plan view of Area A, Figure 6 According to the embodiment along Figure 5 A cross-sectional view taken along line AA' of Figure 7 According to the embodiment along Figure 5 A cross-sectional view taken along line BB'.

[0330] In an embodiment, the dam unit DD may be positioned in the non-display area PA.

[0331] The dam unit DD may include at least two dams D1 and D2 .

[0332] Figure 5 An example of a structure in which two dams D1 and D2 are provided is shown, but the present invention is not limited thereto.

[0333] In the embodiment, when forming Figure 4 When the organic encapsulation layer EOL of the encapsulation layer 400 in the substrate 110 is formed, the dam unit DD may prevent the overflow of the organic encapsulation layer EOL by blocking the organic material from flowing toward the edge of the substrate 110 .

[0334] In an embodiment, the dam unit DD may be formed in the non-display area PA (see Figure 1 ) is arranged to at least partially surround the display area DA (see Figure 1 ).

[0335] In an embodiment, the first dam D1 and the second dam D2 may be provided separately from each other, and the first dam D1 may be arranged to surround at least a portion of the second dam D2.

[0336] In embodiments, the first dam D1 and the second dam D2 may have a single layer or multiple layers.

[0337] In the examples and with reference to Figure 6 , the first dam D1 includes a first-1 dam D1-1 and a first-2 dam D1-2, and the second dam D2 may include a second-1 dam D2-1, a second-2 dam D2-2, and a second-3 dam D2-3.

[0338] The present disclosure describes an embodiment in which the first dam D1 and the second dam D2 have different heights, but the present disclosure is not limited thereto.

[0339] In an embodiment, the first dam D1 and the second dam D2 may include the same material as an organic layer positioned in the display area DA, and may be formed in the same process.

[0340] According to an embodiment, the non-display area PA may include a capping organic layer CL1 connected to the second dam D2 .

[0341] In an embodiment, the capping organic layer CL1 may have a protruding shape from the second dam D2 toward the first dam D1 .

[0342] In embodiments, the capping organic layer CL1 may be separated from the first dam D1 .

[0343] In an embodiment, the capping organic layer CL1 may block a path for moisture to flow from the second dam D2 to the first dam D1 by not being connected to the first dam D1 .

[0344] In an embodiment, the covering organic layer CL1 may be Figure 4 The second organic layer 182 described in EMBODIMENT 1 includes the same material and may be formed in the same process as the second organic layer 182 .

[0345] Alternatively, according to another embodiment, the covering organic layer CL1 may be Figure 4 The third organic layer 183 described in EMBODIMENT 1 includes the same material and may be formed in the same process as the third organic layer 183 .

[0346] In an embodiment, the capping organic layer CL1 may overlap a portion of the common voltage transmitting line 70 .

[0347] In an embodiment, the capping organic layer CL1 may overlap a portion of an edge of the common voltage transmitting line 70 .

[0348] In an embodiment, the common voltage transmission line 70 may include a first edge E1 positioned adjacent to the first dam D1 and a second edge E2 positioned adjacent to the second dam D2 .

[0349] In an embodiment, the shape of the common voltage transmitting line 70 may be determined by the first edge E1 and the second edge E2 .

[0350] In an embodiment, the second edge E2 of the common voltage transmitting line 70 may include a protrusion portion RP directed toward the first dam D1 .

[0351] In an embodiment, the protruding portion RP may be positioned between the first dam D1 and the second dam D2 .

[0352] According to an embodiment, the protruding portion RP may include two first portions R1 protruding from the second edge E2 in the extending direction and a second portion R2 connecting the two first portions R1 .

[0353] For example, in an embodiment, the second edge E2 may extend along the first direction DR1 and may include the protrusion portion RP in the second direction DR2.

[0354] In an embodiment, the protrusion portion RP includes two first portions R1 protruding in the second direction DR2 , and may include a second portion R2 connecting the two first portions R1 and extending in the first direction DR1 .

[0355] However, it is not limited to these embodiments, and according to other embodiments, the second edge E2 extending along the second direction DR2 may also include a protrusion in the first direction DR1.

[0356] In an embodiment, the protrusion portion RP may include two first portions R1 protruding in the first direction DR1 , and may include a second portion R2 extending in the second direction DR2 connecting the two first portions R1 .

[0357] According to an embodiment, the cover organic layer CL1 may cover the protrusion portion from the second edge E2 toward the first dam D1 .

[0358] In an embodiment, the capping organic layer CL1 may overlap the first portion R1 and the second portion R2 of the protrusion portion RP.

[0359] In an embodiment, the cover organic layer CL1 may include a first region P1 covering the first portion R1 and a second region P2 covering the second portion R2 .

[0360] In an embodiment, the first region P1 is connected to the second dam D2 and may extend from the second dam D2.

[0361] In an embodiment, the second region P2 may connect two adjacent first regions P1 to each other.

[0362] According to an embodiment, the common voltage transmitting line 70 may include a first region RR1 having a first width t1 and a second region RR2 having a second width t2.

[0363] In an embodiment, the first width t1 may be greater than the second width t2 .

[0364] In an embodiment, the common voltage transmitting line 70 may have a concave shape in the second region RR2 in a plan view.

[0365] In an embodiment, the common voltage transmission line 70 may include a recess in a plan view.

[0366] In an embodiment, the common voltage transmitting line 70 may overlap at least portions of the first dam D1 and the second dam D2 in the first region RR1 .

[0367] Furthermore, in embodiments, the common voltage transmitting line 70 may overlap the first dam D1 in the second region RR2 , and may be spaced apart from the second dam D2 .

[0368] In embodiments, the second region RR2 may overlap the first dam D1 and cover the organic layer CL1 .

[0369] In an embodiment, the alignment keys MK1 and MK2 may overlap at least a portion of the second dam D2.

[0370] Furthermore, in an embodiment, the alignment keys MK1 and MK2 may be positioned in recesses of the common voltage transmission line 70 in a plan view.

[0371] In an embodiment, the alignment keys MK1 and MK2 may be arranged to have a predetermined distance from the common voltage transmission line 70 .

[0372] In an embodiment, the alignment keys MK1 and MK2 may be used to check an alignment status and other necessary conditions during a manufacturing process.

[0373] In an embodiment, since the alignment keys MK1 and MK2 need to be visible from the outside, the alignment keys MK1 and MK2 may be made of an opaque material.

[0374] Furthermore, in an embodiment, the alignment keys MK1 and MK2 may be configured as island patterns spaced apart from other conductive patterns on a plane to improve visibility.

[0375] In the following, reference will be made to Figure 6 and Figure 7 Describe again in more detail Figure 5 cross-sectional structure.

[0376] According to an embodiment, from the display area DA (see Figure 1 ) extending from the buffer layer 111, the first gate insulating layer 141, the second gate insulating layer 142, the first interlayer insulating layer 161, the third gate insulating layer 143 and the second interlayer insulating layer 161 may be formed in the non-display area PA (see Figure 2 ) is positioned on the substrate 110.

[0377] In embodiments, at least one of the buffer layer 111 , the first gate insulating layer 141 , the second gate insulating layer 142 , the first interlayer insulating layer 161 , the third gate insulating layer 143 , and the second interlayer insulating layer 162 may be partially removed.

[0378] In an embodiment, and as Figure 7 As shown in FIG. 1 , the second interlayer insulating layer 162 may be positioned on the alignment keys MK1 and MK2 .

[0379] In an embodiment, the alignment keys MK1 and MK2 include the same material as the third gate conductive layer of the gate electrode GE3 of the oxide transistor disposed in the display area DA, and may be formed in the same process.

[0380] In an embodiment, the alignment keys MK1 and MK2 may overlap at least some portions of the second dam D2.

[0381] In an embodiment, the align keys MK1 and MK2 may reduce an area occupied by the non-display area PA in the display device by overlapping at least a portion of the second dam D2.

[0382] In an embodiment, the common voltage transmission line 70 may be positioned on the second interlayer insulating layer 162 .

[0383] In an embodiment, the common voltage transmission line 70 may include at least one of a first layer SD1 and a second layer SD2, the first layer SD1 and the connection members C1, C2, C3 and C4 (see Figure 4 ) is formed in the same process as the first data conductive layer, and the second layer SD2 is formed with the anode connection member ACM2 (see Figure 4 ) is formed in the same process.

[0384] According to an embodiment, the common voltage transmission line 70 may include a third layer PXL formed in the same process as the anode.

[0385] In an embodiment, the first dam D1 may be positioned on the common voltage transmission line 70 .

[0386] In an embodiment, the first dam D1 may include a first-1 dam D1-1 and a first-2 dam D1-2.

[0387] In an embodiment, the first-1 dam D1-1 is connected to the pixel defining layer 380 (see Figure 4 ) include the same materials and can be formed in the same process.

[0388] In an embodiment, the first-2 dam D1-2 is aligned with the spacer 385 (see FIG. 1-4 ) positioned in the display area DA. Figure 4 ) include the same materials and can be formed in the same process.

[0389] In an embodiment, the second dam D2 may be positioned on another portion of the common voltage transmission line 70 .

[0390] In an embodiment, the second dam D2 may also include some areas that do not overlap with the common voltage transmitting line 70 .

[0391] According to an embodiment, Figure 6 and Figure 7 A region where the common voltage transmission line 70 is not positioned on the second dam D2 is presented.

[0392] In an embodiment, the second dam D2 may include a second-1 dam D2-1, a second-2 dam D2-2, and a second-3 dam D2-3.

[0393] In an embodiment, the second-1 dam D2-1 is connected to the second organic layer 182 (see Figure 4 ) includes the same material and can be formed in the same process as the second organic layer 182.

[0394] Alternatively, according to another embodiment, the second-1 dam D2-1 may be connected to the third organic layer 183 (see Figure 4 ) includes the same material and can be formed in the same process as the third organic layer 183.

[0395] In an embodiment, the second-2 dam D2-2 may include the same material as the pixel defining layer 380 in the display area DA, and may be formed in the same process.

[0396] In an embodiment, the second-3 dam D2-3 includes the same material as the spacer 385 positioned in the display area DA, and may be formed in the same process.

[0397] According to an embodiment, the capping organic layer CL1 may include the same material as the second organic layer 182 positioned in the display area DA, and may be formed in the same process as the second organic layer 182 .

[0398] Alternatively, in an embodiment, the capping organic layer CL1 may include the same material as the third organic layer 183 , and may be formed in the same process as the third organic layer 183 .

[0399] In embodiments, the capping organic layer CL1 and the second dam D2 may be connected to each other.

[0400] In particular, according to an embodiment, the capping organic layer CL1 may be connected to the second-1 dam D2-1.

[0401] In an embodiment, the capping organic layer CL1 and the second-1 dam D2-1 may be formed in the same process and may be formed as an integral body.

[0402] In an embodiment, the cover organic layer CL1 may cover an end portion of the common voltage transmission line 70 .

[0403] In an embodiment, the covering organic layer CL1 may specifically cover the second edge E2 of the common voltage transmission line 70 (see Figure 5 ) part.

[0404] In an embodiment, the covering organic layer CL1 may cover the second edge E2 toward the first edge E1 (see Figure 5 ) protruding protrusion RP (see Figure 5 ).

[0405] In the examples and with reference to Figure 6 and Figure 7 , the common voltage transmission line 70 may include a portion that is not covered by the first dam D1 , the covering organic layer CL1 , and the second dam D2 .

[0406] In an embodiment, a portion of the upper surface of the common voltage transmitting line 70 may not be covered by the organic layer.

[0407] In an embodiment, the upper surface of the common voltage transmission line 70 may be formed by the first inorganic encapsulation layer EIL1 (see Figure 4 )cover.

[0408] Furthermore, in embodiments, the capping organic layer CL1 and the second dam D2 may include separate regions.

[0409] In an embodiment, in a separated region between the second dam and the cover organic layer CL1 , an upper surface of the second interlayer insulating layer 162 may be exposed.

[0410] In an embodiment, an upper surface of the second interlayer insulating layer 162 that is not covered by other elements may be covered by the first inorganic encapsulation layer EIL1 , which may block a permeation path.

[0411] In an embodiment, since the area occupied by the non-display area PA is reduced, there is a possibility that natural oxidation may occur in an area adjacent to the second dam D2 in a high temperature and high humidity environment.

[0412] According to an embodiment, the first dam D1 and the second dam D2 are spaced apart from each other, and the cover organic layer CL1 covering the end of the common voltage transmitting line 70 may be spaced apart from the first dam D1 .

[0413] In an embodiment, moisture flowing in through the second dam D2 may move to the overlying organic layer CL1 , but may not move to the first dam D1 .

[0414] Therefore, according to an embodiment, the capping organic layer CL1 may protect the wiring by covering the edge of the common voltage transmission line 70 , and may be spaced apart from the first dam D1 , thereby blocking a path for the movement of moisture.

[0415] In the embodiment, a display device having an excellent effect of preventing moisture penetration may be provided.

[0416] In an embodiment, since the common voltage transmission line provides an area where an alignment key is disposed and has a wiring width of a certain level or more, an IR drop may be reduced.

[0417] Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and those of ordinary skill in the art can use the basic concept of the present invention to make various modifications and improvements. The embodiments of the present invention disclosed in this disclosure and shown in the accompanying drawings are provided as specific embodiments to more conveniently illustrate the technical content according to the present invention and help understand the embodiments of the present invention, but they are not intended to limit the scope of the embodiments of the present invention. Therefore, the scope of the present invention should be interpreted as including all changes or modifications derived from the technical ideas of various embodiments in addition to the embodiments disclosed herein. In addition, without departing from the scope of the present invention, the embodiments or parts of the embodiments may be combined in whole or in part.

Claims

1. A display device, in, The display device comprises: A substrate, including a display area and a non-display area; a transistor positioned in the display region; a light emitting element electrically connected to the transistor; a common voltage transmission line positioned in the non-display area and including a recess; a first dam and a second dam positioned in the non-display area and spaced apart from each other, wherein the first dam and the second dam surround at least a portion of the display area; and a covering organic layer overlapping the edge of the recess, Wherein, the edge of the recess is positioned between the first dam and the second dam.

2. The display device according to claim 1, in, The common voltage transmission line comprises: a first region having a first width; and The second region has a second width, wherein the first width is greater than the second width.

3. The display device according to claim 2, in, The second region has a more concave shape than the first region.

4. The display device according to claim 1, in, The common voltage transmission line includes a first edge and a second edge, wherein the first edge is located adjacent to the first dam, the second edge is positioned adjacent to the second dam, At least a portion of the second edge overlaps the second dam, and The second edge includes a protruding portion extending toward the first edge and overlapping the covering organic layer.

5. The display device according to claim 1, in, The display area includes: a first semiconductor layer positioned on the substrate; a first gate conductive layer, positioned on the first semiconductor layer; a second gate conductive layer positioned on the first gate conductive layer; a second semiconductor layer positioned on the second gate conductive layer; a third gate conductive layer, positioned on the second semiconductor layer; A first data conductive layer, positioned on the third gate conductive layer; a second data conductive layer positioned on the first data conductive layer; and A first electrode is positioned on the second data conductive layer, wherein: The common voltage transmission line includes at least one of a first layer positioned on the same layer as the first data conductive layer and a second layer positioned on the same layer as the second data conductive layer.

6. The display device according to claim 5, in, The display device further comprises: An alignment key overlaps at least a portion of the recess in plan view.

7. The display device according to claim 6, in, The alignment key is positioned on the same layer as the third gate conductive layer.

8. The display device according to claim 5, in, The display device further comprises: a first gate insulating layer positioned on the first semiconductor layer; a second gate insulating layer positioned on the first gate conductive layer; a first interlayer insulating layer positioned on the second gate conductive layer; a third gate insulating layer positioned on the second semiconductor layer; a second interlayer insulating layer positioned on the third gate conductive layer; a first organic layer, positioned on the first data conductive layer; A second organic layer and a third organic layer positioned on the second data conductive layer; and A pixel defining layer and a spacer are positioned on the first electrode, wherein The capping organic layer includes a same material as at least one of the second organic layer and the third organic layer.

9. The display device according to claim 8, in, The capping organic layer is connected to the second dam.

10. The display device according to claim 1, in, The first dam and the capping organic layer are spaced apart from each other.

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