Array substrate and display panel

Abstract

The invention discloses an array substrate and a display panel. The array substrate comprises a substrate body and a pixel circuit located on the substrate body. The pixel circuit comprises a dual-gate transistor and a first capacitor plate, and the orthographic projection of the first capacitor plate on the substrate at least partially covers the orthographic projection of a dual-gate node of the dual-gate transistor; the plurality of first capacitor plates are electrically connected to form a conductive wire, and the conductive wire is connected with a fixed potential signal. According to the technical scheme, the use performance of the display panel is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] Organic Light Emitting Diode (OLED) and flat panel display devices based on technologies such as Light Emitting Diode (LED) have been widely used in various consumer electronic products such as mobile phones, televisions, laptops, desktop computers, etc. due to their advantages such as high image quality, power saving, thin body and wide application range, becoming the mainstream in display devices.

[0003] However, the performance of current OLED display products needs to be improved. Summary of the invention

[0004] The present invention provides an array substrate and a display panel to improve the performance of display products.

[0005] According to one aspect of the present invention, an array substrate is provided, the array substrate comprising: a substrate and a pixel circuit located on the substrate;

[0006] The pixel circuit comprises a dual-gate transistor and a first capacitor plate, wherein an orthographic projection of the first capacitor plate at least partially covers an orthographic projection of a dual-gate node of the dual-gate transistor on a substrate;

[0007] The plurality of first capacitor plates are electrically connected to form a conductive trace, and the conductive trace is connected to a fixed potential signal.

[0008] Optionally, the array substrate further comprises a data line; the data line extends along a first direction, and a plurality of the data lines are arranged along a second direction;

[0009] A plurality of first capacitor plates arranged along the first direction are electrically connected to form the conductive trace, and / or a plurality of first capacitor plates arranged along the second direction are electrically connected to form the conductive trace.

[0010] Optionally, the array substrate further includes a first initialization signal line and a second initialization signal line;

[0011] The pixel circuit further includes a driving transistor, a first initialization transistor and a second initialization transistor; the first initialization transistor is connected between the first initialization signal line and the driving transistor; the second initialization transistor is connected between the second initialization signal line and the light emitting element;

[0012] The conductive trace is the first initialization signal line or the second initialization signal line.

[0013] Optionally, the array substrate further includes a first initialization signal line, a second initialization signal line, a first initialization network line, and a second initialization network line;

[0014] The pixel circuit further includes a driving transistor, a first initialization transistor and a second initialization transistor; the first initialization transistor is connected between the first initialization signal line and the driving transistor; the second initialization transistor is connected between the second initialization signal line and the light emitting element;

[0015] The first initialization network cable is electrically connected to the first initialization signal line to form a mesh structure, and the second initialization network cable is electrically connected to the second initialization signal line to form a mesh structure;

[0016] The conductive wire is the first initialization network wire or the second initialization network wire;

[0017] Preferably, the first initialization signal line and the second initialization signal line extend along the second direction; the first initialization network cable and the second initialization network cable extend along the first direction.

[0018] Optionally, the array substrate further includes a first power line and a second power line; the pixel circuit further includes a driving transistor; the first power line is connected to the driving transistor, and the second power line is electrically connected to a light emitting element corresponding to the pixel circuit;

[0019] The conductive trace is the first power line or the second power line;

[0020] Preferably, the first power line and the second power line extend along a first direction.

[0021] Optionally, the array substrate further includes a first power line and a second power line; the pixel circuit further includes a driving transistor; the first power line is connected to the driving transistor, and the second power line is electrically connected to a light emitting element corresponding to the pixel circuit;

[0022] The array substrate further comprises a first power supply network cable and a second power supply network cable extending along a second direction;

[0023] The first power network cable is electrically connected to the first power line to form a mesh structure, and the second power network cable is electrically connected to the second power line to form a mesh structure;

[0024] The conductive trace is the first power network cable or the second power network cable.

[0025] Optionally, the array substrate further includes a data line; the data line extends along a first direction, and a plurality of the data lines are arranged along a second direction; the first capacitor plate includes a first portion, a second portion and a third portion;

[0026] The first portion extends along the first direction, the second portion extends along the second direction, and the second portion is connected between the first portion and the third portion;

[0027] The first portions of the plurality of first capacitor plates arranged along the first direction are electrically connected;

[0028] Alternatively, the first portion is electrically connected to a third portion of the first capacitor plate adjacent in the second direction;

[0029] Preferably, the orthographic projection of the third portion on the substrate at least partially covers the orthographic projection of the dual-gate node.

[0030] Optionally, the array substrate further includes a first power line;

[0031] The orthographic projection of the first portion on the substrate overlaps with the orthographic projection of the first power line on the substrate;

[0032] Preferably, at least part of the orthographic projection of the first portion on the substrate is located between the orthographic projection of the first power line on the substrate and the orthographic projection of the data line on the substrate;

[0033] Preferably, the pixel circuit further comprises a first active portion connected to a control electrode of a driving transistor of the pixel circuit, and an orthographic projection of the first capacitor plate on the substrate at least partially covers an orthographic projection of the first active portion;

[0034] Preferably, at least a portion of the orthographic projection of the first portion on the substrate is located between the orthographic projection of the data line on the substrate and the orthographic projection of the first active portion on the substrate.

[0035] Optionally, two adjacent first portions along the first direction are connected by a first connecting portion; the first connecting portion is located between the orthographic projection of the control electrode of the driving transistor of the pixel circuit and the orthographic projection of the data line on the substrate, at least part of the orthographic projection of the substrate.

[0036] Optionally, the pixel circuit further includes a storage capacitor and a driving transistor, a first electrode of the storage capacitor is electrically connected to a control electrode of the driving transistor, and a second electrode of the storage capacitor is connected to a first power line;

[0037] Preferably, the storage capacitor comprises a second capacitor plate and a third capacitor plate;

[0038] The plurality of third capacitor plates arranged along the second direction are electrically connected to form a first power network cable, and the first power network cable is electrically connected to the first power line to form a mesh structure;

[0039] Preferably, the second capacitor plate is a control electrode of the driving transistor.

[0040] Optionally, the dual-gate transistor includes a first gate and a second gate;

[0041] The pixel circuit further includes a second active portion, the second active portion is located between an orthographic projection of the first gate on the substrate and an orthographic projection of the second gate on the substrate, and the second active portion is the dual-gate node;

[0042] The first capacitor plate and the second active portion form a voltage-stabilizing capacitor, and the voltage-stabilizing capacitor is used to maintain the potential of the dual-gate node.

[0043] Optionally, the pixel circuit further comprises a first light-emitting control transistor, wherein a first electrode of the first light-emitting control transistor is electrically connected to the first power line, and a second electrode of the first light-emitting control transistor is electrically connected to a first electrode of the driving transistor; a control electrode of the first light-emitting control transistor is connected to a light-emitting control line; the first light-emitting control transistor is used to control whether a first power supply voltage on the first power line is transmitted to the first electrode of the driving transistor in response to a light-emitting control signal of the light-emitting control line;

[0044] Preferably, the pixel circuit further comprises a second light emitting control transistor, a first electrode of the second light emitting control transistor is electrically connected to a second electrode of the driving transistor, a second electrode of the second light emitting control transistor is electrically connected to a first electrode of the light emitting element, and a control electrode of the second light emitting control transistor is connected to a light emitting control line; the second light emitting control transistor is used to control whether the driving current of the driving transistor is transmitted to the light emitting element in response to a light emitting control signal of the light emitting control line;

[0045] The second electrode of the light emitting element is connected to the second power line;

[0046] Preferably, the first electrode of the dual-gate transistor is electrically connected to the second electrode of the driving transistor, the second electrode of the dual-gate transistor is electrically connected to the control electrode of the driving transistor, and the control electrode of the dual-gate transistor is connected to a first scanning line; the dual-gate transistor is used to perform threshold compensation on the driving transistor in response to a first scanning signal on the first scanning line;

[0047] Preferably, the pixel circuit further comprises a data writing transistor, a first electrode of the data writing transistor is connected to the data line, a second electrode of the data writing transistor is electrically connected to the first electrode of the driving transistor, and a control electrode of the data writing transistor is connected to the first scanning line; the data writing transistor is used to transmit the data voltage on the data line to the driving transistor in response to the first scanning signal on the first scanning line;

[0048] Preferably, the array substrate further comprises a first initialization signal line and a second initialization signal line;

[0049] The pixel circuit also includes a first initialization transistor and a second initialization transistor; the first initialization transistor is connected between the first initialization signal line and the control electrode of the driving transistor; the second initialization transistor is connected between the second initialization signal line and the light-emitting element; the control electrode of the first initialization transistor and the control electrode of the second initialization transistor are connected to a second scan line; the first initialization transistor is used to initialize the control electrode of the driving transistor in response to a second scan signal on the second scan line, and the second initialization transistor is used to initialize the light-emitting element in response to a second scan signal on the second scan line.

[0050] Optionally, the array substrate comprises a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer located on the substrate;

[0051] The first scanning line, the second scanning line and the light emitting control line are located in the first conductive layer;

[0052] At least a portion of the first initialization signal lines and at least a portion of the second initialization signal lines are located in the second conductive layer;

[0053] The first power line and the second power line are located in the third conductive layer;

[0054] The data line is located in the fourth conductive layer;

[0055] Preferably, the first capacitor plate is located in the second conductive layer;

[0056] Preferably, the conductive trace formed by the electrical connection of the first capacitor plates is located in the second conductive layer; or, part of the conductive trace formed by the electrical connection of the first capacitor plates is located in the second conductive layer, and another part of the conductive trace is located in the third conductive layer.

[0057] Optionally, the first initialization network cables and the second initialization network cables are arranged alternately.

[0058] According to another aspect of the present invention, a display panel is provided. The display panel includes the array substrate described in any embodiment of the present invention.

[0059] The technical solution of the embodiment of the present invention is to set a first capacitor plate, and the first capacitor plate covers at least part of the dual-gate node of the dual-gate transistor, so that the first capacitor plate and the dual-gate node form a voltage-stabilizing capacitor, and the first capacitor plate is connected to a fixed potential signal to maintain the potential of the dual-gate node, which can reduce the leakage current of the dual-gate transistor, and then reduce the leakage current of the driving transistor connected to the dual-gate transistor, so that the light-emitting element connected to the pixel circuit can emit light stably, and improve the display effect of the display panel. In addition, multiple first capacitor plates are electrically connected to form a conductive trace, so that the conductive trace can be reused as a trace carrying a DC signal on the array substrate, so that the traces on the array substrate can be reduced, which is convenient for achieving high pixel density while improving the transmittance of the array substrate, avoiding affecting the photosensitive device, thereby improving the display effect of the display panel formed by the array substrate, which is conducive to improving the display effect of the display panel.

[0060] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0062] Figure 1 is a structural schematic diagram of an array substrate provided by an embodiment of the present invention;

[0063] Figure 2 is a structural schematic diagram of another array substrate provided by an embodiment of the present invention;

[0064] Figure 3 is a structural schematic diagram of another array substrate provided by an embodiment of the present invention;

[0065] Figure 4 is a structural schematic diagram of another array substrate provided by an embodiment of the present invention;

[0066] Figure 5 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0067] Figure 6is a structural schematic diagram of another array substrate provided by an embodiment of the present invention;

[0068] Figure 7 is a structural schematic diagram of another array substrate provided by an embodiment of the present invention;

[0069] Figure 8 is a structural schematic diagram of another array substrate provided by an embodiment of the present invention;

[0070] Fig. 9 yes Figure 8 Cross-sectional view along the direction a1-a2;

[0071] Fig.10 yes Figure 8 Cross-sectional view along the b1-b2 direction;

[0072] Fig.11 It is a schematic diagram of the structure of a display panel provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0073] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0074] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0075] With the continuous improvement of the display performance of display products, high pixel density (Pixels Per Inch, PPI) display products are more and more widely used. When the pixel density is high, the display product can display graphics at a higher density, so that the degree of simulation is higher, which is conducive to improving the visual experience. The display product includes an array substrate, and the array substrate includes a pixel circuit, and the pixel circuit is, for example, a 2T1C pixel circuit and its deformation, or a 7T1C pixel circuit and its deformation. The 2T1C pixel circuit refers to a pixel circuit including two transistors and a storage capacitor, for example, including a data write transistor, a drive transistor and a storage capacitor. The 7T1C pixel circuit refers to a pixel circuit including 7 transistors and a storage capacitor, for example, including a data write transistor, a drive transistor, a threshold compensation transistor, a first initialization transistor, a second initialization transistor, a first light emission control transistor, a second light emission control transistor and a storage capacitor. The array substrate may also include a plurality of first initialization signal lines and a second initialization signal line, the first initialization signal line providing an initialization voltage for the first initialization transistor, and the second initialization signal line providing an initialization voltage for the second initialization transistor.

[0076] In the process of implementing the present invention, the inventors found that the following problems exist in the related art: In order to reduce the voltage drop loss on the initialization signal line, the first initialization signal line and the second initialization signal line can be wired in a mesh wiring form, so that there are more wirings in the array substrate and the wiring density is relatively high. In addition, the power lines in the array substrate are also set to a mesh structure, so that the wiring density is further increased, and the pixel density of the array substrate is relatively high, which reduces the transmittance of the array substrate, affects the photosensitive devices in the display product to obtain light information, affects the sensitivity of fingerprint recognition, infrared recognition and video, and makes the display product have poor performance. If the line width or line spacing of the wiring is only compressed to improve the transmittance and pixel density, the process requirements will be higher, and the specification requirements for the mask will also be higher, resulting in increased costs.

[0077] In view of the above technical problems, an embodiment of the present invention provides an array substrate. Figure 1 is a schematic diagram of the structure of an array substrate provided by an embodiment of the present invention, with reference to Figure 1 , the array substrate comprises: a substrate 11 and a pixel circuit 12 located on the substrate 11;

[0078] The pixel circuit 12 includes a dual-gate transistor T1 and a first capacitor plate C1, and an orthographic projection of the first capacitor plate C1 at least partially covers an orthographic projection of a dual-gate node G1 of the dual-gate transistor T1 on the substrate 11;

[0079] A plurality of first capacitor plates C1 are electrically connected to form a conductive trace L1 , and the conductive trace is connected to a fixed potential signal.

[0080] Among them, the substrate 11 can be a hard substrate or a flexible substrate, which is not limited in this embodiment. The pixel circuit 12 includes a dual-gate transistor T1, which can be a threshold compensation transistor or an initialization transistor. The pixel circuit 12 also includes a driving transistor T2, which is connected to the dual-gate transistor T1. For example, the dual-gate transistor T1 is electrically connected to the control electrode of the driving transistor T2, which can reduce the leakage current of the control electrode of the driving transistor T2, thereby stabilizing the voltage of the control electrode of the driving transistor T2, and stabilizing the driving current generated by the driving transistor T2, so that the light-emitting element connected to the pixel circuit 12 can emit light stably, avoiding flickering of the display panel formed by the array substrate, and improving the display effect of the display panel formed by the array substrate.

[0081] The array substrate includes an active layer, and the active layer can connect the two gates of the dual-gate transistor T1, that is, the dual-gate node G1 of the dual-gate transistor T1 can be a part of the active layer. By setting a first capacitor plate C1, the first capacitor plate C1 covers at least part of the dual-gate node G1, and the first capacitor plate C1 and the dual-gate node G1 can form a voltage-stabilizing capacitor. The first capacitor plate C1 is connected to a fixed potential signal, and the voltage difference of the voltage-stabilizing capacitor remains unchanged, so the voltage-stabilizing capacitor can stabilize the potential of the dual-gate node G1, thereby stabilizing the gate voltage of the dual-gate transistor T1, which is conducive to the stable operation of the dual-gate transistor T1, reducing the leakage current of the dual-gate transistor T1, and then reducing the leakage current of the driving transistor T2, avoiding the current fluctuation of the driving transistor T2 and causing the display panel to flicker.

[0082] Specifically, the array substrate includes a plurality of pixel circuits 12, and the plurality of pixel circuits 12 are arranged in an array, and the array substrate includes a plurality of first capacitor plates C1, and the plurality of first capacitor plates C1 are electrically connected to form a conductive trace L1, which may be horizontally connected, vertically connected, or obliquely connected, and this embodiment does not limit this. Among them, the conductive trace L1 runs through the display area of ​​the array substrate. Figure 1 The case where multiple first capacitor plates C1 are connected horizontally is shown in the figure, but it is not limited. By setting multiple first capacitor plates C1 to be electrically connected to form a conductive trace L1, a fixed potential signal is connected to the conductive trace L1, that is, a DC signal line is formed, so that the conductive trace L1 can be reused as a trace on the array substrate, for example, it can be reused as a power line on the array substrate, it can also be reused as an initialization signal line on the array substrate, and it can also be reused as other traces carrying DC signals, so that the traces on the array substrate can be reduced, which is convenient for achieving high pixel density while improving the transmittance of the array substrate, avoiding affecting the photosensitive device, thereby improving the display effect of the display panel formed by the array substrate, which is beneficial to improving the display effect of the display panel. In addition, there is no need to set up additional traces, which can reduce process requirements and help reduce costs.

[0083] The technical solution of this embodiment is to set a first capacitor plate, and the first capacitor plate covers at least part of the dual-gate node of the dual-gate transistor in the positive projection on the substrate, so that the first capacitor plate and the dual-gate node form a voltage-stabilizing capacitor, and the first capacitor plate is connected to a fixed potential signal to maintain the potential of the dual-gate node, which can reduce the leakage current of the dual-gate transistor, and then reduce the leakage current of the driving transistor connected to the dual-gate transistor, so that the light-emitting element connected to the pixel circuit can emit light stably, and improve the display effect of the display panel. In addition, multiple first capacitor plates are electrically connected to form a conductive trace, so that the conductive trace can be reused as a trace carrying a DC signal on the array substrate, so that the traces on the array substrate can be reduced, which is convenient for achieving high pixel density while improving the transmittance of the array substrate, avoiding affecting the photosensitive device, thereby improving the display effect of the display panel formed by the array substrate, which is conducive to improving the display effect of the display panel.

[0084] Based on the above technical solutions, Figure 2 is a structural schematic diagram of another array substrate provided by an embodiment of the present invention. Figure 3 is a schematic diagram of the structure of another array substrate provided by an embodiment of the present invention. Figure 2 and Figure 3 The array substrate further includes a data line Data, which extends along a first direction Y, and a plurality of data lines Data are arranged along a second direction X. The data line Data can be connected to the pixel circuit 12 to provide a data voltage to the pixel circuit 12, so that the driving transistor T2 generates a driving current according to the data voltage.

[0085] A plurality of first capacitor plates C1 arranged along the first direction Y are electrically connected to form a conductive trace L1, and / or a plurality of first capacitor plates C1 arranged along the second direction X are electrically connected to form a conductive trace L1.

[0086] In one embodiment, reference Figure 2 , a plurality of first capacitor plates C1 arranged along the first direction Y are electrically connected to form a conductive trace L1. In this way, the conductive trace L1 can be reused as a trace extending along the first direction Y, thereby reducing the number of traces, which is conducive to achieving a higher pixel density and a higher light transmittance. It should be noted that Figure 2 The connection method of multiple first capacitor plates C1 is only schematically shown. When the connection lines between the first capacitor plates C1 affect other devices (such as the storage capacitor in the pixel circuit 12, etc.) or other wirings (such as the first initialization signal line or the second initialization signal line), different first capacitor plates C1 can be connected by jumpers to avoid affecting the settings of other devices or wirings.

[0087] In another embodiment, reference Figure 3The plurality of first capacitor plates C1 arranged along the second direction X are electrically connected to form a conductive trace L1. In this way, the conductive trace L1 can be reused as a trace extending along the second direction X, thereby reducing the number of traces, which is conducive to achieving a higher pixel density and a higher light transmittance.

[0088] On the basis of the above technical solution, the conductive trace L1 that can be reused is specifically described below, but it is not intended to limit the present application.

[0089] In one embodiment, Figure 4 is a structural schematic diagram of another array substrate provided by an embodiment of the present invention. Figure 5 is a schematic diagram of a pixel circuit provided by an embodiment of the present invention. Figure 4 and Figure 5 , the array substrate further includes a first initialization signal line Vref1 and a second initialization signal line Vref2; the pixel circuit 12 further includes a driving transistor T2, a first initialization transistor T3 and a second initialization transistor T4; the first initialization transistor T3 is connected between the first initialization signal line Vref1 and the driving transistor T2; the second initialization transistor T4 is connected between the second initialization signal line Vref2 and the light emitting element D1;

[0090] The conductive trace L1 is a first initialization signal line Vref1 or a second initialization signal line Vref2 .

[0091] Specifically, when the first initialization transistor T3 is turned on, the first initialization transistor T3 can transmit the first initialization signal on the first initialization signal line Vref1 to the driving transistor T2, for example, to the control electrode of the driving transistor T2, so as to reset the control electrode of the driving transistor T2, so that the driving transistor T2 can generate a driving current according to the data voltage, and avoid the residual charge of the previous frame from affecting the driving current. The first initialization transistor T3 can be a dual-gate initialization transistor, which is conducive to reducing the leakage current of the control electrode of the driving transistor T2, so that the driving transistor T2 can generate a stable driving current.

[0092] The pixel circuit 12 is connected to the light emitting element D1, which may be an organic light emitting diode. When the second initialization transistor T4 is turned on, the second initialization transistor T4 may transmit the second initialization signal on the second initialization signal line Vref2 to the light emitting element D1, thereby clearing the residual charge of the previous frame, so that the light emitting element D1 may better respond to the driving current of the driving transistor T2 to emit light.

[0093] By setting the conductive trace L1 as the first initialization signal line Vref1 or the second initialization signal line Vref2, that is, the conductive trace L1 can be reused as the first initialization signal line Vref1 or the second initialization signal line Vref2, the number of traces in the array substrate can be reduced, which is conducive to achieving a higher pixel density and a higher light transmittance. In addition, when the conductive trace L1 is the first initialization signal line Vref1 or the second initialization signal line Vref2, the conductive trace L1 does not need to be connected to the first power line VDD or the second power line VSS, so as to avoid the data line Data interfering with the power supply voltage of the first power line VDD and the second power line VSS when the conductive trace L1 is close to the data line Data, thereby avoiding affecting the driving current generated by the driving transistor T2.

[0094] It should be noted that Figure 4 FIG. 4 shows a case where the conductive line L1 is multiplexed as the first initialization signal line Vref1 , but this is not a limitation.

[0095] In another embodiment, Figure 6 is a schematic diagram of the structure of another array substrate provided by an embodiment of the present invention. Figure 5 and Figure 6 The array substrate further includes a first initialization signal line Vref1, a second initialization signal line Vref2, a first initialization network line Vin1, and a second initialization network line Vin2; the pixel circuit 12 further includes a driving transistor T2, a first initialization transistor T3, and a second initialization transistor T4; the first initialization transistor T3 is connected between the first initialization signal line Vref1 and the driving transistor T2; the second initialization transistor T4 is connected between the second initialization signal line Vref2 and the light emitting element D1;

[0096] The first initialization network line Vin1 is electrically connected to the first initialization signal line Vref1 to form a network structure, and the second initialization network line Vin2 is electrically connected to the second initialization signal line Vref2 to form a network structure;

[0097] The conductive trace L1 is a first initialization line Vin1 or a second initialization line Vin2.

[0098] Specifically, by setting the first initialization network cable Vin1 and the second initialization network cable Vin2, the first initialization network cable Vin1 is electrically connected to the first initialization signal line Vref1 to form a mesh structure, and the second initialization network cable Vin2 is electrically connected to the second initialization signal line Vref2 to form a mesh structure, the voltage drop loss on the first initialization signal line Vref1 and the second initialization signal line Vref2 can be reduced, thereby improving the stability and reliability of signal transmission.

[0099] The conductive line L1 is the first initialization line Vin1 or the second initialization line Vin2, that is, the conductive line L1 can be reused as the first initialization line Vin1 or the second initialization line Vin2, which can reduce the number of lines in the array substrate and is conducive to achieving higher pixel density and higher light transmittance.

[0100] It should be noted that Figure 6 The conductive line L1 is shown as the first initialization line Vin1, but this is not a limitation. To avoid affecting the second initialization signal line Vref2, the conductive line L1 (first initialization line Vin1) is connected to the first initialization signal line Vref1 through a jumper.

[0101] Optionally, refer to Figure 6 , the first initialization signal line Vref1 and the second initialization signal line Vref2 extend along the second direction X; the first initialization network line Vin1 and the second initialization network line Vin2 extend along the first direction Y. In this way, the first initialization signal line Vref1 and the first initialization network line Vin1 can be connected to form a mesh structure, and the second initialization signal line Vref2 and the second initialization network line Vin2 can be connected to form a mesh structure, which is convenient for reducing the voltage drop loss on the first initialization signal line Vref1 and the second initialization signal line Vref2.

[0102] In another embodiment, Figure 7 is a schematic diagram of the structure of another array substrate provided by an embodiment of the present invention. Figure 5 and Figure 7 , the array substrate further includes a first power line VDD and a second power line VSS; the pixel circuit 12 further includes a driving transistor T2; the first power line VDD is connected to the driving transistor T2, and the second power line VSS is electrically connected to the light emitting element D1 corresponding to the pixel circuit 12;

[0103] The conductive trace L1 is a first power line VDD or a second power line VSS.

[0104] Specifically, the first power line VDD can provide the first power supply voltage for the driving transistor T2, so that the driving transistor T2 can generate a driving current according to the data voltage and the first power supply voltage. By setting the second power line VSS, a current loop can be formed between the first power line VDD, the driving transistor T2, the light-emitting element D1 and the second power line VSS, so that the driving transistor T2 generates a driving current, so that the light-emitting element D1 emits light in response to the driving current.

[0105] By setting the conductive trace L1 as the first power line VDD or the second power line VSS, that is, the conductive trace L1 can be reused as the first power line VDD or the second power line VSS, the number of traces in the array substrate can be reduced, which is conducive to achieving a higher pixel density and a higher light transmittance. In addition, when the conductive trace L1 is reused as the second power line VSS, the second power line VSS can be set in the display area of ​​the array substrate without setting additional traces, thereby reducing the traces in the border area of ​​the array substrate, which is convenient for achieving a narrow border.

[0106] Optionally, refer to Figure 7 , the first power line VDD and the second power line VSS extend along the first direction Y. When the plurality of first capacitor plates C1 along the first direction Y are electrically connected to form a conductive trace L1, the conductive trace L1 can be used as the first power line VDD or the second power line VSS.

[0107] In another embodiment, Figure 8 is a schematic diagram of the structure of another array substrate provided by an embodiment of the present invention. Figure 5 and Figure 8 , the array substrate further includes a first power line VDD and a second power line VSS; the pixel circuit 12 further includes a driving transistor T2; the first power line VDD is connected to the driving transistor T2, and the second power line VSS is electrically connected to the light emitting element D1 corresponding to the pixel circuit 12;

[0108] The array substrate further includes a first power supply line Vd and a second power supply line Vs extending along the second direction X;

[0109] The first power network line Vd is electrically connected to the first power line VDD to form a mesh structure, and the second power network line Vs is electrically connected to the second power line VSS to form a mesh structure;

[0110] The conductive trace L1 is a first power line Vd or a second power line Vs.

[0111] Specifically, by arranging the first power network line Vd and the second power network line Vs, the first power network line Vd is electrically connected to the first power line VDD to form a mesh structure, and the second power network line Vs is electrically connected to the second power line VSS to form a mesh structure, which can reduce the voltage drop loss on the first power line VDD and the second power line VSS. In addition, by arranging the second power line VSS and the second power network line Vs in the display area of ​​the array substrate, the number of lines in the frame area of ​​the display panel formed by the array substrate can be reduced, which is conducive to reducing the size of the frame area of ​​the display panel formed by the array substrate, and is convenient for realizing a narrow frame.

[0112] By setting the conductive trace L1 as the first power grid line Vd or the second power grid line Vs, the number of traces in the array substrate can be reduced, which is conducive to achieving a higher pixel density and a higher light transmittance.

[0113] On the basis of the above technical solutions, the positional relationship between the first capacitor plate and other wirings is described below, but it is not intended to limit the present application.

[0114] Optionally, refer to Figure 2 , Figure 3 , Figure 7 or Figure 8 , the array substrate further includes a data line Data; the data line Data extends along a first direction Y, and a plurality of data lines Data are arranged along a second direction X; the first capacitor plate C1 includes a first portion C11, a second portion C12, and a third portion C13; the first portion C11 extends along the first direction Y, the second portion C12 extends along the second direction X, and the second portion C12 is connected between the first portion C11 and the third portion C13. In this way, the first capacitor plate C1 covers at least a portion of the dual-gate node G1, and the plurality of first capacitor plates C1 are electrically connected.

[0115] In one embodiment, optionally, reference Figure 2 or Figure 7 , the first parts C11 of the plurality of first capacitor plates C1 arranged along the first direction Y are electrically connected. In this way, it is convenient to electrically connect the plurality of first capacitor plates C1 arranged along the first direction Y to form a conductive line L1, so that the conductive line L1 is reused as a line extending along the first direction Y, for example, reused as a first power line VDD, a second power line VSS, a first initialization network line Vin1 or a second initialization network line Vin2.

[0116] In another embodiment, optionally, reference Figure 3 or Figure 8 , the first portion C11 is electrically connected to the third portion C13 of the first capacitor plate C1 adjacent to the second direction X. In this way, it is convenient to electrically connect a plurality of first capacitor plates C1 arranged along the second direction X to form a conductive trace L1, so that the conductive trace L1 is reused as a trace extending along the second direction X, for example, reused as a first power grid line Vd, a second power grid line Vs, a first initialization signal line Vref1 or a second initialization signal line Vref2.

[0117] Optionally, refer to Figure 2 or Figure 3, the third portion C13 covers at least a portion of the dual-gate node G1. In this way, the first capacitor plate C1 covers at least a portion of the dual-gate node G1, and the first capacitor plate C1 can form a voltage-stabilizing capacitor with the dual-gate node G1, which is beneficial to maintaining the potential of the dual-gate node G1, reducing the leakage current of the dual-gate transistor T1, and further reducing the leakage current of the driving transistor T2.

[0118] On the basis of the above technical solution, optionally, refer to Figure 7 or Figure 8 , the orthographic projection of the first portion C11 on the substrate 11 overlaps with the orthographic projection of the first power line VDD on the substrate 11. In this way, the conductive trace L1 after the first capacitor plate C1 is electrically connected can be reused as the first power line VDD, or the conductive trace L1 after the first capacitor plate C1 is electrically connected is connected to the first power line VDD, thereby being reused as the first power network line Vd. In addition, it can avoid that the trace occupies a large space in the first direction Y or the second direction X, which is conducive to achieving a higher pixel density and a higher light transmittance.

[0119] Optionally, refer to Figure 7 or Figure 8 , at least part of the orthographic projection of the first portion C11 on the substrate 11 is located between the orthographic projection of the first power line VDD on the substrate 11 and the orthographic projection of the data line Data on the substrate 11. In this way, the first portion C11 can isolate the data line Data from the first power line VDD, improve the crosstalk between the signals on the data line Data and the first power line VDD, and help improve the stability and accuracy of the data voltage transmitted on the data line Data.

[0120] Optionally, refer to Figure 8 The pixel circuit 12 further includes a first active portion 101 connected to the control electrode of the driving transistor T2 of the pixel circuit 12, and the first capacitor plate C1 covers at least a portion of the first active portion 101. In this way, the first capacitor plate C1 can isolate the first active portion 101 from the data line Data, thereby preventing the data line Data from interfering with the signal of the control electrode of the driving transistor T2.

[0121] Optionally, refer to Figure 7 or Figure 8 At least part of the orthographic projection of the first portion C11 on the substrate 11 is located between the orthographic projection of the data line Data on the substrate 11 and the orthographic projection of the first active portion 101 on the substrate 11. In this way, the first capacitor plate C1 can further isolate the first active portion 101 from the data line Data, thereby shielding the data line Data from the control electrode of the driving transistor T2.

[0122] On the basis of the above technical solution, optionally, refer to Figure 2, two first portions C11 adjacent to each other along the first direction Y are connected by the first connection portion L0; at least part of the orthographic projection of the first connection portion L0 on the substrate 11 is located between the orthographic projection of the control electrode T21 of the driving transistor T2 of the pixel circuit 12 and the orthographic projection of the data line Data on the substrate 11. In this way, when the plurality of first capacitor plates C1 arranged along the first direction Y are electrically connected, the first connection portion L0 can isolate the data line Data from the control electrode T21 of the driving transistor T2, thereby preventing the data line Data from affecting the potential of the control electrode of the driving transistor T2, thereby ensuring that the driving transistor T2 can generate a driving current according to the transmitted data voltage, and can ensure the stability of the driving current generated by the driving transistor T2, which is beneficial to improving the display effect of the display panel.

[0123] On the basis of the above technical solution, optionally, refer to Figure 7 or Figure 8 The pixel circuit 12 further includes a storage capacitor Cst and a driving transistor T2, wherein a first electrode of the storage capacitor Cst is electrically connected to a control electrode T21 of the driving transistor T2, and a second electrode of the storage capacitor Cst is connected to a first power line VDD. Thus, the potential of the second electrode of the storage capacitor Cst is a fixed potential, and the storage capacitor Cst can store the voltage transmitted to the control electrode T21 of the driving transistor T2 and maintain the potential of the control electrode T21 of the driving transistor T2.

[0124] Optionally, refer to Figure 7 or Figure 8 , the storage capacitor Cst includes a second capacitor plate C2 and a third capacitor plate C3;

[0125] A plurality of third capacitor plates C3 arranged along the second direction X are electrically connected to form a first power network line Vd, and the first power network line Vd is electrically connected to the first power line VDD to form a mesh structure. In this way, there is no need to additionally set up a first power network line, which can further reduce the routing of the array substrate, save wiring space, and thus improve the pixel density and light transmittance of the display panel.

[0126] Optionally, the second capacitor plate C2 is the control electrode T21 of the driving transistor T2. In this way, the number of capacitor plates and metal layers can be reduced, which is beneficial to reducing the thickness of the array substrate and facilitating the thin and light design of the array substrate.

[0127] On the basis of the above technical solution, optionally, refer to Figure 7 , the double-gate transistor T1 includes a first gate T11 and a second gate T12;

[0128] The pixel circuit 12 further includes a second active portion 102, the second active portion 102 is located between the orthographic projection of the first gate T11 on the substrate 11 and the orthographic projection of the second gate T12 on the substrate 11, and the second active portion 102 is a double gate node G1;

[0129] The first capacitor plate C1 and the second active portion 102 form a voltage-stabilizing capacitor C0 , and the voltage-stabilizing capacitor C0 is used to maintain the potential of the dual-gate node G1 .

[0130] Specifically, the first capacitor plate C1 covers at least a portion of the dual-gate node G1, so that the first capacitor plate C1 and the dual-gate node G1 (the second active portion 102) form a voltage-stabilizing capacitor C0. The first capacitor plate C1 in the voltage-stabilizing capacitor C0 is connected to a fixed potential signal, and the voltage difference of the voltage-stabilizing capacitor C0 remains unchanged, so that the potential of the dual-gate node G1 can be maintained, thereby reducing the leakage current of the dual-gate transistor T1 and the leakage current of the driving transistor T2, thereby ensuring the stability of the driving current generated by the driving transistor T2.

[0131] On the basis of the above technical solutions, optionally, refer to Figure 5 , the pixel circuit 12 also includes a first light-emitting control transistor T5, a first electrode of the first light-emitting control transistor T5 is electrically connected to the first power line VDD, and a second electrode of the first light-emitting control transistor T5 is electrically connected to the first electrode of the driving transistor T2; the control electrode of the first light-emitting control transistor T5 is connected to the light-emitting control line EM; the first light-emitting control transistor T5 is used to respond to the light-emitting control signal of the light-emitting control line EM to control whether the first power supply voltage on the first power line VDD is transmitted to the first electrode of the driving transistor T2. In this way, in the non-light-emitting stage, the light-emitting control signal on the light-emitting control line EM controls the first light-emitting control transistor T5 to turn off, so that the driving transistor T2 does not generate a driving current, so that the light-emitting element D1 does not emit light. In the light-emitting stage, the light-emitting control signal on the light-emitting control line EM controls the first light-emitting control transistor T5 to turn on, and the first light-emitting control transistor T5 transmits the first power supply voltage on the first power line VDD to the first electrode of the driving transistor T2, so that the driving transistor T2 generates a driving current according to the first power supply voltage and the data voltage, so that the corresponding light-emitting element D1 emits light in response to the driving current.

[0132] Optionally, refer to Figure 5, the pixel circuit 12 further includes a second light-emitting control transistor T6, a first electrode of the second light-emitting control transistor T6 is electrically connected to the second electrode of the driving transistor T2, a second electrode of the second light-emitting control transistor T6 is electrically connected to the first electrode of the light-emitting element D1, and a control electrode of the second light-emitting control transistor T6 is connected to the light-emitting control line EM; the second light-emitting control transistor T6 is used to respond to the light-emitting control signal of the light-emitting control line EM to control whether the driving current of the driving transistor T2 is transmitted to the light-emitting element D1; the second electrode of the light-emitting element D1 is connected to the second power line VSS. In this way, in the non-light-emitting stage, the light-emitting control signal on the light-emitting control line EM controls the second light-emitting control transistor T6 to turn off, so that the driving current generated by the driving transistor T2 will not be transmitted to the light-emitting element D1, so that the light-emitting element D1 does not emit light. In the light-emitting stage, the light-emitting control signal on the light-emitting control line EM controls the first light-emitting control transistor T5 and the second light-emitting control transistor T6 to be turned on, and the first power line VDD, the first light-emitting control transistor T5, the driving transistor T2, the second light-emitting control transistor T6, the light-emitting element D1 and the second power line VSS form a current loop, and the driving transistor T2 generates a driving current according to the first power supply voltage and the data voltage, so that the corresponding light-emitting element D1 emits light in response to the driving current.

[0133] Optionally, refer to Figure 5 , the first electrode of the dual-gate transistor T1 is electrically connected to the second electrode of the driving transistor T2, the second electrode of the dual-gate transistor T1 is electrically connected to the control electrode of the driving transistor T2, and the control electrode of the dual-gate transistor T1 is connected to the first scanning line S1; the dual-gate transistor T1 is used to respond to the first scanning signal on the first scanning line S1 to perform threshold compensation on the driving transistor T2. That is, the dual-gate transistor T1 is a threshold compensation transistor. In the threshold compensation stage of the pixel circuit driving process, the first scanning signal on the first scanning line S1 controls the dual-gate transistor T1 to be turned on, so that the dual-gate transistor T1 performs threshold compensation on the driving transistor T2, so that the driving current generated by the driving transistor T2 is independent of the threshold voltage of the driving transistor T2, and the change of the driving current caused by the threshold voltage fluctuation of the driving transistor T2 can be avoided, so that the light-emitting element D1 can emit light stably, avoid flickering of the display panel, and improve the display effect of the display panel.

[0134] Optionally, refer to Figure 5, the pixel circuit 12 also includes a data writing transistor T7, a first electrode of the data writing transistor T7 is connected to the data line Data, a second electrode of the data writing transistor T7 is electrically connected to the first electrode of the driving transistor T7, and a control electrode of the data writing transistor T7 is connected to the first scanning line S1; the data writing transistor T7 is used to respond to the first scanning signal on the first scanning line S1 to transmit the data voltage on the data line Data to the driving transistor T2. In this way, the first scanning signal on the first scanning line S1 can control the dual-gate transistor T1 and the data writing transistor T7, so that threshold compensation can be achieved in the data writing stage. In the data writing and threshold compensation stage of the pixel circuit driving process, the first scanning signal on the first scanning line S1 controls the data writing transistor T7 to turn on, and the data writing transistor T7 transmits the data voltage on the data line Data to the control electrode of the driving transistor T2. In addition, the first scanning signal on the first scanning line S1 controls the dual-gate transistor T1 to turn on, so that the dual-gate transistor T1 performs threshold compensation on the driving transistor T2, and the data voltage after threshold compensation can be written to the control electrode of the driving transistor T2, so that the driving transistor T2 can generate a driving current according to the data voltage after threshold compensation.

[0135] Optionally, refer to Figure 5 , the array substrate further includes a first initialization signal line Vref1 and a second initialization signal line Vref2;

[0136] The pixel circuit 12 further includes a first initialization transistor T3 and a second initialization transistor T4; the first initialization transistor T3 is connected between the first initialization signal line Vref1 and the control electrode of the driving transistor T2; the second initialization transistor T4 is connected between the second initialization signal line Vref2 and the light-emitting element D1; the control electrode of the first initialization transistor T3 and the control electrode of the second initialization transistor T4 are connected to the second scan line S2; the first initialization transistor T3 is used to initialize the control electrode of the driving transistor T2 in response to the second scan signal on the second scan line S2, and the second initialization transistor T4 is used to initialize the light-emitting element D1 in response to the second scan signal on the second scan line S2. In this way, in the initialization stage of the pixel circuit driving process, the second scan line signal on the second scan line S2 controls the first initialization transistor T3 and the second initialization transistor T4 to turn on, and the first initialization transistor T3 can transmit the first initialization signal on the first initialization signal line Vref1 to the driving transistor T2, for example, to the control electrode of the driving transistor T2, thereby resetting the control electrode of the driving transistor T2, so that the driving transistor T2 can generate a driving current according to the data voltage, avoiding the residual charge of the previous frame from affecting the driving current. The second initialization transistor T4 can transmit the second initialization signal on the second initialization signal line Vref2 to the light emitting element D1 , thereby clearing the residual charge of the previous frame, so that the light emitting element D1 can better respond to the driving current of the driving transistor T2 to emit light.

[0137] It should be noted that Figure 5 1 shows the case where all transistors in the pixel circuit 12 are P-type transistors, but this is not limiting. In some other embodiments, all transistors in the pixel circuit 12 may be N-type transistors. Alternatively, some transistors in the pixel circuit 12 are N-type transistors, and the other transistors are P-type transistors.

[0138] On the basis of the above-mentioned technical solutions, the film layers where each routing may be located are described below, but this is not intended to limit the present application.

[0139] Fig. 9 yes Figure 8 A cross-sectional view along the direction a1-a2, optionally, referring to Fig. 9 , the array substrate includes a first conductive layer M1, a second conductive layer M2, a third conductive layer M3 and a fourth conductive layer M4 located on a substrate 11;

[0140] The first scan line S1, the second scan line S2 and the light emitting control line EM are located in the first conductive layer M1;

[0141] At least a portion of the first initialization signal lines Vref1 and at least a portion of the second initialization signal lines Vref2 are located in the second conductive layer M2;

[0142] Fig.10 yes Figure 8 A cross-sectional view along the b1-b2 direction, optionally, referring to Fig.10 , a first power line VDD and a second power line VSS are located in a third conductive layer M3;

[0143] The data line Data is located in the fourth conductive layer M4.

[0144] Specifically, in some embodiments, the first initialization signal line Vref1 and the second initialization signal line Vref2 are located in the second conductive layer M2. In some embodiments, a portion of the first initialization signal lines Vref1 are located in the second conductive layer M2, and another portion of the first initialization signal lines Vref1 are located in the third conductive layer M3. A portion of the second initialization signal lines Vref2 are located in the second conductive layer M2, and another portion of the second initialization signal lines Vref2 are located in the third conductive layer M3. This embodiment is not limited. Fig. 9 FIG. 4 shows a case where the first initialization signal line Vref1 and the second initialization signal line Vref2 are located in the second conductive layer M2 , but this is not limiting.

[0145] By arranging the first power line VDD and the second power line VSS in the third conductive layer M3 and the data line Data in the fourth conductive layer M4, the crosstalk between the data line Data and the power lines (the first power line VDD and the second power line VSS) can be reduced to ensure the accuracy and stability of signal transmission.

[0146] Alternatively, if Fig. 9 As shown, the first capacitor plate C1 is located in the second conductive layer M2, so that the first capacitor plate C1 is close to the dual gate node G1, which facilitates the first capacitor plate C1 and the dual gate node G1 to form a voltage-stabilizing capacitor.

[0147] In one embodiment, the conductive trace L1 formed by the electrical connection of the first capacitor plate C1 is located in the second conductive layer M2, and the conductive trace L1 can be the first initialization signal line Vref1 or the second initialization signal line Vref2. Figure 4 As shown, the conductive trace L1 formed by the electrical connection of the first capacitor plate C1 is located in the second conductive layer M2, and the conductive trace L1 is the first initialization signal line Vref1.

[0148] In another embodiment, a portion of the conductive trace L1 formed by the electrical connection of the first capacitor plate C1 is located in the second conductive layer M2, and another portion of the conductive trace L1 is located in the third conductive layer M3. This facilitates the jumper connection. The conductive trace L1 can be the first initialization network line Vin1, the second initialization network line Vin2, the first power line VDD, the second power line VSS, the first power network line Vd, or the second power network line Vs. For example, Figure 6 As shown, part of the conductive trace L1 formed by the electrical connection of the first capacitor plate C1 is located in the second conductive layer M2, and another part of the conductive trace L1 is located in the third conductive layer M3. The conductive trace L1 is the first initialization network line Vin1. Figure 7 As shown, part of the conductive trace L1 formed by the electrical connection of the first capacitor plate C1 is located in the second conductive layer M2, and another part of the conductive trace L1 is located in the third conductive layer M3. The conductive trace L1 is the first power line VDD.

[0149] It should be noted that when the first capacitor plate C1 needs a jumper connection, the following can be used: Figure 6 or Figure 7 The connection can be made in the form of, or in other feasible ways. Figure 6 and Figure 7 This is for illustration only and is not intended to be limiting.

[0150] On the basis of the above technical solutions, optionally, the first initialization mesh wire Vin1 and the second initialization mesh wire Vin2 are arranged alternately. In this way, the number of the first initialization mesh wire Vin1 and the second initialization mesh wire Vin2 can be reduced, and the arrangement of the first initialization signal wire Vref1 and the second initialization signal wire Vref1 can be uniform, thereby making the voltage drop on the first initialization signal wire Vref1 and the second initialization signal wire Vref1 more uniform, which is convenient for improving the display uniformity of the display panel.

[0151] An embodiment of the present invention further provides a display panel. Fig.11 is a schematic diagram of a display panel provided by an embodiment of the present invention, with reference to Fig.11 The display panel 20 includes the array substrate 21 provided by any embodiment of the present invention, and thus has the same beneficial effects as the array substrate provided by any embodiment of the present invention, which will not be described in detail here. The display panel can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, etc.

[0152] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An array substrate, It is characterized in that include: A substrate and a pixel circuit located on the substrate; The pixel circuit comprises a dual-gate transistor and a first capacitor plate, wherein an orthographic projection of the first capacitor plate at least partially covers an orthographic projection of a dual-gate node of the dual-gate transistor on a substrate; The plurality of first capacitor plates are electrically connected to form a conductive trace, and the conductive trace is connected to a fixed potential signal.

2. The array substrate according to claim 1, It is characterized in that The array substrate further comprises a data line; the data line extends along a first direction, and a plurality of the data lines are arranged along a second direction; A plurality of first capacitor plates arranged along the first direction are electrically connected to form the conductive trace, and / or a plurality of first capacitor plates arranged along the second direction are electrically connected to form the conductive trace.

3. The array substrate according to claim 1, It is characterized in that The array substrate further comprises a first initialization signal line and a second initialization signal line; The pixel circuit further includes a driving transistor, a first initialization transistor and a second initialization transistor; the first initialization transistor is connected between the first initialization signal line and the driving transistor; the second initialization transistor is connected between the second initialization signal line and the light emitting element corresponding to the pixel circuit; The conductive trace is the first initialization signal line or the second initialization signal line.

4. The array substrate according to claim 1, It is characterized in that The array substrate further includes a first initialization signal line, a second initialization signal line, a first initialization network line, and a second initialization network line; The pixel circuit further includes a driving transistor, a first initialization transistor and a second initialization transistor; the first initialization transistor is connected between the first initialization signal line and the driving transistor; the second initialization transistor is connected between the second initialization signal line and the light emitting element corresponding to the pixel circuit; The first initialization network cable is electrically connected to the first initialization signal line to form a mesh structure, and the second initialization network cable is electrically connected to the second initialization signal line to form a mesh structure; The conductive wire is the first initialization network wire or the second initialization network wire; Preferably, the first initialization signal line and the second initialization signal line extend along the second direction; the first initialization network cable and the second initialization network cable extend along the first direction.

5. The array substrate according to claim 1, It is characterized in that The array substrate further includes a first power line and a second power line; the pixel circuit further includes a driving transistor; the first power line is connected to the driving transistor, and the second power line is electrically connected to the light emitting element corresponding to the pixel circuit; The conductive trace is the first power line or the second power line; Preferably, the first power line and the second power line extend along a first direction.

6. The array substrate according to claim 1, It is characterized in that The array substrate further includes a first power line and a second power line; the pixel circuit further includes a driving transistor; the first power line is connected to the driving transistor, and the second power line is electrically connected to the light emitting element corresponding to the pixel circuit; The array substrate further comprises a first power supply network cable and a second power supply network cable extending along a second direction; The first power network cable is electrically connected to the first power line to form a mesh structure, and the second power network cable is electrically connected to the second power line to form a mesh structure; The conductive trace is the first power network cable or the second power network cable.

7. The array substrate according to claim 1, It is characterized in that The array substrate further includes a data line; the data line extends along a first direction, and a plurality of the data lines are arranged along a second direction; the first capacitor plate includes a first portion, a second portion and a third portion; The first portion extends along the first direction, the second portion extends along the second direction, and the second portion is connected between the first portion and the third portion; The first portions of the plurality of first capacitor plates arranged along the first direction are electrically connected; Alternatively, the first portion is electrically connected to a third portion of the first capacitor plate adjacent in the second direction; Preferably, the orthographic projection of the third portion on the substrate at least partially covers the orthographic projection of the dual-gate node.

8. The array substrate according to claim 7, It is characterized in that The array substrate further includes a first power line; The orthographic projection of the first portion on the substrate overlaps with the orthographic projection of the first power line on the substrate; Preferably, at least part of the orthographic projection of the first portion on the substrate is located between the orthographic projection of the first power line on the substrate and the orthographic projection of the data line on the substrate; Preferably, the pixel circuit further comprises a first active portion connected to a control electrode of a driving transistor of the pixel circuit, and an orthographic projection of the first capacitor plate on the substrate at least partially covers an orthographic projection of the first active portion; Preferably, at least a portion of the orthographic projection of the first portion on the substrate is located between the orthographic projection of the data line on the substrate and the orthographic projection of the first active portion on the substrate.

9. The array substrate according to claim 7, It is characterized in that Two first portions adjacent to each other along the first direction are connected by a first connecting portion; the first connecting portion is located between the orthographic projection of the control electrode of the driving transistor of the pixel circuit and the orthographic projection of the data line on the substrate at least in part of the orthographic projection of the substrate.

10. The array substrate according to claim 1, It is characterized in that The pixel circuit further comprises a storage capacitor and a driving transistor, wherein a first electrode of the storage capacitor is electrically connected to a control electrode of the driving transistor, and a second electrode of the storage capacitor is connected to a first power line; Preferably, the storage capacitor comprises a second capacitor plate and a third capacitor plate; The plurality of third capacitor plates arranged along the second direction are electrically connected to form a first power network cable, and the first power network cable is electrically connected to the first power line to form a mesh structure; Preferably, the second capacitor plate is a control electrode of the driving transistor.

11. The array substrate according to claim 1, It is characterized in that The dual-gate transistor includes a first gate and a second gate; The pixel circuit further includes a second active portion, the second active portion is located between an orthographic projection of the first gate on the substrate and an orthographic projection of the second gate on the substrate, and the second active portion is the dual-gate node; The first capacitor plate and the second active portion form a voltage-stabilizing capacitor, and the voltage-stabilizing capacitor is used to maintain the potential of the dual-gate node.

12. The array substrate according to claim 5 or 6, It is characterized in that The pixel circuit further includes a first light emission control transistor, a first electrode of the first light emission control transistor is electrically connected to the first power line, a second electrode of the first light emission control transistor is electrically connected to the first electrode of the driving transistor; and a control electrode of the first light emission control transistor is connected to a light emission control line; The first light emission control transistor is used to control whether the first power supply voltage on the first power supply line is transmitted to the first electrode of the driving transistor in response to the light emission control signal of the light emission control line; Preferably, the pixel circuit further comprises a second light emitting control transistor, a first electrode of the second light emitting control transistor is electrically connected to a second electrode of the driving transistor, a second electrode of the second light emitting control transistor is electrically connected to a first electrode of the light emitting element, and a control electrode of the second light emitting control transistor is connected to a light emitting control line; The second light emitting control transistor is used for controlling whether the driving current of the driving transistor is transmitted to the light emitting element in response to the light emitting control signal of the light emitting control line; The second electrode of the light emitting element is connected to the second power line; Preferably, the first electrode of the dual-gate transistor is electrically connected to the second electrode of the driving transistor, the second electrode of the dual-gate transistor is electrically connected to the control electrode of the driving transistor, and the control electrode of the dual-gate transistor is connected to a first scanning line; the dual-gate transistor is used to perform threshold compensation on the driving transistor in response to a first scanning signal on the first scanning line; Preferably, the pixel circuit further comprises a data writing transistor, a first electrode of the data writing transistor is connected to the data line, a second electrode of the data writing transistor is electrically connected to the first electrode of the driving transistor, and a control electrode of the data writing transistor is connected to the first scanning line; the data writing transistor is used to transmit the data voltage on the data line to the driving transistor in response to the first scanning signal on the first scanning line; Preferably, the array substrate further comprises a first initialization signal line and a second initialization signal line; The pixel circuit also includes a first initialization transistor and a second initialization transistor; the first initialization transistor is connected between the first initialization signal line and the control electrode of the driving transistor; the second initialization transistor is connected between the second initialization signal line and the light-emitting element; the control electrode of the first initialization transistor and the control electrode of the second initialization transistor are connected to a second scan line; the first initialization transistor is used to initialize the control electrode of the driving transistor in response to a second scan signal on the second scan line, and the second initialization transistor is used to initialize the light-emitting element in response to a second scan signal on the second scan line.

13. The array substrate according to claim 12, It is characterized in that The array substrate comprises a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer located on the substrate; The first scanning line, the second scanning line and the light emitting control line are located in the first conductive layer; At least a portion of the first initialization signal lines and at least a portion of the second initialization signal lines are located in the second conductive layer; The first power line and the second power line are located in the third conductive layer; The data line is located in the fourth conductive layer; Preferably, the first capacitor plate is located in the second conductive layer; Preferably, the conductive trace formed by the electrical connection of the first capacitor plates is located in the second conductive layer; or, part of the conductive trace formed by the electrical connection of the first capacitor plates is located in the second conductive layer, and another part of the conductive trace is located in the third conductive layer.

14. The array substrate according to claim 4, It is characterized in that The first initialization network cables and the second initialization network cables are arranged alternately.

15. A display panel, It is characterized in that Comprising the array substrate according to any one of claims 1 to 14.

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