Structure and method for testing GIDL of MOS field effect transistor

Abstract

The invention provides a structure and a method for testing a field effect transistor (GIDL) of a metal oxide semiconductor (MOS), which belong to the technical field of integrated circuits, and are characterized in that a PAD is arranged as a control end, a reverse bias diode is connected between the control end and a grounding end, and a fuse is connected between a G end and the control end. On the basis of a conventional MOSFET test structure in the prior art, a fuse device connection and a PAD for control are added, so that the same structure is realized, test items of the conventional MOSFET can be tested, and the added fuse device can be burnt off by controlling the voltage of the PAD and the GATE, so that a structure capable of supporting a GIDL test is realized.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a structure and method for testing a MOS field effect transistor GIDL. Background Art

[0002] As the size of integrated circuits continues to shrink, leakage problems become more and more serious. Static power consumption, also known as leakage power consumption, is the power consumption generated by leakage current when the circuit is in a waiting or inactive state. Leakage current includes many forms. When the device in the circuit is in the off state or in the waiting state, gate-induced drain leakage (GIDL) is the dominant one.

[0003] In integrated circuit design, static power consumption directly affects the total power consumption and operating temperature of the chip, which in turn affects the reliability and life of the system. With the development of technology, designing circuits with low static power consumption has become the key to improving energy efficiency and reducing heat dissipation requirements. Therefore, the measurement of device leakage and the evaluation of circuit static power consumption are becoming increasingly important.

[0004] From the perspective of the device IV curve of the metal-oxide-semiconductor field-effect transistor (MOSFET), when measuring the Id-Vg curve, Vg<0 is the GIDL characteristic of the device. The GIDL test of MOS field-effect transistors is an indispensable test item in the integrated circuit process, and a specially designed test structure is required. Taking the test structure of N-type MOSFET as an example, the conventional test structure of the device in the existing technology (such as G terminal positive voltage, device opening related tests) is as follows Figure 1 However, GIDL tests the case where the voltage at the G terminal is negative and the voltage at the D terminal is positive. Figure 1 If the structure is not good, all the current will escape from the diode and the leakage current cannot be measured. Therefore, the diode needs to be removed to test GIDL. Figure 2 This results in incompatibility between other MOSFET test structures and the GIDL test structure, which requires the design of two types of test structures, resulting in an increase in design effort and test structure area. Summary of the invention

[0005] The purpose of the present invention is to provide a structure and method for testing a MOS field effect transistor GIDL to solve the technical problem that the prior art mentioned in the above background technology requires designing two types of test structures, resulting in increased design investment and test structure area.

[0006] To achieve the above object, the present invention provides the following technical solutions: A structure for testing a MOS field effect transistor GIDL includes setting a PAD as a control terminal (CTRL), connecting a reverse biased diode (Diode) between the control terminal and a ground terminal (VSS), and connecting a fuse (fuse) between a G terminal and the control terminal.

[0007] Preferably, the fuse is a poly fuse or a metal fuse.

[0008] Another object of the present invention is to provide a method for testing MOS field effect transistor GIDL. Based on the above structure, for conventional testing of MOS field effect transistors: the voltage at the G terminal is positive, the device is turned on, positive voltages are applied to both the G terminal and the D terminal, and the control terminal is floating; when testing the GIDL of the MOS field effect transistor, it is divided into the following two steps: the first step is to control the voltage difference between the G terminal and the control terminal so that a large current continues to flow through the fuse until it burns out; the second step is to add a negative voltage to the G terminal and a positive voltage to the D terminal to test GIDL.

[0009] The present invention has the following beneficial effects: 1. One test structure to test multiple characteristics of the device (G terminal connected to positive or negative pressure).

[0010] 2. Save the area and design investment of the test structure and reduce costs.

[0011] The present invention adds a fuse device connection and a PAD for control on the basis of the conventional MOSFET test structure of the existing process, so as to realize the same structure, which can not only test the test items of the conventional MOSFET (such as the linear and saturation test of Id, etc.), but also burn out the added fuse device by controlling the voltage of PAD and GATE, so as to realize the structure that can support GIDL test. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0013] Figure 1 It is a conventional test structure for MOSFET; Figure 2 The structures needed to test GIDL; Figure 3 It is a schematic diagram of the N-type MOSFET test structure; Figure 4Schematic diagram of the test Id-Vg curve of N-type MOSFET (curve showing the change of drain current Id with gate voltage Vg). DETAILED DESCRIPTION

[0014] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0015] See also Figure 3-Figure 4 As shown in FIG. 1 , a structure for testing a MOS field effect transistor GIDL is provided, a PAD is set as a control terminal (CTRL), a reverse biased diode (Diode) is connected between the control terminal and a ground terminal (VSS), and a fuse (fuse) is connected between the G terminal and the control terminal. The test structure diagram is shown in FIG. Figure 3 As shown in the figure, the three PADs G, S and D are connected to the gate, source and drain of the device respectively, and the substrate (BULK) of the device is grounded to VSS.

[0016] The fuse uses a poly fuse or a metal fuse. Based on the thermal effect caused by current overload or circuit failure, its internal material melts and the circuit is cut off. It is usually composed of a wire, and the melting point of the wire material is generally set to be slightly higher than the temperature when the circuit is working normally. When current passes through, it will conduct current under normal circumstances. If the current exceeds its rated current, it will generate heat and the temperature will rise. As the temperature rises, the wire material eventually reaches its melting point and the wire melts. That is, it can be achieved by controlling the voltage difference at both ends to allow a large current to flow through, and burn it for a period of time, so as to achieve the effect of opening the connection relationship.

[0017] The testing method of the structure of the present invention is as follows: 1. Conventional test for MOSFET: The voltage at the G terminal is positive, and the device is turned on. Figure 3 The G and D terminals in the test are both positively voltageed, and the control terminal is left floating. Figure 4 The right half of the vertical axis is shown.

[0018] 2. The GIDL test for MOSFET is divided into the following two steps: The first step is to control the voltage difference between G and the control terminal so that the fuse continues to have a large current until it burns out; The second step is to add negative pressure to the G end and positive pressure to the D end to test GIDL. The test curve is as follows Figure 4 The left half of the vertical axis is shown.

[0019] The overall scheme of the present invention is to add a fuse device between the G terminal and the diode (Diode) on the basis of the conventional test structure, and to add a PAD (CTRL) at the same time, so that the same test structure can not only test the IV characteristics of the conventional MOSFET, but also burn the fuse device by controlling the voltage difference between G and CTRL to perform the GIDL test of the MOSFET. This scheme can save the design investment and layout area of ​​the test structure.

[0020] The test structure and principle for P-type MOSFET are similar.

[0021] The preferred embodiments of the present invention disclosed above are only used to help explain the present invention. The preferred embodiments do not describe all the details in detail, nor do they limit the invention to the specific implementation methods described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well.

Claims

1. A structure for testing a MOS field effect transistor GIDL, characterized in that: A PAD is set as a control terminal, a reverse biased diode is connected between the control terminal and the ground terminal, and a fuse is connected between the G terminal and the control terminal.

2. A structure for testing a MOS field effect transistor GIDL according to claim 1, characterized in that: The fuse is a polymer fuse or a metal fuse.

3. A method for testing a MOS field effect transistor GIDL, based on the structure of claim 1, characterized in that: Conventional test for MOS field effect transistors: the voltage at the G terminal is positive, the device is turned on, positive voltage is applied to both the G terminal and the D terminal, and the control terminal is floating; when testing the GIDL of MOS field effect transistors, it is divided into the following two steps: the first step is to control the voltage difference between the G terminal and the control terminal so that a large current continues to flow through the fuse until it burns out; the second step is to add a negative voltage to the G terminal and a positive voltage to the D terminal to test the GIDL.

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