Radar signal processing method, integrated circuit, radio device and terminal equipment

Abstract

The embodiment of the invention relates to the technical field of laser radars, and discloses a radar signal processing method, an integrated circuit, a radio device and terminal equipment, in the application, when a transceiver circuit waits for a working clock to reach P working clock cycles, the transmission of a chirp signal of a next frame is started; when the analog-to-digital converter waits for the work clock of the analog-to-digital converter to reach K work clock cycles, sampling of a frequency mixing signal is started, and the frequency mixing signal is obtained by utilizing the chirp signal and the corresponding echo signal; wherein the P working clock cycles and the K working clock cycles are used for timing the duration of the same frame interval, so that the phase error of a front frame and a rear frame at the beginning of sampling of the analog-to-digital converter is avoided, the ADC sampling operation and the transmitting operation of the transmitting and receiving circuit can tend to stably correspond, and the accuracy when a plurality of continuous frames are used for measurement is ensured.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of radar technology, and in particular to a radar signal processing technology. Background Art

[0002] In application scenarios such as automobiles, radar sensors use multiple transmitted electromagnetic waves and their corresponding echoes to measure the physical quantities between them and surrounding objects. This requires the transceiver circuit and ADC (Analog-to-digital converter) in the radar sensor to stably convert the analog signal generated based on the echo into a digital signal in each transmission cycle, so as to use the digital signal to calculate the corresponding physical quantity. The stable operation includes but is not limited to: reducing the phase deviation fluctuation between at least two transmitted signals and the corresponding digital signal.

[0003] In order to improve the measurement accuracy in engineering, the stable correspondence between the transmission operation of the transceiver circuit and the sampling operation of the ADC needs to be improved. Summary of the invention

[0004] The purpose of the embodiments of the present invention is to provide a radar signal processing method, an integrated circuit, a radio device and a terminal device, so that when the transceiver circuit transmits the first chirp of the previous and next frames, the ADC sampling operation and the transmission operation of the transceiver circuit can tend to correspond stably, so as to reduce the fluctuation of the phase deviation between the digital signal output by the ADC and the transmission signal (also called chirp, chirp signal).

[0005] To solve the above technical problems, an embodiment of the present invention provides a radar signal processing method, comprising:

[0006] When the transceiver circuit waits for its working clock to reach P working clock cycles, it starts transmitting the chirp signal of the next frame;

[0007] When the analog-to-digital converter waits for its working clock to reach K working clock cycles, it starts sampling the mixing signal, wherein the mixing signal is obtained using the chirp signal and its corresponding echo signal; wherein the P working clock cycles and the K working clock cycles both time the duration of the same frame interval.

[0008] An embodiment of the present invention further provides an integrated circuit, comprising: a transceiver circuit, a working clock circuit of the transceiver circuit, an analog-to-digital converter, and a working clock circuit of the analog-to-digital converter; the working clock circuit of the transceiver circuit is connected to the transceiver circuit, the transceiver circuit is connected to the analog-to-digital converter, and the analog-to-digital converter is connected to the working clock circuit of the analog-to-digital converter;

[0009] The working clock circuit of the transceiver circuit provides a working clock to the transceiver circuit;

[0010] The working clock circuit of the analog-to-digital converter provides a working clock to the analog-to-digital converter;

[0011] Under the control of the working clock of the transceiver circuit, the transceiver circuit transmits a chirp signal through a transmitting antenna and receives an echo signal of the chirp signal through a receiving antenna, mixes the echo signal with the chirp signal, and outputs a corresponding mixed signal to the analog-to-digital converter;

[0012] Under the control of the working clock of the analog-to-digital converter, the analog-to-digital converter samples the mixing signal corresponding to the chirp signal;

[0013] The transceiver circuit starts transmitting the chirp signal of the next frame when waiting for P working clock cycles; and

[0014] The analog-to-digital converter starts sampling a mixing signal when waiting for K working clock cycles, wherein the mixing signal is obtained by using the chirp signal and its corresponding echo signal; wherein the P working clock cycles and the K working clock cycles both time the duration of the same frame interval.

[0015] An embodiment of the present invention also provides a radio device, comprising: a carrier; an integrated circuit such as the above, arranged on the carrier; an antenna, arranged on the carrier, or the antenna and the integrated circuit are integrated into an integral device arranged on the carrier; wherein the integrated circuit is connected to the antenna for transmitting the chirp and receiving the echo signal of the chirp.

[0016] An embodiment of the present invention further provides a terminal device, comprising: a device body; and a radio device as described above, which is arranged on the device body; wherein the radio device is used for target detection to provide measurement information of the detected target to the device body.

[0017] In the embodiment of the present invention, by controlling the actual frame interval of the frame signal to be P working clock cycles of the transceiver circuit and K working clock cycles of the analog-to-digital converter, when the working clock cycle of the transceiver circuit is T1 and the working clock cycle of the analog-to-digital converter is T2, the frame interval between two adjacent frames is T1*P=T2*K. In this way, the two working clock cycles are matched to achieve the purpose of stable matching between the transmission operation of the transceiver circuit and the sampling operation of the ADC. Therefore, after the transceiver circuit completes the transmission of a frame signal, the transmission of the next frame signal is automatically triggered when the working clock cycles of the transceiver circuit are reached. When the analog-to-digital converter completes the sampling of a frame signal, the sampling of the mixing signal corresponding to the next frame signal is automatically triggered when the working clock cycles of the analog-to-digital converter are reached, thereby achieving a stable phase deviation between the first chirp of each frame and the corresponding digital signal. The problem of the phase error ΔT between the transmission starting point and the sampling starting point of the first chirp of each frame gradually accumulating due to the asynchronous working clock cycle of the transceiver circuit and the working clock cycle of the analog-to-digital converter and the unstable phase deviation fluctuation is avoided. In other words, the present application effectively reduces the continuous accumulation of phase errors at the beginning of ADC sampling of the first chirp of the two frames before and after, which is equivalent to realizing the cross-clock synchronization of the transmission of the transceiver circuit and the sampling of the analog-to-digital converter, so that the ADC sampling operation and the transmission operation of the transceiver circuit can tend to correspond stably, further ensuring the accuracy of FMCW radar speed measurement. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] One or more embodiments are exemplarily described by the pictures in the corresponding drawings, and these exemplary descriptions do not constitute limitations on the embodiments.

[0019] Figure 1 The structure of an integrated circuit according to an embodiment of the present application is shown in FIG. Figure 1 ;

[0020] Figure 2 Schematic diagram of the phase error introduced for asynchronous working clock;

[0021] Figure 3 The structure of an integrated circuit according to an embodiment of the present application is shown in FIG. Figure 2 ;

[0022] Figure 4 The structure of an integrated circuit according to an embodiment of the present application is shown in FIG. Figure 3 ;

[0023] Figure 5 The structure of an integrated circuit according to an embodiment of the present application is shown in FIG. Figure 4 ;

[0024] Figure 6This is a schematic diagram of the working principle of a first timer and a second timer in one embodiment of the present application;

[0025] Figure 7 is a flow chart of allocation of M and N values ​​in an embodiment of the present application;

[0026] Figure 8 This is a schematic diagram of another working principle of a first timer and a second timer in an embodiment of the present application;

[0027] Fig. 9 is a flow chart of the allocation of P and K values ​​in one embodiment of the present application;

[0028] Fig.10 The structure of an integrated circuit according to an embodiment of the present application is shown in FIG. Figure 5 . DETAILED DESCRIPTION

[0029] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, each embodiment of the present application will be described in detail below in conjunction with the accompanying drawings. However, it will be appreciated by those skilled in the art that in each embodiment of the present application, many technical details are proposed in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present application can also be implemented. The division of the following embodiments is for the convenience of description, and the specific implementation of the present application should not constitute any limitation, and the various embodiments can be combined with each other and referenced to each other without contradiction.

[0030] The ranging technology of FMCW radar is a technology used in high-precision radar ranging. Its basic principle is that the transmitted wave is a high-frequency continuous wave, and its frequency changes with time according to the law of triangular waves. The electromagnetic wave with a continuously changing frequency emitted by the FMCW radar is reflected by the object to form an echo. The echo and the electromagnetic wave have a certain frequency difference based on the distance between the radar and the object. The detection of the frequency difference can realize the measurement of physical quantities between the object and the radar, such as relative distance information, relative speed information, relative angle information and other physical quantities. Among them, the electrical signal corresponding to the electromagnetic wave with a continuously changing frequency is called the FMCW signal (or the transmitting signal; chirp, chirp signal). Correspondingly, the electrical signal corresponding to the echo is called the echo signal. After the intermediate frequency signal after the transmission signal and the echo signal are mixed, FFT is performed inside the chirp and FFT is performed between the chirps, which is called Doppler-FFT. In this way, the two-dimensional spectrum of distance-Doppler can be obtained, and the distance information and speed information between the target and the radar can be detected.

[0031] In order to transmit chirps and output sampled digital signals, the FMCW radar includes a transceiver circuit and an analog-to-digital converter. The transceiver circuit is used to transmit chirps and receive chirp echo signals under the control of the working clock circuit of the transceiver circuit, mix the echo signals with the chirps, and output the mixed intermediate frequency signals to the analog-to-digital converter, which converts the intermediate frequency signals into digital signals and outputs them.

[0032] In order to ensure that the frequency change of the chirp is close to linear, the transceiver circuit generates the chirp signal according to the preset frequency band and frequency sweep duration. As for the ADC, it samples the difference frequency signal after the chirp signal and the echo signal are mixed, and the difference frequency signal is the intermediate frequency signal (also called the mixing signal). Therefore, the frequency of the sampling clock signal of the ADC is usually set based on the frequency of the intermediate frequency signal, which makes the working clock cycle based on which the transceiver circuit works and the working clock cycle based on which the ADC samples are completely independent, or based on the same clock source and have a multiple relationship.

[0033] The present application provides an integrated circuit to describe the process of transmitting and receiving signals provided by a radar for measurement and calculation. Figure 1 As shown, the integrated circuit includes: a transceiver circuit 101, a working clock circuit 102 of the transceiver circuit, an analog-to-digital converter 103, and a working clock circuit 104 of the analog-to-digital converter. The working clock circuit 102 of the transceiver circuit is connected to the transceiver circuit 101, the transceiver circuit 101 is connected to the analog-to-digital converter 103, and the analog-to-digital converter 103 is connected to the working clock circuit 104 of the analog-to-digital converter.

[0034] The working clock circuit 102 of the transceiver circuit provides a working clock to the transceiver circuit 101; the working clock circuit 104 of the analog-to-digital converter provides a working clock to the analog-to-digital converter 103. The transceiver circuit 101 is used to transmit the chirp through the transmitting antenna and receive the echo signal of the chirp through the receiving antenna under the control of the working clock of the transceiver circuit, and mix the echo signal with the chirp, and output the mixed intermediate frequency signal to the analog-to-digital converter 103.

[0035] In some examples, the working clock (also called working clock signal CLK_1 or working clock CLK_1) generated by the working clock circuit 102 of the transceiver circuit mainly provides beat frequency control for the operation of the transceiver circuit 101. For example, the working clock CLK_1 is used for the transceiver circuit 101 to adjust the following: Figure 2 The frequency of each chirp in the signal is adjusted so that the frequency envelope of the chirp emitted by the transceiver circuit 101 is continuously modulated. The working frequency of the working clock CLI_1 is 100 MHz, and the corresponding working clock period is 10 ns. Figure 2For each chirp in the figure, the horizontal axis in the X direction represents time, and the vertical axis in the Y direction represents frequency; Figure 2 For each working clock in the figure, the horizontal axis in the X direction also represents time, but the vertical axis in the Y direction represents amplitude.

[0036] The transceiver circuit 101 includes a transmitting circuit and a receiving circuit (neither of which is shown in the figure). The transmitting circuit generates a chirp of a preset waveform at the clock beat frequency of the working clock CLK_1 and sends it to the transmitting antenna. For example, the transmitting circuit gradually increases the frequency at the clock beat frequency of the working clock CLK_1 to form a chirp. Figure 2 The chirp of each FMCW is shown. Here, the technician should understand that the chirp can also be a gradually decreasing frequency, or other waveforms.

[0037] The receiving circuit includes a variety of amplification circuits, a variety of filters and mixers, etc. In some examples of receiving circuits, the receiving antenna converts the echo signal into a corresponding echo electrical signal, which is filtered and amplified by a low noise amplifier and sent to the mixer. The mixer uses the local oscillator signal (LO) corresponding to the chirp and the received echo electrical signal to perform down-mixing to obtain a mixed signal that can reflect the measurement information. Optionally, the intermediate frequency signal is adjusted by a circuit such as an automatic gain amplifier and sent to the analog-to-digital converter 103 (ADC).

[0038] The analog-to-digital converter 103 operates at the beat frequency of the working clock (also called working clock signal CLK_2, or working clock CLK_2) provided by its working clock circuit 104. For example, the working clock CLK_2 generated by the working clock circuit 104 of the analog-to-digital converter is used for the analog-to-digital converter 103 to sample the received analog level and to provide beat frequency control for the output operation of the converted digital signal. In relation to the frequency band of the intermediate frequency signal processed by it, the working frequency of the working clock CLK_2 is approximately between 20-60 MHz, for example, 50 MHz.

[0039] The digital signal output after being processed by the analog-to-digital converter 103 will be used as a digital signal for generating measurement information and will be processed by subsequent circuits, such as a data processor, etc. The data processor is a circuit module including a CPU, memory, etc. that can perform data logic operations.

[0040] The transceiver circuit 101 and the analog-to-digital converter 103 can perform their respective operations by receiving the same control signal (such as a frame control signal). As described in the above examples, the operation of the transceiver circuit 101 is exemplified by transmitting a chirp, or waiting for transmitting a chirp; correspondingly, the operation of the analog-to-digital converter 103 is exemplified by sampling a mixed signal corresponding to the chirp, or waiting for sampling a corresponding mixed signal.

[0041] In the above integrated circuit, the two working clocks (CLK_1 and CLK_2) may cause the data volume of the digital signal corresponding to different chirps to fluctuate, or cause the phase deviation between different chirps to fluctuate; it may even cause the phase deviation between frames to fluctuate. These fluctuations have a negative impact on the accuracy of radar detection. Figure 2 As shown, when the first chirp is transmitted, there will be a phase error ΔT between the sampling start point and the transmission start point. Since the transceiver circuit 101 and the analog-to-digital converter 103 use an asynchronous working clock, when the second chirp is transmitted, the ΔT between the sampling start point and the transmission start point will continue to accumulate, such as Figure 2 The ΔT' in , makes ΔT' contain the phase deviation ΔT of the first chirp and the sum of the phase deviation of the second chirp. This results in inaccurate measurement of the final FMCW radar.

[0042] In order to solve at least some of the above problems, the present application proposes a method of using respective working clocks (CLK_1 and CLK_2) to time the same time period, so as to reduce the negative impact caused by the above problems. To this end, by using the different working clock cycles between the working clock CLK_1 and the working clock CLK_2, the corresponding cycle multiples are preset, so that the transceiver circuit 101 and the analog-to-digital converter 103 can process their respective signals in the same time period, or wait for the same amount of time.

[0043] For example, when the M-fold period of the working clock CLK_1 and the N-fold period of the working clock CLK_2 are theoretically the same length, the transmission period of a chirp can be preset to be the M-fold period of the working clock CLK_1 and the N-fold period of the working clock CLK_2. Wherein, M and N are positive integers. In this way, the transceiver circuit 101 and the analog-to-digital converter 103 can operate in the same chirp transmission period. Wherein, for ease of description, the transmission period of a chirp may include a valid interval of the chirp and an invalid interval of the chirp, and optionally, also includes an idle interval of the chirp. Figure 2 In the example, the frequency rising interval of the chirp in the first chirp transmission cycle is the valid interval of the chirp, the frequency falling interval of the chirp is the invalid interval of the chirp (not shown), and the time slot with unchanged frequency before the chirp valid interval can be regarded as an idle interval. In other examples, the timing of each interval in the chirp transmission cycle may vary.

[0044] For another example, when the P times period of the working clock CLK_1 and the K times period of the working clock CLK_2 are theoretically the same length, the interval between two adjacent frames can be preset to be the P times period of the working clock CLK_1 and the K times period of the working clock CLK_2. Where P and K are positive integers. In this way, the transceiver circuit 101 and the analog-to-digital converter 103 can wait in the same interval so as to start the corresponding operation of the next frame at the same time.

[0045] To achieve any of the above timing purposes, the above two working clocks CLK_1 and CLK_2 can be output under the control of the same control signal. Alternatively, the transceiver circuit 101 and the analog-to-digital converter 103 can operate based on the same control signal and the working clocks received by each. Alternatively, a circuit that can operate across clock domains, such as the cross-clock synchronization circuit described below, is used to achieve timing control of the operation of the transceiver circuit 101 and the analog-to-digital converter 103.

[0046] In some examples, the integrated circuit further includes: a timing circuit to simultaneously perform timing detection on different working clocks CLK_1 and CLK_2. When the timing detects that the working clock CLK_1 reaches M working clock cycles, and the timing working clock CLK_2 reaches N working clock cycles, it is determined that the transceiver circuit 101 and the analog-to-digital converter 103 have passed the same time period, and reset or output a timing mark (such as a pulse signal, etc.). For example, under the continuous reset operation of the timing circuit, or under the instruction of the timing mark, the transceiver circuit 101 and the analog-to-digital converter 103 can continuously transmit chirps and sampled mixing signals simultaneously in the same time period. For another example, under the continuous reset operation of the timing circuit, or under the instruction of the timing mark, the working clock circuit 102 of the transceiver circuit and the working clock circuit 104 of the analog-to-digital converter output / prohibit output of the corresponding working clock. For another example, under the continuous reset operation of the timing circuit, or under the instruction of the timing mark, the data processor (or dedicated circuit) performs chirp counting to count the number of chirps in a frame, etc.

[0047] In some examples, the timing circuit receives the working clock of the transceiver circuit and the working clock of the analog-to-digital converter, respectively, and represents the same time period corresponding to the transceiver circuit 101 and the analog-to-digital converter 103 by simultaneously timing the M times (or P times) working clock cycle of the working clock CLK_1 and the N times (or K times) working clock cycle of the working clock CLK_2.

[0048] According to the characteristics of the same time period being timed, the timing circuit may include two or more timers to adapt to the different durations corresponding to multiple "same time periods"; or a time division multiplexing method may be used to use a shared timer to time the durations of multiple "same time periods" to simplify the complexity of the integrated circuit. Examples of different types of "same time periods" are the chirp transmission cycle or frame interval.

[0049] For example, the timing circuit includes two timers to respectively count the number of cycles of different working clocks under the control of a control signal. When one of the timers counts to M (or P) and the other timer counts to N (or K), it indicates that the transceiver circuit 101 and the analog-to-digital converter 103 have passed the same time period. For another example, the timing circuit includes two timers to respectively adjust the charge in the capacitor used for timing under the control of the same control signal and different working clocks until the timing levels output by the two timers match the reference level corresponding to the M times (or P times) working clock cycle of the working clock CLK_1, or the reference level corresponding to the N times (or K times) working clock cycle of the working clock CLK_2. This indicates that the transceiver circuit 101 and the analog-to-digital converter 103 have passed the same time period.

[0050] In some other examples, the timing circuit includes a first timer and a second timer. The first timer performs timing according to a working clock cycle of a working clock CLK_1. The second timer performs timing according to a working clock cycle of a working clock CLK_2.

[0051] like Figure 3 As shown, the first timer 105 is connected to the transceiver circuit 101 (as shown by the solid line), or the first timer 105 is connected to the working clock circuit 102 of the transceiver circuit (as shown by the dotted line). The first timer 105 uses the working clock cycle of CLK_1 to count. Similarly, the second timer 106 is connected to the analog-to-digital converter 103 (as shown by the solid line), or the second timer 106 is connected to the working clock circuit 104 of the analog-to-digital converter (as shown by the dotted line). The second timer 106 uses the working clock cycle of CLK_2 to count. The timing circuit uses the first timer 105 and the second timer 106 so as to respectively use two working clocks to count the same time period.

[0052] In order to improve the response accuracy of the radar in terms of transmission and reception control, the integrated circuit also includes a cross-clock synchronization circuit 107, such as Figure 4As shown, it is connected between the clock domain of the transceiver circuit and the clock domain of the analog-to-digital converter. For example, the cross-clock synchronization circuit 107 can be connected between the transceiver circuit 101 and the analog-to-digital converter 103, and / or, connected between the working clock circuit 102 of the transceiver circuit and the working clock circuit 104 of the analog-to-digital converter, or connected between the transceiver circuit 101 and the second timer 106. Its purpose is to start the timing of the same time period by the two working clock domains.

[0053] The cross-clock synchronization circuit 107 operates under the beat frequency control of one of the working clocks. When a control signal is received and corresponds to the beat of the working clock, a signal with a jump edge is output. In order to improve the response speed of the cross-clock synchronization circuit 107, it can operate under the control of a working clock with a faster working clock frequency, such as operating under the beat frequency control of the working clock based on the transceiver circuit. The cross-clock synchronization circuit 107 is exemplified as a register circuit including one or more cascaded registers. For example, a register circuit including two registers cascaded to reduce potential problems such as register metastable state.

[0054] In order to obtain the multiples of the working clock cycles of the two working clocks used to time the same time period, the integrated circuit may further include a data processor 108, such as Figure 5 As shown, the data processor 108 is connected to the first timer 105 and the second timer 106 respectively, and the data processor 108 allocates the above-mentioned M and N (or P and K) values ​​to the two timers according to the least common multiple of each cycle of the two working clocks and a pre-set chirp transmission cycle (or frame interval). In an example, the data processor 108 is also connected to the transceiver circuit 101 (not shown in the figure) to output the control signal (SPI) generated based on the program operation to the first timer 105 and the transceiver circuit 101, wherein the control signal is, for example, an instruction to start the transmission of the chirp. The input end of the cross-clock synchronization circuit 107 is connected to the transceiver circuit 101, and the input end is used to receive the control signal from the transceiver circuit 101, and the output end of the cross-clock synchronization circuit 107 is connected to the second timer 106. Under the control of the control signal of the data processor 108, the first timer 105 starts timing. At the same time, the cross-clock synchronization circuit 107 (such as a register circuit) outputs the control signal from the transceiver circuit 101 to the second timer 106 under the beat frequency control of CLK_1. The second timer 106 instructs the analog-to-digital converter 103 to start sampling the mixed signal corresponding to the chirp according to the beat frequency of the working clock CLK_2.

[0055] In this way, the circuits in two different clock domains achieve substantially simultaneous timing operations in the first slower working clock cycle, and in multiple time periods thereafter, the phase error between the chirp emitted by the transceiver circuit 101 and the corresponding digital signal output after processing by the digital converter 103 remains substantially unchanged.

[0056] In order to adapt the integrated circuit to different radar application scenarios, the same time period corresponding to the coordinated operation / non-coordinated operation of the transceiver circuit 101 and the analog-to-digital converter 103 can be of equal length or unequal length.

[0057] In some examples, the above-mentioned equal or unequal time periods are preset in the integrated circuit. For example, the respective coefficients, i.e., the above-mentioned M and N, or the values ​​of P and K, are determined based on the least common multiple of the working clock period T1 of the working clock CLK_1 and the working clock period T2 of the working clock CLK_2, and the preset time period is obtained using the coefficient and the corresponding working clock period. In other words, the time period is obtained according to the above-mentioned calculation method. Among them, if the coefficients corresponding to different time periods in the timing sequence are the same, the corresponding time periods are equal in length; otherwise, they are unequal in length.

[0058] For example, the working clock cycle T1 is 20ns, and the working clock cycle T2 is 30ns. In order to make the time duration of each working clock the same, according to the least common multiple of the two, 60, the coefficient of the working clock cycle T1 is preset to 3, and the coefficient of the working clock cycle T2 is preset to 2. Thus, the transmission period of the same chirp is set to 60ns, or an integer multiple of 60ns. Under the control of the same control signal, and using different working clocks CLK_1 and CLK_2, and the timing circuit, the transceiver circuit 101 and the analog-to-digital converter 103 work together / do not work together in the same time period.

[0059] As can be seen from the above example, in a radar configuration that needs to transmit multiple chirps in one frame, the transmission periods of different chirps can be of equal duration or different durations, and the transmission period of the same chirp in which the transceiver circuit 101 and the analog-to-digital converter 103 work in collaboration can be adjusted by presetting different coefficient pairs (M, N).

[0060] As can be seen from the above example, in a radar configuration that needs to transmit multiple chirp frames, the frame interval between adjacent frames can be of equal length or different lengths, and the length of the same frame interval for the collaborative waiting of the transceiver circuit 101 and the analog-to-digital converter 103 can be adjusted by presetting different coefficient pairs (P, K).

[0061] In order to configure the chirp transceiver mechanism more flexibly to adapt to the actual application scenario of the radar system, the computer device or data processor 108 connected to the radar also supports the operation of programs for human-computer interaction. Using the human-computer interaction interface, the computer device or data processor 108 determines the above-mentioned equal or unequal time periods to be provided in the chirp transceiver mechanism. For example, determine the coefficients of the two working clocks, or determine the total length of the time period, etc.

[0062] In some examples, some preset coefficient pair options are provided in the corresponding interface for pre-selection by the technician.

[0063] In other examples, an arbitrarily configurable interactive interface, such as a program interface or an input box, is provided in the corresponding interface, so that the computer device or the data processor 108 can obtain a preset time period τ'.

[0064] It should be noted that the time period τ' obtained in the above interactive interface should be understood as various parameters that can be converted into the time period τ', including but not limited to directly obtaining the time period τ', or obtaining data such as chirp frequency that can be converted into the time period τ'.

[0065] In order to achieve the purpose of the same time period when the transceiver circuit 101 and the analog-to-digital converter 103 work / do not work together, the computer device or data processor 108 allocates coefficients corresponding to each working clock cycle according to the least common multiple of each cycle of the two working clocks; and adjusts each coefficient based on the preset time period τ' to obtain an actual time period τ that is similar to the preset time period τ'. The actual time period τ is the same time period when the transceiver circuit 101 and the analog-to-digital converter 103 work / do not work together.

[0066] For example, the set time period τ' of the chirp received through the human-computer interaction interface is 110.01us, the period T1 of CLK_1 is 100MHz=10ns, and the period T2 of CLK_2 is 50MHz=20ns. If CLK_1 is used to time τ', 110.01us=110010ns=11001×10ns is obtained, that is, the coefficient of CLK_1 is 11001. However, since 110010ns cannot be divided by 20ns, that is, CLK_2 cannot use the integer multiple of the self-excited working clock cycle to time the same time period τ', it is impossible to ensure that the transceiver circuit 101 and the analog-to-digital converter 103 work together (or not work together) in the same time period τ'. Therefore, the computer device (or data processor 108) will perform approximate calculations to obtain the same time period corresponding to the collaborative work (or non-collaborative work) and close to the set time period τ'.

[0067] In order to effectively reduce the fluctuation of the phase error between the multiple transmitted chirps by the transceiver circuit 101 and the mixed signals sampled by the analog-to-digital converter 103, the transceiver circuit 101 and the analog-to-digital converter 103 use their respective working clocks (CLK_1 and CLK_2) to time the transmission cycle of the same chirp, so that when the transceiver circuit 101 sends multiple chirps continuously, the phase deviation between the previously transmitted chirps and the corresponding sampled mixed signals is stable.

[0068] For example, Figure 6 As shown, the transceiver circuit 101 and the analog-to-digital converter 103 have a phase error during the transmission period of the first chirp in a frame, such as Figure 2 The ΔT shown. Figure 2 The difference is that, starting from the second chirp transmission cycle, since the timing of the transmission cycle of the same chirp by the transceiver circuit 101 and the analog-to-digital converter 103 is stable, the transmission operation starting point of each chirp and the corresponding mixing signal sampling operation starting point are basically synchronized in the timing of the transmission cycles of multiple consecutive chirps. Figure 6 As shown, during the transmission period of the second chirp, the phase error ΔT" between the chirp signal and the sampling signal is substantially the same as the ΔT of the transmission period of the first chirp. In this way, the fluctuation of the phase error between multiple chirps in one frame is reduced.

[0069] Combination Figure 4 and Figure 6In the example of, the data processor 108 sends a control signal to the transceiver circuit 101 and the first timer 105, and the control signal is used to indicate the start of chirp transmission. When the first timer 105 receives the control signal, it uses the working clock cycle of CLK_1 to time the working clock CLK_1. When the transceiver circuit 101 receives the control signal, it starts the first chirp transmission of a frame, and outputs a control signal to the cross-clock synchronization circuit 107, and the control signal is used to indicate the start of chirp transmission, so that the cross-clock synchronization circuit 107 triggers the analog-to-digital converter 103 to start sampling of the mixing signal based on the control signal. In one example, the cross-clock synchronization circuit 107 operates under the beat frequency control of the working clock CLK_1, and when receiving the control signal output by the transceiver circuit 101 and corresponding to the beat of CLK_1, it outputs a signal with a jump edge to the second timer 106. After receiving the signal, the second timer 106 uses the working clock cycle of CLK_2 to time the working clock CLK_2 and triggers the analog-to-digital converter 103 to start sampling the mixed signal. In another example, the data processor 108 can also only send a control signal to the transceiver circuit 101, and the control signal is used to indicate the start of the chirp transmission, and the transceiver circuit 101 sends an indication signal to the first timer 105 to start timing. When receiving the control signal output by the transceiver circuit 101 and corresponding to the beat of CLK_1, the cross-clock synchronization circuit 107 can also output a signal with a jump edge to the digital converter 103, triggering the analog-to-digital converter 103 to start sampling the mixed signal, and the analog-to-digital converter 103 sends an indication signal to the second timer 106 to start timing the second timer 106.

[0070] When the first timer 105 counts to M working clock cycles of CLK_1, it outputs a timing mark or resets to the transceiver circuit 101, indicating that a chirp transmission cycle has been completed. When the transceiver circuit 101 receives the timing mark or detects the reset operation of the first timer 105, it starts the transmission of the next chirp. When the second timer 106 counts to N working clock cycles of the working clock CLK_2, it outputs a timing mark or resets to the analog-to-digital converter 103, indicating that the sampling corresponding to the transmission cycle of a chirp has been completed. When the analog-to-digital converter 103 receives the timing mark or detects the reset operation of the second timer 106, it starts the sampling of the mixing signal corresponding to the next chirp. Under the continuous resetting operation of the first timer 105 and the second timer 106 or the indication of the timing mark, the transceiver circuit 101 and the analog-to-digital converter 103 can continuously transmit the chirp and the sampled mixing signal simultaneously in the transmission cycle of each chirp, that is, starting from the second chirp of each frame, the coordinated operation of the transceiver circuit 101 and the analog-to-digital converter 103 is maintained.

[0071] In other words, M working clock cycles of CLK_1 and N working clock cycles of CLK_2 are obtained by timing the first timer 105 and the second timer 106 respectively, and a chirp transmission cycle is T1*M=T2*N, wherein T1 is the working clock cycle of CLK_1, and T2 is the working clock cycle of CLK_2. Therefore, the coordinated operation of the transceiver circuit 101 and the analog-to-digital converter 103 can be controlled by the timing of the first timer 106 and the second timer 106. For example, after receiving the signal to start chirp transmission, the first timer 105 starts timing, taking M as 10000 as an example, when the first timer 105 times 10000 working clock cycles of CLK_1, it automatically clears to start the next timing, until the number of timing rounds of the first timer 105 reaches L, where L is the total number of chirps included in a frame signal. The second timer 106 starts timing when the analog-to-digital converter 103 starts sampling the mixed signal corresponding to the first chirp of each frame, and is automatically reset and starts the next count when the timing reaches N CLK_2 working clock cycles, until the number of timing rounds of the second timer 106 reaches L, where L is the total number of chirps included in a frame signal, for example, L is 256.

[0072] The working principle diagram of the first timer 105 and the second timer 105 is as follows: Figure 6 As shown, the FMCW linear frequency modulation continuous wave works on the working clock CLK_1 of the transceiver circuit 101, and the transmission period of the chirp is M working clock periods of the working clock CLK_1, and is N working clock periods of the working clock CLK_2. The first timer 105 counts at the rising edge of each working clock CLK_1 of the transceiver circuit 101, and the count size is M. After counting to M, it automatically clears the count of the next chirp transmission period until all chirps in one frame are counted. The second timer 106 accumulates the count at the rising edge of the working clock CLK_2 of each analog-to-digital converter 103, and after counting to N, it automatically clears the count of the next chirp transmission period until all chirps in one frame are counted. Since the transmission cycle of the chirp is T1*M=T2*N, when the transceiver circuit 101 completes the transmission of a chirp and starts the transmission of the next chirp, the corresponding analog-to-digital converter 103 also completes the sampling of a chirp and automatically starts the sampling of the next chirp, which is equivalent to realizing the cross-clock synchronization of the transmission of the transceiver circuit 101 and the sampling of the analog-to-digital converter 103. In this way, the purpose of stable matching between the transmission operation of the transceiver circuit 101 and the sampling operation of the ADC is achieved by matching the two working clock cycles.

[0073] Combination Figure 5 and Figure 6 In the example of the present invention, the data processor 108 is further used to output the assigned M value and N value to the first timer 105 and the second timer 106, respectively. In one example, the data processor assigns the M value to the first timer 105 and the N value to the second timer 106 according to the least common multiple of each cycle of the two working clocks and a preset chirp transmission cycle, so as to obtain a chirp transmission cycle actually used to transmit the chirp corresponding to the set chirp transmission cycle.

[0074] Before the transceiver circuit 101 starts the transmission of the chirp, the data processor 108 first determines the M value and the N value, transmits the M value to the first timer 105, and transmits the N value to the second timer 106. Then, the data processor 108 sends a control signal to the transceiver circuit 101 and the first timer 105, and the control signal is used to instruct to start the transmission of the chirp. Figure 5 and Figure 6 The example is the same as that of , and will not be repeated here.

[0075] In some examples of configurable chirp transmission periods, such as Figure 7 As shown, in step 701, the data processor 108 determines the least common multiple of T1 and T2 based on the respective working clock periods T1 and T2 of CLK_1 and CLK_2.

[0076] In step 702, the data processor 108 determines whether a predetermined chirp transmission period is divisible by the least common multiple determined in step 701. In one example, the chirp transmission period received through the human-computer interaction interface can be used as the predetermined chirp transmission period, or the predetermined chirp transmission period is obtained by reading the memory, and then it is determined whether the predetermined chirp transmission period is an integer of the least common multiple of T1 and T2.

[0077] If in step 702, the preset chirp transmission period cannot be divided by the least common multiple determined in step 701, then step 703 will be entered to adjust the chirp transmission period and assign the values ​​of M and N. The adjusted chirp transmission period can be divided by the least common multiple and is close to the preset chirp transmission period. As in the above example, the working clock period T1 is 10ns, the working clock period T2 is 20ns, the least common multiple of T1 and T2 is 20, and the preset chirp transmission period is 110.01us=110010ns. Since 110010ns cannot be divided by the least common multiple 20 of T1 and T2, 110010ns needs to be adjusted to obtain 110000ns, which is close to 110010ns and can be divided by 60. The adjusted 110000ns is the chirp transmission period actually used to transmit the chirp. According to the adjusted 110000ns, as well as T1 and T2, the value of M is allocated as 110000ns / 10ns=11000, and the value of N is allocated as 110000ns / 20ns=5500. It can be understood that if the ratio of T1 and T2 is an integer ratio, N can be obtained according to M and the ratio of T1 and T2 after M is allocated, or N can be allocated first, and then M can be obtained according to N and the ratio of T1 and T2 after N is obtained. As in the above example, the ratio of T1 and T2 is 1:2. Since the transmission period of the chirp needs to meet the condition of T1*M=T2*N, after M=11000 is obtained, N=5500 can be obtained according to the ratio of T1 and T2. Or N=5500 can be allocated first, and then M=11000 can be obtained according to the ratio of T1 and T2.

[0078] In one example, when the preset chirp transmission period needs to be adjusted, the adjusted chirp transmission period can also be displayed to the user through the human-computer interaction interface.

[0079] When the preset chirp transmission period is divisible by the least common multiple determined in step 701, step 704 is entered to allocate the values ​​of M and N based on the preset chirp transmission period. For example, if the preset chirp transmission period is 110000ns, then the value of M can be allocated to 110000ns / 10ns=11000 and the value of N can be allocated to 110000ns / 20ns=5500 directly based on 110000ns and T1 and T2.

[0080] In addition, since multiple chirps need to be transmitted in one frame, the transmission period of each chirp can be of equal duration or different duration. Therefore, in one example, when the transmission periods of different chirps are different, the values ​​of M and N need to be dynamically adjusted, that is, steps 702 to 704 can be repeatedly performed to ensure that the corresponding values ​​of M and N are obtained before each chirp is transmitted. For any chirp, the condition that the transmission period is T1*M=T2*N needs to be met.

[0081] It can be seen from the above examples that when a frame contains multiple chirps, signal transmission and reception control according to the circuit provided in the present application and the above working timing can greatly improve the stability of the phase error between each chirp in a frame and its corresponding digital signal.

[0082] In other radar applications, such as medical breathing and heartbeat monitoring, in order to monitor the vital signs of living bodies, the radar transceiver circuit 101 and analog-to-digital converter 103 need to cooperate with the subsequent data processing algorithm to control the fluctuation of the phase error between the chirp of each frame and its corresponding digital signal as small as possible. Therefore, the transceiver circuit 101 and the analog-to-digital converter 103 use their own working clocks (CLK_1 and CLK_2) to time the same frame interval. Within the same frame interval, the transceiver circuit 101 and the analog-to-digital converter 103 do not work together to avoid the phase of the previous and next two frames from causing additional random phase changes due to the asynchronous working clocks of the transceiver circuit 101 and the analog-to-digital converter 103.

[0083] By using the transceiver circuit 101, the working clock circuit 102 of the transceiver circuit, the analog-to-digital converter 103, the working clock circuit 104 of the analog-to-digital converter, and the timing circuit in the present application, transceiver control based on basic synchronization of the frame interval can also be provided.

[0084] Combination Figure 4 and Figure 8 As shown, when the transceiver circuit 101 completes the transmission of a frame of chirp, it outputs a control signal to the first timer 105 to indicate that the transmission of a frame of chirp has been completed. When the first timer 105 receives the control signal, it uses the working clock cycle of CLK_1 to time the working clock CLK_1. When the first timer 105 counts to P working clock cycles of CLK_1, it outputs a timing mark or reset to the transceiver circuit 101, indicating that the frame interval has been reached and the transmission of the next frame of chirp has begun. When the transceiver circuit 101 receives the timing mark or detects the reset operation of the first timer 105, it starts the transmission of the next frame of chirp.

[0085] After completing the sampling of a frame signal, the analog-to-digital converter 103 outputs a control signal to the second timer 106 to instruct the second timer 106 to start timing. When the second timer 106 receives the control signal, it uses the working clock cycle of CLK_2 to time the working clock CLK_2. When the second timer 106 times K working clock cycles of CLK_2, it outputs a timing mark or reset to the analog-to-digital converter 103, indicating that the frame interval has been reached and the sampling mixing signal is started. When the analog-to-digital converter 103 receives the timing mark or detects the reset operation of the second timer 106, it starts the sampling of the mixing signal corresponding to the next frame chirp. Among them, the duration of the working clock cycles of P CLK_1 and the working clock cycles of K CLK_2 is the same, that is, the frame interval between the previous and next two frames is T1*P=T2*K.

[0086] The transceiver circuit 101 can send a control signal to the first timer 105 to start re-counting of the first timer 105 each time it completes the transmission of a frame of chirp. Similarly, the analog-to-digital converter 103 outputs a control signal to the second timer 106 after completing the sampling of each frame signal to start re-counting of the second timer 106, so that in each frame interval, the transceiver circuit 101 and the analog-to-digital converter 103 can cooperate without operation, and during the non-frame interval period, the transceiver circuit 101 and the analog-to-digital converter 103 can process multiple frames of chirp signals.

[0087] The working principle diagram of the first timer 105 and the second timer 105 is as follows: Figure 8 As shown, while the transceiver circuit 101 is transmitting a signal, the first timer 105 remains unchanged at the initial value. Between frames where the transmission of the signal is stopped, the first timer 105 counts at the rising edge of each working clock CLK_1 of the transceiver circuit 101, and the count size is P. After counting to P, it automatically returns to the initial value and remains unchanged, and at the same time starts the transceiver circuit 101 to transmit the chirp of the next frame.

[0088] When the analog-to-digital converter 103 is working, that is, when the analog-to-digital converter 103 is sampling, the second timer 106 remains at the initial value unchanged. When the analog-to-digital converter 103 stops sampling, that is, when the sampling of one frame of signal is completed, the second timer 106 counts at the rising edge of each working clock CLK_2 of the analog-to-digital converter 103. After the count size is K, it automatically returns to the initial value and remains unchanged. At the same time, the analog-to-digital converter 103 is started for sampling. The second timer 106 remains at the initial value unchanged until the next sampling stops and another round of counting begins.

[0089] Since the frame interval is T1*P=T2*K, the two working clock cycles are matched to achieve the purpose of stable matching between the transmission operation of the transceiver circuit 101 and the sampling operation of the ADC. Therefore, after the transceiver circuit 101 completes the transmission of a frame of signals, it automatically triggers the transmission of the next frame of signals when P working clock cycles of the transceiver circuit are reached, and after the analog-to-digital converter 103 completes the sampling of a frame of signals, it automatically triggers the sampling of the mixing signal corresponding to the next frame of signals when K working clock cycles of the analog-to-digital converter are reached, thereby achieving a stable phase deviation between the first chirp of each frame and the corresponding digital signal, ensuring that the phases of the previous and next frames will not have additional random phase changes due to the asynchronous working clocks of the transceiver circuit 101 and the analog-to-digital converter 103.

[0090] Combination Figure 5 and Figure 8 As shown, different from the previous example, the values ​​of P and K can be allocated by the data processor 108. That is, the data processor 108 is also used to output the allocated P value and K value to the first timer 105 and the second timer 106 respectively. In one example, the data processor allocates the P value to the first timer 105 and allocates the K value to the second timer 106 according to the least common multiple of each cycle of the two working clocks and a preset frame interval, so as to obtain a frame interval actually used for transmitting the chirp signal that is close to the set frame interval.

[0091] In some examples where the frame interval can be configured, such as Fig. 9 As shown, in step 901, the data processor 108 determines the least common multiple of T1 and T2 based on the respective working clock periods T1 and T2 of CLK_1 and CLK_2.

[0092] In step 902, the data processor 108 determines whether a preset frame interval is divisible by the least common multiple determined in step 901. In one example, the frame interval received through the human-computer interaction interface can be used as the preset frame interval, or the preset frame interval can be obtained by reading the memory, and then determining whether the preset frame interval is an integer of the least common multiple of T1 and T2.

[0093] If in step 902, the preset frame interval cannot be divided by the least common multiple determined in step 901, then step 903 will be entered to adjust the frame interval and allocate the values ​​of P and K. The adjusted frame interval can be divided by the least common multiple and is close to the preset frame interval. The specific adjustment method is similar to the adjustment method of the chirp transmission period in step 703, except that the time period adjusted in step 703 is the chirp transmission period, and the time period adjusted in step 903 is the frame interval, which will not be repeated here. Similarly, it can be understood that if the ratio of T1 and T2 is a divisible ratio, after P is allocated, K can be obtained according to P and the ratio of T1 and T2, or K can be allocated first, and after K is obtained, P can be obtained according to K and the ratio of T1 and T2.

[0094] In one example, when the preset frame interval needs to be adjusted, the adjusted frame interval can also be displayed to the user through the human-computer interaction interface.

[0095] When the preset frame interval is divisible by the least common multiple determined in step 901, the process proceeds to step 904 to allocate the values ​​of P and K based on the preset frame interval.

[0096] In addition, the frame intervals of different frame signals may be different. Since the frame intervals of the frame signals to be transmitted may be the same or different, in one example, the values ​​of P and K may be dynamically adjusted according to the frame intervals of the frame signals to be transmitted. That is, steps 902 to 904 may be repeatedly performed to ensure that the corresponding values ​​of P and K are obtained before the frame signal of each frame is transmitted. For any frame interval, the condition that the frame interval is T1*P=T2*K needs to be satisfied.

[0097] It can be seen from the above examples that when the radar needs to send and receive multiple frames of chirps, and the transceiver circuit 101 and the analog-to-digital converter 103 basically keep the timing of the durations between frames consistent, signal transmission and reception control according to the circuit provided in this application and the above-mentioned working timing can greatly improve the stability of the phase error between multiple frames of chirps and their corresponding digital signals, so as to better provide measurement services for fields such as the medical field.

[0098] It should be noted that in the above-mentioned inter-frame timing scheme, the timing method of the transmission period of each chirp in the frame can use the timing scheme provided in the present application, or adopt other timing methods.

[0099] The present application also provides a transceiver control scheme that can both time the transmission cycle of the chirp and the frame interval. In some examples of multiplexable timers, when the transceiver circuit 101 starts the transmission of the first chirp of a frame, the first timer 105 starts counting the working clock cycle of CLK_1, and automatically returns to the initial value when the count reaches M, such as automatically clearing to zero, and then starts the next count until the number of counting rounds of the first timer 105 reaches the total number of chirps included in a frame signal. When the analog-to-digital converter 103 starts sampling the mixing signal corresponding to the first chirp of a frame, the second timer 106 starts counting the working clock cycle of CLK_2, and automatically returns to the initial value when the count reaches N, such as automatically clearing to zero, and then automatically starts the next count until the number of counting rounds of the second timer 106 reaches the total number of chirps included in a frame signal.

[0100] After the transceiver circuit 101 completes the transmission of a frame of signals, the first timer 105 starts counting between frames, and automatically returns to the initial value after counting from the initial value to P, at which time the transceiver circuit 101 is triggered to start the transmission of the first chirp of the next frame, and the first timer 105 restarts counting with a period of M. After the analog-to-digital converter 103 completes sampling of a frame of signals, the second timer 106 starts counting between frames, and starts counting from the initial value, and automatically returns to the initial value after counting to K, at which time the analog-to-digital converter 103 is started to sample the next frame, and the second timer restarts counting with a period of N.

[0101] In other words, within a frame, the first timer 105 uses M as a counting cycle, and triggers the transceiver circuit 101 to transmit the next chirp each time the count reaches M. When the number of counting rounds reaches the total number of chirps included in a frame signal, it means that the transmission of a frame signal has been completed. At this time, the first timer 105 uses P as a counting cycle. Before the count reaches P, the transceiver circuit 101 does not transmit a signal. When the count reaches P, the transceiver circuit 101 is triggered to start transmitting the next frame signal. Within a frame, the second timer 106 uses N as a counting cycle, and triggers the sampling of the analog-to-digital converter 103 each time the count reaches N. When the number of counting rounds reaches the total number of chirps included in a frame signal, it means that the sampling of a frame signal has been completed. At this time, the second timer 106 uses K as a counting cycle. Before the count reaches K, the analog-to-digital converter 103 does not perform sampling. When the count reaches K, the analog-to-digital converter 103 is triggered to start sampling the next frame signal.

[0102] The transceiver circuit 101 can identify whether the current reset operation indicates the transmission of the next chirp in a frame or the transmission of the frame signal of the next frame by detecting whether the number of resets of the first timer 105 reaches the total number of chirps included in a frame signal. Similarly, the analog-to-digital converter 103 can also identify whether the current reset operation indicates the sampling operation corresponding to the next chirp in a frame or the sampling operation corresponding to the frame signal of the next frame by detecting the number of resets of the second timer 106.

[0103] Since the chirp transmission period in each frame is T1*M=T2*N, when the transceiver circuit 101 completes the transmission of a chirp, the corresponding analog-to-digital converter 103 also completes the sampling of a chirp. At the same time, the frame interval between two adjacent frames is T1*P=T2*K, so that the waiting time before the transceiver circuit 101 starts the transmission of the next frame signal after completing the transmission of one frame signal is completely matched with the waiting time before the analog-to-digital converter 103 starts the sampling of the next frame signal after completing the sampling of one frame signal. Therefore, not only the phase offset within the FMCW frame can be reduced, but also the phase offset between FMCW frames can be reduced.

[0104] In order to further reduce the additional phase error caused by the timer reset, in some other examples, a timer is set for the count within a frame and the count between frames respectively.

[0105] like Fig.10 As shown, the timing circuit further includes a third timer 109 and a fourth timer 110. The third timer 109 is connected to the transceiver circuit 101 (as shown by the solid line), or the third timer 110 is connected to the first timer 105 (as shown by the dotted line); the fourth timer 110 is connected to the analog-to-digital converter 103 (as shown by the solid line), or the fourth timer 110 is connected to the second timer 106 (as shown by the dotted line).

[0106] The first timer 105 and the third timer 109 are both used to count the working clock period T1 of the transceiver circuit 101 to time the working clock CLK_1 of the transceiver circuit 101, wherein one timer is used for timing within a frame, and the other timer is used for timing between frames. For example, the first timer 105 uses M as a counting period for timing within a frame, and the third timer 109 uses P as a counting period for timing between frames. The second timer 106 and the fourth timer 110 are both used to count the working clock period T2 of the analog-to-digital converter 103 to time the working clock CLK_2 of the analog-to-digital converter 103, wherein one timer is used for timing within a frame, and the other timer is used for timing between frames. For example, the second timer 106 uses N as a counting period, and the fourth timer 110 uses K as a counting period.

[0107] The third timer 109 and the fourth timer 110 may also be connected to the data processor 108 , and the data processor 108 sends the allocated P value or M value to the third timer 109 , and sends the allocated K value or N value to the fourth timer 110 .

[0108] Taking the first timer 105 and the second timer 106 for timing within a frame, and the third timer 109 and the fourth timer 110 for timing between frames as an example, when the transceiver circuit 101 starts transmitting the first chirp of a frame, the first timer 105 starts counting the working clock cycle T1 of CLK_1, and automatically returns to the initial value when counting to M, such as automatically clearing to zero, and then starts the next counting, until the number of counting rounds of the first timer 105 reaches the total number of chirps included in a frame signal. The second timer 106 starts counting the working clock cycle T2 of CLK_2 when the analog-to-digital converter 103 starts sampling the mixing signal corresponding to the first chirp of a frame, and automatically returns to the initial value when counting to N, such as automatically clearing to zero, and then automatically starts the next counting, until the number of counting rounds of the second timer 106 reaches the total number of chirps included in a frame signal.

[0109] After the transceiver circuit 101 completes the transmission of a frame signal, the transceiver circuit 101 sends a control signal to the third timer 109 to indicate that the transmission of a frame signal is completed, triggering the third timer 109 to start the inter-frame counting, or the third timer 109 starts the inter-frame counting when it detects that the number of counting rounds of the second timer 106 reaches the total number of chirps included in a frame signal. When the third timer 109 starts the inter-frame counting, it counts from the initial value to P and then automatically returns to the initial value, at which time the transceiver circuit 101 is triggered to start the transmission of the first chirp of the next frame, and the first timer 105 restarts the counting with a period of M. Among them, the restart of the first timer 105 can be triggered by the transceiver circuit 101 or by the third timer 109.

[0110] After the analog-to-digital converter 103 completes sampling of a frame of signals, the fourth timer 110 starts counting from the initial value, and automatically returns to the initial value after counting to K. At this time, the analog-to-digital converter 103 is started to sample the next frame, and the second timer 106 restarts counting with a period of N. The restart of the second timer 106 can be triggered by the analog-to-digital converter 103 or by the fourth timer 110.

[0111] Through the first timer 105 and the second timer 106, it is ensured that within the transmission period of each chirp of a frame, the sampling operation of the analog-to-digital converter 103 and the transmission operation of the transceiver circuit 101 can tend to be stably corresponding. Through the third timer 109 and the fourth timer 110, it is ensured that when the transceiver circuit 101 transmits the first chirp of the previous and next frames, the ADC sampling operation and the transmission operation of the transceiver circuit 101 can tend to be stably corresponding, thereby ensuring that the phase of the previous and next frames will not cause additional random phase changes due to the asynchronous working clocks of the transceiver circuit 101 and the analog-to-digital converter 103.

[0112] Another embodiment of the present application relates to a radio device, comprising: a carrier; an integrated circuit such as the above embodiment, arranged on the carrier; an antenna, arranged on the carrier, or the antenna and the integrated circuit are integrated into a device arranged on the carrier; wherein the integrated circuit is connected to the antenna for transmitting chirp and receiving chirp echo signals.

[0113] When the antenna and the integrated circuit are not integrated into one device, the integrated circuit is connected to the antenna through a first transmission line, and the first transmission line can be a PCB trace. The carrier can be a printed circuit board PCB, such as a development board, a data acquisition board or a main board of a device, etc., which will not be described in detail here.

[0114] Since the structure and working principle of the integrated circuit included in the radio device have been described in detail in the above embodiments, they will not be described in detail here.

[0115] Another embodiment of the present application relates to a terminal device, comprising: a device body; and a radio device as described in the previous embodiment, which is arranged on the device body; wherein the radio device is used for target detection to provide measurement information of the detected target to the device body.

[0116] In one embodiment of the present application, the radio device may be disposed outside the device body, in another embodiment of the present application, the radio device may also be disposed inside the device body, and in other embodiments of the present application, the radio device may also be partially disposed inside the device body and partially disposed outside the device body. The present application embodiment does not limit this, and it depends on the specific situation.

[0117] It should be noted that the radio device can realize functions such as target detection by transmitting and receiving radio signals to provide the device body with measurement information of the detected target, thereby assisting or even controlling the operation of the device body. The measurement information includes, for example, at least one of relative distance, relative speed, and relative angle.

[0118] In an optional embodiment, the device body may be a component or product used in fields such as transportation, consumer electronics, monitoring, in-cabin detection, and health care. For example, the device body may be intelligent transportation equipment (such as automobiles, motorcycles, ships, subways, trains, etc.), security equipment (such as cameras), liquid level / flow rate detection equipment, intelligent wearable devices (such as bracelets, glasses, etc.), smart home devices (such as sweeping robots, door locks, televisions, air conditioners, smart lights, etc.), various communication devices (such as mobile phones, tablet computers, etc.), and gates, intelligent traffic lights, intelligent signs, traffic cameras, and various industrialized robotic arms (or robots), etc. It may also be various instruments for detecting life characteristic parameters and various equipment equipped with the instruments, such as in-cabin detection of automobiles, indoor personnel monitoring, intelligent medical equipment, consumer electronic equipment, etc.

[0119] In another optional embodiment, when the above-mentioned device body is applied to an advanced driver assistance system (i.e., ADAS), the radio device as a vehicle-mounted sensor can provide various functional safety guarantees for the ADAS system such as automatic braking assistance (i.e., AEB), blind spot detection warning (i.e., BSD), lane change assistance warning (i.e., LCA), and reversing assistance warning (i.e., RCTA).

[0120] Those skilled in the art will appreciate that the above-mentioned embodiments are specific examples for implementing the present application, and in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present application.

Claims

1. A method for processing radar signals, characterized in that: include: When the transceiver circuit waits for its working clock to reach P working clock cycles, it starts transmitting the chirp signal of the next frame; When the analog-to-digital converter waits for its working clock to reach K working clock cycles, it starts sampling the mixing signal, wherein the mixing signal is obtained using the chirp signal and its corresponding echo signal; wherein the P working clock cycles and the K working clock cycles both time the duration of the same frame interval.

2. The radar signal processing method according to claim 1, characterized in that: The P working clock cycles are obtained by counting by the first timer.

3. The radar signal processing method according to claim 1, characterized in that: The transceiver circuit and the analog-to-digital converter cooperate to process multi-frame chirp signals.

4. The radar signal processing method according to claim 1, characterized in that: The K working clock cycles are obtained by counting by the second timer.

5. The radar signal processing method according to any one of claims 1 to 4, characterized in that: Different frame signals have different frame intervals.

6. The radar signal processing method according to any one of claims 1 to 4, characterized in that: Also includes: The P and K values ​​are allocated according to the least common multiple of the periods of the two working clocks and a preset frame interval to obtain a frame interval actually used for transmitting the chirp signal that is close to the preset frame interval.

7. An integrated circuit, characterized in that: include: A transceiver circuit, a working clock circuit of the transceiver circuit, an analog-to-digital converter, and a working clock circuit of the analog-to-digital converter; The working clock circuit of the transceiver circuit is connected to the transceiver circuit, the transceiver circuit is connected to the analog-to-digital converter, and the analog-to-digital converter is connected to the working clock circuit of the analog-to-digital converter; The working clock circuit of the transceiver circuit provides a working clock to the transceiver circuit; The working clock circuit of the analog-to-digital converter provides a working clock to the analog-to-digital converter; Under the control of the working clock of the transceiver circuit, the transceiver circuit transmits a chirp signal through a transmitting antenna and receives an echo signal of the chirp signal through a receiving antenna, mixes the echo signal with the chirp signal, and outputs a corresponding mixed signal to the analog-to-digital converter; Under the control of the working clock of the analog-to-digital converter, the analog-to-digital converter samples the mixing signal corresponding to the chirp signal; The transceiver circuit starts transmitting the chirp signal of the next frame when waiting for P working clock cycles; as well as The analog-to-digital converter starts sampling a mixing signal when waiting for K working clock cycles, wherein the mixing signal is obtained by using the chirp signal and its corresponding echo signal; wherein the P working clock cycles and the K working clock cycles both time the duration of the same frame interval.

8. The integrated circuit according to claim 7, characterized in that Also includes: a first timer connected to the transceiver circuit; The first timer is used to count the working clock of the transceiver circuit to obtain the P working clock cycles.

9. The integrated circuit according to claim 7, characterized in that: The transceiver circuit and the analog-to-digital converter cooperate to process multi-frame chirp signals.

10. The integrated circuit according to claim 7, characterized in that Also includes: a second timer connected to the analog-to-digital converter; The second timer is used to count the working clock of the analog-to-digital converter to obtain the K working clock cycles.

11. The integrated circuit according to any one of claims 7 to 10, characterized in that Different frame signals have different frame intervals.

12. The integrated circuit according to any one of claims 7 to 10, characterized in that Also includes: a data processor connected to the transceiver circuit and the analog-to-digital converter respectively; The data processor is used to allocate the P and K values ​​according to the least common multiple of the cycles of the two working clocks and a preset frame interval to obtain a frame interval actually used for transmitting the chirp signal that is close to the preset frame interval.

13. A radio device, characterized in that: include: Carrier; An integrated circuit as claimed in any one of claims 7 or 12, arranged on a carrier; An antenna is arranged on the carrier, or the antenna and the integrated circuit are integrated into one device and arranged on the carrier; The integrated circuit is connected to the antenna and is used to transmit the chirp signal and receive an echo signal of the chirp signal.

14. A terminal device, characterized in that: include: Equipment body; as well as The radio device according to claim 13 is arranged on the device body; The radio device is used to detect a target based on an echo signal, so as to provide measurement information of the detected target to the device body.

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