Method for improving in-chip overlay error performance and overlay mark

Abstract

The invention provides a method for improving in-chip overlay error performance and an overlay identifier, and the method comprises the steps: setting an overlay identifier which comprises a previous-layer overlay identifier and a current-layer overlay identifier; providing a wafer, and forming an auxiliary pattern on the front layer corresponding to the area where the front layer overlay mark is to be placed on the front layer; the line extension direction of the auxiliary pattern is perpendicular to the line extension direction of the front-layer overlay mark; photoetching and etching processes of a front layer are completed, and a front layer overlay mark is formed on the front layer; completing the photoetching process of the current layer, and forming a current layer overlay mark on the current layer; and measuring the overlay error of the current layer to the previous layer. The auxiliary pattern is arranged in the front layer below the front layer overlay mark, the pattern distribution density requirement of the front layer is met, and the CMP load effect influence is reduced. By adding the auxiliary pattern, defects are not generated, and normal use of the overlay mark on the front layer is not affected. After the auxiliary pattern is designed, the scanning test wafer has no defects of edge breakage, peeling or falling off, and also has no bridging phenomenon.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a method for improving on-chip overlay error performance and an overlay mark. Background Art

[0002] The stability of overlay error (OVL) is crucial for mass production lithography process and is the key to improving process capability and increasing process window. As the minimum line width of integrated circuit manufacturing process continues to shrink, the requirements for overlay error in advanced node manufacturing process are becoming more and more stringent.

[0003] With the development of technology, the application of chips is becoming more and more extensive, and the demand for large-size chip production (such as 1mm*2mm, etc.) is also increasing. For photolithography, the cutting path space is limited. In order to compensate for the high-order requirements of photolithography overlay errors, it is necessary to set overlay marks on the wafer. The overlay marks are set within the scribe line of the wafer and occupy a fixed position, that is, each layer of overlay marks occupies one position, and all overlay marks do not interfere with each other. The area outside the overlay mark in the scribe line is mostly blank area, and there is a lack of such large blank area in the wafer; in addition, there are density requirements in each layer of the chip and the influence of CMP load effect (the metal distribution on the wafer to be polished layer is uneven, resulting in uneven CMP grinding), which makes the wafer have the risk of defects such as edge collapse. Summary of the invention

[0004] The purpose of the present invention is to provide a method for improving the performance of intra-chip overlay error and an overlay mark, wherein an auxiliary pattern is set in the front-front layer below the front-layer overlay mark to meet the distribution density requirements of the front-front layer pattern and reduce the influence of the CMP load effect. Adding the auxiliary pattern neither produces defects nor affects the normal use of the front-layer overlay mark.

[0005] The present invention provides a method for improving intra-chip overlay error performance, comprising:

[0006] Setting an overlay mark on the corresponding mask, wherein the overlay mark includes a matching previous layer overlay mark and a current layer overlay mark;

[0007] Providing a wafer, wherein the wafer comprises a front-front layer, a front layer and a current layer from bottom to top;

[0008] An auxiliary pattern is formed on the front layer corresponding to the area of ​​the front layer where the front layer overlay mark is to be placed; the line extension direction of the auxiliary pattern is perpendicular to the line extension direction of the front layer overlay mark;

[0009] Complete the photolithography and etching process of the front layer, and form the front layer overlay mark on the front layer;

[0010] Complete the photolithography process of the current layer, and form the current layer overlay mark on the current layer;

[0011] An overlay error of the current layer with respect to the previous layer is measured.

[0012] Furthermore, the auxiliary graphics include a group of dense line groups formed by densely arranged lines in parallel; the front layer overlay mark includes a group of line groups formed by parallel arranged lines; the line extension direction of the dense line group is perpendicular to the line extension direction of the line group.

[0013] Furthermore, the auxiliary graphics include four groups of dense line groups distributed in four quadrants, and the line extension directions of adjacent dense line groups in the four groups of dense line groups are perpendicular to each other; the front layer overlay mark includes four groups of line groups distributed correspondingly to the four groups of dense line groups in the upper and lower directions of the wafer thickness, and the line extension direction of each group of line groups correspondingly distributed upper and lower is perpendicular to the line extension direction of the dense line group.

[0014] Furthermore, the width of each line of the dense line group is the critical dimension line width of the previous layer, and the distance between adjacent lines of the dense line group is the critical dimension spacing of the previous layer.

[0015] Furthermore, the auxiliary pattern is made of metal; the auxiliary pattern is embedded in the front layer, or the auxiliary pattern is located on the surface of the front layer.

[0016] Furthermore, the material of the auxiliary pattern includes any one of copper, tungsten or aluminum.

[0017] Furthermore, the previous layer overlay mark and the current layer overlay mark are formed in the chip or the cutting path of the wafer.

[0018] Furthermore, the measurement procedure for measuring the overlay error includes: an image-based overlay error measurement method and a diffraction-based overlay error measurement method.

[0019] Furthermore, a metal wiring layer for leading out signals is formed on the wafer, and the line arrangement of the metal wiring layer is the same as the line arrangement of the auxiliary pattern.

[0020] The present invention also provides an overlay mark, comprising:

[0021] From bottom to top, the anterior, anterior and current layers;

[0022] A front layer overlay mark is formed on the front layer, and a current layer overlay mark is formed on the current layer, and the current layer overlay mark matches the front layer overlay mark;

[0023] An auxiliary pattern is formed on the front layer corresponding to a region where the front layer overlay mark is set; the line extension direction of the auxiliary pattern is perpendicular to the line extension direction of the front layer overlay mark.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] The present invention provides a method for improving the performance of intra-chip overlay error and an overlay mark, comprising: setting an overlay mark on a corresponding mask, the overlay mark comprising a matching front layer overlay mark and a current layer overlay mark; providing a wafer, the wafer comprising a front-front layer, a front layer and a current layer from bottom to top; forming an auxiliary pattern on the front-front layer corresponding to the area of ​​the front layer where the front layer overlay mark is to be placed; the line extension direction of the auxiliary pattern is perpendicular to the line extension direction of the front layer overlay mark; completing the photolithography and etching process of the front layer, forming the front layer overlay mark on the front layer; completing the photolithography process of the current layer, forming the current layer overlay mark on the current layer; measuring the overlay error of the current layer to the front layer. The present invention sets an auxiliary pattern in the front-front layer below the front layer overlay mark, meets the front-front layer pattern distribution density requirement, and reduces the influence of the CMP load effect. Adding the auxiliary pattern neither produces defects nor affects the normal use of the front layer overlay mark. After auxiliary pattern design, the wafer was scanned and tested to have no defects such as edge chipping, peeling or falling off, and no bridging phenomenon. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 The present invention is a flow chart of a method for improving intra-chip overlay error performance according to an embodiment of the present invention.

[0027] Figure 2 It is a schematic diagram of an auxiliary graphic according to an embodiment of the present invention.

[0028] Figure 3 It is a schematic diagram of an auxiliary diagram of another embodiment of the present invention. DETAILED DESCRIPTION

[0029] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in a very simplified form and use an inaccurate scale, which is only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0030] For ease of description, some embodiments of the present application may use spatially relative terms such as "above", "below", "top", "below", etc. to describe the relationship between one element or component and another (or other) elements or components as shown in the various figures of the embodiments. It should be understood that in addition to the orientations described in the drawings, the spatially relative terms are also intended to include different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the elements or components described as being "below" or "below" other elements or components will subsequently be positioned as being "above" or "above" other elements or components. The terms "first", "second", etc. below are used to distinguish between similar elements and are not necessarily used to describe a specific order or time sequence. It is to be understood that these terms used in this way are interchangeable where appropriate.

[0031] The embodiment of the present invention provides a method for improving the performance of intra-chip overlay error, such as Figure 1 As shown, including:

[0032] Step S1, setting an overlay mark on a corresponding mask, the overlay mark including a matching previous layer overlay mark and a current layer overlay mark;

[0033] Step S2, providing a wafer, wherein the wafer includes a front-front layer, a front layer and a current layer from bottom to top;

[0034] Step S3, forming an auxiliary pattern on the front layer corresponding to the area where the front layer overlay mark is to be placed; the extension direction of the lines of the auxiliary pattern is perpendicular to the extension direction of the lines of the front layer overlay mark;

[0035] Step S4, completing the photolithography and etching process of the front layer, and forming the front layer overlay mark on the front layer;

[0036] Step S5, completing the photolithography process of the current layer, and forming the current layer overlay mark on the current layer;

[0037] Step S6, measuring the overlay error of the current layer with respect to the previous layer.

[0038] The method for improving intra-chip overlay error performance according to an embodiment of the present invention is described in detail below.

[0039] Step S1, setting an overlay mark on a corresponding mask, the overlay mark including a matching previous layer overlay mark and a current layer overlay mark.

[0040] The overlay error of a certain point in the chip circuit diagram can be expressed as the relative displacement of the corresponding points on the two layers on the wafer in the coordinate system. Through mathematical models, the overlay error vectors of multiple points can be decomposed into various geometric deformations according to the wafer surface or exposure unit area. Some deformations can be corrected and compensated by moving the projection lens or exposure stage. Quantitative calculation and processing of these geometric deformations can obtain the control parameters of compensation correction.

[0041] Measure the overlay marks at several locations on the wafer, and build a vector equation model based on the coordinates and vectors of each mark to describe the overlay error of the wafer. The coordinates of a point in the Cartesian coordinate system are (x, y), and the overlay error measurement vector of this point is (x', y'). It can be expressed by a polynomial equation.

[0042] x'=f(x,y)=T x +M xx x+M xy y+Cx 2 +Dxy+…

[0043] y'=g(x,y)=T y +M yx x+M yy y+Ey 2 +Fxy+…

[0044] Among them, T*, M*, C*, E*, D, F... are freedom coefficients independent of x and y, and are usually divided into low-order parameters and high-order parameters according to the order of the x and y degrees of freedom. Order 0 to 2 are low-order, and order 3 and above are high-order. The higher the order, the more accurate it is. The present invention meets the high-order requirements of overlay error.

[0045] Step S2, providing a wafer, the wafer including a front-front layer, a front layer and a current layer from bottom to top. In one example, the front-front layer is, for example, a substrate layer or a dielectric layer in the wafer; the front layer is, for example, any one of a substrate layer, a dielectric layer or other functional layer in the wafer; the current layer is, for example, a photoresist layer or a layer having a photoresist-like function and other suitable layers.

[0046] Step S3, forming an auxiliary pattern on the front layer corresponding to the area where the front layer overlay mark is to be placed; the line extension direction of the auxiliary pattern is perpendicular to the line extension direction of the front layer overlay mark.

[0047] Figure 2 FIG. 1 is a schematic diagram of an auxiliary diagram of an embodiment of the present invention. Figure 2 As shown, the auxiliary graphics include a group of dense line groups formed by intensive lines arranged in parallel. The front layer overlay mark includes a group of line groups formed by parallel arranged lines; the line extension direction of the dense line group is perpendicular to the line extension direction of the line group.

[0048] Figure 3 FIG. 2 is a schematic diagram of an auxiliary diagram of another embodiment of the present invention. Figure 3 As shown, the auxiliary pattern includes four groups of dense line groups distributed in four quadrants, and the line extension directions of adjacent dense line groups in the four groups of dense line groups are arranged perpendicularly in pairs. The front layer overlay mark includes four groups of line groups corresponding to the four groups of dense line groups distributed in the upper and lower directions in the wafer thickness direction, and the line extension direction of each group of line groups corresponding to the upper and lower directions is perpendicular to the line extension direction of the dense line group. Exemplarily, the four groups of dense line groups can be centrally symmetrical patterns.

[0049] For example, Figure 2 and Figure 3 In the example, the width of each line of the dense line group is the key dimension line width of the previous layer, and the auxiliary graphics use the smallest width of dense lines to reduce signal noise. The distance between adjacent lines of the dense line group is the key dimension spacing of the previous layer, and the spacing between adjacent lines of the dense line group of the auxiliary graphics is balanced. That is, the larger the spacing between adjacent lines of the dense line group, the safer it is, and the spacing between adjacent lines of the dense line group cannot affect the measurement signal, that is, the smaller the better.

[0050] The extending direction of the auxiliary pattern of the present invention is perpendicular to the extending direction of the line of the front layer overlay mark. The inventor has found that the front layer overlay mark is divided into X / Y directions, and the auxiliary pattern set randomly simulated by the simulation software has different degrees of influence on the test signal of detecting the front layer overlay mark in the X / Y direction.

[0051] When the line extension direction of the auxiliary pattern specially designed in the present invention is perpendicular to the line extension direction of the previous layer overlay mark, the auxiliary pattern has the same influence on the test signal of the overlay mark in the X / Y direction, and simulation shows that the test signal results of detecting the overlay mark are the same with and without the auxiliary pattern, that is, by designing the line extension direction of the auxiliary pattern to be perpendicular to the line extension direction of the previous layer overlay mark, the accuracy of detecting the overlay mark is no longer affected.

[0052] The present invention sets an auxiliary pattern in the front-front layer below the front-layer overlay mark to meet the front-front layer pattern distribution density requirement and reduce the influence of CMP load effect. Adding the auxiliary pattern neither produces defects nor affects the normal use of the front-layer overlay mark. After the auxiliary pattern is designed, the wafer is scanned and tested without edge collapse, peeling or falling defects, and no bridging phenomenon.

[0053] The auxiliary pattern is made of metal, is embedded in the front layer, or is located on the surface of the front layer, and is made of any one of copper, tungsten or aluminum.

[0054] Step S4, completing the photolithography and etching process of the front layer, and forming the front layer overlay mark on the front layer;

[0055] Step S5, completing the photolithography process of the current layer, and forming the overlay mark of the current layer on the current layer; the overlay mark of the previous layer and the overlay mark of the current layer are formed in the chip or the cutting path of the wafer.

[0056] Step S6, measuring the overlay error of the current layer to the previous layer. The measurement procedures for measuring the overlay error include: image-based overlay error (IBO) measurement method and diffraction-based overlay error (DBO) measurement method.

[0057] A metal lead layer for leading out signals is also formed on the wafer. The line arrangement of the metal lead layer is the same as that of the auxiliary pattern. The line extension direction of the metal lead layer is perpendicular to the line extension direction of the previous layer overlay mark. The line arrangement of the auxiliary pattern is the same as that of the metal lead layer, which is convenient for manufacturing.

[0058] The present invention also provides an overlay mark, comprising:

[0059] From bottom to top, the anterior, anterior and current layers;

[0060] A front layer overlay mark is formed on the front layer, and a current layer overlay mark is formed on the current layer, and the current layer overlay mark matches the front layer overlay mark;

[0061] An auxiliary pattern is formed on the front layer in an area corresponding to the front layer where the front layer overlay mark is set; the line extension direction of the auxiliary pattern is perpendicular to the line extension direction of the front layer overlay mark.

[0062] Figure 2 FIG. 1 is a schematic diagram of an auxiliary diagram of an embodiment of the present invention. Figure 2 As shown, the auxiliary graphics include a group of dense line groups formed by intensive lines arranged in parallel. The front layer overlay mark includes a group of line groups formed by parallel arranged lines; the line extension direction of the dense line group is perpendicular to the line extension direction of the line group.

[0063] Figure 3 FIG. 2 is a schematic diagram of an auxiliary diagram of another embodiment of the present invention. Figure 3 As shown, the auxiliary pattern includes four groups of dense line groups distributed in four quadrants, and the line extension directions of adjacent dense line groups in the four groups of dense line groups are arranged perpendicularly in pairs. The front layer overlay mark includes four groups of line groups corresponding to the four groups of dense line groups distributed in the upper and lower directions in the wafer thickness direction, and the line extension direction of each group of line groups corresponding to the upper and lower directions is perpendicular to the line extension direction of the dense line group. Exemplarily, the four groups of dense line groups can be centrally symmetrical patterns.

[0064] The auxiliary pattern is made of metal, is embedded in the front layer, or is located on the surface of the front layer, and is made of any one of copper, tungsten or aluminum.

[0065] In summary, the present invention provides a method for improving the performance of intra-wafer overlay error and an overlay mark, comprising: setting an overlay mark on a corresponding mask, the overlay mark comprising a matching front layer overlay mark and a current layer overlay mark; providing a wafer, the wafer comprising a front-front layer, a front layer and a current layer from bottom to top; forming an auxiliary pattern on the front-front layer corresponding to the area where the front layer overlay mark is to be placed on the front layer; the line extension direction of the auxiliary pattern is perpendicular to the line extension direction of the front layer overlay mark; completing the photolithography and etching process of the front layer, forming the front layer overlay mark on the front layer; completing the photolithography process of the current layer, forming the current layer overlay mark on the current layer; measuring the overlay error of the current layer to the front layer. An auxiliary pattern is set in the front-front layer below the front layer overlay mark to meet the distribution density requirements of the front-front layer pattern and reduce the influence of the CMP load effect. Adding an auxiliary pattern neither generates defects nor affects the normal use of the front layer overlay mark. After the auxiliary pattern is designed, the wafer is scanned and tested to have no defects such as edge collapse, peeling or falling off, and no bridging phenomenon.

[0066] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the method disclosed in the embodiment, since it corresponds to the device disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0067] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any technical personnel in this field can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A method for improving intra-chip overlay error performance, characterized in that: include: Setting an overlay mark on the corresponding mask, wherein the overlay mark includes a matching previous layer overlay mark and a current layer overlay mark; Providing a wafer, wherein the wafer comprises a front-front layer, a front layer and a current layer from bottom to top; An auxiliary pattern is formed on the front layer corresponding to the area of ​​the front layer where the front layer overlay mark is to be placed; the line extension direction of the auxiliary pattern is perpendicular to the line extension direction of the front layer overlay mark; Complete the photolithography and etching process of the front layer, and form the front layer overlay mark on the front layer; Complete the photolithography process of the current layer, and form the current layer overlay mark on the current layer; An overlay error of the current layer with respect to the previous layer is measured.

2. The method for improving intra-chip overlay error performance according to claim 1, characterized in that: The auxiliary pattern includes a group of dense lines arranged in parallel to form a dense line group; The front layer overlay mark includes a group of line groups formed by parallel arranged lines; An extending direction of the lines of the dense line group is perpendicular to an extending direction of the lines of the line group.

3. The method for improving intra-chip overlay error performance according to claim 1, characterized in that: The auxiliary pattern includes four groups of dense line groups distributed in four quadrants, and the lines of adjacent dense line groups in the four groups of dense line groups extend in directions perpendicular to each other; The front layer overlay mark includes four groups of line groups correspondingly distributed up and down with the four groups of dense line groups in the wafer thickness direction, and the line extension direction of each group of line groups correspondingly distributed up and down is perpendicular to the line extension direction of the dense line group.

4. The method for improving intra-chip overlay error performance according to claim 2 or 3, characterized in that: The width of each line of the dense line group is the critical dimension line width of the previous layer, and the distance between adjacent lines of the dense line group is the critical dimension spacing of the previous layer.

5. The method for improving intra-chip overlay error performance according to claim 1, characterized in that: The auxiliary pattern is made of metal; the auxiliary pattern is embedded in the front layer, or the auxiliary pattern is located on the surface of the front layer.

6. The method for improving intra-chip overlay error performance as claimed in claim 5, characterized in that: The auxiliary pattern is made of any one of copper, tungsten or aluminum.

7. The method for improving intra-chip overlay error performance according to claim 1, characterized in that: The previous layer overlay mark and the current layer overlay mark are formed in the chip or the dicing road of the wafer.

8. The method for improving intra-chip overlay error performance as claimed in claim 1, characterized in that: The measurement procedures for measuring the overlay error include: an image-based overlay error measurement method and a diffraction-based overlay error measurement method.

9. The method for improving intra-chip overlay error performance as claimed in claim 1, characterized in that: A metal wiring layer for leading out signals is also formed on the wafer, and the line arrangement of the metal wiring layer is the same as the line arrangement of the auxiliary pattern.

10. An overlay mark, characterized in that: include: From bottom to top, the anterior, anterior and current layers; A front layer overlay mark is formed on the front layer, and a current layer overlay mark is formed on the current layer, and the current layer overlay mark matches the front layer overlay mark; An auxiliary pattern is formed on the front layer corresponding to a region where the front layer overlay mark is set; an extension direction of lines of the auxiliary pattern is perpendicular to an extension direction of lines of the front layer overlay mark.

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