Semiconductor device with ohmic metal isolation layer and manufacturing method thereof

Abstract

The present invention provides a semiconductor device with an ohmic metal isolation layer and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a gallium nitride substrate, and depositing a first dielectric layer; depositing a diffusion barrier layer; preparing an ohmic contact hole; depositing an ohmic metal layer, and annealing the ohmic metal layer; depositing a titanium nitride metal layer; preparing an ohmic electrode; depositing a dielectric stack; preparing a gate region and a field plate region; preparing a gate metal and a gate field plate; depositing an insulating layer; preparing contact holes for the gate, source and drain; depositing a metal layer, and preparing a gate, source and drain. Annealing is performed before depositing the titanium nitride metal layer on the ohmic metal layer, so that the titanium nitride metal layer and the ohmic metal layer are not annealed at the same time, effectively solving the problem of ohmic contact resistance degradation; the diffusion barrier layer can prevent the ohmic metal from diffusing to the first dielectric layer during the annealing process, effectively improving chip reliability, and facilitating the realization of a smaller device size.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular to a semiconductor device with an ohmic metal isolation layer and a manufacturing method thereof. Background Art

[0002] GaN high electron mobility transistor devices have superior device performance and have broad application prospects in the field of high frequency and high power. The typical structures of current power GaN products are mainly divided into depletion-mode devices and enhancement-mode devices. The structure of depletion-mode GaN devices is simple, which enables them to retain the high electron concentration and high electron mobility of GaN heterojunction HEMT to the greatest extent, and its gate is also very reliable. How to further optimize the process flow of depletion-mode GaN devices and improve the electrical properties and reliability of devices is of great significance.

[0003] The current GaN technology platform, ohmic metal stacking structure, and RTP annealing treatment have a great impact on ohmic contact resistance. In the prior art, ohmic electrodes are usually formed by etching ohmic metals, and then annealed. However, this process will cause the ohmic contact resistance (Rc) to deteriorate. In order to achieve lower device on-resistance, the device size needs to be increased, resulting in a reduction in the number of devices on a single wafer and an increase in cost. Summary of the invention

[0004] The present invention provides a semiconductor device with an ohmic metal isolation layer and a manufacturing method thereof, which can solve the problem of ohmic contact resistance degradation, improve the accuracy of the ohmic electrode profile, and facilitate the realization of a smaller device size.

[0005] An embodiment of the present invention provides a method for manufacturing a semiconductor device having an ohmic metal isolation layer, comprising the following steps:

[0006] a. providing a gallium nitride substrate, and depositing a first dielectric layer on the gallium nitride substrate;

[0007] b. depositing a diffusion barrier layer on the first dielectric layer;

[0008] c. Etching the diffusion barrier layer, the first dielectric layer and the gallium nitride substrate in the source region and the drain region to form ohmic contact holes;

[0009] d. depositing an ohmic metal layer, and annealing the ohmic metal layer;

[0010] e. depositing a titanium nitride metal layer on the ohmic metal layer;

[0011] f. Etching the titanium nitride metal layer, the ohmic metal layer and the diffusion barrier layer outside the source region and the drain region to form a source ohmic electrode and a drain ohmic electrode;

[0012] g. Depositing a dielectric stack on the source ohmic electrode, the drain ohmic electrode and the first dielectric layer;

[0013] h. Etching the dielectric stack in the gate region and the field plate region to form the gate region and the field plate region;

[0014] i. depositing a metal layer, and etching the metal layer outside the gate region and the field plate region to form a gate metal and a gate field plate;

[0015] j. Depositing an insulating layer on the dielectric stack, the gate metal and the gate field plate and planarizing them;

[0016] k. Etching the insulating layer in the gate region to form a gate contact hole; and etching the insulating layer, the dielectric stack and the titanium nitride metal layer in the source region and the drain region to form a source contact hole and a drain contact hole;

[0017] 1. Depositing a metal layer, and etching the metal layer outside the gate contact hole, the source contact hole, and the drain contact hole to form a gate, a source, and a drain.

[0018] The gallium nitride substrate comprises a silicon substrate, a gallium nitride layer, an aluminum gallium nitride layer, and a silicon nitride layer which are arranged in sequence; and the first dielectric layer is deposited on a side of the gallium nitride substrate away from the silicon substrate.

[0019] The depth of the ohmic contact hole reaches the aluminum gallium nitride layer; the depth of the gate region reaches the silicon nitride layer.

[0020] Wherein, the dielectric stack includes a second dielectric layer, a first barrier layer and a third dielectric layer deposited in sequence; the field plate region includes a first field plate region and a second field plate region;

[0021] The step of etching the dielectric stack of the gate region and the field plate region to form the gate region and the field plate region comprises:

[0022] Carving through the third dielectric layer and the first barrier layer at the gate region position and at both sides thereof to form the first field plate region on the second dielectric layer and the second field plate region on the third dielectric layer;

[0023] The second dielectric layer and the first dielectric layer are etched through at the gate region to expose the silicon nitride layer, so as to form the gate region.

[0024] The dielectric stack includes a second dielectric layer, a first barrier layer, a third dielectric layer, a second barrier layer and a fourth dielectric layer deposited in sequence; the field plate region includes a first field plate region, a second field plate region and a third field plate region;

[0025] The step of etching the dielectric stack of the gate region and the field plate region to form the gate region and the field plate region comprises:

[0026] Carving through the fourth dielectric layer and the second barrier layer to form the third field plate region on the fourth dielectric layer;

[0027] Carving through the third dielectric layer and the first barrier layer at the gate region position and at both sides thereof to form the first field plate region on the second dielectric layer and the second field plate region on the third dielectric layer;

[0028] The second dielectric layer and the first dielectric layer are etched through at the gate region to expose the silicon nitride layer, so as to form the gate region.

[0029] Wherein, the gate metal and the gate field plate are connected; or, the gate metal and the gate field plate are separated.

[0030] Wherein, the diffusion barrier layer is aluminum nitride or aluminum oxide deposited by atomic vapor deposition or physical vapor deposition, or silicon oxide, silicon nitride, or silicon oxynitride with high density deposited by chemical vapor deposition.

[0031] Wherein, the ohmic metal layer is a stacked layer of titanium and aluminum metals.

[0032] The semiconductor devices include but are not limited to MIS-HEMT devices, P-GaN HEMT devices and SBD-Gate HEMT devices.

[0033] On the other hand, the present invention provides a semiconductor device prepared using the above-mentioned manufacturing method, the semiconductor device comprising a gallium nitride substrate, a first dielectric layer, a dielectric stack, an insulating layer and an ohmic electrode which are stacked in sequence, a gate field plate is provided between the dielectric stack and the insulating layer, a gate metal is provided between the first dielectric layer and the insulating layer, a gate is provided in the insulating layer, and the gate is connected to the gate metal; the ohmic electrode is T-shaped, and the metal layers on both sides of the top are located between the dielectric stack and the first dielectric layer, and a diffusion barrier layer is provided between the ohmic electrode and the first dielectric layer; the ohmic electrode penetrates downward through the first dielectric layer and extends to the gallium nitride substrate; a titanium nitride metal layer is provided on the top of the ohmic electrode; there are more than two ohmic electrodes, including a source ohmic electrode and a drain ohmic electrode, a source and a drain are provided in the insulating layer and the dielectric stack, the source is connected to the top of the source ohmic electrode, and the drain is connected to the top of the drain ohmic electrode.

[0034] The semiconductor device with an ohmic metal isolation layer provided by the present invention and the manufacturing method thereof are characterized in that an annealing treatment is performed before a titanium nitride metal layer is deposited on the ohmic metal layer to ensure the performance of the ohmic metal layer, so that the titanium nitride metal layer and the ohmic metal layer will not be annealed at the same time, and the problem of ohmic contact resistance degradation is effectively solved; the diffusion barrier layer can prevent the ohmic metal from diffusing to the first dielectric layer during the annealing process, and the chip reliability is effectively improved; after the ohmic metal layer is annealed, the titanium nitride metal layer is deposited, and then the titanium nitride metal layer and the ohmic metal layer are etched, at which time the titanium nitride metal layer acts as an anti-reflection layer, which can improve the etching accuracy, thereby improving the accuracy of the ohmic electrode profile, which is conducive to achieving a smaller device size, increasing the number of devices on a single wafer and reducing costs; the subsequent titanium nitride metal layer can be used as an etching stop layer for source and drain contact holes to ensure the accuracy of the source and drain. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 The present invention provides a flow chart of a method for manufacturing a semiconductor device with an ohmic metal isolation layer.

[0036] Figure 2A-2N The figure is a schematic diagram of the manufacturing process of the semiconductor device with an ohmic metal isolation layer of the present invention. DETAILED DESCRIPTION

[0037] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0038] Example 1.

[0039] The semiconductor device with an ohmic metal isolation layer prepared in this embodiment is a D-type gallium nitride high electron mobility transistor, which can be used as a high-power application device such as a switching device or an amplifier device.

[0040] Specifically, Figure 1 As shown, the method for manufacturing a semiconductor device with an ohmic metal isolation layer in this embodiment includes the following steps.

[0041] Step S10 : providing a gallium nitride substrate 1 , and depositing a first dielectric layer 21 on the gallium nitride substrate 1 .

[0042] In this step, if Figure 2A As shown, the gallium nitride substrate 1 includes a silicon substrate 11, a gallium nitride (GaN) layer 12, an aluminum gallium nitride (ALGaN) layer 13, and a silicon nitride (SIN) layer 14 arranged in sequence. A first dielectric layer 21 is deposited on a side of the gallium nitride substrate 1 away from the silicon substrate 11 .

[0043] Step S20, depositing a diffusion barrier layer 3 on the first dielectric layer 21. Figure 2B FIG. 1 is a schematic diagram of the structure after the diffusion barrier layer 3 is deposited.

[0044] The diffusion barrier layer can prevent the ohmic metal from diffusing into the first dielectric layer 21 in subsequent steps.

[0045] The diffusion barrier layer 3 is aluminum nitride or aluminum oxide deposited by atomic vapor deposition or physical vapor deposition, or silicon oxide, silicon nitride, or silicon oxynitride with high density deposited by chemical vapor deposition. In this embodiment, the diffusion barrier layer 3 is an aluminum nitride layer.

[0046] The diffusion barrier layer 3 is a dielectric layer with good density, which is used to prevent the ohmic metal layer from diffusing toward the first dielectric layer 21 below during the annealing process, thereby improving the reliability of the device.

[0047] Step S30, etching the diffusion barrier layer 3, the first dielectric layer 21 and the gallium nitride substrate 1 in the source region and the drain region to form an ohmic contact hole 40. This step can form an ohmic contact hole 40 in the source region and the drain region at the same time. Figure 2C , which is a schematic diagram of the structure after etching to form ohmic contact holes 40. There are at least two ohmic contact holes 40, one in the source region and the other in the drain region.

[0048] The ohmic contact hole 40 penetrates the first dielectric layer 21 and the silicon nitride layer 14 , and its depth reaches the aluminum gallium nitride layer 13 , so that the manufactured ohmic electrode can contact the aluminum gallium nitride layer 13 .

[0049] Step S40 , depositing an ohmic metal layer 41 , and performing annealing treatment on the ohmic metal layer 41 .

[0050] like Figure 2D FIG. 4 is a schematic diagram of a structure after depositing an ohmic metal layer 41 and annealing. Annealing can ensure that a good contact resistance is obtained.

[0051] In this step, the ohmic metal layer 41 covers the diffusion barrier layer 3 and fills the ohmic contact hole 40. The ohmic metal layer 41 is preferably a stack of titanium and aluminum metals. Titanium has strong adhesion to the gallium nitride substrate, which can ensure the mechanical stability of the ohmic metal contact; aluminum can naturally form an ohmic contact with the gallium nitride substrate. Of course, here, in other embodiments, the ohmic metal layer 41 can also be a multilayer structure formed by different combinations of metals such as titanium, aluminum, nickel, and gold.

[0052] In this step, the ohmic metal layer may be annealed using an RTP (Rapid Thermal Processing) annealing process to repair lattice defects, eliminate stress, and optimize the conductive properties of the material.

[0053] Because the diffusion barrier layer 3 is added to protect the first dielectric layer before depositing the ohmic metal layer, the ohmic metal can be prevented from diffusing into the first dielectric layer 21 during the RTP annealing process, thereby effectively improving chip reliability.

[0054] Step S50 , depositing a titanium nitride metal layer 5 on the ohmic metal layer 41 .

[0055] The titanium nitride metal layer 5 covers the ohmic metal layer 41. Figure 2E FIG. 1 is a schematic diagram of the structure after the titanium nitride metal layer 5 is deposited.

[0056] The ohmic metal layer 41 is annealed before the titanium nitride metal layer 5 is deposited, so that the titanium nitride metal layer and the ohmic metal layer are not annealed at the same time to avoid affecting the performance of the contact resistance.

[0057] Step S60, etching the titanium nitride metal layer 5, the ohmic metal layer 41 and the diffusion barrier layer 3 outside the source region and the drain region to form a source ohmic electrode 421 and a drain ohmic electrode 422. Figure 2F As shown, it is a schematic diagram of the structure after the ohmic electrode is formed.

[0058] When etching the ohmic metal layer 41, the titanium nitride metal layer 5 acts as an anti-reflection layer, which can improve the etching accuracy, thereby improving the accuracy of the ohmic electrode profile, which is conducive to achieving a smaller device size, increasing the number of devices on a single wafer and reducing costs; the subsequent titanium nitride metal layer 5 can also be used as an etching stop layer for contact holes such as the source and drain to ensure the accuracy of the source, drain, etc.

[0059] Step S70, as Figure 2GAs shown, a dielectric stack 2 is deposited on the source ohmic electrode 421 , the drain ohmic electrode 422 and the first dielectric layer 21 .

[0060] Step S80 , etching the dielectric stack 2 in the gate region and the field plate region to form the gate region and the field plate region.

[0061] In this embodiment, Figure 2G As shown, the dielectric stack 2 includes a second dielectric layer 22, a first barrier layer 25, a third dielectric layer 23, a second barrier layer 26 and a fourth dielectric layer 24 deposited in sequence. The first barrier layer 25 can be used as an etching stop layer when etching the third dielectric layer 23, and the second barrier layer 26 can be used as an etching stop layer when etching the fourth dielectric layer 24. The field plate region includes a first field plate region, a second field plate region and a third field plate region.

[0062] In step S80 , the fourth dielectric layer 24 , the second barrier layer 26 , the third dielectric layer 23 , the first barrier layer 25 , the second dielectric layer 22 and the first dielectric layer 21 are sequentially etched to expose the silicon nitride layer 14 to form a gate region and a field plate region.

[0063] The depth of the gate region reaches the silicon nitride layer 14 so that the gate metal can contact the silicon nitride layer 14;

[0064] Step S80 specifically includes the following sub-steps.

[0065] Step S81, as Figure 2H As shown, the fourth dielectric layer 24 and the second barrier layer 26 are etched through to form a third field plate region on the fourth dielectric layer 24 .

[0066] Step S82, as Fig.2I As shown, the third dielectric layer 23 and the first barrier layer 25 are etched through at the gate region and at both sides thereof to form a first field plate region on the second dielectric layer 22 and a second field plate region on the third dielectric layer 23 .

[0067] Step S83, as Figure 2J As shown, the second dielectric layer 22 and the first dielectric layer 21 are etched through at the gate region to expose the silicon nitride layer 14 to form a gate region.

[0068] Step S9, depositing a metal layer, and etching the metal outside the gate region and the field plate region to form a gate metal 61 and a gate field plate 62. Figure 2K, which is a schematic diagram of the structure after the gate metal 61 and the gate field plate 62 are prepared and formed. The gate metal 61 is located in the gate region, and the gate field plate 62 is located in the field plate region, which includes a first field plate 621, a second field plate 622 and a third field plate 623, which are respectively located in the first field plate region, the second field plate region and the third field plate region. The first field plate 621 is located in the first field plate region, i.e., on the second dielectric layer 22, the second field plate 622 is located in the second field plate region, i.e., on the third dielectric layer 23, and the third field plate 623 is located in the third field plate region, i.e., on the fourth dielectric layer 24.

[0069] In this embodiment, the gate region, the first field plate region, the second field plate region, and the third field plate region are sequentially arranged adjacent to each other, so that the prepared gate metal 61 is connected to the gate field plate 62. Here, in other embodiments, in the gate region, the first field plate region, the second field plate region, and the third field plate region, two adjacent regions may not be connected to each other, so that the prepared gate metal and the gate field plate are separated; or, the tertiary region is connected to the field plate region, but when preparing the gate metal and the gate field plate, the gate metal and the gate field plate are separated by etching so that the two are not connected, that is, separated, so as to avoid stress caused by the connection of large pieces of metal and cause device damage, thereby improving device reliability.

[0070] Step S100 , depositing an insulating layer 7 on the dielectric stack 2 , the gate metal 61 and the gate field plate 62 and planarizing the insulating layer 7 .

[0071] In this embodiment, the insulating layer 7 is an interlayer dielectric layer (ILD, Inter Layer Dielectric).

[0072] In this step, the surface of the insulating layer 7 may be polished by chemical mechanical polishing to make the upper surface of the insulating layer 7 a flat surface. Figure 2L FIG. 4 is a schematic diagram of the structure after completing step S100 .

[0073] Step S110, etching the insulating layer 7 in the gate region to form a gate contact hole 73; and etching the insulating layer, dielectric stack 2 and titanium nitride metal layer 5 in the source region and drain region to form a source contact hole 71 and a drain contact hole 72. Figure 2M , which is a schematic diagram of the structure after the gate contact hole 73 , the source contact hole 71 and the drain contact hole 72 are formed.

[0074] Step S120 , depositing a metal layer, and etching the metal layer other than the gate contact hole, the source contact hole, and the drain contact hole to form a gate 83 , a source 81 , and a drain 82 .

[0075] like Figure 2N , which is a schematic diagram of the structure after the gate 83, the source 81 and the drain 82 are formed.

[0076] The method for manufacturing a semiconductor device with an ohmic metal isolation layer provided by the present invention comprises the following steps: performing an annealing treatment before depositing a titanium nitride metal layer on the ohmic metal layer to ensure the overall shape of the ohmic metal layer, thereby effectively solving the problem of deterioration of the ohmic contact resistance; depositing a titanium nitride metal layer after the ohmic metal layer is annealed, and then etching the titanium nitride metal layer and the ohmic metal layer. At this time, the titanium nitride metal layer serves as an anti-reflection layer, which can improve the etching accuracy, thereby improving the accuracy of the ohmic electrode profile, which is conducive to achieving a smaller device size, increasing the number of devices on a single wafer and reducing costs; and the subsequent titanium nitride metal layer can be used as an etching stop layer for a gate, a source, a drain, etc., thereby ensuring the accuracy of the gate, the source, the drain, etc.

[0077] The present invention also provides a semiconductor device with an ohmic metal isolation layer, which is manufactured using the manufacturing method of the semiconductor device with an ohmic metal isolation layer of the aforementioned embodiment 1, and includes but is not limited to a MIS-HEMT device, a P-GaN HEMT device, and a SBD-Gate HEMT device. For example, it can be a D-type gallium nitride high electron mobility transistor, which can be used as a high-power application device such as a switching device or an amplifier device.

[0078] The semiconductor device comprises a gallium nitride substrate 1, a first dielectric layer 21, a dielectric stack 2, an insulating layer 7 and an ohmic electrode (421, 422) which are stacked in sequence, a gate field plate 62 is provided between the dielectric stack 2 and the insulating layer 7, a gate metal 61 is provided between the silicon nitride layer 14 and the insulating layer 7, a gate 83 is provided in the insulating layer 7, and the gate 83 is connected to the gate metal 61; the ohmic electrode is T-shaped, and the metal layers on both sides of the top are located between the dielectric stack 2 and the first dielectric layer 21, and are connected to the first dielectric layer A diffusion barrier layer 3 is arranged between the insulating layer 7 and the dielectric stack 21; the ohmic electrodes (421, 422) penetrate downwardly through the first dielectric layer 21 and extend to the gallium nitride substrate 1; a titanium nitride metal layer 5 is arranged on the top of the ohmic electrodes; there are more than two ohmic electrodes, including a source ohmic electrode 421 and a drain ohmic electrode 422, and a source 81 and a drain 82 are arranged in the insulating layer 7 and the dielectric stack 2, the source 81 is connected to the top of the source ohmic electrode 421, and the drain 82 is connected to the top of the drain ohmic electrode 422.

[0079] In the semiconductor device provided by the present invention, a diffusion barrier layer is arranged between the metal layers on both sides of the top of the ohmic electrode and the first dielectric layer, which can prevent the ohmic metal from diffusing into the first dielectric layer during the annealing process, and effectively improve the chip reliability. A titanium nitride metal layer is arranged on the top of the ohmic electrode, and the titanium nitride metal layer acts as an anti-reflection layer in the process of forming the ohmic electrode by etching, which can improve the etching accuracy, thereby improving the accuracy of the ohmic electrode profile, which is conducive to achieving a smaller device size, increasing the number of devices on a single wafer and reducing costs; the ohmic metal layer for preparing the ohmic electrode does not need to be annealed at the same time as the titanium nitride metal layer, which effectively solves the problem of ohmic contact resistance degradation.

[0080] In this embodiment, the gallium nitride substrate 1 includes a silicon substrate 11, a gallium nitride (GaN) layer 12, an aluminum gallium nitride (ALGaN) layer 13, and a silicon nitride (SIN) layer 14 arranged in sequence. The first dielectric layer 21 is located on the side of the gallium nitride substrate 1 away from the silicon substrate 11. The ohmic contact hole 40 penetrates the first dielectric layer 21 and the silicon nitride layer 14, and its depth reaches the aluminum gallium nitride layer 13, so that the manufactured ohmic electrode can contact the aluminum gallium nitride layer 13.

[0081] The ohmic electrode 4 is preferably a metal stack of titanium and aluminum. Titanium has strong adhesion to the gallium nitride substrate, which can ensure the mechanical stability of the ohmic metal contact; aluminum can naturally form an ohmic contact with the gallium nitride substrate. Of course, here, in other embodiments, the ohmic electrode can also be a multilayer structure formed by different combinations of metals such as titanium, aluminum, nickel, and gold.

[0082] The dielectric stack 2 includes a second dielectric layer 22, a first barrier layer 25, a third dielectric layer 23, a second barrier layer 26 and a fourth dielectric layer 24, which are sequentially arranged from bottom to top. The first barrier layer 25 can be used as an etching stop layer when etching the third dielectric layer 23, and the second barrier layer 26 can be used as an etching stop layer when etching the fourth dielectric layer 24.

[0083] The gate metal 61 is deep enough to the silicon nitride layer 14 so that the two are in contact. The gate field plate 62 includes a first field plate 621, a second field plate 622, and a third field plate 623. The first field plate 621 is located between the second dielectric layer 22 and the insulating layer 7, the second field plate 622 is located between the third dielectric layer 23 and the insulating layer 7, and the third field plate 623 is located between the fourth dielectric layer 24 and the insulating layer 7. The dielectric stack 2 can be used to make the gate field plate 62 a multi-layer structure so as to control the electric field distribution.

[0084] In this embodiment, the gate metal 61 is connected to the gate field plate 62 for ease of preparation. Of course, in other embodiments, the gate metal 61 can also be separated from the gate field plate to avoid stress caused by large metal pieces connected to each other, thereby improving device reliability.

[0085] Example 2

[0086] In this embodiment, the dielectric stack includes a second dielectric layer, a first barrier layer and a third dielectric layer deposited in sequence, wherein the first barrier layer 25 can be used as an etching stop layer when etching the third dielectric layer. The field plate region includes a first field plate region and a second field plate region.

[0087] In step S80, the third dielectric layer, the first barrier layer, the second dielectric layer and the first dielectric layer are sequentially etched through to expose the silicon nitride layer, so as to form a gate region and a field plate region.

[0088] Specifically, step S80 includes the following sub-steps.

[0089] Step S81 , etching through the third dielectric layer 23 and the first barrier layer at the gate region and at both sides thereof to form a first field plate region on the second dielectric layer 22 and a second field plate region on the third dielectric layer 23 .

[0090] Step S82, etching through the second dielectric layer 22 and the first dielectric layer 21 at the gate region to expose the silicon nitride layer 14 to form a gate region.

[0091] At this point, step S80 of another embodiment is completed.

[0092] It can be seen from the above that the second barrier layer and the fourth dielectric layer may not be provided in the dielectric stack, and therefore the number of dielectric layers and barrier layers may be determined according to the structural requirements of the gate field plate.

[0093] The present invention also provides a semiconductor device with an ohmic metal isolation layer, which is manufactured using the manufacturing method of a semiconductor device with an ohmic metal isolation layer of the aforementioned embodiment 2. The difference between its structure and that of embodiment 1 lies in the absence of a fourth dielectric layer and a second barrier layer. Accordingly, the gate field plate does not contain a third field plate. The other parts of the structure are the same as those of the first embodiment and will not be described again here.

[0094] In summary, although the present invention has been disclosed as above in terms of preferred embodiments, the above preferred embodiments are not intended to limit the present invention. A person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined in the claims.

Claims

1. A method for manufacturing a semiconductor device having an ohmic metal isolation layer, characterized in that: The following steps are involved: a. providing a gallium nitride substrate, and depositing a first dielectric layer on the gallium nitride substrate; b. depositing a diffusion barrier layer on the first dielectric layer; c. Etching the diffusion barrier layer, the first dielectric layer and the gallium nitride substrate in the source region and the drain region to form ohmic contact holes; d. depositing an ohmic metal layer, and annealing the ohmic metal layer; e. depositing a titanium nitride metal layer on the ohmic metal layer; f. Etching the titanium nitride metal layer, the ohmic metal layer and the diffusion barrier layer outside the source region and the drain region to form a source ohmic electrode and a drain ohmic electrode; g. Depositing a dielectric stack on the source ohmic electrode, the drain ohmic electrode and the first dielectric layer; h. Etching the dielectric stack in the gate region and the field plate region to form the gate region and the field plate region; i. depositing a metal layer, and etching the metal layer outside the gate region and the field plate region to form a gate metal and a gate field plate; j. Depositing an insulating layer on the dielectric stack, the gate metal and the gate field plate and planarizing them; k. Etching the insulating layer in the gate region to form a gate contact hole; and etching the insulating layer, the dielectric stack and the titanium nitride metal layer in the source region and the drain region to form a source contact hole and a drain contact hole; 1. Depositing a metal layer, and etching the metal layer outside the gate contact hole, the source contact hole, and the drain contact hole to form a gate, a source, and a drain.

2. The method for manufacturing a semiconductor device having an ohmic metal isolation layer according to claim 1, characterized in that: The gallium nitride substrate comprises a silicon substrate, a gallium nitride layer, an aluminum gallium nitride layer, and a silicon nitride layer which are arranged in sequence; the first dielectric layer is deposited on a side of the gallium nitride substrate away from the silicon substrate.

3. The method for manufacturing a semiconductor device having an ohmic metal isolation layer according to claim 2, characterized in that: The depth of the ohmic contact hole reaches the aluminum gallium nitride layer; the depth of the gate region reaches the silicon nitride layer.

4. The method for manufacturing a semiconductor device having an ohmic metal isolation layer according to claim 2, characterized in that: The dielectric stack includes a second dielectric layer, a first barrier layer and a third dielectric layer deposited in sequence; the field plate region includes a first field plate region and a second field plate region; The step of etching the dielectric stack of the gate region and the field plate region to form the gate region and the field plate region comprises: Carving through the third dielectric layer and the first barrier layer at the gate region position and at both sides thereof to form the first field plate region on the second dielectric layer and the second field plate region on the third dielectric layer; The second dielectric layer and the first dielectric layer are etched through at the gate region to expose the silicon nitride layer, so as to form the gate region.

5. The method for manufacturing a semiconductor device having an ohmic metal isolation layer according to claim 2, characterized in that: The dielectric stack includes a second dielectric layer, a first barrier layer, a third dielectric layer, a second barrier layer and a fourth dielectric layer deposited in sequence; the field plate region includes a first field plate region, a second field plate region and a third field plate region; The step of etching the dielectric stack of the gate region and the field plate region to form the gate region and the field plate region comprises: Carving through the fourth dielectric layer and the second barrier layer to form the third field plate region on the fourth dielectric layer; Carving through the third dielectric layer and the first barrier layer at the gate region position and at both sides thereof to form the first field plate region on the second dielectric layer and the second field plate region on the third dielectric layer; The second dielectric layer and the first dielectric layer are etched through at the gate region to expose the silicon nitride layer, so as to form the gate region.

6. The method for manufacturing a semiconductor device having an ohmic metal isolation layer according to claim 1, characterized in that: The gate metal and the gate field plate are connected; or, the gate metal and the gate field plate are separated.

7. The method for manufacturing a semiconductor device having an ohmic metal isolation layer according to claim 1, characterized in that: The diffusion barrier layer is aluminum nitride or aluminum oxide deposited by atomic vapor deposition or physical vapor deposition, or silicon oxide, silicon nitride, or silicon oxynitride with high density deposited by chemical vapor deposition.

8. The method for manufacturing a semiconductor device having an ohmic metal isolation layer according to claim 1, characterized in that: The ohmic metal layer is a stacked layer of titanium and aluminum.

9. The method for manufacturing a semiconductor device having an ohmic metal isolation layer according to claim 1, characterized in that: The semiconductor devices include MIS-HEMT devices, P-GaN HEMT devices and SBD-Gate HEMT devices.

10. A semiconductor device manufactured using the manufacturing method according to any one of claims 1 to 9, characterized in that: The semiconductor device comprises a gallium nitride substrate, a first dielectric layer, a dielectric stack, an insulating layer and an ohmic electrode which are stacked in sequence, a gate field plate is arranged between the dielectric stack and the insulating layer, a gate metal is arranged between the first dielectric layer and the insulating layer, a gate is arranged in the insulating layer, and the gate is connected to the gate metal; the ohmic electrode is T-shaped, and the metal layers on both sides of the top are located between the dielectric stack and the first dielectric layer, and a diffusion barrier layer is arranged between the ohmic electrode and the first dielectric layer; the ohmic electrode penetrates downward through the first dielectric layer and extends to the gallium nitride substrate; a titanium nitride metal layer is arranged on the top of the ohmic electrode; there are more than two ohmic electrodes, including a source ohmic electrode and a drain ohmic electrode, a source and a drain are arranged in the insulating layer and the dielectric stack, the source is connected to the top of the source ohmic electrode, and the drain is connected to the top of the drain ohmic electrode.

Images